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tools/power turbostat: add precision to --debug frequency output
[linux-block.git] / tools / power / x86 / turbostat / turbostat.c
CommitLineData
103a8fea
LB		 1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
144b44b1 5 * Copyright (c) 2013 Intel Corporation.
103a8fea
LB		 6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
88c3281f 22#define _GNU_SOURCE
b731f311 23#include MSRHEADER
869ce69e 24#include INTEL_FAMILY_HEADER
95aebc44 25#include <stdarg.h>
103a8fea 26#include <stdio.h>
b2c95d90 27#include <err.h>
103a8fea
LB		 28#include <unistd.h>
29#include <sys/types.h>
30#include <sys/wait.h>
31#include <sys/stat.h>
32#include <sys/resource.h>
33#include <fcntl.h>
34#include <signal.h>
35#include <sys/time.h>
36#include <stdlib.h>
d8af6f5f 37#include <getopt.h>
103a8fea
LB		 38#include <dirent.h>
39#include <string.h>
40#include <ctype.h>
88c3281f 41#include <sched.h>
2a0609c0 42#include <time.h>
2b92865e 43#include <cpuid.h>
98481e79
LB		 44#include <linux/capability.h>
45#include <errno.h>
103a8fea 46
103a8fea 47char *proc_stat = "/proc/stat";
b7d8c148 48FILE *outf;
36229897 49int *fd_percpu;
2a0609c0 50struct timespec interval_ts = {5, 0};
d8af6f5f
LB		 51unsigned int debug;
52unsigned int rapl_joules;
53unsigned int summary_only;
54unsigned int dump_only;
103a8fea 55unsigned int do_snb_cstates;
fb5d4327 56unsigned int do_knl_cstates;
ee7e38e3
LB		 57unsigned int do_pc2;
58unsigned int do_pc3;
59unsigned int do_pc6;
60unsigned int do_pc7;
ca58710f 61unsigned int do_c8_c9_c10;
0b2bb692 62unsigned int do_skl_residency;
144b44b1
LB		 63unsigned int do_slm_cstates;
64unsigned int use_c1_residency_msr;
103a8fea 65unsigned int has_aperf;
889facbe 66unsigned int has_epb;
5a63426e
LB		 67unsigned int do_irtl_snb;
68unsigned int do_irtl_hsw;
fc04cc67 69unsigned int units = 1000000; /* MHz etc */
103a8fea
LB		 70unsigned int genuine_intel;
71unsigned int has_invariant_tsc;
d7899447 72unsigned int do_nhm_platform_info;
cf4cbe53 73unsigned int no_MSR_MISC_PWR_MGMT;
b2b34dfe 74unsigned int aperf_mperf_multiplier = 1;
103a8fea 75double bclk;
a2b7b749 76double base_hz;
21ed5574 77unsigned int has_base_hz;
a2b7b749 78double tsc_tweak = 1.0;
c98d5d94
LB		 79unsigned int show_pkg_only;
80unsigned int show_core_only;
81char *output_buffer, *outp;
889facbe
LB		 82unsigned int do_rapl;
83unsigned int do_dts;
84unsigned int do_ptm;
fdf676e5 85unsigned long long gfx_cur_rc6_ms;
27d47356 86unsigned int gfx_cur_mhz;
889facbe
LB		 87unsigned int tcc_activation_temp;
88unsigned int tcc_activation_temp_override;
40ee8e3b
AS		 89double rapl_power_units, rapl_time_units;
90double rapl_dram_energy_units, rapl_energy_units;
889facbe 91double rapl_joule_counter_range;
3a9a941d
LB		 92unsigned int do_core_perf_limit_reasons;
93unsigned int do_gfx_perf_limit_reasons;
94unsigned int do_ring_perf_limit_reasons;
8a5bdf41
LB		 95unsigned int crystal_hz;
96unsigned long long tsc_hz;
7ce7d5de 97int base_cpu;
21ed5574 98double discover_bclk(unsigned int family, unsigned int model);
7f5c258e
LB		 99unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
100 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
101unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */
102unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
103unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
104unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
889facbe 105
e6f9bb3c
LB		 106#define RAPL_PKG (1 << 0)
107 /* 0x610 MSR_PKG_POWER_LIMIT */
108 /* 0x611 MSR_PKG_ENERGY_STATUS */
109#define RAPL_PKG_PERF_STATUS (1 << 1)
110 /* 0x613 MSR_PKG_PERF_STATUS */
111#define RAPL_PKG_POWER_INFO (1 << 2)
112 /* 0x614 MSR_PKG_POWER_INFO */
113
114#define RAPL_DRAM (1 << 3)
115 /* 0x618 MSR_DRAM_POWER_LIMIT */
116 /* 0x619 MSR_DRAM_ENERGY_STATUS */
e6f9bb3c
LB		 117#define RAPL_DRAM_PERF_STATUS (1 << 4)
118 /* 0x61b MSR_DRAM_PERF_STATUS */
0b2bb692
LB		 119#define RAPL_DRAM_POWER_INFO (1 << 5)
120 /* 0x61c MSR_DRAM_POWER_INFO */
e6f9bb3c 121
9148494c 122#define RAPL_CORES_POWER_LIMIT (1 << 6)
e6f9bb3c 123 /* 0x638 MSR_PP0_POWER_LIMIT */
0b2bb692 124#define RAPL_CORE_POLICY (1 << 7)
e6f9bb3c
LB		 125 /* 0x63a MSR_PP0_POLICY */
126
0b2bb692 127#define RAPL_GFX (1 << 8)
e6f9bb3c
LB		 128 /* 0x640 MSR_PP1_POWER_LIMIT */
129 /* 0x641 MSR_PP1_ENERGY_STATUS */
130 /* 0x642 MSR_PP1_POLICY */
9148494c
JP		 131
132#define RAPL_CORES_ENERGY_STATUS (1 << 9)
133 /* 0x639 MSR_PP0_ENERGY_STATUS */
134#define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
889facbe
LB		 135#define TJMAX_DEFAULT 100
136
137#define MAX(a, b) ((a) > (b) ? (a) : (b))
103a8fea 138
388e9c81
LB		 139/*
140 * buffer size used by sscanf() for added column names
141 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
142 */
143#define NAME_BYTES 20
144
103a8fea
LB		 145int backwards_count;
146char *progname;
103a8fea 147
c98d5d94
LB		 148cpu_set_t *cpu_present_set, *cpu_affinity_set;
149size_t cpu_present_setsize, cpu_affinity_setsize;
678a3bd1 150#define MAX_ADDED_COUNTERS 16
c98d5d94
LB		 151
152struct thread_data {
153 unsigned long long tsc;
154 unsigned long long aperf;
155 unsigned long long mperf;
144b44b1 156 unsigned long long c1;
562a2d37 157 unsigned int irq_count;
1ed51011 158 unsigned int smi_count;
c98d5d94
LB		 159 unsigned int cpu_id;
160 unsigned int flags;
161#define CPU_IS_FIRST_THREAD_IN_CORE 0x2
162#define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
678a3bd1 163 unsigned long long counter[MAX_ADDED_COUNTERS];
c98d5d94
LB		 164} *thread_even, *thread_odd;
165
166struct core_data {
167 unsigned long long c3;
168 unsigned long long c6;
169 unsigned long long c7;
0539ba11 170 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */
889facbe 171 unsigned int core_temp_c;
c98d5d94 172 unsigned int core_id;
678a3bd1 173 unsigned long long counter[MAX_ADDED_COUNTERS];
c98d5d94
LB		 174} *core_even, *core_odd;
175
176struct pkg_data {
177 unsigned long long pc2;
178 unsigned long long pc3;
179 unsigned long long pc6;
180 unsigned long long pc7;
ca58710f
KCA		 181 unsigned long long pc8;
182 unsigned long long pc9;
183 unsigned long long pc10;
0b2bb692
LB		 184 unsigned long long pkg_wtd_core_c0;
185 unsigned long long pkg_any_core_c0;
186 unsigned long long pkg_any_gfxe_c0;
187 unsigned long long pkg_both_core_gfxe_c0;
9185e988 188 long long gfx_rc6_ms;
27d47356 189 unsigned int gfx_mhz;
c98d5d94 190 unsigned int package_id;
889facbe
LB		 191 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */
192 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */
193 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */
194 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */
195 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
196 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
197 unsigned int pkg_temp_c;
678a3bd1 198 unsigned long long counter[MAX_ADDED_COUNTERS];
c98d5d94
LB		 199} *package_even, *package_odd;
200
201#define ODD_COUNTERS thread_odd, core_odd, package_odd
202#define EVEN_COUNTERS thread_even, core_even, package_even
203
204#define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \
205 (thread_base + (pkg_no) * topo.num_cores_per_pkg * \
206 topo.num_threads_per_core + \
207 (core_no) * topo.num_threads_per_core + (thread_no))
208#define GET_CORE(core_base, core_no, pkg_no) \
209 (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no))
210#define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
211
388e9c81
LB		 212enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE};
213enum counter_type {COUNTER_CYCLES, COUNTER_SECONDS};
214enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT};
215
216struct msr_counter {
217 unsigned int msr_num;
218 char name[NAME_BYTES];
219 unsigned int width;
220 enum counter_type type;
221 enum counter_format format;
222 struct msr_counter *next;
812db3f7
LB		 223 unsigned int flags;
224#define FLAGS_HIDE (1 << 0)
225#define FLAGS_SHOW (1 << 1)
388e9c81
LB		 226};
227
228struct sys_counters {
678a3bd1
LB		 229 unsigned int added_thread_counters;
230 unsigned int added_core_counters;
231 unsigned int added_package_counters;
388e9c81
LB		 232 struct msr_counter *tp;
233 struct msr_counter *cp;
234 struct msr_counter *pp;
235} sys;
236
c98d5d94
LB		 237struct system_summary {
238 struct thread_data threads;
239 struct core_data cores;
240 struct pkg_data packages;
388e9c81 241} average;
c98d5d94
LB		 242
243
244struct topo_params {
245 int num_packages;
246 int num_cpus;
247 int num_cores;
248 int max_cpu_num;
249 int num_cores_per_pkg;
250 int num_threads_per_core;
251} topo;
252
253struct timeval tv_even, tv_odd, tv_delta;
254
562a2d37
LB		 255int *irq_column_2_cpu; /* /proc/interrupts column numbers */
256int *irqs_per_cpu; /* indexed by cpu_num */
257
c98d5d94
LB		 258void setup_all_buffers(void);
259
260int cpu_is_not_present(int cpu)
d15cf7c1 261{
c98d5d94 262 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
d15cf7c1 263}
88c3281f 264/*
c98d5d94
LB		 265 * run func(thread, core, package) in topology order
266 * skip non-present cpus
88c3281f 267 */
c98d5d94
LB		 268
269int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *),
270 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
88c3281f 271{
c98d5d94 272 int retval, pkg_no, core_no, thread_no;
d15cf7c1 273
c98d5d94
LB		 274 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
275 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
276 for (thread_no = 0; thread_no <
277 topo.num_threads_per_core; ++thread_no) {
278 struct thread_data *t;
279 struct core_data *c;
280 struct pkg_data *p;
88c3281f 281
c98d5d94
LB		 282 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
283
284 if (cpu_is_not_present(t->cpu_id))
285 continue;
286
287 c = GET_CORE(core_base, core_no, pkg_no);
288 p = GET_PKG(pkg_base, pkg_no);
289
290 retval = func(t, c, p);
291 if (retval)
292 return retval;
293 }
294 }
295 }
296 return 0;
88c3281f
LB		 297}
298
299int cpu_migrate(int cpu)
300{
c98d5d94
LB		 301 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
302 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
303 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
88c3281f
LB		 304 return -1;
305 else
306 return 0;
307}
36229897 308int get_msr_fd(int cpu)
103a8fea 309{
103a8fea
LB		 310 char pathname[32];
311 int fd;
312
36229897
LB		 313 fd = fd_percpu[cpu];
314
315 if (fd)
316 return fd;
317
103a8fea
LB		 318 sprintf(pathname, "/dev/cpu/%d/msr", cpu);
319 fd = open(pathname, O_RDONLY);
15aaa346 320 if (fd < 0)
98481e79 321 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
103a8fea 322
36229897
LB		 323 fd_percpu[cpu] = fd;
324
325 return fd;
326}
327
328int get_msr(int cpu, off_t offset, unsigned long long *msr)
329{
330 ssize_t retval;
331
332 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
15aaa346 333
98481e79 334 if (retval != sizeof *msr)
cf4cbe53 335 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset);
15aaa346
LB		 336
337 return 0;
103a8fea
LB		 338}
339
fc04cc67 340/*
812db3f7
LB		 341 * Each string in this array is compared in --show and --hide cmdline.
342 * Thus, strings that are proper sub-sets must follow their more specific peers.
fc04cc67 343 */
812db3f7
LB		 344struct msr_counter bic[] = {
345 { 0x0, "Package" },
346 { 0x0, "Avg_MHz" },
347 { 0x0, "Bzy_MHz" },
348 { 0x0, "TSC_MHz" },
349 { 0x0, "IRQ" },
350 { 0x0, "SMI", 32, 0, FORMAT_DELTA, NULL},
351 { 0x0, "Busy%" },
352 { 0x0, "CPU%c1" },
353 { 0x0, "CPU%c3" },
354 { 0x0, "CPU%c6" },
355 { 0x0, "CPU%c7" },
356 { 0x0, "ThreadC" },
357 { 0x0, "CoreTmp" },
358 { 0x0, "CoreCnt" },
359 { 0x0, "PkgTmp" },
360 { 0x0, "GFX%rc6" },
361 { 0x0, "GFXMHz" },
362 { 0x0, "Pkg%pc2" },
363 { 0x0, "Pkg%pc3" },
364 { 0x0, "Pkg%pc6" },
365 { 0x0, "Pkg%pc7" },
366 { 0x0, "PkgWatt" },
367 { 0x0, "CorWatt" },
368 { 0x0, "GFXWatt" },
369 { 0x0, "PkgCnt" },
370 { 0x0, "RAMWatt" },
371 { 0x0, "PKG_%" },
372 { 0x0, "RAM_%" },
373 { 0x0, "Pkg_J" },
374 { 0x0, "Cor_J" },
375 { 0x0, "GFX_J" },
376 { 0x0, "RAM_J" },
377 { 0x0, "Core" },
378 { 0x0, "CPU" },
0539ba11 379 { 0x0, "Mod%c6" },
812db3f7
LB		 380};
381
382#define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
383#define BIC_Package (1ULL << 0)
384#define BIC_Avg_MHz (1ULL << 1)
385#define BIC_Bzy_MHz (1ULL << 2)
386#define BIC_TSC_MHz (1ULL << 3)
387#define BIC_IRQ (1ULL << 4)
388#define BIC_SMI (1ULL << 5)
389#define BIC_Busy (1ULL << 6)
390#define BIC_CPU_c1 (1ULL << 7)
391#define BIC_CPU_c3 (1ULL << 8)
392#define BIC_CPU_c6 (1ULL << 9)
393#define BIC_CPU_c7 (1ULL << 10)
394#define BIC_ThreadC (1ULL << 11)
395#define BIC_CoreTmp (1ULL << 12)
396#define BIC_CoreCnt (1ULL << 13)
397#define BIC_PkgTmp (1ULL << 14)
398#define BIC_GFX_rc6 (1ULL << 15)
399#define BIC_GFXMHz (1ULL << 16)
400#define BIC_Pkgpc2 (1ULL << 17)
401#define BIC_Pkgpc3 (1ULL << 18)
402#define BIC_Pkgpc6 (1ULL << 19)
403#define BIC_Pkgpc7 (1ULL << 20)
404#define BIC_PkgWatt (1ULL << 21)
405#define BIC_CorWatt (1ULL << 22)
406#define BIC_GFXWatt (1ULL << 23)
407#define BIC_PkgCnt (1ULL << 24)
408#define BIC_RAMWatt (1ULL << 27)
409#define BIC_PKG__ (1ULL << 28)
410#define BIC_RAM__ (1ULL << 29)
411#define BIC_Pkg_J (1ULL << 30)
412#define BIC_Cor_J (1ULL << 31)
413#define BIC_GFX_J (1ULL << 30)
414#define BIC_RAM_J (1ULL << 31)
415#define BIC_Core (1ULL << 32)
416#define BIC_CPU (1ULL << 33)
0539ba11 417#define BIC_Mod_c6 (1ULL << 34)
812db3f7
LB		 418
419unsigned long long bic_enabled = 0xFFFFFFFFFFFFFFFFULL;
420unsigned long long bic_present;
421
422#define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME)
423#define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT)
424
425/*
426 * bic_lookup
427 * for all the strings in comma separate name_list,
428 * set the approprate bit in return value.
429 */
430unsigned long long bic_lookup(char *name_list)
431{
432 int i;
433 unsigned long long retval = 0;
434
435 while (name_list) {
436 char *comma;
437
438 comma = strchr(name_list, ',');
439
440 if (comma)
441 *comma = '\0';
442
443 for (i = 0; i < MAX_BIC; ++i) {
444 if (!strcmp(name_list, bic[i].name)) {
445 retval |= (1ULL << i);
446 break;
447 }
448 }
449 if (i == MAX_BIC) {
450 fprintf(stderr, "Invalid counter name: %s\n", name_list);
451 exit(-1);
452 }
453
454 name_list = comma;
455 if (name_list)
456 name_list++;
457
458 }
459 return retval;
460}
fc04cc67 461
a829eb4d 462void print_header(void)
103a8fea 463{
388e9c81
LB		 464 struct msr_counter *mp;
465
812db3f7 466 if (DO_BIC(BIC_Package))
3d109de2 467 outp += sprintf(outp, "\tPackage");
812db3f7 468 if (DO_BIC(BIC_Core))
3d109de2 469 outp += sprintf(outp, "\tCore");
812db3f7 470 if (DO_BIC(BIC_CPU))
3d109de2 471 outp += sprintf(outp, "\tCPU");
812db3f7 472 if (DO_BIC(BIC_Avg_MHz))
3d109de2 473 outp += sprintf(outp, "\tAvg_MHz");
812db3f7 474 if (DO_BIC(BIC_Busy))
3d109de2 475 outp += sprintf(outp, "\tBusy%%");
812db3f7 476 if (DO_BIC(BIC_Bzy_MHz))
3d109de2 477 outp += sprintf(outp, "\tBzy_MHz");
812db3f7
LB		 478 if (DO_BIC(BIC_TSC_MHz))
479 outp += sprintf(outp, "\tTSC_MHz");
1cc21f7b 480
1cc21f7b
LB		 481 if (!debug)
482 goto done;
483
812db3f7 484 if (DO_BIC(BIC_IRQ))
3d109de2 485 outp += sprintf(outp, "\tIRQ");
812db3f7 486 if (DO_BIC(BIC_SMI))
3d109de2 487 outp += sprintf(outp, "\tSMI");
1cc21f7b 488
812db3f7 489 if (DO_BIC(BIC_CPU_c1))
3d109de2 490 outp += sprintf(outp, "\tCPU%%c1");
889facbe 491
388e9c81
LB		 492 for (mp = sys.tp; mp; mp = mp->next) {
493 if (mp->format == FORMAT_RAW) {
494 if (mp->width == 64)
495 outp += sprintf(outp, "\t%18.18s", mp->name);
496 else
497 outp += sprintf(outp, "\t%10.10s", mp->name);
498 } else {
499 outp += sprintf(outp, "\t%-7.7s", mp->name);
500 }
501 }
502
812db3f7 503 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates)
678a3bd1 504 outp += sprintf(outp, "\tCPU%%c3");
812db3f7 505 if (DO_BIC(BIC_CPU_c6))
678a3bd1 506 outp += sprintf(outp, "\tCPU%%c6");
812db3f7 507 if (DO_BIC(BIC_CPU_c7))
678a3bd1
LB		 508 outp += sprintf(outp, "\tCPU%%c7");
509
0539ba11
LB		 510 if (DO_BIC(BIC_Mod_c6))
511 outp += sprintf(outp, "\tMod%%c6");
678a3bd1 512
812db3f7 513 if (DO_BIC(BIC_CoreTmp))
3d109de2 514 outp += sprintf(outp, "\tCoreTmp");
388e9c81
LB		 515
516 for (mp = sys.cp; mp; mp = mp->next) {
517 if (mp->format == FORMAT_RAW) {
518 if (mp->width == 64)
519 outp += sprintf(outp, "\t%18.18s", mp->name);
520 else
521 outp += sprintf(outp, "\t%10.10s", mp->name);
522 } else {
523 outp += sprintf(outp, "\t%-7.7s", mp->name);
524 }
525 }
526
812db3f7 527 if (DO_BIC(BIC_PkgTmp))
3d109de2 528 outp += sprintf(outp, "\tPkgTmp");
889facbe 529
812db3f7 530 if (DO_BIC(BIC_GFX_rc6))
3d109de2 531 outp += sprintf(outp, "\tGFX%%rc6");
fdf676e5 532
812db3f7 533 if (DO_BIC(BIC_GFXMHz))
3d109de2 534 outp += sprintf(outp, "\tGFXMHz");
27d47356 535
0b2bb692 536 if (do_skl_residency) {
3d109de2
LB		 537 outp += sprintf(outp, "\tTotl%%C0");
538 outp += sprintf(outp, "\tAny%%C0");
539 outp += sprintf(outp, "\tGFX%%C0");
540 outp += sprintf(outp, "\tCPUGFX%%");
0b2bb692
LB		 541 }
542
ee7e38e3 543 if (do_pc2)
3d109de2 544 outp += sprintf(outp, "\tPkg%%pc2");
ee7e38e3 545 if (do_pc3)
3d109de2 546 outp += sprintf(outp, "\tPkg%%pc3");
ee7e38e3 547 if (do_pc6)
3d109de2 548 outp += sprintf(outp, "\tPkg%%pc6");
ee7e38e3 549 if (do_pc7)
3d109de2 550 outp += sprintf(outp, "\tPkg%%pc7");
ca58710f 551 if (do_c8_c9_c10) {
3d109de2
LB		 552 outp += sprintf(outp, "\tPkg%%pc8");
553 outp += sprintf(outp, "\tPkg%%pc9");
554 outp += sprintf(outp, "\tPk%%pc10");
ca58710f 555 }
103a8fea 556
5c56be9a 557 if (do_rapl && !rapl_joules) {
812db3f7 558 if (DO_BIC(BIC_PkgWatt))
3d109de2 559 outp += sprintf(outp, "\tPkgWatt");
812db3f7 560 if (DO_BIC(BIC_CorWatt))
3d109de2 561 outp += sprintf(outp, "\tCorWatt");
812db3f7 562 if (DO_BIC(BIC_GFXWatt))
3d109de2 563 outp += sprintf(outp, "\tGFXWatt");
812db3f7 564 if (DO_BIC(BIC_RAMWatt))
3d109de2 565 outp += sprintf(outp, "\tRAMWatt");
812db3f7 566 if (DO_BIC(BIC_PKG__))
3d109de2 567 outp += sprintf(outp, "\tPKG_%%");
812db3f7 568 if (DO_BIC(BIC_RAM__))
3d109de2 569 outp += sprintf(outp, "\tRAM_%%");
d7899447 570 } else if (do_rapl && rapl_joules) {
812db3f7 571 if (DO_BIC(BIC_Pkg_J))
3d109de2 572 outp += sprintf(outp, "\tPkg_J");
812db3f7 573 if (DO_BIC(BIC_Cor_J))
3d109de2 574 outp += sprintf(outp, "\tCor_J");
812db3f7 575 if (DO_BIC(BIC_GFX_J))
3d109de2 576 outp += sprintf(outp, "\tGFX_J");
812db3f7 577 if (DO_BIC(BIC_RAM_J))
3d109de2 578 outp += sprintf(outp, "\tRAM_J");
812db3f7 579 if (DO_BIC(BIC_PKG__))
3d109de2 580 outp += sprintf(outp, "\tPKG_%%");
812db3f7 581 if (DO_BIC(BIC_RAM__))
3d109de2 582 outp += sprintf(outp, "\tRAM_%%");
5c56be9a 583 }
388e9c81
LB		 584 for (mp = sys.pp; mp; mp = mp->next) {
585 if (mp->format == FORMAT_RAW) {
586 if (mp->width == 64)
587 outp += sprintf(outp, "\t%18.18s", mp->name);
588 else
589 outp += sprintf(outp, "\t%10.10s", mp->name);
590 } else {
591 outp += sprintf(outp, "\t%-7.7s", mp->name);
592 }
593 }
594
595done:
c98d5d94 596 outp += sprintf(outp, "\n");
103a8fea
LB		 597}
598
c98d5d94
LB		 599int dump_counters(struct thread_data *t, struct core_data *c,
600 struct pkg_data *p)
103a8fea 601{
388e9c81
LB		 602 int i;
603 struct msr_counter *mp;
604
3b4d5c7f 605 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
c98d5d94
LB		 606
607 if (t) {
3b4d5c7f
AS		 608 outp += sprintf(outp, "CPU: %d flags 0x%x\n",
609 t->cpu_id, t->flags);
610 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
611 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
612 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
613 outp += sprintf(outp, "c1: %016llX\n", t->c1);
6886fee4 614
812db3f7 615 if (DO_BIC(BIC_IRQ))
562a2d37 616 outp += sprintf(outp, "IRQ: %08X\n", t->irq_count);
812db3f7 617 if (DO_BIC(BIC_SMI))
3b4d5c7f 618 outp += sprintf(outp, "SMI: %08X\n", t->smi_count);
388e9c81
LB		 619
620 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
621 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n",
622 i, mp->msr_num, t->counter[i]);
623 }
c98d5d94 624 }
103a8fea 625
c98d5d94 626 if (c) {
3b4d5c7f
AS		 627 outp += sprintf(outp, "core: %d\n", c->core_id);
628 outp += sprintf(outp, "c3: %016llX\n", c->c3);
629 outp += sprintf(outp, "c6: %016llX\n", c->c6);
630 outp += sprintf(outp, "c7: %016llX\n", c->c7);
631 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
388e9c81
LB		 632
633 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
634 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n",
635 i, mp->msr_num, c->counter[i]);
636 }
0539ba11 637 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us);
c98d5d94 638 }
103a8fea 639
c98d5d94 640 if (p) {
3b4d5c7f 641 outp += sprintf(outp, "package: %d\n", p->package_id);
0b2bb692
LB		 642
643 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
644 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
645 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
646 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
647
3b4d5c7f 648 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
ee7e38e3
LB		 649 if (do_pc3)
650 outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
651 if (do_pc6)
652 outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
653 if (do_pc7)
654 outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
3b4d5c7f
AS		 655 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
656 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
657 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
658 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg);
659 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores);
660 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx);
661 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram);
662 outp += sprintf(outp, "Throttle PKG: %0X\n",
663 p->rapl_pkg_perf_status);
664 outp += sprintf(outp, "Throttle RAM: %0X\n",
665 p->rapl_dram_perf_status);
666 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
388e9c81
LB		 667
668 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
669 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n",
670 i, mp->msr_num, p->counter[i]);
671 }
c98d5d94 672 }
3b4d5c7f
AS		 673
674 outp += sprintf(outp, "\n");
675
c98d5d94 676 return 0;
103a8fea
LB		 677}
678
e23da037
LB		 679/*
680 * column formatting convention & formats
e23da037 681 */
c98d5d94
LB		 682int format_counters(struct thread_data *t, struct core_data *c,
683 struct pkg_data *p)
103a8fea
LB		 684{
685 double interval_float;
fc04cc67 686 char *fmt8;
388e9c81
LB		 687 int i;
688 struct msr_counter *mp;
103a8fea 689
c98d5d94
LB		 690 /* if showing only 1st thread in core and this isn't one, bail out */
691 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
692 return 0;
693
694 /* if showing only 1st thread in pkg and this isn't one, bail out */
695 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
696 return 0;
697
103a8fea
LB		 698 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0;
699
c98d5d94
LB		 700 /* topo columns, print blanks on 1st (average) line */
701 if (t == &average.threads) {
812db3f7 702 if (DO_BIC(BIC_Package))
3d109de2 703 outp += sprintf(outp, "\t-");
812db3f7 704 if (DO_BIC(BIC_Core))
3d109de2 705 outp += sprintf(outp, "\t-");
812db3f7 706 if (DO_BIC(BIC_CPU))
3d109de2 707 outp += sprintf(outp, "\t-");
103a8fea 708 } else {
812db3f7 709 if (DO_BIC(BIC_Package)) {
c98d5d94 710 if (p)
3d109de2 711 outp += sprintf(outp, "\t%d", p->package_id);
c98d5d94 712 else
3d109de2 713 outp += sprintf(outp, "\t-");
c98d5d94 714 }
812db3f7 715 if (DO_BIC(BIC_Core)) {
c98d5d94 716 if (c)
3d109de2 717 outp += sprintf(outp, "\t%d", c->core_id);
c98d5d94 718 else
3d109de2 719 outp += sprintf(outp, "\t-");
c98d5d94 720 }
812db3f7 721 if (DO_BIC(BIC_CPU))
3d109de2 722 outp += sprintf(outp, "\t%d", t->cpu_id);
103a8fea 723 }
fc04cc67 724
812db3f7 725 if (DO_BIC(BIC_Avg_MHz))
3d109de2 726 outp += sprintf(outp, "\t%.0f",
fc04cc67
LB		 727 1.0 / units * t->aperf / interval_float);
728
812db3f7 729 if (DO_BIC(BIC_Busy))
3d109de2 730 outp += sprintf(outp, "\t%.2f", 100.0 * t->mperf/t->tsc/tsc_tweak);
103a8fea 731
812db3f7 732 if (DO_BIC(BIC_Bzy_MHz)) {
21ed5574 733 if (has_base_hz)
3d109de2 734 outp += sprintf(outp, "\t%.0f", base_hz / units * t->aperf / t->mperf);
21ed5574 735 else
3d109de2 736 outp += sprintf(outp, "\t%.0f",
21ed5574
LB		 737 1.0 * t->tsc / units * t->aperf / t->mperf / interval_float);
738 }
103a8fea 739
812db3f7
LB		 740 if (DO_BIC(BIC_TSC_MHz))
741 outp += sprintf(outp, "\t%.0f", 1.0 * t->tsc/units/interval_float);
103a8fea 742
1cc21f7b
LB		 743 if (!debug)
744 goto done;
745
562a2d37 746 /* IRQ */
812db3f7 747 if (DO_BIC(BIC_IRQ))
3d109de2 748 outp += sprintf(outp, "\t%d", t->irq_count);
562a2d37 749
1cc21f7b 750 /* SMI */
812db3f7 751 if (DO_BIC(BIC_SMI))
3d109de2 752 outp += sprintf(outp, "\t%d", t->smi_count);
1cc21f7b 753
678a3bd1 754 /* C1 */
812db3f7 755 if (DO_BIC(BIC_CPU_c1))
3d109de2 756 outp += sprintf(outp, "\t%.2f", 100.0 * t->c1/t->tsc);
c98d5d94 757
678a3bd1 758 /* Added counters */
388e9c81
LB		 759 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
760 if (mp->format == FORMAT_RAW) {
761 if (mp->width == 32)
762 outp += sprintf(outp, "\t0x%08lx", (unsigned long) t->counter[i]);
763 else
764 outp += sprintf(outp, "\t0x%016llx", t->counter[i]);
765 } else if (mp->format == FORMAT_DELTA) {
678a3bd1 766 outp += sprintf(outp, "\t%lld", t->counter[i]);
388e9c81
LB		 767 } else if (mp->format == FORMAT_PERCENT) {
768 outp += sprintf(outp, "\t%.2f", 100.0 * t->counter[i]/t->tsc);
769 }
770 }
771
678a3bd1
LB		 772 /* print per-core data only for 1st thread in core */
773 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
774 goto done;
775
812db3f7 776 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates)
678a3bd1 777 outp += sprintf(outp, "\t%.2f", 100.0 * c->c3/t->tsc);
812db3f7 778 if (DO_BIC(BIC_CPU_c6))
678a3bd1 779 outp += sprintf(outp, "\t%.2f", 100.0 * c->c6/t->tsc);
812db3f7 780 if (DO_BIC(BIC_CPU_c7))
678a3bd1
LB		 781 outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/t->tsc);
782
0539ba11
LB		 783 /* Mod%c6 */
784 if (DO_BIC(BIC_Mod_c6))
785 outp += sprintf(outp, "\t%.2f", 100.0 * c->mc6_us / t->tsc);
786
812db3f7 787 if (DO_BIC(BIC_CoreTmp))
3d109de2 788 outp += sprintf(outp, "\t%d", c->core_temp_c);
889facbe 789
388e9c81
LB		 790 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
791 if (mp->format == FORMAT_RAW) {
792 if (mp->width == 32)
793 outp += sprintf(outp, "\t0x%08lx", (unsigned long) c->counter[i]);
794 else
795 outp += sprintf(outp, "\t0x%016llx", c->counter[i]);
796 } else if (mp->format == FORMAT_DELTA) {
678a3bd1 797 outp += sprintf(outp, "\t%lld", c->counter[i]);
388e9c81
LB		 798 } else if (mp->format == FORMAT_PERCENT) {
799 outp += sprintf(outp, "\t%.2f", 100.0 * c->counter[i]/t->tsc);
800 }
801 }
802
c98d5d94
LB		 803 /* print per-package data only for 1st core in package */
804 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
805 goto done;
806
0b2bb692 807 /* PkgTmp */
812db3f7 808 if (DO_BIC(BIC_PkgTmp))
3d109de2 809 outp += sprintf(outp, "\t%d", p->pkg_temp_c);
889facbe 810
fdf676e5 811 /* GFXrc6 */
812db3f7 812 if (DO_BIC(BIC_GFX_rc6)) {
ba3dec99 813 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */
3d109de2 814 outp += sprintf(outp, "\t**.**");
9185e988 815 } else {
3d109de2 816 outp += sprintf(outp, "\t%.2f",
9185e988
LB		 817 p->gfx_rc6_ms / 10.0 / interval_float);
818 }
819 }
fdf676e5 820
27d47356 821 /* GFXMHz */
812db3f7 822 if (DO_BIC(BIC_GFXMHz))
3d109de2 823 outp += sprintf(outp, "\t%d", p->gfx_mhz);
27d47356 824
0b2bb692
LB		 825 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
826 if (do_skl_residency) {
3d109de2
LB		 827 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_wtd_core_c0/t->tsc);
828 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_core_c0/t->tsc);
829 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_gfxe_c0/t->tsc);
830 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_both_core_gfxe_c0/t->tsc);
0b2bb692
LB		 831 }
832
ee7e38e3 833 if (do_pc2)
3d109de2 834 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc2/t->tsc);
ee7e38e3 835 if (do_pc3)
3d109de2 836 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc3/t->tsc);
ee7e38e3 837 if (do_pc6)
3d109de2 838 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc6/t->tsc);
ee7e38e3 839 if (do_pc7)
3d109de2 840 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc7/t->tsc);
ca58710f 841 if (do_c8_c9_c10) {
3d109de2
LB		 842 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc8/t->tsc);
843 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc9/t->tsc);
844 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc10/t->tsc);
ca58710f 845 }
889facbe
LB		 846
847 /*
848 * If measurement interval exceeds minimum RAPL Joule Counter range,
849 * indicate that results are suspect by printing "**" in fraction place.
850 */
fc04cc67 851 if (interval_float < rapl_joule_counter_range)
3d109de2 852 fmt8 = "\t%.2f";
fc04cc67 853 else
e975db5d 854 fmt8 = "%6.0f**";
889facbe 855
812db3f7
LB		 856 if (DO_BIC(BIC_PkgWatt))
857 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float);
858 if (DO_BIC(BIC_CorWatt))
859 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float);
860 if (DO_BIC(BIC_GFXWatt))
861 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float);
862 if (DO_BIC(BIC_RAMWatt))
863 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float);
864 if (DO_BIC(BIC_Pkg_J))
865 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units);
866 if (DO_BIC(BIC_Cor_J))
867 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units);
868 if (DO_BIC(BIC_GFX_J))
869 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units);
870 if (DO_BIC(BIC_RAM_J))
871 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units);
872 if (DO_BIC(BIC_PKG__))
873 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
874 if (DO_BIC(BIC_RAM__))
875 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
876
388e9c81
LB		 877 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
878 if (mp->format == FORMAT_RAW) {
879 if (mp->width == 32)
880 outp += sprintf(outp, "\t0x%08lx", (unsigned long) p->counter[i]);
881 else
882 outp += sprintf(outp, "\t0x%016llx", p->counter[i]);
883 } else if (mp->format == FORMAT_DELTA) {
678a3bd1 884 outp += sprintf(outp, "\t%lld", p->counter[i]);
388e9c81
LB		 885 } else if (mp->format == FORMAT_PERCENT) {
886 outp += sprintf(outp, "\t%.2f", 100.0 * p->counter[i]/t->tsc);
887 }
888 }
889
c98d5d94 890done:
c98d5d94
LB		 891 outp += sprintf(outp, "\n");
892
893 return 0;
103a8fea
LB		 894}
895
b7d8c148 896void flush_output_stdout(void)
c98d5d94 897{
b7d8c148
LB		 898 FILE *filep;
899
900 if (outf == stderr)
901 filep = stdout;
902 else
903 filep = outf;
904
905 fputs(output_buffer, filep);
906 fflush(filep);
907
c98d5d94
LB		 908 outp = output_buffer;
909}
b7d8c148 910void flush_output_stderr(void)
c98d5d94 911{
b7d8c148
LB		 912 fputs(output_buffer, outf);
913 fflush(outf);
c98d5d94
LB		 914 outp = output_buffer;
915}
916void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 917{
e23da037 918 static int printed;
103a8fea 919
e23da037
LB		 920 if (!printed || !summary_only)
921 print_header();
103a8fea 922
c98d5d94
LB		 923 if (topo.num_cpus > 1)
924 format_counters(&average.threads, &average.cores,
925 &average.packages);
103a8fea 926
e23da037
LB		 927 printed = 1;
928
929 if (summary_only)
930 return;
931
c98d5d94 932 for_all_cpus(format_counters, t, c, p);
103a8fea
LB		 933}
934
889facbe
LB		 935#define DELTA_WRAP32(new, old) \
936 if (new > old) { \
937 old = new - old; \
938 } else { \
939 old = 0x100000000 + new - old; \
940 }
941
ba3dec99 942int
c98d5d94
LB		 943delta_package(struct pkg_data *new, struct pkg_data *old)
944{
388e9c81
LB		 945 int i;
946 struct msr_counter *mp;
0b2bb692
LB		 947
948 if (do_skl_residency) {
949 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
950 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
951 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
952 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
953 }
c98d5d94 954 old->pc2 = new->pc2 - old->pc2;
ee7e38e3
LB		 955 if (do_pc3)
956 old->pc3 = new->pc3 - old->pc3;
957 if (do_pc6)
958 old->pc6 = new->pc6 - old->pc6;
959 if (do_pc7)
960 old->pc7 = new->pc7 - old->pc7;
ca58710f
KCA		 961 old->pc8 = new->pc8 - old->pc8;
962 old->pc9 = new->pc9 - old->pc9;
963 old->pc10 = new->pc10 - old->pc10;
889facbe
LB		 964 old->pkg_temp_c = new->pkg_temp_c;
965
9185e988
LB		 966 /* flag an error when rc6 counter resets/wraps */
967 if (old->gfx_rc6_ms > new->gfx_rc6_ms)
968 old->gfx_rc6_ms = -1;
969 else
970 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
971
27d47356
LB		 972 old->gfx_mhz = new->gfx_mhz;
973
889facbe
LB		 974 DELTA_WRAP32(new->energy_pkg, old->energy_pkg);
975 DELTA_WRAP32(new->energy_cores, old->energy_cores);
976 DELTA_WRAP32(new->energy_gfx, old->energy_gfx);
977 DELTA_WRAP32(new->energy_dram, old->energy_dram);
978 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status);
979 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status);
ba3dec99 980
388e9c81
LB		 981 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
982 if (mp->format == FORMAT_RAW)
983 old->counter[i] = new->counter[i];
984 else
985 old->counter[i] = new->counter[i] - old->counter[i];
986 }
987
ba3dec99 988 return 0;
c98d5d94 989}
103a8fea 990
c98d5d94
LB		 991void
992delta_core(struct core_data *new, struct core_data *old)
103a8fea 993{
388e9c81
LB		 994 int i;
995 struct msr_counter *mp;
996
c98d5d94
LB		 997 old->c3 = new->c3 - old->c3;
998 old->c6 = new->c6 - old->c6;
999 old->c7 = new->c7 - old->c7;
889facbe 1000 old->core_temp_c = new->core_temp_c;
0539ba11 1001 old->mc6_us = new->mc6_us - old->mc6_us;
388e9c81
LB		 1002
1003 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1004 if (mp->format == FORMAT_RAW)
1005 old->counter[i] = new->counter[i];
1006 else
1007 old->counter[i] = new->counter[i] - old->counter[i];
1008 }
c98d5d94 1009}
103a8fea 1010
c3ae331d
LB		 1011/*
1012 * old = new - old
1013 */
ba3dec99 1014int
c98d5d94
LB		 1015delta_thread(struct thread_data *new, struct thread_data *old,
1016 struct core_data *core_delta)
1017{
388e9c81
LB		 1018 int i;
1019 struct msr_counter *mp;
1020
c98d5d94
LB		 1021 old->tsc = new->tsc - old->tsc;
1022
1023 /* check for TSC < 1 Mcycles over interval */
b2c95d90
JT		 1024 if (old->tsc < (1000 * 1000))
1025 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
1026 "You can disable all c-states by booting with \"idle=poll\"\n"
1027 "or just the deep ones with \"processor.max_cstate=1\"");
103a8fea 1028
c98d5d94 1029 old->c1 = new->c1 - old->c1;
103a8fea 1030
812db3f7 1031 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) {
a729617c
LB		 1032 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
1033 old->aperf = new->aperf - old->aperf;
1034 old->mperf = new->mperf - old->mperf;
1035 } else {
ba3dec99 1036 return -1;
103a8fea 1037 }
c98d5d94 1038 }
103a8fea 1039
103a8fea 1040
144b44b1
LB		 1041 if (use_c1_residency_msr) {
1042 /*
1043 * Some models have a dedicated C1 residency MSR,
1044 * which should be more accurate than the derivation below.
1045 */
1046 } else {
1047 /*
1048 * As counter collection is not atomic,
1049 * it is possible for mperf's non-halted cycles + idle states
1050 * to exceed TSC's all cycles: show c1 = 0% in that case.
1051 */
1052 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc)
1053 old->c1 = 0;
1054 else {
1055 /* normal case, derive c1 */
1056 old->c1 = old->tsc - old->mperf - core_delta->c3
c98d5d94 1057 - core_delta->c6 - core_delta->c7;
144b44b1 1058 }
c98d5d94 1059 }
c3ae331d 1060
c98d5d94 1061 if (old->mperf == 0) {
b7d8c148
LB		 1062 if (debug > 1)
1063 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
c98d5d94 1064 old->mperf = 1; /* divide by 0 protection */
103a8fea 1065 }
c98d5d94 1066
812db3f7 1067 if (DO_BIC(BIC_IRQ))
562a2d37
LB		 1068 old->irq_count = new->irq_count - old->irq_count;
1069
812db3f7 1070 if (DO_BIC(BIC_SMI))
1ed51011 1071 old->smi_count = new->smi_count - old->smi_count;
ba3dec99 1072
388e9c81
LB		 1073 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1074 if (mp->format == FORMAT_RAW)
1075 old->counter[i] = new->counter[i];
1076 else
1077 old->counter[i] = new->counter[i] - old->counter[i];
1078 }
ba3dec99 1079 return 0;
c98d5d94
LB		 1080}
1081
1082int delta_cpu(struct thread_data *t, struct core_data *c,
1083 struct pkg_data *p, struct thread_data *t2,
1084 struct core_data *c2, struct pkg_data *p2)
1085{
ba3dec99
LB		 1086 int retval = 0;
1087
c98d5d94
LB		 1088 /* calculate core delta only for 1st thread in core */
1089 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE)
1090 delta_core(c, c2);
1091
1092 /* always calculate thread delta */
ba3dec99
LB		 1093 retval = delta_thread(t, t2, c2); /* c2 is core delta */
1094 if (retval)
1095 return retval;
c98d5d94
LB		 1096
1097 /* calculate package delta only for 1st core in package */
1098 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)
ba3dec99 1099 retval = delta_package(p, p2);
c98d5d94 1100
ba3dec99 1101 return retval;
103a8fea
LB		 1102}
1103
c98d5d94
LB		 1104void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1105{
388e9c81
LB		 1106 int i;
1107 struct msr_counter *mp;
1108
c98d5d94
LB		 1109 t->tsc = 0;
1110 t->aperf = 0;
1111 t->mperf = 0;
1112 t->c1 = 0;
1113
562a2d37
LB		 1114 t->irq_count = 0;
1115 t->smi_count = 0;
1116
c98d5d94
LB		 1117 /* tells format_counters to dump all fields from this set */
1118 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE;
1119
1120 c->c3 = 0;
1121 c->c6 = 0;
1122 c->c7 = 0;
0539ba11 1123 c->mc6_us = 0;
889facbe 1124 c->core_temp_c = 0;
c98d5d94 1125
0b2bb692
LB		 1126 p->pkg_wtd_core_c0 = 0;
1127 p->pkg_any_core_c0 = 0;
1128 p->pkg_any_gfxe_c0 = 0;
1129 p->pkg_both_core_gfxe_c0 = 0;
1130
c98d5d94 1131 p->pc2 = 0;
ee7e38e3
LB		 1132 if (do_pc3)
1133 p->pc3 = 0;
1134 if (do_pc6)
1135 p->pc6 = 0;
1136 if (do_pc7)
1137 p->pc7 = 0;
ca58710f
KCA		 1138 p->pc8 = 0;
1139 p->pc9 = 0;
1140 p->pc10 = 0;
889facbe
LB		 1141
1142 p->energy_pkg = 0;
1143 p->energy_dram = 0;
1144 p->energy_cores = 0;
1145 p->energy_gfx = 0;
1146 p->rapl_pkg_perf_status = 0;
1147 p->rapl_dram_perf_status = 0;
1148 p->pkg_temp_c = 0;
27d47356 1149
fdf676e5 1150 p->gfx_rc6_ms = 0;
27d47356 1151 p->gfx_mhz = 0;
388e9c81
LB		 1152 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next)
1153 t->counter[i] = 0;
1154
1155 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next)
1156 c->counter[i] = 0;
1157
1158 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next)
1159 p->counter[i] = 0;
c98d5d94
LB		 1160}
1161int sum_counters(struct thread_data *t, struct core_data *c,
1162 struct pkg_data *p)
103a8fea 1163{
388e9c81
LB		 1164 int i;
1165 struct msr_counter *mp;
1166
c98d5d94
LB		 1167 average.threads.tsc += t->tsc;
1168 average.threads.aperf += t->aperf;
1169 average.threads.mperf += t->mperf;
1170 average.threads.c1 += t->c1;
103a8fea 1171
562a2d37
LB		 1172 average.threads.irq_count += t->irq_count;
1173 average.threads.smi_count += t->smi_count;
1174
388e9c81
LB		 1175 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1176 if (mp->format == FORMAT_RAW)
1177 continue;
1178 average.threads.counter[i] += t->counter[i];
1179 }
1180
c98d5d94
LB		 1181 /* sum per-core values only for 1st thread in core */
1182 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1183 return 0;
103a8fea 1184
c98d5d94
LB		 1185 average.cores.c3 += c->c3;
1186 average.cores.c6 += c->c6;
1187 average.cores.c7 += c->c7;
0539ba11 1188 average.cores.mc6_us += c->mc6_us;
c98d5d94 1189
889facbe
LB		 1190 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
1191
388e9c81
LB		 1192 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1193 if (mp->format == FORMAT_RAW)
1194 continue;
1195 average.cores.counter[i] += c->counter[i];
1196 }
1197
c98d5d94
LB		 1198 /* sum per-pkg values only for 1st core in pkg */
1199 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1200 return 0;
1201
0b2bb692
LB		 1202 if (do_skl_residency) {
1203 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
1204 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
1205 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
1206 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
1207 }
1208
c98d5d94 1209 average.packages.pc2 += p->pc2;
ee7e38e3
LB		 1210 if (do_pc3)
1211 average.packages.pc3 += p->pc3;
1212 if (do_pc6)
1213 average.packages.pc6 += p->pc6;
1214 if (do_pc7)
1215 average.packages.pc7 += p->pc7;
ca58710f
KCA		 1216 average.packages.pc8 += p->pc8;
1217 average.packages.pc9 += p->pc9;
1218 average.packages.pc10 += p->pc10;
c98d5d94 1219
889facbe
LB		 1220 average.packages.energy_pkg += p->energy_pkg;
1221 average.packages.energy_dram += p->energy_dram;
1222 average.packages.energy_cores += p->energy_cores;
1223 average.packages.energy_gfx += p->energy_gfx;
1224
fdf676e5 1225 average.packages.gfx_rc6_ms = p->gfx_rc6_ms;
27d47356
LB		 1226 average.packages.gfx_mhz = p->gfx_mhz;
1227
889facbe
LB		 1228 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
1229
1230 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
1231 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
388e9c81
LB		 1232
1233 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1234 if (mp->format == FORMAT_RAW)
1235 continue;
1236 average.packages.counter[i] += p->counter[i];
1237 }
c98d5d94
LB		 1238 return 0;
1239}
1240/*
1241 * sum the counters for all cpus in the system
1242 * compute the weighted average
1243 */
1244void compute_average(struct thread_data *t, struct core_data *c,
1245 struct pkg_data *p)
1246{
388e9c81
LB		 1247 int i;
1248 struct msr_counter *mp;
1249
c98d5d94
LB		 1250 clear_counters(&average.threads, &average.cores, &average.packages);
1251
1252 for_all_cpus(sum_counters, t, c, p);
1253
1254 average.threads.tsc /= topo.num_cpus;
1255 average.threads.aperf /= topo.num_cpus;
1256 average.threads.mperf /= topo.num_cpus;
1257 average.threads.c1 /= topo.num_cpus;
1258
1259 average.cores.c3 /= topo.num_cores;
1260 average.cores.c6 /= topo.num_cores;
1261 average.cores.c7 /= topo.num_cores;
0539ba11 1262 average.cores.mc6_us /= topo.num_cores;
c98d5d94 1263
0b2bb692
LB		 1264 if (do_skl_residency) {
1265 average.packages.pkg_wtd_core_c0 /= topo.num_packages;
1266 average.packages.pkg_any_core_c0 /= topo.num_packages;
1267 average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
1268 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
1269 }
1270
c98d5d94 1271 average.packages.pc2 /= topo.num_packages;
ee7e38e3
LB		 1272 if (do_pc3)
1273 average.packages.pc3 /= topo.num_packages;
1274 if (do_pc6)
1275 average.packages.pc6 /= topo.num_packages;
1276 if (do_pc7)
1277 average.packages.pc7 /= topo.num_packages;
ca58710f
KCA		 1278
1279 average.packages.pc8 /= topo.num_packages;
1280 average.packages.pc9 /= topo.num_packages;
1281 average.packages.pc10 /= topo.num_packages;
388e9c81
LB		 1282
1283 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1284 if (mp->format == FORMAT_RAW)
1285 continue;
1286 average.threads.counter[i] /= topo.num_cpus;
1287 }
1288 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1289 if (mp->format == FORMAT_RAW)
1290 continue;
1291 average.cores.counter[i] /= topo.num_cores;
1292 }
1293 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1294 if (mp->format == FORMAT_RAW)
1295 continue;
1296 average.packages.counter[i] /= topo.num_packages;
1297 }
103a8fea
LB		 1298}
1299
c98d5d94 1300static unsigned long long rdtsc(void)
103a8fea 1301{
c98d5d94 1302 unsigned int low, high;
15aaa346 1303
c98d5d94 1304 asm volatile("rdtsc" : "=a" (low), "=d" (high));
15aaa346 1305
c98d5d94
LB		 1306 return low | ((unsigned long long)high) << 32;
1307}
15aaa346 1308
c98d5d94
LB		 1309/*
1310 * get_counters(...)
1311 * migrate to cpu
1312 * acquire and record local counters for that cpu
1313 */
1314int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1315{
1316 int cpu = t->cpu_id;
889facbe 1317 unsigned long long msr;
0102b067 1318 int aperf_mperf_retry_count = 0;
388e9c81
LB		 1319 struct msr_counter *mp;
1320 int i;
88c3281f 1321
e52966c0 1322 if (cpu_migrate(cpu)) {
b7d8c148 1323 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
c98d5d94 1324 return -1;
e52966c0 1325 }
15aaa346 1326
0102b067 1327retry:
c98d5d94
LB		 1328 t->tsc = rdtsc(); /* we are running on local CPU of interest */
1329
812db3f7 1330 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) {
0102b067
LB		 1331 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time;
1332
1333 /*
1334 * The TSC, APERF and MPERF must be read together for
1335 * APERF/MPERF and MPERF/TSC to give accurate results.
1336 *
1337 * Unfortunately, APERF and MPERF are read by
1338 * individual system call, so delays may occur
1339 * between them. If the time to read them
1340 * varies by a large amount, we re-read them.
1341 */
1342
1343 /*
1344 * This initial dummy APERF read has been seen to
1345 * reduce jitter in the subsequent reads.
1346 */
1347
1348 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
1349 return -3;
1350
1351 t->tsc = rdtsc(); /* re-read close to APERF */
1352
1353 tsc_before = t->tsc;
1354
9c63a650 1355 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
c98d5d94 1356 return -3;
0102b067
LB		 1357
1358 tsc_between = rdtsc();
1359
9c63a650 1360 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
c98d5d94 1361 return -4;
0102b067
LB		 1362
1363 tsc_after = rdtsc();
1364
1365 aperf_time = tsc_between - tsc_before;
1366 mperf_time = tsc_after - tsc_between;
1367
1368 /*
1369 * If the system call latency to read APERF and MPERF
1370 * differ by more than 2x, then try again.
1371 */
1372 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) {
1373 aperf_mperf_retry_count++;
1374 if (aperf_mperf_retry_count < 5)
1375 goto retry;
1376 else
1377 warnx("cpu%d jitter %lld %lld",
1378 cpu, aperf_time, mperf_time);
1379 }
1380 aperf_mperf_retry_count = 0;
1381
b2b34dfe
HC		 1382 t->aperf = t->aperf * aperf_mperf_multiplier;
1383 t->mperf = t->mperf * aperf_mperf_multiplier;
c98d5d94
LB		 1384 }
1385
812db3f7 1386 if (DO_BIC(BIC_IRQ))
562a2d37 1387 t->irq_count = irqs_per_cpu[cpu];
812db3f7 1388 if (DO_BIC(BIC_SMI)) {
1ed51011
LB		 1389 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
1390 return -5;
1391 t->smi_count = msr & 0xFFFFFFFF;
1392 }
0539ba11 1393 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) {
144b44b1
LB		 1394 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
1395 return -6;
1396 }
1397
388e9c81
LB		 1398 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1399 if (get_msr(cpu, mp->msr_num, &t->counter[i]))
1400 return -10;
1401 }
1402
1403
c98d5d94
LB		 1404 /* collect core counters only for 1st thread in core */
1405 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1406 return 0;
1407
812db3f7 1408 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) {
c98d5d94
LB		 1409 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
1410 return -6;
144b44b1
LB		 1411 }
1412
812db3f7 1413 if (DO_BIC(BIC_CPU_c6) && !do_knl_cstates) {
c98d5d94
LB		 1414 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
1415 return -7;
fb5d4327
DC		 1416 } else if (do_knl_cstates) {
1417 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
1418 return -7;
c98d5d94
LB		 1419 }
1420
812db3f7 1421 if (DO_BIC(BIC_CPU_c7))
c98d5d94
LB		 1422 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
1423 return -8;
1424
0539ba11
LB		 1425 if (DO_BIC(BIC_Mod_c6))
1426 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
1427 return -8;
1428
812db3f7 1429 if (DO_BIC(BIC_CoreTmp)) {
889facbe
LB		 1430 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
1431 return -9;
1432 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1433 }
1434
388e9c81
LB		 1435 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1436 if (get_msr(cpu, mp->msr_num, &c->counter[i]))
1437 return -10;
1438 }
889facbe 1439
c98d5d94
LB		 1440 /* collect package counters only for 1st core in package */
1441 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1442 return 0;
1443
0b2bb692
LB		 1444 if (do_skl_residency) {
1445 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
1446 return -10;
1447 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
1448 return -11;
1449 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
1450 return -12;
1451 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
1452 return -13;
1453 }
ee7e38e3 1454 if (do_pc3)
c98d5d94
LB		 1455 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
1456 return -9;
0539ba11
LB		 1457 if (do_pc6) {
1458 if (do_slm_cstates) {
1459 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6))
1460 return -10;
1461 } else {
1462 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
1463 return -10;
1464 }
1465 }
1466
ee7e38e3 1467 if (do_pc2)
c98d5d94
LB		 1468 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
1469 return -11;
ee7e38e3 1470 if (do_pc7)
c98d5d94
LB		 1471 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
1472 return -12;
ca58710f
KCA		 1473 if (do_c8_c9_c10) {
1474 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
1475 return -13;
1476 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
1477 return -13;
1478 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
1479 return -13;
1480 }
889facbe
LB		 1481 if (do_rapl & RAPL_PKG) {
1482 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr))
1483 return -13;
1484 p->energy_pkg = msr & 0xFFFFFFFF;
1485 }
9148494c 1486 if (do_rapl & RAPL_CORES_ENERGY_STATUS) {
889facbe
LB		 1487 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr))
1488 return -14;
1489 p->energy_cores = msr & 0xFFFFFFFF;
1490 }
1491 if (do_rapl & RAPL_DRAM) {
1492 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
1493 return -15;
1494 p->energy_dram = msr & 0xFFFFFFFF;
1495 }
1496 if (do_rapl & RAPL_GFX) {
1497 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr))
1498 return -16;
1499 p->energy_gfx = msr & 0xFFFFFFFF;
1500 }
1501 if (do_rapl & RAPL_PKG_PERF_STATUS) {
1502 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr))
1503 return -16;
1504 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF;
1505 }
1506 if (do_rapl & RAPL_DRAM_PERF_STATUS) {
1507 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr))
1508 return -16;
1509 p->rapl_dram_perf_status = msr & 0xFFFFFFFF;
1510 }
812db3f7 1511 if (DO_BIC(BIC_PkgTmp)) {
889facbe
LB		 1512 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
1513 return -17;
1514 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1515 }
fdf676e5 1516
812db3f7 1517 if (DO_BIC(BIC_GFX_rc6))
fdf676e5
LB		 1518 p->gfx_rc6_ms = gfx_cur_rc6_ms;
1519
812db3f7 1520 if (DO_BIC(BIC_GFXMHz))
27d47356
LB		 1521 p->gfx_mhz = gfx_cur_mhz;
1522
388e9c81
LB		 1523 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1524 if (get_msr(cpu, mp->msr_num, &p->counter[i]))
1525 return -10;
1526 }
1527
15aaa346 1528 return 0;
103a8fea
LB		 1529}
1530
ee7e38e3
LB		 1531/*
1532 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
1533 * If you change the values, note they are used both in comparisons
1534 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
1535 */
1536
1537#define PCLUKN 0 /* Unknown */
1538#define PCLRSV 1 /* Reserved */
1539#define PCL__0 2 /* PC0 */
1540#define PCL__1 3 /* PC1 */
1541#define PCL__2 4 /* PC2 */
1542#define PCL__3 5 /* PC3 */
1543#define PCL__4 6 /* PC4 */
1544#define PCL__6 7 /* PC6 */
1545#define PCL_6N 8 /* PC6 No Retention */
1546#define PCL_6R 9 /* PC6 Retention */
1547#define PCL__7 10 /* PC7 */
1548#define PCL_7S 11 /* PC7 Shrink */
0b2bb692
LB		 1549#define PCL__8 12 /* PC8 */
1550#define PCL__9 13 /* PC9 */
1551#define PCLUNL 14 /* Unlimited */
ee7e38e3
LB		 1552
1553int pkg_cstate_limit = PCLUKN;
1554char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
0b2bb692 1555 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"};
ee7e38e3 1556
e9257f5f
LB		 1557int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1558int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1559int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
0539ba11 1560int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7};
f2642888 1561int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
e9257f5f 1562int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
e4085d54 1563int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
d8ebb442 1564int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
ee7e38e3 1565
a2b7b749
LB		 1566
1567static void
1568calculate_tsc_tweak()
1569{
a2b7b749
LB		 1570 tsc_tweak = base_hz / tsc_hz;
1571}
1572
fcd17211
LB		 1573static void
1574dump_nhm_platform_info(void)
103a8fea
LB		 1575{
1576 unsigned long long msr;
1577 unsigned int ratio;
1578
ec0adc53 1579 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
103a8fea 1580
b7d8c148 1581 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
6574a5d5 1582
103a8fea 1583 ratio = (msr >> 40) & 0xFF;
710f273b 1584 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n",
103a8fea
LB		 1585 ratio, bclk, ratio * bclk);
1586
1587 ratio = (msr >> 8) & 0xFF;
710f273b 1588 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n",
103a8fea
LB		 1589 ratio, bclk, ratio * bclk);
1590
7ce7d5de 1591 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
b7d8c148 1592 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
bfae2052 1593 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
67920418 1594
fcd17211
LB		 1595 return;
1596}
1597
1598static void
1599dump_hsw_turbo_ratio_limits(void)
1600{
1601 unsigned long long msr;
1602 unsigned int ratio;
1603
7ce7d5de 1604 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
fcd17211 1605
b7d8c148 1606 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
fcd17211
LB		 1607
1608 ratio = (msr >> 8) & 0xFF;
1609 if (ratio)
710f273b 1610 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n",
fcd17211
LB		 1611 ratio, bclk, ratio * bclk);
1612
1613 ratio = (msr >> 0) & 0xFF;
1614 if (ratio)
710f273b 1615 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n",
fcd17211
LB		 1616 ratio, bclk, ratio * bclk);
1617 return;
1618}
1619
1620static void
1621dump_ivt_turbo_ratio_limits(void)
1622{
1623 unsigned long long msr;
1624 unsigned int ratio;
6574a5d5 1625
7ce7d5de 1626 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
6574a5d5 1627
b7d8c148 1628 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
6574a5d5
LB		 1629
1630 ratio = (msr >> 56) & 0xFF;
1631 if (ratio)
710f273b 1632 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n",
6574a5d5
LB		 1633 ratio, bclk, ratio * bclk);
1634
1635 ratio = (msr >> 48) & 0xFF;
1636 if (ratio)
710f273b 1637 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n",
6574a5d5
LB		 1638 ratio, bclk, ratio * bclk);
1639
1640 ratio = (msr >> 40) & 0xFF;
1641 if (ratio)
710f273b 1642 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n",
6574a5d5
LB		 1643 ratio, bclk, ratio * bclk);
1644
1645 ratio = (msr >> 32) & 0xFF;
1646 if (ratio)
710f273b 1647 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n",
6574a5d5
LB		 1648 ratio, bclk, ratio * bclk);
1649
1650 ratio = (msr >> 24) & 0xFF;
1651 if (ratio)
710f273b 1652 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n",
6574a5d5
LB		 1653 ratio, bclk, ratio * bclk);
1654
1655 ratio = (msr >> 16) & 0xFF;
1656 if (ratio)
710f273b 1657 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n",
6574a5d5
LB		 1658 ratio, bclk, ratio * bclk);
1659
1660 ratio = (msr >> 8) & 0xFF;
1661 if (ratio)
710f273b 1662 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n",
6574a5d5
LB		 1663 ratio, bclk, ratio * bclk);
1664
1665 ratio = (msr >> 0) & 0xFF;
1666 if (ratio)
710f273b 1667 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n",
6574a5d5 1668 ratio, bclk, ratio * bclk);
fcd17211
LB		 1669 return;
1670}
6574a5d5 1671
fcd17211
LB		 1672static void
1673dump_nhm_turbo_ratio_limits(void)
1674{
1675 unsigned long long msr;
1676 unsigned int ratio;
103a8fea 1677
7ce7d5de 1678 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
103a8fea 1679
b7d8c148 1680 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
6574a5d5
LB		 1681
1682 ratio = (msr >> 56) & 0xFF;
1683 if (ratio)
710f273b 1684 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 8 active cores\n",
6574a5d5
LB		 1685 ratio, bclk, ratio * bclk);
1686
1687 ratio = (msr >> 48) & 0xFF;
1688 if (ratio)
710f273b 1689 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 7 active cores\n",
6574a5d5
LB		 1690 ratio, bclk, ratio * bclk);
1691
1692 ratio = (msr >> 40) & 0xFF;
1693 if (ratio)
710f273b 1694 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 6 active cores\n",
6574a5d5
LB		 1695 ratio, bclk, ratio * bclk);
1696
1697 ratio = (msr >> 32) & 0xFF;
1698 if (ratio)
710f273b 1699 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 5 active cores\n",
6574a5d5
LB		 1700 ratio, bclk, ratio * bclk);
1701
103a8fea
LB		 1702 ratio = (msr >> 24) & 0xFF;
1703 if (ratio)
710f273b 1704 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n",
103a8fea
LB		 1705 ratio, bclk, ratio * bclk);
1706
1707 ratio = (msr >> 16) & 0xFF;
1708 if (ratio)
710f273b 1709 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n",
103a8fea
LB		 1710 ratio, bclk, ratio * bclk);
1711
1712 ratio = (msr >> 8) & 0xFF;
1713 if (ratio)
710f273b 1714 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n",
103a8fea
LB		 1715 ratio, bclk, ratio * bclk);
1716
1717 ratio = (msr >> 0) & 0xFF;
1718 if (ratio)
710f273b 1719 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active cores\n",
103a8fea 1720 ratio, bclk, ratio * bclk);
fcd17211
LB		 1721 return;
1722}
3a9a941d 1723
fb5d4327
DC		 1724static void
1725dump_knl_turbo_ratio_limits(void)
1726{
cbf97aba
HC		 1727 const unsigned int buckets_no = 7;
1728
fb5d4327 1729 unsigned long long msr;
cbf97aba
HC		 1730 int delta_cores, delta_ratio;
1731 int i, b_nr;
1732 unsigned int cores[buckets_no];
1733 unsigned int ratio[buckets_no];
fb5d4327 1734
ebf5926a 1735 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
fb5d4327 1736
b7d8c148 1737 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n",
bfae2052 1738 base_cpu, msr);
fb5d4327
DC		 1739
1740 /**
1741 * Turbo encoding in KNL is as follows:
cbf97aba
HC		 1742 * [0] -- Reserved
1743 * [7:1] -- Base value of number of active cores of bucket 1.
fb5d4327
DC		 1744 * [15:8] -- Base value of freq ratio of bucket 1.
1745 * [20:16] -- +ve delta of number of active cores of bucket 2.
1746 * i.e. active cores of bucket 2 =
1747 * active cores of bucket 1 + delta
1748 * [23:21] -- Negative delta of freq ratio of bucket 2.
1749 * i.e. freq ratio of bucket 2 =
1750 * freq ratio of bucket 1 - delta
1751 * [28:24]-- +ve delta of number of active cores of bucket 3.
1752 * [31:29]-- -ve delta of freq ratio of bucket 3.
1753 * [36:32]-- +ve delta of number of active cores of bucket 4.
1754 * [39:37]-- -ve delta of freq ratio of bucket 4.
1755 * [44:40]-- +ve delta of number of active cores of bucket 5.
1756 * [47:45]-- -ve delta of freq ratio of bucket 5.
1757 * [52:48]-- +ve delta of number of active cores of bucket 6.
1758 * [55:53]-- -ve delta of freq ratio of bucket 6.
1759 * [60:56]-- +ve delta of number of active cores of bucket 7.
1760 * [63:61]-- -ve delta of freq ratio of bucket 7.
1761 */
cbf97aba
HC		 1762
1763 b_nr = 0;
1764 cores[b_nr] = (msr & 0xFF) >> 1;
1765 ratio[b_nr] = (msr >> 8) & 0xFF;
1766
1767 for (i = 16; i < 64; i += 8) {
fb5d4327 1768 delta_cores = (msr >> i) & 0x1F;
cbf97aba
HC		 1769 delta_ratio = (msr >> (i + 5)) & 0x7;
1770
1771 cores[b_nr + 1] = cores[b_nr] + delta_cores;
1772 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
1773 b_nr++;
fb5d4327 1774 }
cbf97aba
HC		 1775
1776 for (i = buckets_no - 1; i >= 0; i--)
1777 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
b7d8c148 1778 fprintf(outf,
710f273b 1779 "%d * %.1f = %.1f MHz max turbo %d active cores\n",
cbf97aba 1780 ratio[i], bclk, ratio[i] * bclk, cores[i]);
fb5d4327
DC		 1781}
1782
fcd17211
LB		 1783static void
1784dump_nhm_cst_cfg(void)
1785{
1786 unsigned long long msr;
1787
1df2e55a 1788 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
fcd17211
LB		 1789
1790#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
1791#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
1792
1df2e55a 1793 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr);
fcd17211 1794
b7d8c148 1795 fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n",
fcd17211
LB		 1796 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
1797 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
1798 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
1799 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
1800 (msr & (1 << 15)) ? "" : "UN",
6c34f160 1801 (unsigned int)msr & 0xF,
fcd17211
LB		 1802 pkg_cstate_limit_strings[pkg_cstate_limit]);
1803 return;
103a8fea
LB		 1804}
1805
6fb3143b
LB		 1806static void
1807dump_config_tdp(void)
1808{
1809 unsigned long long msr;
1810
1811 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
b7d8c148 1812 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
685b535b 1813 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF);
6fb3143b
LB		 1814
1815 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
b7d8c148 1816 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
6fb3143b 1817 if (msr) {
685b535b
CY		 1818 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
1819 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
1820 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
1821 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF);
6fb3143b 1822 }
b7d8c148 1823 fprintf(outf, ")\n");
6fb3143b
LB		 1824
1825 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
b7d8c148 1826 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
6fb3143b 1827 if (msr) {
685b535b
CY		 1828 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
1829 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
1830 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
1831 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF);
6fb3143b 1832 }
b7d8c148 1833 fprintf(outf, ")\n");
6fb3143b
LB		 1834
1835 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
b7d8c148 1836 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
6fb3143b 1837 if ((msr) & 0x3)
b7d8c148
LB		 1838 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
1839 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
1840 fprintf(outf, ")\n");
36229897 1841
6fb3143b 1842 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
b7d8c148 1843 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
685b535b 1844 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF);
b7d8c148
LB		 1845 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
1846 fprintf(outf, ")\n");
6fb3143b 1847}
5a63426e
LB		 1848
1849unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
1850
1851void print_irtl(void)
1852{
1853 unsigned long long msr;
1854
1855 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
1856 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr);
1857 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1858 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1859
1860 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
1861 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr);
1862 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1863 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1864
1865 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
1866 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr);
1867 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1868 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1869
1870 if (!do_irtl_hsw)
1871 return;
1872
1873 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
1874 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr);
1875 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1876 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1877
1878 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
1879 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr);
1880 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1881 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1882
1883 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
1884 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr);
1885 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1886 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1887
1888}
36229897
LB		 1889void free_fd_percpu(void)
1890{
1891 int i;
1892
01a67adf 1893 for (i = 0; i < topo.max_cpu_num + 1; ++i) {
36229897
LB		 1894 if (fd_percpu[i] != 0)
1895 close(fd_percpu[i]);
1896 }
1897
1898 free(fd_percpu);
6fb3143b
LB		 1899}
1900
c98d5d94 1901void free_all_buffers(void)
103a8fea 1902{
c98d5d94
LB		 1903 CPU_FREE(cpu_present_set);
1904 cpu_present_set = NULL;
36229897 1905 cpu_present_setsize = 0;
103a8fea 1906
c98d5d94
LB		 1907 CPU_FREE(cpu_affinity_set);
1908 cpu_affinity_set = NULL;
1909 cpu_affinity_setsize = 0;
103a8fea 1910
c98d5d94
LB		 1911 free(thread_even);
1912 free(core_even);
1913 free(package_even);
103a8fea 1914
c98d5d94
LB		 1915 thread_even = NULL;
1916 core_even = NULL;
1917 package_even = NULL;
103a8fea 1918
c98d5d94
LB		 1919 free(thread_odd);
1920 free(core_odd);
1921 free(package_odd);
103a8fea 1922
c98d5d94
LB		 1923 thread_odd = NULL;
1924 core_odd = NULL;
1925 package_odd = NULL;
103a8fea 1926
c98d5d94
LB		 1927 free(output_buffer);
1928 output_buffer = NULL;
1929 outp = NULL;
36229897
LB		 1930
1931 free_fd_percpu();
562a2d37
LB		 1932
1933 free(irq_column_2_cpu);
1934 free(irqs_per_cpu);
103a8fea
LB		 1935}
1936
57a42a34
JT		 1937/*
1938 * Open a file, and exit on failure
1939 */
1940FILE *fopen_or_die(const char *path, const char *mode)
1941{
b7d8c148 1942 FILE *filep = fopen(path, mode);
b2c95d90
JT		 1943 if (!filep)
1944 err(1, "%s: open failed", path);
57a42a34
JT		 1945 return filep;
1946}
1947
c98d5d94 1948/*
95aebc44 1949 * Parse a file containing a single int.
c98d5d94 1950 */
95aebc44 1951int parse_int_file(const char *fmt, ...)
103a8fea 1952{
95aebc44
JT		 1953 va_list args;
1954 char path[PATH_MAX];
c98d5d94 1955 FILE *filep;
95aebc44 1956 int value;
103a8fea 1957
95aebc44
JT		 1958 va_start(args, fmt);
1959 vsnprintf(path, sizeof(path), fmt, args);
1960 va_end(args);
57a42a34 1961 filep = fopen_or_die(path, "r");
b2c95d90
JT		 1962 if (fscanf(filep, "%d", &value) != 1)
1963 err(1, "%s: failed to parse number from file", path);
c98d5d94 1964 fclose(filep);
95aebc44
JT		 1965 return value;
1966}
1967
1968/*
e275b388
DC		 1969 * get_cpu_position_in_core(cpu)
1970 * return the position of the CPU among its HT siblings in the core
1971 * return -1 if the sibling is not in list
95aebc44 1972 */
e275b388 1973int get_cpu_position_in_core(int cpu)
95aebc44 1974{
e275b388
DC		 1975 char path[64];
1976 FILE *filep;
1977 int this_cpu;
1978 char character;
1979 int i;
1980
1981 sprintf(path,
1982 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list",
1983 cpu);
1984 filep = fopen(path, "r");
1985 if (filep == NULL) {
1986 perror(path);
1987 exit(1);
1988 }
1989
1990 for (i = 0; i < topo.num_threads_per_core; i++) {
1991 fscanf(filep, "%d", &this_cpu);
1992 if (this_cpu == cpu) {
1993 fclose(filep);
1994 return i;
1995 }
1996
1997 /* Account for no separator after last thread*/
1998 if (i != (topo.num_threads_per_core - 1))
1999 fscanf(filep, "%c", &character);
2000 }
2001
2002 fclose(filep);
2003 return -1;
103a8fea
LB		 2004}
2005
c98d5d94
LB		 2006/*
2007 * cpu_is_first_core_in_package(cpu)
2008 * return 1 if given CPU is 1st core in package
2009 */
2010int cpu_is_first_core_in_package(int cpu)
103a8fea 2011{
95aebc44 2012 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
103a8fea
LB		 2013}
2014
2015int get_physical_package_id(int cpu)
2016{
95aebc44 2017 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
103a8fea
LB		 2018}
2019
2020int get_core_id(int cpu)
2021{
95aebc44 2022 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
103a8fea
LB		 2023}
2024
c98d5d94
LB		 2025int get_num_ht_siblings(int cpu)
2026{
2027 char path[80];
2028 FILE *filep;
e275b388
DC		 2029 int sib1;
2030 int matches = 0;
c98d5d94 2031 char character;
e275b388
DC		 2032 char str[100];
2033 char *ch;
c98d5d94
LB		 2034
2035 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu);
57a42a34 2036 filep = fopen_or_die(path, "r");
e275b388 2037
c98d5d94
LB		 2038 /*
2039 * file format:
e275b388
DC		 2040 * A ',' separated or '-' separated set of numbers
2041 * (eg 1-2 or 1,3,4,5)
c98d5d94 2042 */
e275b388
DC		 2043 fscanf(filep, "%d%c\n", &sib1, &character);
2044 fseek(filep, 0, SEEK_SET);
2045 fgets(str, 100, filep);
2046 ch = strchr(str, character);
2047 while (ch != NULL) {
2048 matches++;
2049 ch = strchr(ch+1, character);
2050 }
c98d5d94
LB		 2051
2052 fclose(filep);
e275b388 2053 return matches+1;
c98d5d94
LB		 2054}
2055
103a8fea 2056/*
c98d5d94
LB		 2057 * run func(thread, core, package) in topology order
2058 * skip non-present cpus
103a8fea
LB		 2059 */
2060
c98d5d94
LB		 2061int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *,
2062 struct pkg_data *, struct thread_data *, struct core_data *,
2063 struct pkg_data *), struct thread_data *thread_base,
2064 struct core_data *core_base, struct pkg_data *pkg_base,
2065 struct thread_data *thread_base2, struct core_data *core_base2,
2066 struct pkg_data *pkg_base2)
2067{
2068 int retval, pkg_no, core_no, thread_no;
2069
2070 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
2071 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
2072 for (thread_no = 0; thread_no <
2073 topo.num_threads_per_core; ++thread_no) {
2074 struct thread_data *t, *t2;
2075 struct core_data *c, *c2;
2076 struct pkg_data *p, *p2;
2077
2078 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
2079
2080 if (cpu_is_not_present(t->cpu_id))
2081 continue;
2082
2083 t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no);
2084
2085 c = GET_CORE(core_base, core_no, pkg_no);
2086 c2 = GET_CORE(core_base2, core_no, pkg_no);
2087
2088 p = GET_PKG(pkg_base, pkg_no);
2089 p2 = GET_PKG(pkg_base2, pkg_no);
2090
2091 retval = func(t, c, p, t2, c2, p2);
2092 if (retval)
2093 return retval;
2094 }
2095 }
2096 }
2097 return 0;
2098}
2099
2100/*
2101 * run func(cpu) on every cpu in /proc/stat
2102 * return max_cpu number
2103 */
2104int for_all_proc_cpus(int (func)(int))
103a8fea
LB		 2105{
2106 FILE *fp;
c98d5d94 2107 int cpu_num;
103a8fea
LB		 2108 int retval;
2109
57a42a34 2110 fp = fopen_or_die(proc_stat, "r");
103a8fea
LB		 2111
2112 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
b2c95d90
JT		 2113 if (retval != 0)
2114 err(1, "%s: failed to parse format", proc_stat);
103a8fea 2115
c98d5d94
LB		 2116 while (1) {
2117 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
103a8fea
LB		 2118 if (retval != 1)
2119 break;
2120
c98d5d94
LB		 2121 retval = func(cpu_num);
2122 if (retval) {
2123 fclose(fp);
2124 return(retval);
2125 }
103a8fea
LB		 2126 }
2127 fclose(fp);
c98d5d94 2128 return 0;
103a8fea
LB		 2129}
2130
2131void re_initialize(void)
2132{
c98d5d94
LB		 2133 free_all_buffers();
2134 setup_all_buffers();
2135 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus);
103a8fea
LB		 2136}
2137
c98d5d94 2138
103a8fea 2139/*
c98d5d94
LB		 2140 * count_cpus()
2141 * remember the last one seen, it will be the max
103a8fea 2142 */
c98d5d94 2143int count_cpus(int cpu)
103a8fea 2144{
c98d5d94
LB		 2145 if (topo.max_cpu_num < cpu)
2146 topo.max_cpu_num = cpu;
103a8fea 2147
c98d5d94
LB		 2148 topo.num_cpus += 1;
2149 return 0;
2150}
2151int mark_cpu_present(int cpu)
2152{
2153 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
15aaa346 2154 return 0;
103a8fea
LB		 2155}
2156
562a2d37
LB		 2157/*
2158 * snapshot_proc_interrupts()
2159 *
2160 * read and record summary of /proc/interrupts
2161 *
2162 * return 1 if config change requires a restart, else return 0
2163 */
2164int snapshot_proc_interrupts(void)
2165{
2166 static FILE *fp;
2167 int column, retval;
2168
2169 if (fp == NULL)
2170 fp = fopen_or_die("/proc/interrupts", "r");
2171 else
2172 rewind(fp);
2173
2174 /* read 1st line of /proc/interrupts to get cpu* name for each column */
2175 for (column = 0; column < topo.num_cpus; ++column) {
2176 int cpu_number;
2177
2178 retval = fscanf(fp, " CPU%d", &cpu_number);
2179 if (retval != 1)
2180 break;
2181
2182 if (cpu_number > topo.max_cpu_num) {
2183 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num);
2184 return 1;
2185 }
2186
2187 irq_column_2_cpu[column] = cpu_number;
2188 irqs_per_cpu[cpu_number] = 0;
2189 }
2190
2191 /* read /proc/interrupt count lines and sum up irqs per cpu */
2192 while (1) {
2193 int column;
2194 char buf[64];
2195
2196 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */
2197 if (retval != 1)
2198 break;
2199
2200 /* read the count per cpu */
2201 for (column = 0; column < topo.num_cpus; ++column) {
2202
2203 int cpu_number, irq_count;
2204
2205 retval = fscanf(fp, " %d", &irq_count);
2206 if (retval != 1)
2207 break;
2208
2209 cpu_number = irq_column_2_cpu[column];
2210 irqs_per_cpu[cpu_number] += irq_count;
2211
2212 }
2213
2214 while (getc(fp) != '\n')
2215 ; /* flush interrupt description */
2216
2217 }
2218 return 0;
2219}
fdf676e5
LB		 2220/*
2221 * snapshot_gfx_rc6_ms()
2222 *
2223 * record snapshot of
2224 * /sys/class/drm/card0/power/rc6_residency_ms
2225 *
2226 * return 1 if config change requires a restart, else return 0
2227 */
2228int snapshot_gfx_rc6_ms(void)
2229{
2230 FILE *fp;
2231 int retval;
2232
2233 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
2234
2235 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms);
2236 if (retval != 1)
2237 err(1, "GFX rc6");
2238
2239 fclose(fp);
2240
2241 return 0;
2242}
27d47356
LB		 2243/*
2244 * snapshot_gfx_mhz()
2245 *
2246 * record snapshot of
2247 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
2248 *
2249 * return 1 if config change requires a restart, else return 0
2250 */
2251int snapshot_gfx_mhz(void)
2252{
2253 static FILE *fp;
2254 int retval;
2255
2256 if (fp == NULL)
2257 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
2258 else
2259 rewind(fp);
2260
2261 retval = fscanf(fp, "%d", &gfx_cur_mhz);
2262 if (retval != 1)
2263 err(1, "GFX MHz");
2264
2265 return 0;
2266}
562a2d37
LB		 2267
2268/*
2269 * snapshot /proc and /sys files
2270 *
2271 * return 1 if configuration restart needed, else return 0
2272 */
2273int snapshot_proc_sysfs_files(void)
2274{
2275 if (snapshot_proc_interrupts())
2276 return 1;
2277
812db3f7 2278 if (DO_BIC(BIC_GFX_rc6))
fdf676e5
LB		 2279 snapshot_gfx_rc6_ms();
2280
812db3f7 2281 if (DO_BIC(BIC_GFXMHz))
27d47356
LB		 2282 snapshot_gfx_mhz();
2283
562a2d37
LB		 2284 return 0;
2285}
2286
103a8fea
LB		 2287void turbostat_loop()
2288{
c98d5d94 2289 int retval;
e52966c0 2290 int restarted = 0;
c98d5d94 2291
103a8fea 2292restart:
e52966c0
LB		 2293 restarted++;
2294
562a2d37 2295 snapshot_proc_sysfs_files();
c98d5d94 2296 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
d91bb17c
LB		 2297 if (retval < -1) {
2298 exit(retval);
2299 } else if (retval == -1) {
e52966c0
LB		 2300 if (restarted > 1) {
2301 exit(retval);
2302 }
c98d5d94
LB		 2303 re_initialize();
2304 goto restart;
2305 }
e52966c0 2306 restarted = 0;
103a8fea
LB		 2307 gettimeofday(&tv_even, (struct timezone *)NULL);
2308
2309 while (1) {
c98d5d94 2310 if (for_all_proc_cpus(cpu_is_not_present)) {
103a8fea
LB		 2311 re_initialize();
2312 goto restart;
2313 }
2a0609c0 2314 nanosleep(&interval_ts, NULL);
562a2d37
LB		 2315 if (snapshot_proc_sysfs_files())
2316 goto restart;
c98d5d94 2317 retval = for_all_cpus(get_counters, ODD_COUNTERS);
d91bb17c
LB		 2318 if (retval < -1) {
2319 exit(retval);
2320 } else if (retval == -1) {
15aaa346
LB		 2321 re_initialize();
2322 goto restart;
2323 }
103a8fea 2324 gettimeofday(&tv_odd, (struct timezone *)NULL);
103a8fea 2325 timersub(&tv_odd, &tv_even, &tv_delta);
ba3dec99
LB		 2326 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) {
2327 re_initialize();
2328 goto restart;
2329 }
c98d5d94
LB		 2330 compute_average(EVEN_COUNTERS);
2331 format_all_counters(EVEN_COUNTERS);
b7d8c148 2332 flush_output_stdout();
2a0609c0 2333 nanosleep(&interval_ts, NULL);
562a2d37
LB		 2334 if (snapshot_proc_sysfs_files())
2335 goto restart;
c98d5d94 2336 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
d91bb17c
LB		 2337 if (retval < -1) {
2338 exit(retval);
2339 } else if (retval == -1) {
103a8fea
LB		 2340 re_initialize();
2341 goto restart;
2342 }
103a8fea 2343 gettimeofday(&tv_even, (struct timezone *)NULL);
103a8fea 2344 timersub(&tv_even, &tv_odd, &tv_delta);
ba3dec99
LB		 2345 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) {
2346 re_initialize();
2347 goto restart;
2348 }
c98d5d94
LB		 2349 compute_average(ODD_COUNTERS);
2350 format_all_counters(ODD_COUNTERS);
b7d8c148 2351 flush_output_stdout();
103a8fea
LB		 2352 }
2353}
2354
2355void check_dev_msr()
2356{
2357 struct stat sb;
7ce7d5de 2358 char pathname[32];
103a8fea 2359
7ce7d5de
PB		 2360 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
2361 if (stat(pathname, &sb))
a21d38c8
LB		 2362 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
2363 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
103a8fea
LB		 2364}
2365
98481e79 2366void check_permissions()
103a8fea 2367{
98481e79
LB		 2368 struct __user_cap_header_struct cap_header_data;
2369 cap_user_header_t cap_header = &cap_header_data;
2370 struct __user_cap_data_struct cap_data_data;
2371 cap_user_data_t cap_data = &cap_data_data;
2372 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap);
2373 int do_exit = 0;
7ce7d5de 2374 char pathname[32];
98481e79
LB		 2375
2376 /* check for CAP_SYS_RAWIO */
2377 cap_header->pid = getpid();
2378 cap_header->version = _LINUX_CAPABILITY_VERSION;
2379 if (capget(cap_header, cap_data) < 0)
2380 err(-6, "capget(2) failed");
2381
2382 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) {
2383 do_exit++;
2384 warnx("capget(CAP_SYS_RAWIO) failed,"
2385 " try \"# setcap cap_sys_rawio=ep %s\"", progname);
2386 }
2387
2388 /* test file permissions */
7ce7d5de
PB		 2389 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
2390 if (euidaccess(pathname, R_OK)) {
98481e79
LB		 2391 do_exit++;
2392 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
2393 }
2394
2395 /* if all else fails, thell them to be root */
2396 if (do_exit)
2397 if (getuid() != 0)
d7899447 2398 warnx("... or simply run as root");
98481e79
LB		 2399
2400 if (do_exit)
2401 exit(-6);
103a8fea
LB		 2402}
2403
d7899447
LB		 2404/*
2405 * NHM adds support for additional MSRs:
2406 *
2407 * MSR_SMI_COUNT 0x00000034
2408 *
ec0adc53 2409 * MSR_PLATFORM_INFO 0x000000ce
1df2e55a 2410 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
d7899447 2411 *
cf4cbe53
LB		 2412 * MSR_MISC_PWR_MGMT 0x000001aa
2413 *
d7899447
LB		 2414 * MSR_PKG_C3_RESIDENCY 0x000003f8
2415 * MSR_PKG_C6_RESIDENCY 0x000003f9
2416 * MSR_CORE_C3_RESIDENCY 0x000003fc
2417 * MSR_CORE_C6_RESIDENCY 0x000003fd
2418 *
ee7e38e3 2419 * Side effect:
1df2e55a 2420 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL
d7899447 2421 */
ee7e38e3 2422int probe_nhm_msrs(unsigned int family, unsigned int model)
103a8fea 2423{
ee7e38e3 2424 unsigned long long msr;
21ed5574 2425 unsigned int base_ratio;
ee7e38e3
LB		 2426 int *pkg_cstate_limits;
2427
103a8fea
LB		 2428 if (!genuine_intel)
2429 return 0;
2430
2431 if (family != 6)
2432 return 0;
2433
21ed5574
LB		 2434 bclk = discover_bclk(family, model);
2435
103a8fea 2436 switch (model) {
869ce69e
LB		 2437 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
2438 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
103a8fea 2439 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
869ce69e
LB		 2440 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */
2441 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */
2442 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
2443 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
ee7e38e3
LB		 2444 pkg_cstate_limits = nhm_pkg_cstate_limits;
2445 break;
869ce69e
LB		 2446 case INTEL_FAM6_SANDYBRIDGE: /* SNB */
2447 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */
2448 case INTEL_FAM6_IVYBRIDGE: /* IVB */
2449 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
ee7e38e3
LB		 2450 pkg_cstate_limits = snb_pkg_cstate_limits;
2451 break;
869ce69e
LB		 2452 case INTEL_FAM6_HASWELL_CORE: /* HSW */
2453 case INTEL_FAM6_HASWELL_X: /* HSX */
2454 case INTEL_FAM6_HASWELL_ULT: /* HSW */
2455 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
2456 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
2457 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
2458 case INTEL_FAM6_BROADWELL_X: /* BDX */
2459 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2460 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
2461 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
2462 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
2463 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
ee7e38e3
LB		 2464 pkg_cstate_limits = hsw_pkg_cstate_limits;
2465 break;
d8ebb442
LB		 2466 case INTEL_FAM6_SKYLAKE_X: /* SKX */
2467 pkg_cstate_limits = skx_pkg_cstate_limits;
2468 break;
869ce69e 2469 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
cf4cbe53 2470 no_MSR_MISC_PWR_MGMT = 1;
869ce69e 2471 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
ee7e38e3
LB		 2472 pkg_cstate_limits = slv_pkg_cstate_limits;
2473 break;
869ce69e 2474 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */
ee7e38e3 2475 pkg_cstate_limits = amt_pkg_cstate_limits;
cf4cbe53 2476 no_MSR_MISC_PWR_MGMT = 1;
ee7e38e3 2477 break;
869ce69e 2478 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */
005c82d6 2479 case INTEL_FAM6_XEON_PHI_KNM:
ee7e38e3
LB		 2480 pkg_cstate_limits = phi_pkg_cstate_limits;
2481 break;
869ce69e
LB		 2482 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
2483 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
e4085d54
LB		 2484 pkg_cstate_limits = bxt_pkg_cstate_limits;
2485 break;
103a8fea
LB		 2486 default:
2487 return 0;
2488 }
1df2e55a 2489 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
e9257f5f 2490 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
ee7e38e3 2491
ec0adc53 2492 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
21ed5574
LB		 2493 base_ratio = (msr >> 8) & 0xFF;
2494
2495 base_hz = base_ratio * bclk * 1000000;
2496 has_base_hz = 1;
ee7e38e3 2497 return 1;
103a8fea 2498}
d7899447
LB		 2499int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
2500{
d7899447
LB		 2501 switch (model) {
2502 /* Nehalem compatible, but do not include turbo-ratio limit support */
869ce69e
LB		 2503 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
2504 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
2505 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */
005c82d6 2506 case INTEL_FAM6_XEON_PHI_KNM:
d7899447
LB		 2507 return 0;
2508 default:
2509 return 1;
2510 }
2511}
6574a5d5
LB		 2512int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
2513{
2514 if (!genuine_intel)
2515 return 0;
2516
2517 if (family != 6)
2518 return 0;
2519
2520 switch (model) {
869ce69e
LB		 2521 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
2522 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
fcd17211
LB		 2523 return 1;
2524 default:
2525 return 0;
2526 }
2527}
2528int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model)
2529{
2530 if (!genuine_intel)
2531 return 0;
2532
2533 if (family != 6)
2534 return 0;
2535
2536 switch (model) {
869ce69e 2537 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
6574a5d5
LB		 2538 return 1;
2539 default:
2540 return 0;
2541 }
2542}
2543
fb5d4327
DC		 2544int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model)
2545{
2546 if (!genuine_intel)
2547 return 0;
2548
2549 if (family != 6)
2550 return 0;
2551
2552 switch (model) {
869ce69e 2553 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
005c82d6 2554 case INTEL_FAM6_XEON_PHI_KNM:
fb5d4327
DC		 2555 return 1;
2556 default:
2557 return 0;
2558 }
2559}
6fb3143b
LB		 2560int has_config_tdp(unsigned int family, unsigned int model)
2561{
2562 if (!genuine_intel)
2563 return 0;
2564
2565 if (family != 6)
2566 return 0;
2567
2568 switch (model) {
869ce69e
LB		 2569 case INTEL_FAM6_IVYBRIDGE: /* IVB */
2570 case INTEL_FAM6_HASWELL_CORE: /* HSW */
2571 case INTEL_FAM6_HASWELL_X: /* HSX */
2572 case INTEL_FAM6_HASWELL_ULT: /* HSW */
2573 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
2574 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
2575 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
2576 case INTEL_FAM6_BROADWELL_X: /* BDX */
2577 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2578 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
2579 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
2580 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
2581 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
2582 case INTEL_FAM6_SKYLAKE_X: /* SKX */
2583
2584 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
005c82d6 2585 case INTEL_FAM6_XEON_PHI_KNM:
6fb3143b
LB		 2586 return 1;
2587 default:
2588 return 0;
2589 }
2590}
2591
fcd17211 2592static void
1b69317d 2593dump_cstate_pstate_config_info(unsigned int family, unsigned int model)
fcd17211
LB		 2594{
2595 if (!do_nhm_platform_info)
2596 return;
2597
2598 dump_nhm_platform_info();
2599
2600 if (has_hsw_turbo_ratio_limit(family, model))
2601 dump_hsw_turbo_ratio_limits();
2602
2603 if (has_ivt_turbo_ratio_limit(family, model))
2604 dump_ivt_turbo_ratio_limits();
2605
2606 if (has_nhm_turbo_ratio_limit(family, model))
2607 dump_nhm_turbo_ratio_limits();
2608
fb5d4327
DC		 2609 if (has_knl_turbo_ratio_limit(family, model))
2610 dump_knl_turbo_ratio_limits();
2611
6fb3143b
LB		 2612 if (has_config_tdp(family, model))
2613 dump_config_tdp();
2614
fcd17211
LB		 2615 dump_nhm_cst_cfg();
2616}
2617
2618
889facbe
LB		 2619/*
2620 * print_epb()
2621 * Decode the ENERGY_PERF_BIAS MSR
2622 */
2623int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2624{
2625 unsigned long long msr;
2626 char *epb_string;
2627 int cpu;
2628
2629 if (!has_epb)
2630 return 0;
2631
2632 cpu = t->cpu_id;
2633
2634 /* EPB is per-package */
2635 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2636 return 0;
2637
2638 if (cpu_migrate(cpu)) {
b7d8c148 2639 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 2640 return -1;
2641 }
2642
2643 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr))
2644 return 0;
2645
e9be7dd6 2646 switch (msr & 0xF) {
889facbe
LB		 2647 case ENERGY_PERF_BIAS_PERFORMANCE:
2648 epb_string = "performance";
2649 break;
2650 case ENERGY_PERF_BIAS_NORMAL:
2651 epb_string = "balanced";
2652 break;
2653 case ENERGY_PERF_BIAS_POWERSAVE:
2654 epb_string = "powersave";
2655 break;
2656 default:
2657 epb_string = "custom";
2658 break;
2659 }
b7d8c148 2660 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string);
889facbe
LB		 2661
2662 return 0;
2663}
7f5c258e
LB		 2664/*
2665 * print_hwp()
2666 * Decode the MSR_HWP_CAPABILITIES
2667 */
2668int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2669{
2670 unsigned long long msr;
2671 int cpu;
2672
2673 if (!has_hwp)
2674 return 0;
2675
2676 cpu = t->cpu_id;
2677
2678 /* MSR_HWP_CAPABILITIES is per-package */
2679 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2680 return 0;
2681
2682 if (cpu_migrate(cpu)) {
b7d8c148 2683 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
7f5c258e
LB		 2684 return -1;
2685 }
2686
2687 if (get_msr(cpu, MSR_PM_ENABLE, &msr))
2688 return 0;
2689
b7d8c148 2690 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n",
7f5c258e
LB		 2691 cpu, msr, (msr & (1 << 0)) ? "" : "No-");
2692
2693 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
2694 if ((msr & (1 << 0)) == 0)
2695 return 0;
2696
2697 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
2698 return 0;
2699
b7d8c148 2700 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
7f5c258e
LB		 2701 "(high 0x%x guar 0x%x eff 0x%x low 0x%x)\n",
2702 cpu, msr,
2703 (unsigned int)HWP_HIGHEST_PERF(msr),
2704 (unsigned int)HWP_GUARANTEED_PERF(msr),
2705 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr),
2706 (unsigned int)HWP_LOWEST_PERF(msr));
2707
2708 if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
2709 return 0;
2710
b7d8c148 2711 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
7f5c258e
LB		 2712 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x pkg 0x%x)\n",
2713 cpu, msr,
2714 (unsigned int)(((msr) >> 0) & 0xff),
2715 (unsigned int)(((msr) >> 8) & 0xff),
2716 (unsigned int)(((msr) >> 16) & 0xff),
2717 (unsigned int)(((msr) >> 24) & 0xff),
2718 (unsigned int)(((msr) >> 32) & 0xff3),
2719 (unsigned int)(((msr) >> 42) & 0x1));
2720
2721 if (has_hwp_pkg) {
2722 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
2723 return 0;
2724
b7d8c148 2725 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
7f5c258e
LB		 2726 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x)\n",
2727 cpu, msr,
2728 (unsigned int)(((msr) >> 0) & 0xff),
2729 (unsigned int)(((msr) >> 8) & 0xff),
2730 (unsigned int)(((msr) >> 16) & 0xff),
2731 (unsigned int)(((msr) >> 24) & 0xff),
2732 (unsigned int)(((msr) >> 32) & 0xff3));
2733 }
2734 if (has_hwp_notify) {
2735 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
2736 return 0;
2737
b7d8c148 2738 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
7f5c258e
LB		 2739 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
2740 cpu, msr,
2741 ((msr) & 0x1) ? "EN" : "Dis",
2742 ((msr) & 0x2) ? "EN" : "Dis");
2743 }
2744 if (get_msr(cpu, MSR_HWP_STATUS, &msr))
2745 return 0;
2746
b7d8c148 2747 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
7f5c258e
LB		 2748 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
2749 cpu, msr,
2750 ((msr) & 0x1) ? "" : "No-",
2751 ((msr) & 0x2) ? "" : "No-");
889facbe
LB		 2752
2753 return 0;
2754}
2755
3a9a941d
LB		 2756/*
2757 * print_perf_limit()
2758 */
2759int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2760{
2761 unsigned long long msr;
2762 int cpu;
2763
2764 cpu = t->cpu_id;
2765
2766 /* per-package */
2767 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2768 return 0;
2769
2770 if (cpu_migrate(cpu)) {
b7d8c148 2771 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3a9a941d
LB		 2772 return -1;
2773 }
2774
2775 if (do_core_perf_limit_reasons) {
2776 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 2777 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2778 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
e33cbe85 2779 (msr & 1 << 15) ? "bit15, " : "",
3a9a941d 2780 (msr & 1 << 14) ? "bit14, " : "",
e33cbe85
LB		 2781 (msr & 1 << 13) ? "Transitions, " : "",
2782 (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
2783 (msr & 1 << 11) ? "PkgPwrL2, " : "",
2784 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2785 (msr & 1 << 9) ? "CorePwr, " : "",
2786 (msr & 1 << 8) ? "Amps, " : "",
2787 (msr & 1 << 6) ? "VR-Therm, " : "",
2788 (msr & 1 << 5) ? "Auto-HWP, " : "",
2789 (msr & 1 << 4) ? "Graphics, " : "",
2790 (msr & 1 << 2) ? "bit2, " : "",
2791 (msr & 1 << 1) ? "ThermStatus, " : "",
2792 (msr & 1 << 0) ? "PROCHOT, " : "");
b7d8c148 2793 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
e33cbe85 2794 (msr & 1 << 31) ? "bit31, " : "",
3a9a941d 2795 (msr & 1 << 30) ? "bit30, " : "",
e33cbe85
LB		 2796 (msr & 1 << 29) ? "Transitions, " : "",
2797 (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
2798 (msr & 1 << 27) ? "PkgPwrL2, " : "",
2799 (msr & 1 << 26) ? "PkgPwrL1, " : "",
2800 (msr & 1 << 25) ? "CorePwr, " : "",
2801 (msr & 1 << 24) ? "Amps, " : "",
2802 (msr & 1 << 22) ? "VR-Therm, " : "",
2803 (msr & 1 << 21) ? "Auto-HWP, " : "",
2804 (msr & 1 << 20) ? "Graphics, " : "",
2805 (msr & 1 << 18) ? "bit18, " : "",
2806 (msr & 1 << 17) ? "ThermStatus, " : "",
2807 (msr & 1 << 16) ? "PROCHOT, " : "");
3a9a941d
LB		 2808
2809 }
2810 if (do_gfx_perf_limit_reasons) {
2811 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 2812 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2813 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
3a9a941d
LB		 2814 (msr & 1 << 0) ? "PROCHOT, " : "",
2815 (msr & 1 << 1) ? "ThermStatus, " : "",
2816 (msr & 1 << 4) ? "Graphics, " : "",
2817 (msr & 1 << 6) ? "VR-Therm, " : "",
2818 (msr & 1 << 8) ? "Amps, " : "",
2819 (msr & 1 << 9) ? "GFXPwr, " : "",
2820 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2821 (msr & 1 << 11) ? "PkgPwrL2, " : "");
b7d8c148 2822 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
3a9a941d
LB		 2823 (msr & 1 << 16) ? "PROCHOT, " : "",
2824 (msr & 1 << 17) ? "ThermStatus, " : "",
2825 (msr & 1 << 20) ? "Graphics, " : "",
2826 (msr & 1 << 22) ? "VR-Therm, " : "",
2827 (msr & 1 << 24) ? "Amps, " : "",
2828 (msr & 1 << 25) ? "GFXPwr, " : "",
2829 (msr & 1 << 26) ? "PkgPwrL1, " : "",
2830 (msr & 1 << 27) ? "PkgPwrL2, " : "");
2831 }
2832 if (do_ring_perf_limit_reasons) {
2833 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 2834 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2835 fprintf(outf, " (Active: %s%s%s%s%s%s)",
3a9a941d
LB		 2836 (msr & 1 << 0) ? "PROCHOT, " : "",
2837 (msr & 1 << 1) ? "ThermStatus, " : "",
2838 (msr & 1 << 6) ? "VR-Therm, " : "",
2839 (msr & 1 << 8) ? "Amps, " : "",
2840 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2841 (msr & 1 << 11) ? "PkgPwrL2, " : "");
b7d8c148 2842 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
3a9a941d
LB		 2843 (msr & 1 << 16) ? "PROCHOT, " : "",
2844 (msr & 1 << 17) ? "ThermStatus, " : "",
2845 (msr & 1 << 22) ? "VR-Therm, " : "",
2846 (msr & 1 << 24) ? "Amps, " : "",
2847 (msr & 1 << 26) ? "PkgPwrL1, " : "",
2848 (msr & 1 << 27) ? "PkgPwrL2, " : "");
2849 }
2850 return 0;
2851}
2852
889facbe
LB		 2853#define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
2854#define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
2855
1b69317d 2856double get_tdp(unsigned int model)
144b44b1
LB		 2857{
2858 unsigned long long msr;
2859
2860 if (do_rapl & RAPL_PKG_POWER_INFO)
7ce7d5de 2861 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
144b44b1
LB		 2862 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
2863
2864 switch (model) {
869ce69e
LB		 2865 case INTEL_FAM6_ATOM_SILVERMONT1:
2866 case INTEL_FAM6_ATOM_SILVERMONT2:
144b44b1
LB		 2867 return 30.0;
2868 default:
2869 return 135.0;
2870 }
2871}
2872
40ee8e3b
AS		 2873/*
2874 * rapl_dram_energy_units_probe()
2875 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
2876 */
2877static double
2878rapl_dram_energy_units_probe(int model, double rapl_energy_units)
2879{
2880 /* only called for genuine_intel, family 6 */
2881
2882 switch (model) {
869ce69e
LB		 2883 case INTEL_FAM6_HASWELL_X: /* HSX */
2884 case INTEL_FAM6_BROADWELL_X: /* BDX */
2885 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2886 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
005c82d6 2887 case INTEL_FAM6_XEON_PHI_KNM:
40ee8e3b
AS		 2888 return (rapl_dram_energy_units = 15.3 / 1000000);
2889 default:
2890 return (rapl_energy_units);
2891 }
2892}
2893
144b44b1 2894
889facbe
LB		 2895/*
2896 * rapl_probe()
2897 *
144b44b1 2898 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
889facbe
LB		 2899 */
2900void rapl_probe(unsigned int family, unsigned int model)
2901{
2902 unsigned long long msr;
144b44b1 2903 unsigned int time_unit;
889facbe
LB		 2904 double tdp;
2905
2906 if (!genuine_intel)
2907 return;
2908
2909 if (family != 6)
2910 return;
2911
2912 switch (model) {
869ce69e
LB		 2913 case INTEL_FAM6_SANDYBRIDGE:
2914 case INTEL_FAM6_IVYBRIDGE:
2915 case INTEL_FAM6_HASWELL_CORE: /* HSW */
2916 case INTEL_FAM6_HASWELL_ULT: /* HSW */
2917 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
2918 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
2919 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
144b44b1 2920 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
812db3f7
LB		 2921 if (rapl_joules) {
2922 BIC_PRESENT(BIC_Pkg_J);
2923 BIC_PRESENT(BIC_Cor_J);
2924 BIC_PRESENT(BIC_GFX_J);
2925 } else {
2926 BIC_PRESENT(BIC_PkgWatt);
2927 BIC_PRESENT(BIC_CorWatt);
2928 BIC_PRESENT(BIC_GFXWatt);
2929 }
889facbe 2930 break;
869ce69e 2931 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
e4085d54 2932 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
812db3f7
LB		 2933 if (rapl_joules)
2934 BIC_PRESENT(BIC_Pkg_J);
2935 else
2936 BIC_PRESENT(BIC_PkgWatt);
e4085d54 2937 break;
869ce69e
LB		 2938 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
2939 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
2940 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
2941 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
0b2bb692 2942 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
812db3f7
LB		 2943 BIC_PRESENT(BIC_PKG__);
2944 BIC_PRESENT(BIC_RAM__);
2945 if (rapl_joules) {
2946 BIC_PRESENT(BIC_Pkg_J);
2947 BIC_PRESENT(BIC_Cor_J);
2948 BIC_PRESENT(BIC_RAM_J);
2949 } else {
2950 BIC_PRESENT(BIC_PkgWatt);
2951 BIC_PRESENT(BIC_CorWatt);
2952 BIC_PRESENT(BIC_RAMWatt);
2953 }
0b2bb692 2954 break;
869ce69e
LB		 2955 case INTEL_FAM6_HASWELL_X: /* HSX */
2956 case INTEL_FAM6_BROADWELL_X: /* BDX */
2957 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2958 case INTEL_FAM6_SKYLAKE_X: /* SKX */
2959 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
005c82d6 2960 case INTEL_FAM6_XEON_PHI_KNM:
0b2bb692 2961 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
812db3f7
LB		 2962 BIC_PRESENT(BIC_PKG__);
2963 BIC_PRESENT(BIC_RAM__);
2964 if (rapl_joules) {
2965 BIC_PRESENT(BIC_Pkg_J);
2966 BIC_PRESENT(BIC_RAM_J);
2967 } else {
2968 BIC_PRESENT(BIC_PkgWatt);
2969 BIC_PRESENT(BIC_RAMWatt);
2970 }
e6f9bb3c 2971 break;
869ce69e
LB		 2972 case INTEL_FAM6_SANDYBRIDGE_X:
2973 case INTEL_FAM6_IVYBRIDGE_X:
0b2bb692 2974 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
812db3f7
LB		 2975 BIC_PRESENT(BIC_PKG__);
2976 BIC_PRESENT(BIC_RAM__);
2977 if (rapl_joules) {
2978 BIC_PRESENT(BIC_Pkg_J);
2979 BIC_PRESENT(BIC_Cor_J);
2980 BIC_PRESENT(BIC_RAM_J);
2981 } else {
2982 BIC_PRESENT(BIC_PkgWatt);
2983 BIC_PRESENT(BIC_CorWatt);
2984 BIC_PRESENT(BIC_RAMWatt);
2985 }
144b44b1 2986 break;
869ce69e
LB		 2987 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
2988 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
9148494c 2989 do_rapl = RAPL_PKG | RAPL_CORES;
812db3f7
LB		 2990 if (rapl_joules) {
2991 BIC_PRESENT(BIC_Pkg_J);
2992 BIC_PRESENT(BIC_Cor_J);
2993 } else {
2994 BIC_PRESENT(BIC_PkgWatt);
2995 BIC_PRESENT(BIC_CorWatt);
2996 }
889facbe 2997 break;
869ce69e 2998 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
0f644909 2999 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
812db3f7
LB		 3000 BIC_PRESENT(BIC_PKG__);
3001 BIC_PRESENT(BIC_RAM__);
3002 if (rapl_joules) {
3003 BIC_PRESENT(BIC_Pkg_J);
3004 BIC_PRESENT(BIC_Cor_J);
3005 BIC_PRESENT(BIC_RAM_J);
3006 } else {
3007 BIC_PRESENT(BIC_PkgWatt);
3008 BIC_PRESENT(BIC_CorWatt);
3009 BIC_PRESENT(BIC_RAMWatt);
3010 }
0f644909 3011 break;
889facbe
LB		 3012 default:
3013 return;
3014 }
3015
3016 /* units on package 0, verify later other packages match */
7ce7d5de 3017 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
889facbe
LB		 3018 return;
3019
3020 rapl_power_units = 1.0 / (1 << (msr & 0xF));
869ce69e 3021 if (model == INTEL_FAM6_ATOM_SILVERMONT1)
144b44b1
LB		 3022 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
3023 else
3024 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
889facbe 3025
40ee8e3b
AS		 3026 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units);
3027
144b44b1
LB		 3028 time_unit = msr >> 16 & 0xF;
3029 if (time_unit == 0)
3030 time_unit = 0xA;
889facbe 3031
144b44b1 3032 rapl_time_units = 1.0 / (1 << (time_unit));
889facbe 3033
144b44b1 3034 tdp = get_tdp(model);
889facbe 3035
144b44b1 3036 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
d8af6f5f 3037 if (debug)
b7d8c148 3038 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
889facbe
LB		 3039
3040 return;
3041}
3042
1b69317d 3043void perf_limit_reasons_probe(unsigned int family, unsigned int model)
3a9a941d
LB		 3044{
3045 if (!genuine_intel)
3046 return;
3047
3048 if (family != 6)
3049 return;
3050
3051 switch (model) {
869ce69e
LB		 3052 case INTEL_FAM6_HASWELL_CORE: /* HSW */
3053 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3054 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
3a9a941d 3055 do_gfx_perf_limit_reasons = 1;
869ce69e 3056 case INTEL_FAM6_HASWELL_X: /* HSX */
3a9a941d
LB		 3057 do_core_perf_limit_reasons = 1;
3058 do_ring_perf_limit_reasons = 1;
3059 default:
3060 return;
3061 }
3062}
3063
889facbe
LB		 3064int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3065{
3066 unsigned long long msr;
3067 unsigned int dts;
3068 int cpu;
3069
3070 if (!(do_dts || do_ptm))
3071 return 0;
3072
3073 cpu = t->cpu_id;
3074
3075 /* DTS is per-core, no need to print for each thread */
388e9c81 3076 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
889facbe
LB		 3077 return 0;
3078
3079 if (cpu_migrate(cpu)) {
b7d8c148 3080 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 3081 return -1;
3082 }
3083
3084 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) {
3085 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
3086 return 0;
3087
3088 dts = (msr >> 16) & 0x7F;
b7d8c148 3089 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n",
889facbe
LB		 3090 cpu, msr, tcc_activation_temp - dts);
3091
3092#ifdef THERM_DEBUG
3093 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
3094 return 0;
3095
3096 dts = (msr >> 16) & 0x7F;
3097 dts2 = (msr >> 8) & 0x7F;
b7d8c148 3098 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
889facbe
LB		 3099 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
3100#endif
3101 }
3102
3103
3104 if (do_dts) {
3105 unsigned int resolution;
3106
3107 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
3108 return 0;
3109
3110 dts = (msr >> 16) & 0x7F;
3111 resolution = (msr >> 27) & 0xF;
b7d8c148 3112 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
889facbe
LB		 3113 cpu, msr, tcc_activation_temp - dts, resolution);
3114
3115#ifdef THERM_DEBUG
3116 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
3117 return 0;
3118
3119 dts = (msr >> 16) & 0x7F;
3120 dts2 = (msr >> 8) & 0x7F;
b7d8c148 3121 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
889facbe
LB		 3122 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
3123#endif
3124 }
3125
3126 return 0;
3127}
36229897 3128
889facbe
LB		 3129void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
3130{
b7d8c148 3131 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n",
889facbe
LB		 3132 cpu, label,
3133 ((msr >> 15) & 1) ? "EN" : "DIS",
3134 ((msr >> 0) & 0x7FFF) * rapl_power_units,
3135 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
3136 (((msr >> 16) & 1) ? "EN" : "DIS"));
3137
3138 return;
3139}
3140
3141int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3142{
3143 unsigned long long msr;
3144 int cpu;
889facbe
LB		 3145
3146 if (!do_rapl)
3147 return 0;
3148
3149 /* RAPL counters are per package, so print only for 1st thread/package */
3150 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3151 return 0;
3152
3153 cpu = t->cpu_id;
3154 if (cpu_migrate(cpu)) {
b7d8c148 3155 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 3156 return -1;
3157 }
3158
3159 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
3160 return -1;
3161
d8af6f5f 3162 if (debug) {
b7d8c148 3163 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx "
889facbe 3164 "(%f Watts, %f Joules, %f sec.)\n", cpu, msr,
144b44b1 3165 rapl_power_units, rapl_energy_units, rapl_time_units);
889facbe 3166 }
144b44b1
LB		 3167 if (do_rapl & RAPL_PKG_POWER_INFO) {
3168
889facbe
LB		 3169 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
3170 return -5;
3171
3172
b7d8c148 3173 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
889facbe
LB		 3174 cpu, msr,
3175 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3176 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3177 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3178 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
3179
144b44b1
LB		 3180 }
3181 if (do_rapl & RAPL_PKG) {
3182
889facbe
LB		 3183 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
3184 return -9;
3185
b7d8c148 3186 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
889facbe
LB		 3187 cpu, msr, (msr >> 63) & 1 ? "": "UN");
3188
3189 print_power_limit_msr(cpu, msr, "PKG Limit #1");
b7d8c148 3190 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n",
889facbe
LB		 3191 cpu,
3192 ((msr >> 47) & 1) ? "EN" : "DIS",
3193 ((msr >> 32) & 0x7FFF) * rapl_power_units,
3194 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
3195 ((msr >> 48) & 1) ? "EN" : "DIS");
3196 }
3197
0b2bb692 3198 if (do_rapl & RAPL_DRAM_POWER_INFO) {
889facbe
LB		 3199 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
3200 return -6;
3201
b7d8c148 3202 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
889facbe
LB		 3203 cpu, msr,
3204 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3205 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3206 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3207 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
0b2bb692
LB		 3208 }
3209 if (do_rapl & RAPL_DRAM) {
889facbe
LB		 3210 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
3211 return -9;
b7d8c148 3212 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
889facbe
LB		 3213 cpu, msr, (msr >> 31) & 1 ? "": "UN");
3214
3215 print_power_limit_msr(cpu, msr, "DRAM Limit");
3216 }
144b44b1 3217 if (do_rapl & RAPL_CORE_POLICY) {
d8af6f5f 3218 if (debug) {
889facbe
LB		 3219 if (get_msr(cpu, MSR_PP0_POLICY, &msr))
3220 return -7;
3221
b7d8c148 3222 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
144b44b1
LB		 3223 }
3224 }
9148494c 3225 if (do_rapl & RAPL_CORES_POWER_LIMIT) {
d8af6f5f 3226 if (debug) {
889facbe
LB		 3227 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
3228 return -9;
b7d8c148 3229 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
889facbe
LB		 3230 cpu, msr, (msr >> 31) & 1 ? "": "UN");
3231 print_power_limit_msr(cpu, msr, "Cores Limit");
3232 }
3233 }
3234 if (do_rapl & RAPL_GFX) {
d8af6f5f 3235 if (debug) {
889facbe
LB		 3236 if (get_msr(cpu, MSR_PP1_POLICY, &msr))
3237 return -8;
3238
b7d8c148 3239 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
889facbe
LB		 3240
3241 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
3242 return -9;
b7d8c148 3243 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
889facbe
LB		 3244 cpu, msr, (msr >> 31) & 1 ? "": "UN");
3245 print_power_limit_msr(cpu, msr, "GFX Limit");
3246 }
3247 }
3248 return 0;
3249}
3250
d7899447
LB		 3251/*
3252 * SNB adds support for additional MSRs:
3253 *
3254 * MSR_PKG_C7_RESIDENCY 0x000003fa
3255 * MSR_CORE_C7_RESIDENCY 0x000003fe
3256 * MSR_PKG_C2_RESIDENCY 0x0000060d
3257 */
103a8fea 3258
d7899447 3259int has_snb_msrs(unsigned int family, unsigned int model)
103a8fea
LB		 3260{
3261 if (!genuine_intel)
3262 return 0;
3263
3264 switch (model) {
869ce69e
LB		 3265 case INTEL_FAM6_SANDYBRIDGE:
3266 case INTEL_FAM6_SANDYBRIDGE_X:
3267 case INTEL_FAM6_IVYBRIDGE: /* IVB */
3268 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
3269 case INTEL_FAM6_HASWELL_CORE: /* HSW */
3270 case INTEL_FAM6_HASWELL_X: /* HSW */
3271 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3272 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
3273 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
3274 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
3275 case INTEL_FAM6_BROADWELL_X: /* BDX */
3276 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
3277 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3278 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3279 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3280 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3281 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3282 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
5bbac26e 3283 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
103a8fea
LB		 3284 return 1;
3285 }
3286 return 0;
3287}
3288
71616c8e
LB		 3289/*
3290 * SLV client has supporet for unique MSRs:
3291 *
3292 * MSR_CC6_DEMOTION_POLICY_CONFIG
3293 * MSR_MC6_DEMOTION_POLICY_CONFIG
3294 */
3295
3296int has_slv_msrs(unsigned int family, unsigned int model)
3297{
3298 if (!genuine_intel)
3299 return 0;
3300
3301 switch (model) {
3302 case INTEL_FAM6_ATOM_SILVERMONT1:
3303 case INTEL_FAM6_ATOM_MERRIFIELD:
3304 case INTEL_FAM6_ATOM_MOOREFIELD:
3305 return 1;
3306 }
3307 return 0;
3308}
3309
d7899447
LB		 3310/*
3311 * HSW adds support for additional MSRs:
3312 *
5a63426e
LB		 3313 * MSR_PKG_C8_RESIDENCY 0x00000630
3314 * MSR_PKG_C9_RESIDENCY 0x00000631
3315 * MSR_PKG_C10_RESIDENCY 0x00000632
3316 *
3317 * MSR_PKGC8_IRTL 0x00000633
3318 * MSR_PKGC9_IRTL 0x00000634
3319 * MSR_PKGC10_IRTL 0x00000635
3320 *
d7899447
LB		 3321 */
3322int has_hsw_msrs(unsigned int family, unsigned int model)
ca58710f
KCA		 3323{
3324 if (!genuine_intel)
3325 return 0;
3326
3327 switch (model) {
869ce69e
LB		 3328 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3329 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
3330 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3331 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3332 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3333 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3334 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
0b2bb692
LB		 3335 return 1;
3336 }
3337 return 0;
3338}
3339
3340/*
3341 * SKL adds support for additional MSRS:
3342 *
3343 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
3344 * MSR_PKG_ANY_CORE_C0_RES 0x00000659
3345 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
3346 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
3347 */
3348int has_skl_msrs(unsigned int family, unsigned int model)
3349{
3350 if (!genuine_intel)
3351 return 0;
3352
3353 switch (model) {
869ce69e
LB		 3354 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3355 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3356 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3357 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
ca58710f
KCA		 3358 return 1;
3359 }
3360 return 0;
3361}
3362
144b44b1
LB		 3363int is_slm(unsigned int family, unsigned int model)
3364{
3365 if (!genuine_intel)
3366 return 0;
3367 switch (model) {
869ce69e
LB		 3368 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
3369 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
144b44b1
LB		 3370 return 1;
3371 }
3372 return 0;
3373}
3374
fb5d4327
DC		 3375int is_knl(unsigned int family, unsigned int model)
3376{
3377 if (!genuine_intel)
3378 return 0;
3379 switch (model) {
869ce69e 3380 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
005c82d6 3381 case INTEL_FAM6_XEON_PHI_KNM:
fb5d4327
DC		 3382 return 1;
3383 }
3384 return 0;
3385}
3386
b2b34dfe
HC		 3387unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model)
3388{
3389 if (is_knl(family, model))
3390 return 1024;
3391 return 1;
3392}
3393
144b44b1
LB		 3394#define SLM_BCLK_FREQS 5
3395double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0};
3396
3397double slm_bclk(void)
3398{
3399 unsigned long long msr = 3;
3400 unsigned int i;
3401 double freq;
3402
7ce7d5de 3403 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
b7d8c148 3404 fprintf(outf, "SLM BCLK: unknown\n");
144b44b1
LB		 3405
3406 i = msr & 0xf;
3407 if (i >= SLM_BCLK_FREQS) {
b7d8c148 3408 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
0a91e551 3409 i = 3;
144b44b1
LB		 3410 }
3411 freq = slm_freq_table[i];
3412
8f6196c1
LB		 3413 if (debug)
3414 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
144b44b1
LB		 3415
3416 return freq;
3417}
3418
103a8fea
LB		 3419double discover_bclk(unsigned int family, unsigned int model)
3420{
121b48bb 3421 if (has_snb_msrs(family, model) || is_knl(family, model))
103a8fea 3422 return 100.00;
144b44b1
LB		 3423 else if (is_slm(family, model))
3424 return slm_bclk();
103a8fea
LB		 3425 else
3426 return 133.33;
3427}
3428
889facbe
LB		 3429/*
3430 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
3431 * the Thermal Control Circuit (TCC) activates.
3432 * This is usually equal to tjMax.
3433 *
3434 * Older processors do not have this MSR, so there we guess,
3435 * but also allow cmdline over-ride with -T.
3436 *
3437 * Several MSR temperature values are in units of degrees-C
3438 * below this value, including the Digital Thermal Sensor (DTS),
3439 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
3440 */
3441int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3442{
3443 unsigned long long msr;
3444 unsigned int target_c_local;
3445 int cpu;
3446
3447 /* tcc_activation_temp is used only for dts or ptm */
3448 if (!(do_dts || do_ptm))
3449 return 0;
3450
3451 /* this is a per-package concept */
3452 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3453 return 0;
3454
3455 cpu = t->cpu_id;
3456 if (cpu_migrate(cpu)) {
b7d8c148 3457 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 3458 return -1;
3459 }
3460
3461 if (tcc_activation_temp_override != 0) {
3462 tcc_activation_temp = tcc_activation_temp_override;
b7d8c148 3463 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n",
889facbe
LB		 3464 cpu, tcc_activation_temp);
3465 return 0;
3466 }
3467
3468 /* Temperature Target MSR is Nehalem and newer only */
d7899447 3469 if (!do_nhm_platform_info)
889facbe
LB		 3470 goto guess;
3471
7ce7d5de 3472 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
889facbe
LB		 3473 goto guess;
3474
3482124a 3475 target_c_local = (msr >> 16) & 0xFF;
889facbe 3476
d8af6f5f 3477 if (debug)
b7d8c148 3478 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n",
889facbe
LB		 3479 cpu, msr, target_c_local);
3480
3482124a 3481 if (!target_c_local)
889facbe
LB		 3482 goto guess;
3483
3484 tcc_activation_temp = target_c_local;
3485
3486 return 0;
3487
3488guess:
3489 tcc_activation_temp = TJMAX_DEFAULT;
b7d8c148 3490 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n",
889facbe
LB		 3491 cpu, tcc_activation_temp);
3492
3493 return 0;
3494}
69807a63 3495
aa8d8cc7
LB		 3496void decode_feature_control_msr(void)
3497{
3498 unsigned long long msr;
3499
3500 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr))
3501 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
3502 base_cpu, msr,
3503 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-",
3504 msr & (1 << 18) ? "SGX" : "");
3505}
3506
69807a63
LB		 3507void decode_misc_enable_msr(void)
3508{
3509 unsigned long long msr;
3510
3511 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
b7d8c148 3512 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%s %s %s)\n",
69807a63
LB		 3513 base_cpu, msr,
3514 msr & (1 << 3) ? "TCC" : "",
3515 msr & (1 << 16) ? "EIST" : "",
3516 msr & (1 << 18) ? "MONITOR" : "");
3517}
3518
f0057310
LB		 3519/*
3520 * Decode MSR_MISC_PWR_MGMT
3521 *
3522 * Decode the bits according to the Nehalem documentation
3523 * bit[0] seems to continue to have same meaning going forward
3524 * bit[1] less so...
3525 */
3526void decode_misc_pwr_mgmt_msr(void)
3527{
3528 unsigned long long msr;
3529
3530 if (!do_nhm_platform_info)
3531 return;
3532
cf4cbe53
LB		 3533 if (no_MSR_MISC_PWR_MGMT)
3534 return;
3535
f0057310 3536 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
ddadb8ad 3537 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
f0057310
LB		 3538 base_cpu, msr,
3539 msr & (1 << 0) ? "DIS" : "EN",
ddadb8ad
SP		 3540 msr & (1 << 1) ? "EN" : "DIS",
3541 msr & (1 << 8) ? "EN" : "DIS");
f0057310 3542}
71616c8e
LB		 3543/*
3544 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG
3545 *
3546 * This MSRs are present on Silvermont processors,
3547 * Intel Atom processor E3000 series (Baytrail), and friends.
3548 */
3549void decode_c6_demotion_policy_msr(void)
3550{
3551 unsigned long long msr;
3552
3553 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
3554 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n",
3555 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
3556
3557 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
3558 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n",
3559 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
3560}
7f5c258e 3561
fcd17211 3562void process_cpuid()
103a8fea 3563{
61a87ba7 3564 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level;
103a8fea
LB		 3565 unsigned int fms, family, model, stepping;
3566
3567 eax = ebx = ecx = edx = 0;
3568
5aea2f7f 3569 __cpuid(0, max_level, ebx, ecx, edx);
103a8fea
LB		 3570
3571 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e)
3572 genuine_intel = 1;
3573
d8af6f5f 3574 if (debug)
b7d8c148 3575 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ",
103a8fea
LB		 3576 (char *)&ebx, (char *)&edx, (char *)&ecx);
3577
5aea2f7f 3578 __cpuid(1, fms, ebx, ecx, edx);
103a8fea
LB		 3579 family = (fms >> 8) & 0xf;
3580 model = (fms >> 4) & 0xf;
3581 stepping = fms & 0xf;
3582 if (family == 6 || family == 0xf)
3583 model += ((fms >> 16) & 0xf) << 4;
3584
69807a63 3585 if (debug) {
b7d8c148 3586 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n",
103a8fea 3587 max_level, family, model, stepping, family, model, stepping);
aa8d8cc7 3588 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s\n",
69807a63
LB		 3589 ecx & (1 << 0) ? "SSE3" : "-",
3590 ecx & (1 << 3) ? "MONITOR" : "-",
aa8d8cc7 3591 ecx & (1 << 6) ? "SMX" : "-",
69807a63
LB		 3592 ecx & (1 << 7) ? "EIST" : "-",
3593 ecx & (1 << 8) ? "TM2" : "-",
3594 edx & (1 << 4) ? "TSC" : "-",
3595 edx & (1 << 5) ? "MSR" : "-",
3596 edx & (1 << 22) ? "ACPI-TM" : "-",
3597 edx & (1 << 29) ? "TM" : "-");
3598 }
103a8fea 3599
b2c95d90
JT		 3600 if (!(edx & (1 << 5)))
3601 errx(1, "CPUID: no MSR");
103a8fea
LB		 3602
3603 /*
3604 * check max extended function levels of CPUID.
3605 * This is needed to check for invariant TSC.
3606 * This check is valid for both Intel and AMD.
3607 */
3608 ebx = ecx = edx = 0;
5aea2f7f 3609 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx);
103a8fea 3610
61a87ba7 3611 if (max_extended_level >= 0x80000007) {
103a8fea 3612
d7899447
LB		 3613 /*
3614 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
3615 * this check is valid for both Intel and AMD
3616 */
5aea2f7f 3617 __cpuid(0x80000007, eax, ebx, ecx, edx);
d7899447
LB		 3618 has_invariant_tsc = edx & (1 << 8);
3619 }
103a8fea
LB		 3620
3621 /*
3622 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
3623 * this check is valid for both Intel and AMD
3624 */
3625
5aea2f7f 3626 __cpuid(0x6, eax, ebx, ecx, edx);
8209e054 3627 has_aperf = ecx & (1 << 0);
812db3f7
LB		 3628 if (has_aperf) {
3629 BIC_PRESENT(BIC_Avg_MHz);
3630 BIC_PRESENT(BIC_Busy);
3631 BIC_PRESENT(BIC_Bzy_MHz);
3632 }
889facbe 3633 do_dts = eax & (1 << 0);
812db3f7
LB		 3634 if (do_dts)
3635 BIC_PRESENT(BIC_CoreTmp);
889facbe 3636 do_ptm = eax & (1 << 6);
812db3f7
LB		 3637 if (do_ptm)
3638 BIC_PRESENT(BIC_PkgTmp);
7f5c258e
LB		 3639 has_hwp = eax & (1 << 7);
3640 has_hwp_notify = eax & (1 << 8);
3641 has_hwp_activity_window = eax & (1 << 9);
3642 has_hwp_epp = eax & (1 << 10);
3643 has_hwp_pkg = eax & (1 << 11);
889facbe
LB		 3644 has_epb = ecx & (1 << 3);
3645
d8af6f5f 3646 if (debug)
b7d8c148 3647 fprintf(outf, "CPUID(6): %sAPERF, %sDTS, %sPTM, %sHWP, "
7f5c258e
LB		 3648 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
3649 has_aperf ? "" : "No-",
3650 do_dts ? "" : "No-",
3651 do_ptm ? "" : "No-",
3652 has_hwp ? "" : "No-",
3653 has_hwp_notify ? "" : "No-",
3654 has_hwp_activity_window ? "" : "No-",
3655 has_hwp_epp ? "" : "No-",
3656 has_hwp_pkg ? "" : "No-",
3657 has_epb ? "" : "No-");
103a8fea 3658
69807a63
LB		 3659 if (debug)
3660 decode_misc_enable_msr();
3661
8ae72255 3662 if (max_level >= 0x7 && debug) {
aa8d8cc7 3663 int has_sgx;
103a8fea 3664
aa8d8cc7
LB		 3665 ecx = 0;
3666
3667 __cpuid_count(0x7, 0, eax, ebx, ecx, edx);
3668
3669 has_sgx = ebx & (1 << 2);
3670 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-");
3671
3672 if (has_sgx)
3673 decode_feature_control_msr();
3674 }
3675
61a87ba7 3676 if (max_level >= 0x15) {
8a5bdf41
LB		 3677 unsigned int eax_crystal;
3678 unsigned int ebx_tsc;
3679
3680 /*
3681 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
3682 */
3683 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
5aea2f7f 3684 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx);
8a5bdf41
LB		 3685
3686 if (ebx_tsc != 0) {
3687
3688 if (debug && (ebx != 0))
b7d8c148 3689 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
8a5bdf41
LB		 3690 eax_crystal, ebx_tsc, crystal_hz);
3691
3692 if (crystal_hz == 0)
3693 switch(model) {
869ce69e
LB		 3694 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3695 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3696 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3697 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
e8efbc80
LB		 3698 crystal_hz = 24000000; /* 24.0 MHz */
3699 break;
869ce69e 3700 case INTEL_FAM6_SKYLAKE_X: /* SKX */
7268d407 3701 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
ec53e594
LB		 3702 crystal_hz = 25000000; /* 25.0 MHz */
3703 break;
869ce69e 3704 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
e8efbc80 3705 crystal_hz = 19200000; /* 19.2 MHz */
8a5bdf41
LB		 3706 break;
3707 default:
3708 crystal_hz = 0;
3709 }
3710
3711 if (crystal_hz) {
3712 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal;
3713 if (debug)
b7d8c148 3714 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
8a5bdf41
LB		 3715 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal);
3716 }
3717 }
3718 }
61a87ba7
LB		 3719 if (max_level >= 0x16) {
3720 unsigned int base_mhz, max_mhz, bus_mhz, edx;
3721
3722 /*
3723 * CPUID 16H Base MHz, Max MHz, Bus MHz
3724 */
3725 base_mhz = max_mhz = bus_mhz = edx = 0;
3726
5aea2f7f 3727 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx);
61a87ba7 3728 if (debug)
b7d8c148 3729 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
61a87ba7
LB		 3730 base_mhz, max_mhz, bus_mhz);
3731 }
8a5bdf41 3732
b2b34dfe
HC		 3733 if (has_aperf)
3734 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
3735
812db3f7
LB		 3736 BIC_PRESENT(BIC_IRQ);
3737 BIC_PRESENT(BIC_TSC_MHz);
3738
3739 if (probe_nhm_msrs(family, model)) {
3740 do_nhm_platform_info = 1;
3741 BIC_PRESENT(BIC_CPU_c1);
3742 BIC_PRESENT(BIC_CPU_c3);
3743 BIC_PRESENT(BIC_CPU_c6);
3744 BIC_PRESENT(BIC_SMI);
3745 }
d7899447 3746 do_snb_cstates = has_snb_msrs(family, model);
812db3f7
LB		 3747
3748 if (do_snb_cstates)
3749 BIC_PRESENT(BIC_CPU_c7);
3750
5a63426e 3751 do_irtl_snb = has_snb_msrs(family, model);
ee7e38e3
LB		 3752 do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2);
3753 do_pc3 = (pkg_cstate_limit >= PCL__3);
3754 do_pc6 = (pkg_cstate_limit >= PCL__6);
3755 do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7);
0539ba11
LB		 3756 if (has_slv_msrs(family, model)) {
3757 do_pc2 = do_pc3 = do_pc7 = 0;
3758 do_pc6 = 1;
3759 BIC_PRESENT(BIC_Mod_c6);
3760 use_c1_residency_msr = 1;
3761 }
d7899447 3762 do_c8_c9_c10 = has_hsw_msrs(family, model);
5a63426e 3763 do_irtl_hsw = has_hsw_msrs(family, model);
0b2bb692 3764 do_skl_residency = has_skl_msrs(family, model);
144b44b1 3765 do_slm_cstates = is_slm(family, model);
fb5d4327 3766 do_knl_cstates = is_knl(family, model);
103a8fea 3767
f0057310
LB		 3768 if (debug)
3769 decode_misc_pwr_mgmt_msr();
3770
71616c8e
LB		 3771 if (debug && has_slv_msrs(family, model))
3772 decode_c6_demotion_policy_msr();
3773
889facbe 3774 rapl_probe(family, model);
3a9a941d 3775 perf_limit_reasons_probe(family, model);
889facbe 3776
fcd17211 3777 if (debug)
1b69317d 3778 dump_cstate_pstate_config_info(family, model);
fcd17211 3779
a2b7b749
LB		 3780 if (has_skl_msrs(family, model))
3781 calculate_tsc_tweak();
3782
812db3f7
LB		 3783 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK))
3784 BIC_PRESENT(BIC_GFX_rc6);
fdf676e5 3785
812db3f7
LB		 3786 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK))
3787 BIC_PRESENT(BIC_GFXMHz);
27d47356 3788
889facbe 3789 return;
103a8fea
LB		 3790}
3791
d8af6f5f 3792void help()
103a8fea 3793{
b7d8c148 3794 fprintf(outf,
d8af6f5f
LB		 3795 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
3796 "\n"
3797 "Turbostat forks the specified COMMAND and prints statistics\n"
3798 "when COMMAND completes.\n"
3799 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
3800 "to print statistics, until interrupted.\n"
388e9c81
LB		 3801 "--add add a counter\n"
3802 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n"
d8af6f5f
LB		 3803 "--debug run in \"debug\" mode\n"
3804 "--interval sec Override default 5-second measurement interval\n"
3805 "--help print this help message\n"
b7d8c148 3806 "--out file create or truncate \"file\" for all output\n"
d8af6f5f
LB		 3807 "--version print version information\n"
3808 "\n"
3809 "For more help, run \"man turbostat\"\n");
103a8fea
LB		 3810}
3811
3812
3813/*
3814 * in /dev/cpu/ return success for names that are numbers
3815 * ie. filter out ".", "..", "microcode".
3816 */
3817int dir_filter(const struct dirent *dirp)
3818{
3819 if (isdigit(dirp->d_name[0]))
3820 return 1;
3821 else
3822 return 0;
3823}
3824
3825int open_dev_cpu_msr(int dummy1)
3826{
3827 return 0;
3828}
3829
c98d5d94
LB		 3830void topology_probe()
3831{
3832 int i;
3833 int max_core_id = 0;
3834 int max_package_id = 0;
3835 int max_siblings = 0;
3836 struct cpu_topology {
3837 int core_id;
3838 int physical_package_id;
3839 } *cpus;
3840
3841 /* Initialize num_cpus, max_cpu_num */
3842 topo.num_cpus = 0;
3843 topo.max_cpu_num = 0;
3844 for_all_proc_cpus(count_cpus);
3845 if (!summary_only && topo.num_cpus > 1)
812db3f7 3846 BIC_PRESENT(BIC_CPU);
c98d5d94 3847
d8af6f5f 3848 if (debug > 1)
b7d8c148 3849 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
c98d5d94
LB		 3850
3851 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology));
b2c95d90
JT		 3852 if (cpus == NULL)
3853 err(1, "calloc cpus");
c98d5d94
LB		 3854
3855 /*
3856 * Allocate and initialize cpu_present_set
3857 */
3858 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
b2c95d90
JT		 3859 if (cpu_present_set == NULL)
3860 err(3, "CPU_ALLOC");
c98d5d94
LB		 3861 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
3862 CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
3863 for_all_proc_cpus(mark_cpu_present);
3864
3865 /*
3866 * Allocate and initialize cpu_affinity_set
3867 */
3868 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
b2c95d90
JT		 3869 if (cpu_affinity_set == NULL)
3870 err(3, "CPU_ALLOC");
c98d5d94
LB		 3871 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
3872 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
3873
3874
3875 /*
3876 * For online cpus
3877 * find max_core_id, max_package_id
3878 */
3879 for (i = 0; i <= topo.max_cpu_num; ++i) {
3880 int siblings;
3881
3882 if (cpu_is_not_present(i)) {
d8af6f5f 3883 if (debug > 1)
b7d8c148 3884 fprintf(outf, "cpu%d NOT PRESENT\n", i);
c98d5d94
LB		 3885 continue;
3886 }
3887 cpus[i].core_id = get_core_id(i);
3888 if (cpus[i].core_id > max_core_id)
3889 max_core_id = cpus[i].core_id;
3890
3891 cpus[i].physical_package_id = get_physical_package_id(i);
3892 if (cpus[i].physical_package_id > max_package_id)
3893 max_package_id = cpus[i].physical_package_id;
3894
3895 siblings = get_num_ht_siblings(i);
3896 if (siblings > max_siblings)
3897 max_siblings = siblings;
d8af6f5f 3898 if (debug > 1)
b7d8c148 3899 fprintf(outf, "cpu %d pkg %d core %d\n",
c98d5d94
LB		 3900 i, cpus[i].physical_package_id, cpus[i].core_id);
3901 }
3902 topo.num_cores_per_pkg = max_core_id + 1;
d8af6f5f 3903 if (debug > 1)
b7d8c148 3904 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n",
c98d5d94 3905 max_core_id, topo.num_cores_per_pkg);
1cc21f7b 3906 if (debug && !summary_only && topo.num_cores_per_pkg > 1)
812db3f7 3907 BIC_PRESENT(BIC_Core);
c98d5d94
LB		 3908
3909 topo.num_packages = max_package_id + 1;
d8af6f5f 3910 if (debug > 1)
b7d8c148 3911 fprintf(outf, "max_package_id %d, sizing for %d packages\n",
c98d5d94 3912 max_package_id, topo.num_packages);
1cc21f7b 3913 if (debug && !summary_only && topo.num_packages > 1)
812db3f7 3914 BIC_PRESENT(BIC_Package);
c98d5d94
LB		 3915
3916 topo.num_threads_per_core = max_siblings;
d8af6f5f 3917 if (debug > 1)
b7d8c148 3918 fprintf(outf, "max_siblings %d\n", max_siblings);
c98d5d94
LB		 3919
3920 free(cpus);
3921}
3922
3923void
3924allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p)
3925{
3926 int i;
3927
3928 *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg *
678a3bd1 3929 topo.num_packages, sizeof(struct thread_data));
c98d5d94
LB		 3930 if (*t == NULL)
3931 goto error;
3932
3933 for (i = 0; i < topo.num_threads_per_core *
3934 topo.num_cores_per_pkg * topo.num_packages; i++)
3935 (*t)[i].cpu_id = -1;
3936
3937 *c = calloc(topo.num_cores_per_pkg * topo.num_packages,
678a3bd1 3938 sizeof(struct core_data));
c98d5d94
LB		 3939 if (*c == NULL)
3940 goto error;
3941
3942 for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++)
3943 (*c)[i].core_id = -1;
3944
678a3bd1 3945 *p = calloc(topo.num_packages, sizeof(struct pkg_data));
c98d5d94
LB		 3946 if (*p == NULL)
3947 goto error;
3948
3949 for (i = 0; i < topo.num_packages; i++)
3950 (*p)[i].package_id = i;
3951
3952 return;
3953error:
b2c95d90 3954 err(1, "calloc counters");
c98d5d94
LB		 3955}
3956/*
3957 * init_counter()
3958 *
3959 * set cpu_id, core_num, pkg_num
3960 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
3961 *
3962 * increment topo.num_cores when 1st core in pkg seen
3963 */
3964void init_counter(struct thread_data *thread_base, struct core_data *core_base,
3965 struct pkg_data *pkg_base, int thread_num, int core_num,
3966 int pkg_num, int cpu_id)
3967{
3968 struct thread_data *t;
3969 struct core_data *c;
3970 struct pkg_data *p;
3971
3972 t = GET_THREAD(thread_base, thread_num, core_num, pkg_num);
3973 c = GET_CORE(core_base, core_num, pkg_num);
3974 p = GET_PKG(pkg_base, pkg_num);
3975
3976 t->cpu_id = cpu_id;
3977 if (thread_num == 0) {
3978 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE;
3979 if (cpu_is_first_core_in_package(cpu_id))
3980 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE;
3981 }
3982
3983 c->core_id = core_num;
3984 p->package_id = pkg_num;
3985}
3986
3987
3988int initialize_counters(int cpu_id)
3989{
3990 int my_thread_id, my_core_id, my_package_id;
3991
3992 my_package_id = get_physical_package_id(cpu_id);
3993 my_core_id = get_core_id(cpu_id);
e275b388
DC		 3994 my_thread_id = get_cpu_position_in_core(cpu_id);
3995 if (!my_thread_id)
c98d5d94 3996 topo.num_cores++;
c98d5d94
LB		 3997
3998 init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
3999 init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
4000 return 0;
4001}
4002
4003void allocate_output_buffer()
4004{
3b4d5c7f 4005 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024);
c98d5d94 4006 outp = output_buffer;
b2c95d90
JT		 4007 if (outp == NULL)
4008 err(-1, "calloc output buffer");
c98d5d94 4009}
36229897
LB		 4010void allocate_fd_percpu(void)
4011{
01a67adf 4012 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
36229897
LB		 4013 if (fd_percpu == NULL)
4014 err(-1, "calloc fd_percpu");
4015}
562a2d37
LB		 4016void allocate_irq_buffers(void)
4017{
4018 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int));
4019 if (irq_column_2_cpu == NULL)
4020 err(-1, "calloc %d", topo.num_cpus);
c98d5d94 4021
01a67adf 4022 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int));
562a2d37 4023 if (irqs_per_cpu == NULL)
01a67adf 4024 err(-1, "calloc %d", topo.max_cpu_num + 1);
562a2d37 4025}
c98d5d94
LB		 4026void setup_all_buffers(void)
4027{
4028 topology_probe();
562a2d37 4029 allocate_irq_buffers();
36229897 4030 allocate_fd_percpu();
c98d5d94
LB		 4031 allocate_counters(&thread_even, &core_even, &package_even);
4032 allocate_counters(&thread_odd, &core_odd, &package_odd);
4033 allocate_output_buffer();
4034 for_all_proc_cpus(initialize_counters);
4035}
3b4d5c7f 4036
7ce7d5de
PB		 4037void set_base_cpu(void)
4038{
4039 base_cpu = sched_getcpu();
4040 if (base_cpu < 0)
4041 err(-ENODEV, "No valid cpus found");
4042
4043 if (debug > 1)
b7d8c148 4044 fprintf(outf, "base_cpu = %d\n", base_cpu);
7ce7d5de
PB		 4045}
4046
103a8fea
LB		 4047void turbostat_init()
4048{
7ce7d5de
PB		 4049 setup_all_buffers();
4050 set_base_cpu();
103a8fea 4051 check_dev_msr();
98481e79 4052 check_permissions();
fcd17211 4053 process_cpuid();
103a8fea 4054
103a8fea 4055
7f5c258e
LB		 4056 if (debug)
4057 for_all_cpus(print_hwp, ODD_COUNTERS);
4058
d8af6f5f 4059 if (debug)
889facbe
LB		 4060 for_all_cpus(print_epb, ODD_COUNTERS);
4061
d8af6f5f 4062 if (debug)
3a9a941d
LB		 4063 for_all_cpus(print_perf_limit, ODD_COUNTERS);
4064
d8af6f5f 4065 if (debug)
889facbe
LB		 4066 for_all_cpus(print_rapl, ODD_COUNTERS);
4067
4068 for_all_cpus(set_temperature_target, ODD_COUNTERS);
4069
d8af6f5f 4070 if (debug)
889facbe 4071 for_all_cpus(print_thermal, ODD_COUNTERS);
5a63426e
LB		 4072
4073 if (debug && do_irtl_snb)
4074 print_irtl();
103a8fea
LB		 4075}
4076
4077int fork_it(char **argv)
4078{
103a8fea 4079 pid_t child_pid;
d91bb17c 4080 int status;
d15cf7c1 4081
d91bb17c
LB		 4082 status = for_all_cpus(get_counters, EVEN_COUNTERS);
4083 if (status)
4084 exit(status);
c98d5d94
LB		 4085 /* clear affinity side-effect of get_counters() */
4086 sched_setaffinity(0, cpu_present_setsize, cpu_present_set);
103a8fea
LB		 4087 gettimeofday(&tv_even, (struct timezone *)NULL);
4088
4089 child_pid = fork();
4090 if (!child_pid) {
4091 /* child */
4092 execvp(argv[0], argv);
4093 } else {
103a8fea
LB		 4094
4095 /* parent */
b2c95d90
JT		 4096 if (child_pid == -1)
4097 err(1, "fork");
103a8fea
LB		 4098
4099 signal(SIGINT, SIG_IGN);
4100 signal(SIGQUIT, SIG_IGN);
b2c95d90
JT		 4101 if (waitpid(child_pid, &status, 0) == -1)
4102 err(status, "waitpid");
103a8fea 4103 }
c98d5d94
LB		 4104 /*
4105 * n.b. fork_it() does not check for errors from for_all_cpus()
4106 * because re-starting is problematic when forking
4107 */
4108 for_all_cpus(get_counters, ODD_COUNTERS);
103a8fea 4109 gettimeofday(&tv_odd, (struct timezone *)NULL);
103a8fea 4110 timersub(&tv_odd, &tv_even, &tv_delta);
ba3dec99
LB		 4111 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS))
4112 fprintf(outf, "%s: Counter reset detected\n", progname);
4113 else {
4114 compute_average(EVEN_COUNTERS);
4115 format_all_counters(EVEN_COUNTERS);
4116 }
103a8fea 4117
b7d8c148
LB		 4118 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0);
4119
4120 flush_output_stderr();
103a8fea 4121
d91bb17c 4122 return status;
103a8fea
LB		 4123}
4124
3b4d5c7f
AS		 4125int get_and_dump_counters(void)
4126{
4127 int status;
4128
4129 status = for_all_cpus(get_counters, ODD_COUNTERS);
4130 if (status)
4131 return status;
4132
4133 status = for_all_cpus(dump_counters, ODD_COUNTERS);
4134 if (status)
4135 return status;
4136
b7d8c148 4137 flush_output_stdout();
3b4d5c7f
AS		 4138
4139 return status;
4140}
4141
d8af6f5f 4142void print_version() {
0539ba11 4143 fprintf(outf, "turbostat version 4.17 10 Jan 2017"
d8af6f5f
LB		 4144 " - Len Brown <lenb@kernel.org>\n");
4145}
4146
388e9c81
LB		 4147int add_counter(unsigned int msr_num, char *name, unsigned int width,
4148 enum counter_scope scope, enum counter_type type,
4149 enum counter_format format)
4150{
4151 struct msr_counter *msrp;
4152
4153 msrp = calloc(1, sizeof(struct msr_counter));
4154 if (msrp == NULL) {
4155 perror("calloc");
4156 exit(1);
4157 }
4158
4159 msrp->msr_num = msr_num;
4160 strncpy(msrp->name, name, NAME_BYTES);
4161 msrp->width = width;
4162 msrp->type = type;
4163 msrp->format = format;
4164
4165 switch (scope) {
4166
4167 case SCOPE_CPU:
388e9c81
LB		 4168 msrp->next = sys.tp;
4169 sys.tp = msrp;
678a3bd1
LB		 4170 sys.added_thread_counters++;
4171 if (sys.added_thread_counters > MAX_ADDED_COUNTERS) {
4172 fprintf(stderr, "exceeded max %d added thread counters\n",
4173 MAX_ADDED_COUNTERS);
4174 exit(-1);
4175 }
388e9c81
LB		 4176 break;
4177
4178 case SCOPE_CORE:
388e9c81
LB		 4179 msrp->next = sys.cp;
4180 sys.cp = msrp;
678a3bd1
LB		 4181 sys.added_core_counters++;
4182 if (sys.added_core_counters > MAX_ADDED_COUNTERS) {
4183 fprintf(stderr, "exceeded max %d added core counters\n",
4184 MAX_ADDED_COUNTERS);
4185 exit(-1);
4186 }
388e9c81
LB		 4187 break;
4188
4189 case SCOPE_PACKAGE:
388e9c81
LB		 4190 msrp->next = sys.pp;
4191 sys.pp = msrp;
678a3bd1
LB		 4192 sys.added_package_counters++;
4193 if (sys.added_package_counters > MAX_ADDED_COUNTERS) {
4194 fprintf(stderr, "exceeded max %d added package counters\n",
4195 MAX_ADDED_COUNTERS);
4196 exit(-1);
4197 }
388e9c81
LB		 4198 break;
4199 }
4200
4201 return 0;
4202}
4203
4204void parse_add_command(char *add_command)
4205{
4206 int msr_num = 0;
4207 char name_buffer[NAME_BYTES];
4208 int width = 64;
4209 int fail = 0;
4210 enum counter_scope scope = SCOPE_CPU;
4211 enum counter_type type = COUNTER_CYCLES;
4212 enum counter_format format = FORMAT_DELTA;
4213
4214 while (add_command) {
4215
4216 if (sscanf(add_command, "msr0x%x", &msr_num) == 1)
4217 goto next;
4218
4219 if (sscanf(add_command, "msr%d", &msr_num) == 1)
4220 goto next;
4221
4222 if (sscanf(add_command, "u%d", &width) == 1) {
4223 if ((width == 32) || (width == 64))
4224 goto next;
4225 width = 64;
4226 }
4227 if (!strncmp(add_command, "cpu", strlen("cpu"))) {
4228 scope = SCOPE_CPU;
4229 goto next;
4230 }
4231 if (!strncmp(add_command, "core", strlen("core"))) {
4232 scope = SCOPE_CORE;
4233 goto next;
4234 }
4235 if (!strncmp(add_command, "package", strlen("package"))) {
4236 scope = SCOPE_PACKAGE;
4237 goto next;
4238 }
4239 if (!strncmp(add_command, "cycles", strlen("cycles"))) {
4240 type = COUNTER_CYCLES;
4241 goto next;
4242 }
4243 if (!strncmp(add_command, "seconds", strlen("seconds"))) {
4244 type = COUNTER_SECONDS;
4245 goto next;
4246 }
4247 if (!strncmp(add_command, "raw", strlen("raw"))) {
4248 format = FORMAT_RAW;
4249 goto next;
4250 }
4251 if (!strncmp(add_command, "delta", strlen("delta"))) {
4252 format = FORMAT_DELTA;
4253 goto next;
4254 }
4255 if (!strncmp(add_command, "percent", strlen("percent"))) {
4256 format = FORMAT_PERCENT;
4257 goto next;
4258 }
4259
4260 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */
4261 char *eos;
4262
4263 eos = strchr(name_buffer, ',');
4264 if (eos)
4265 *eos = '\0';
4266 goto next;
4267 }
4268
4269next:
4270 add_command = strchr(add_command, ',');
4271 if (add_command)
4272 add_command++;
4273
4274 }
4275 if (msr_num == 0) {
4276 fprintf(stderr, "--add: (msrDDD | msr0xXXX) required\n");
4277 fail++;
4278 }
4279
4280 /* generate default column header */
4281 if (*name_buffer == '\0') {
4282 if (format == FORMAT_RAW) {
4283 if (width == 32)
4284 sprintf(name_buffer, "msr%d", msr_num);
4285 else
4286 sprintf(name_buffer, "MSR%d", msr_num);
4287 } else if (format == FORMAT_DELTA) {
4288 if (width == 32)
4289 sprintf(name_buffer, "cnt%d", msr_num);
4290 else
4291 sprintf(name_buffer, "CNT%d", msr_num);
4292 } else if (format == FORMAT_PERCENT) {
4293 if (width == 32)
4294 sprintf(name_buffer, "msr%d%%", msr_num);
4295 else
4296 sprintf(name_buffer, "MSR%d%%", msr_num);
4297 }
4298 }
4299
4300 if (add_counter(msr_num, name_buffer, width, scope, type, format))
4301 fail++;
4302
4303 if (fail) {
4304 help();
4305 exit(1);
4306 }
4307}
812db3f7
LB		 4308/*
4309 * HIDE_LIST - hide this list of counters, show the rest [default]
4310 * SHOW_LIST - show this list of counters, hide the rest
4311 */
4312enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST;
4313
4314int shown;
4315/*
4316 * parse_show_hide() - process cmdline to set default counter action
4317 */
4318void parse_show_hide(char *optarg, enum show_hide_mode new_mode)
4319{
4320 /*
4321 * --show: show only those specified
4322 * The 1st invocation will clear and replace the enabled mask
4323 * subsequent invocations can add to it.
4324 */
4325 if (new_mode == SHOW_LIST) {
4326 if (shown == 0)
4327 bic_enabled = bic_lookup(optarg);
4328 else
4329 bic_enabled |= bic_lookup(optarg);
4330 shown = 1;
4331
4332 return;
4333 }
4334
4335 /*
4336 * --hide: do not show those specified
4337 * multiple invocations simply clear more bits in enabled mask
4338 */
4339 bic_enabled &= ~bic_lookup(optarg);
4340}
4341
103a8fea
LB		 4342void cmdline(int argc, char **argv)
4343{
4344 int opt;
d8af6f5f
LB		 4345 int option_index = 0;
4346 static struct option long_options[] = {
388e9c81 4347 {"add", required_argument, 0, 'a'},
d8af6f5f
LB		 4348 {"Dump", no_argument, 0, 'D'},
4349 {"debug", no_argument, 0, 'd'},
4350 {"interval", required_argument, 0, 'i'},
4351 {"help", no_argument, 0, 'h'},
812db3f7 4352 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help
d8af6f5f 4353 {"Joules", no_argument, 0, 'J'},
b7d8c148 4354 {"out", required_argument, 0, 'o'},
d8af6f5f
LB		 4355 {"Package", no_argument, 0, 'p'},
4356 {"processor", no_argument, 0, 'p'},
812db3f7 4357 {"show", required_argument, 0, 's'},
d8af6f5f
LB		 4358 {"Summary", no_argument, 0, 'S'},
4359 {"TCC", required_argument, 0, 'T'},
4360 {"version", no_argument, 0, 'v' },
4361 {0, 0, 0, 0 }
4362 };
103a8fea
LB		 4363
4364 progname = argv[0];
4365
b7d8c148 4366 while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:PpST:v",
d8af6f5f 4367 long_options, &option_index)) != -1) {
103a8fea 4368 switch (opt) {
388e9c81
LB		 4369 case 'a':
4370 parse_add_command(optarg);
4371 break;
d8af6f5f 4372 case 'D':
3b4d5c7f
AS		 4373 dump_only++;
4374 break;
d8af6f5f
LB		 4375 case 'd':
4376 debug++;
103a8fea 4377 break;
812db3f7
LB		 4378 case 'H':
4379 parse_show_hide(optarg, HIDE_LIST);
4380 break;
d8af6f5f
LB		 4381 case 'h':
4382 default:
4383 help();
4384 exit(1);
103a8fea 4385 case 'i':
2a0609c0
LB		 4386 {
4387 double interval = strtod(optarg, NULL);
4388
4389 if (interval < 0.001) {
b7d8c148 4390 fprintf(outf, "interval %f seconds is too small\n",
2a0609c0
LB		 4391 interval);
4392 exit(2);
4393 }
4394
4395 interval_ts.tv_sec = interval;
4396 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
4397 }
103a8fea 4398 break;
d8af6f5f
LB		 4399 case 'J':
4400 rapl_joules++;
8e180f3c 4401 break;
b7d8c148
LB		 4402 case 'o':
4403 outf = fopen_or_die(optarg, "w");
4404 break;
d8af6f5f
LB		 4405 case 'P':
4406 show_pkg_only++;
4407 break;
4408 case 'p':
4409 show_core_only++;
103a8fea 4410 break;
812db3f7
LB		 4411 case 's':
4412 parse_show_hide(optarg, SHOW_LIST);
4413 break;
d8af6f5f
LB		 4414 case 'S':
4415 summary_only++;
889facbe
LB		 4416 break;
4417 case 'T':
4418 tcc_activation_temp_override = atoi(optarg);
4419 break;
d8af6f5f
LB		 4420 case 'v':
4421 print_version();
4422 exit(0);
5c56be9a 4423 break;
103a8fea
LB		 4424 }
4425 }
4426}
4427
4428int main(int argc, char **argv)
4429{
b7d8c148
LB		 4430 outf = stderr;
4431
103a8fea
LB		 4432 cmdline(argc, argv);
4433
d8af6f5f
LB		 4434 if (debug)
4435 print_version();
103a8fea
LB		 4436
4437 turbostat_init();
4438
3b4d5c7f
AS		 4439 /* dump counters and exit */
4440 if (dump_only)
4441 return get_and_dump_counters();
4442
103a8fea
LB		 4443 /*
4444 * if any params left, it must be a command to fork
4445 */
4446 if (argc - optind)
4447 return fork_it(argv + optind);
4448 else
4449 turbostat_loop();
4450
4451 return 0;
4452}
Linux 6.x block layer and io_uring tree(s)