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tools/power turbostat: extend --add option to accept /sys path
[linux-block.git] / tools / power / x86 / turbostat / turbostat.c
CommitLineData
103a8fea
LB		 1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
144b44b1 5 * Copyright (c) 2013 Intel Corporation.
103a8fea
LB		 6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
88c3281f 22#define _GNU_SOURCE
b731f311 23#include MSRHEADER
869ce69e 24#include INTEL_FAMILY_HEADER
95aebc44 25#include <stdarg.h>
103a8fea 26#include <stdio.h>
b2c95d90 27#include <err.h>
103a8fea
LB		 28#include <unistd.h>
29#include <sys/types.h>
30#include <sys/wait.h>
31#include <sys/stat.h>
32#include <sys/resource.h>
33#include <fcntl.h>
34#include <signal.h>
35#include <sys/time.h>
36#include <stdlib.h>
d8af6f5f 37#include <getopt.h>
103a8fea
LB		 38#include <dirent.h>
39#include <string.h>
40#include <ctype.h>
88c3281f 41#include <sched.h>
2a0609c0 42#include <time.h>
2b92865e 43#include <cpuid.h>
98481e79
LB		 44#include <linux/capability.h>
45#include <errno.h>
103a8fea 46
103a8fea 47char *proc_stat = "/proc/stat";
b7d8c148 48FILE *outf;
36229897 49int *fd_percpu;
2a0609c0 50struct timespec interval_ts = {5, 0};
d8af6f5f 51unsigned int debug;
96e47158 52unsigned int quiet;
d8af6f5f
LB		 53unsigned int rapl_joules;
54unsigned int summary_only;
55unsigned int dump_only;
103a8fea 56unsigned int do_snb_cstates;
fb5d4327 57unsigned int do_knl_cstates;
0b2bb692 58unsigned int do_skl_residency;
144b44b1
LB		 59unsigned int do_slm_cstates;
60unsigned int use_c1_residency_msr;
103a8fea 61unsigned int has_aperf;
889facbe 62unsigned int has_epb;
5a63426e
LB		 63unsigned int do_irtl_snb;
64unsigned int do_irtl_hsw;
fc04cc67 65unsigned int units = 1000000; /* MHz etc */
103a8fea
LB		 66unsigned int genuine_intel;
67unsigned int has_invariant_tsc;
d7899447 68unsigned int do_nhm_platform_info;
cf4cbe53 69unsigned int no_MSR_MISC_PWR_MGMT;
b2b34dfe 70unsigned int aperf_mperf_multiplier = 1;
103a8fea 71double bclk;
a2b7b749 72double base_hz;
21ed5574 73unsigned int has_base_hz;
a2b7b749 74double tsc_tweak = 1.0;
c98d5d94
LB		 75unsigned int show_pkg_only;
76unsigned int show_core_only;
77char *output_buffer, *outp;
889facbe
LB		 78unsigned int do_rapl;
79unsigned int do_dts;
80unsigned int do_ptm;
fdf676e5 81unsigned long long gfx_cur_rc6_ms;
27d47356 82unsigned int gfx_cur_mhz;
889facbe
LB		 83unsigned int tcc_activation_temp;
84unsigned int tcc_activation_temp_override;
40ee8e3b
AS		 85double rapl_power_units, rapl_time_units;
86double rapl_dram_energy_units, rapl_energy_units;
889facbe 87double rapl_joule_counter_range;
3a9a941d
LB		 88unsigned int do_core_perf_limit_reasons;
89unsigned int do_gfx_perf_limit_reasons;
90unsigned int do_ring_perf_limit_reasons;
8a5bdf41
LB		 91unsigned int crystal_hz;
92unsigned long long tsc_hz;
7ce7d5de 93int base_cpu;
21ed5574 94double discover_bclk(unsigned int family, unsigned int model);
7f5c258e
LB		 95unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
96 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
97unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */
98unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
99unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
100unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
33148d67 101unsigned int has_misc_feature_control;
889facbe 102
e6f9bb3c
LB		 103#define RAPL_PKG (1 << 0)
104 /* 0x610 MSR_PKG_POWER_LIMIT */
105 /* 0x611 MSR_PKG_ENERGY_STATUS */
106#define RAPL_PKG_PERF_STATUS (1 << 1)
107 /* 0x613 MSR_PKG_PERF_STATUS */
108#define RAPL_PKG_POWER_INFO (1 << 2)
109 /* 0x614 MSR_PKG_POWER_INFO */
110
111#define RAPL_DRAM (1 << 3)
112 /* 0x618 MSR_DRAM_POWER_LIMIT */
113 /* 0x619 MSR_DRAM_ENERGY_STATUS */
e6f9bb3c
LB		 114#define RAPL_DRAM_PERF_STATUS (1 << 4)
115 /* 0x61b MSR_DRAM_PERF_STATUS */
0b2bb692
LB		 116#define RAPL_DRAM_POWER_INFO (1 << 5)
117 /* 0x61c MSR_DRAM_POWER_INFO */
e6f9bb3c 118
9148494c 119#define RAPL_CORES_POWER_LIMIT (1 << 6)
e6f9bb3c 120 /* 0x638 MSR_PP0_POWER_LIMIT */
0b2bb692 121#define RAPL_CORE_POLICY (1 << 7)
e6f9bb3c
LB		 122 /* 0x63a MSR_PP0_POLICY */
123
0b2bb692 124#define RAPL_GFX (1 << 8)
e6f9bb3c
LB		 125 /* 0x640 MSR_PP1_POWER_LIMIT */
126 /* 0x641 MSR_PP1_ENERGY_STATUS */
127 /* 0x642 MSR_PP1_POLICY */
9148494c
JP		 128
129#define RAPL_CORES_ENERGY_STATUS (1 << 9)
130 /* 0x639 MSR_PP0_ENERGY_STATUS */
131#define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
889facbe
LB		 132#define TJMAX_DEFAULT 100
133
134#define MAX(a, b) ((a) > (b) ? (a) : (b))
103a8fea 135
388e9c81
LB		 136/*
137 * buffer size used by sscanf() for added column names
138 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
139 */
140#define NAME_BYTES 20
495c7654 141#define PATH_BYTES 128
388e9c81 142
103a8fea
LB		 143int backwards_count;
144char *progname;
103a8fea 145
c98d5d94
LB		 146cpu_set_t *cpu_present_set, *cpu_affinity_set;
147size_t cpu_present_setsize, cpu_affinity_setsize;
678a3bd1 148#define MAX_ADDED_COUNTERS 16
c98d5d94
LB		 149
150struct thread_data {
151 unsigned long long tsc;
152 unsigned long long aperf;
153 unsigned long long mperf;
144b44b1 154 unsigned long long c1;
562a2d37 155 unsigned int irq_count;
1ed51011 156 unsigned int smi_count;
c98d5d94
LB		 157 unsigned int cpu_id;
158 unsigned int flags;
159#define CPU_IS_FIRST_THREAD_IN_CORE 0x2
160#define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
678a3bd1 161 unsigned long long counter[MAX_ADDED_COUNTERS];
c98d5d94
LB		 162} *thread_even, *thread_odd;
163
164struct core_data {
165 unsigned long long c3;
166 unsigned long long c6;
167 unsigned long long c7;
0539ba11 168 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */
889facbe 169 unsigned int core_temp_c;
c98d5d94 170 unsigned int core_id;
678a3bd1 171 unsigned long long counter[MAX_ADDED_COUNTERS];
c98d5d94
LB		 172} *core_even, *core_odd;
173
174struct pkg_data {
175 unsigned long long pc2;
176 unsigned long long pc3;
177 unsigned long long pc6;
178 unsigned long long pc7;
ca58710f
KCA		 179 unsigned long long pc8;
180 unsigned long long pc9;
181 unsigned long long pc10;
0b2bb692
LB		 182 unsigned long long pkg_wtd_core_c0;
183 unsigned long long pkg_any_core_c0;
184 unsigned long long pkg_any_gfxe_c0;
185 unsigned long long pkg_both_core_gfxe_c0;
9185e988 186 long long gfx_rc6_ms;
27d47356 187 unsigned int gfx_mhz;
c98d5d94 188 unsigned int package_id;
889facbe
LB		 189 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */
190 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */
191 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */
192 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */
193 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
194 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
195 unsigned int pkg_temp_c;
678a3bd1 196 unsigned long long counter[MAX_ADDED_COUNTERS];
c98d5d94
LB		 197} *package_even, *package_odd;
198
199#define ODD_COUNTERS thread_odd, core_odd, package_odd
200#define EVEN_COUNTERS thread_even, core_even, package_even
201
202#define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \
203 (thread_base + (pkg_no) * topo.num_cores_per_pkg * \
204 topo.num_threads_per_core + \
205 (core_no) * topo.num_threads_per_core + (thread_no))
206#define GET_CORE(core_base, core_no, pkg_no) \
207 (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no))
208#define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
209
388e9c81
LB		 210enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE};
211enum counter_type {COUNTER_CYCLES, COUNTER_SECONDS};
212enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT};
213
214struct msr_counter {
215 unsigned int msr_num;
216 char name[NAME_BYTES];
495c7654 217 char path[PATH_BYTES];
388e9c81
LB		 218 unsigned int width;
219 enum counter_type type;
220 enum counter_format format;
221 struct msr_counter *next;
812db3f7
LB		 222 unsigned int flags;
223#define FLAGS_HIDE (1 << 0)
224#define FLAGS_SHOW (1 << 1)
388e9c81
LB		 225};
226
227struct sys_counters {
678a3bd1
LB		 228 unsigned int added_thread_counters;
229 unsigned int added_core_counters;
230 unsigned int added_package_counters;
388e9c81
LB		 231 struct msr_counter *tp;
232 struct msr_counter *cp;
233 struct msr_counter *pp;
234} sys;
235
c98d5d94
LB		 236struct system_summary {
237 struct thread_data threads;
238 struct core_data cores;
239 struct pkg_data packages;
388e9c81 240} average;
c98d5d94
LB		 241
242
243struct topo_params {
244 int num_packages;
245 int num_cpus;
246 int num_cores;
247 int max_cpu_num;
248 int num_cores_per_pkg;
249 int num_threads_per_core;
250} topo;
251
252struct timeval tv_even, tv_odd, tv_delta;
253
562a2d37
LB		 254int *irq_column_2_cpu; /* /proc/interrupts column numbers */
255int *irqs_per_cpu; /* indexed by cpu_num */
256
c98d5d94
LB		 257void setup_all_buffers(void);
258
259int cpu_is_not_present(int cpu)
d15cf7c1 260{
c98d5d94 261 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
d15cf7c1 262}
88c3281f 263/*
c98d5d94
LB		 264 * run func(thread, core, package) in topology order
265 * skip non-present cpus
88c3281f 266 */
c98d5d94
LB		 267
268int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *),
269 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
88c3281f 270{
c98d5d94 271 int retval, pkg_no, core_no, thread_no;
d15cf7c1 272
c98d5d94
LB		 273 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
274 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
275 for (thread_no = 0; thread_no <
276 topo.num_threads_per_core; ++thread_no) {
277 struct thread_data *t;
278 struct core_data *c;
279 struct pkg_data *p;
88c3281f 280
c98d5d94
LB		 281 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
282
283 if (cpu_is_not_present(t->cpu_id))
284 continue;
285
286 c = GET_CORE(core_base, core_no, pkg_no);
287 p = GET_PKG(pkg_base, pkg_no);
288
289 retval = func(t, c, p);
290 if (retval)
291 return retval;
292 }
293 }
294 }
295 return 0;
88c3281f
LB		 296}
297
298int cpu_migrate(int cpu)
299{
c98d5d94
LB		 300 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
301 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
302 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
88c3281f
LB		 303 return -1;
304 else
305 return 0;
306}
36229897 307int get_msr_fd(int cpu)
103a8fea 308{
103a8fea
LB		 309 char pathname[32];
310 int fd;
311
36229897
LB		 312 fd = fd_percpu[cpu];
313
314 if (fd)
315 return fd;
316
103a8fea
LB		 317 sprintf(pathname, "/dev/cpu/%d/msr", cpu);
318 fd = open(pathname, O_RDONLY);
15aaa346 319 if (fd < 0)
98481e79 320 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
103a8fea 321
36229897
LB		 322 fd_percpu[cpu] = fd;
323
324 return fd;
325}
326
327int get_msr(int cpu, off_t offset, unsigned long long *msr)
328{
329 ssize_t retval;
330
331 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
15aaa346 332
98481e79 333 if (retval != sizeof *msr)
cf4cbe53 334 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset);
15aaa346
LB		 335
336 return 0;
103a8fea
LB		 337}
338
fc04cc67 339/*
812db3f7
LB		 340 * Each string in this array is compared in --show and --hide cmdline.
341 * Thus, strings that are proper sub-sets must follow their more specific peers.
fc04cc67 342 */
812db3f7
LB		 343struct msr_counter bic[] = {
344 { 0x0, "Package" },
345 { 0x0, "Avg_MHz" },
346 { 0x0, "Bzy_MHz" },
347 { 0x0, "TSC_MHz" },
348 { 0x0, "IRQ" },
495c7654 349 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL},
812db3f7
LB		 350 { 0x0, "Busy%" },
351 { 0x0, "CPU%c1" },
352 { 0x0, "CPU%c3" },
353 { 0x0, "CPU%c6" },
354 { 0x0, "CPU%c7" },
355 { 0x0, "ThreadC" },
356 { 0x0, "CoreTmp" },
357 { 0x0, "CoreCnt" },
358 { 0x0, "PkgTmp" },
359 { 0x0, "GFX%rc6" },
360 { 0x0, "GFXMHz" },
361 { 0x0, "Pkg%pc2" },
362 { 0x0, "Pkg%pc3" },
363 { 0x0, "Pkg%pc6" },
364 { 0x0, "Pkg%pc7" },
0f47c08d
LB		 365 { 0x0, "Pkg%pc8" },
366 { 0x0, "Pkg%pc9" },
367 { 0x0, "Pkg%pc10" },
812db3f7
LB		 368 { 0x0, "PkgWatt" },
369 { 0x0, "CorWatt" },
370 { 0x0, "GFXWatt" },
371 { 0x0, "PkgCnt" },
372 { 0x0, "RAMWatt" },
373 { 0x0, "PKG_%" },
374 { 0x0, "RAM_%" },
375 { 0x0, "Pkg_J" },
376 { 0x0, "Cor_J" },
377 { 0x0, "GFX_J" },
378 { 0x0, "RAM_J" },
379 { 0x0, "Core" },
380 { 0x0, "CPU" },
0539ba11 381 { 0x0, "Mod%c6" },
812db3f7
LB		 382};
383
384#define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
385#define BIC_Package (1ULL << 0)
386#define BIC_Avg_MHz (1ULL << 1)
387#define BIC_Bzy_MHz (1ULL << 2)
388#define BIC_TSC_MHz (1ULL << 3)
389#define BIC_IRQ (1ULL << 4)
390#define BIC_SMI (1ULL << 5)
391#define BIC_Busy (1ULL << 6)
392#define BIC_CPU_c1 (1ULL << 7)
393#define BIC_CPU_c3 (1ULL << 8)
394#define BIC_CPU_c6 (1ULL << 9)
395#define BIC_CPU_c7 (1ULL << 10)
396#define BIC_ThreadC (1ULL << 11)
397#define BIC_CoreTmp (1ULL << 12)
398#define BIC_CoreCnt (1ULL << 13)
399#define BIC_PkgTmp (1ULL << 14)
400#define BIC_GFX_rc6 (1ULL << 15)
401#define BIC_GFXMHz (1ULL << 16)
402#define BIC_Pkgpc2 (1ULL << 17)
403#define BIC_Pkgpc3 (1ULL << 18)
404#define BIC_Pkgpc6 (1ULL << 19)
405#define BIC_Pkgpc7 (1ULL << 20)
0f47c08d
LB		 406#define BIC_Pkgpc8 (1ULL << 21)
407#define BIC_Pkgpc9 (1ULL << 22)
408#define BIC_Pkgpc10 (1ULL << 23)
409#define BIC_PkgWatt (1ULL << 24)
410#define BIC_CorWatt (1ULL << 25)
411#define BIC_GFXWatt (1ULL << 26)
412#define BIC_PkgCnt (1ULL << 27)
413#define BIC_RAMWatt (1ULL << 28)
414#define BIC_PKG__ (1ULL << 29)
415#define BIC_RAM__ (1ULL << 30)
416#define BIC_Pkg_J (1ULL << 31)
417#define BIC_Cor_J (1ULL << 32)
418#define BIC_GFX_J (1ULL << 33)
419#define BIC_RAM_J (1ULL << 34)
420#define BIC_Core (1ULL << 35)
421#define BIC_CPU (1ULL << 36)
422#define BIC_Mod_c6 (1ULL << 37)
812db3f7
LB		 423
424unsigned long long bic_enabled = 0xFFFFFFFFFFFFFFFFULL;
425unsigned long long bic_present;
426
427#define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME)
428#define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT)
0f47c08d 429#define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT)
812db3f7
LB		 430
431/*
432 * bic_lookup
433 * for all the strings in comma separate name_list,
434 * set the approprate bit in return value.
435 */
436unsigned long long bic_lookup(char *name_list)
437{
438 int i;
439 unsigned long long retval = 0;
440
441 while (name_list) {
442 char *comma;
443
444 comma = strchr(name_list, ',');
445
446 if (comma)
447 *comma = '\0';
448
449 for (i = 0; i < MAX_BIC; ++i) {
450 if (!strcmp(name_list, bic[i].name)) {
451 retval |= (1ULL << i);
452 break;
453 }
454 }
455 if (i == MAX_BIC) {
456 fprintf(stderr, "Invalid counter name: %s\n", name_list);
457 exit(-1);
458 }
459
460 name_list = comma;
461 if (name_list)
462 name_list++;
463
464 }
465 return retval;
466}
fc04cc67 467
a829eb4d 468void print_header(void)
103a8fea 469{
388e9c81
LB		 470 struct msr_counter *mp;
471
812db3f7 472 if (DO_BIC(BIC_Package))
3d109de2 473 outp += sprintf(outp, "\tPackage");
812db3f7 474 if (DO_BIC(BIC_Core))
3d109de2 475 outp += sprintf(outp, "\tCore");
812db3f7 476 if (DO_BIC(BIC_CPU))
3d109de2 477 outp += sprintf(outp, "\tCPU");
812db3f7 478 if (DO_BIC(BIC_Avg_MHz))
3d109de2 479 outp += sprintf(outp, "\tAvg_MHz");
812db3f7 480 if (DO_BIC(BIC_Busy))
3d109de2 481 outp += sprintf(outp, "\tBusy%%");
812db3f7 482 if (DO_BIC(BIC_Bzy_MHz))
3d109de2 483 outp += sprintf(outp, "\tBzy_MHz");
812db3f7
LB		 484 if (DO_BIC(BIC_TSC_MHz))
485 outp += sprintf(outp, "\tTSC_MHz");
1cc21f7b 486
812db3f7 487 if (DO_BIC(BIC_IRQ))
3d109de2 488 outp += sprintf(outp, "\tIRQ");
812db3f7 489 if (DO_BIC(BIC_SMI))
3d109de2 490 outp += sprintf(outp, "\tSMI");
1cc21f7b 491
812db3f7 492 if (DO_BIC(BIC_CPU_c1))
3d109de2 493 outp += sprintf(outp, "\tCPU%%c1");
889facbe 494
388e9c81
LB		 495 for (mp = sys.tp; mp; mp = mp->next) {
496 if (mp->format == FORMAT_RAW) {
497 if (mp->width == 64)
498 outp += sprintf(outp, "\t%18.18s", mp->name);
499 else
500 outp += sprintf(outp, "\t%10.10s", mp->name);
501 } else {
502 outp += sprintf(outp, "\t%-7.7s", mp->name);
503 }
504 }
505
812db3f7 506 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates)
678a3bd1 507 outp += sprintf(outp, "\tCPU%%c3");
812db3f7 508 if (DO_BIC(BIC_CPU_c6))
678a3bd1 509 outp += sprintf(outp, "\tCPU%%c6");
812db3f7 510 if (DO_BIC(BIC_CPU_c7))
678a3bd1
LB		 511 outp += sprintf(outp, "\tCPU%%c7");
512
0539ba11
LB		 513 if (DO_BIC(BIC_Mod_c6))
514 outp += sprintf(outp, "\tMod%%c6");
678a3bd1 515
812db3f7 516 if (DO_BIC(BIC_CoreTmp))
3d109de2 517 outp += sprintf(outp, "\tCoreTmp");
388e9c81
LB		 518
519 for (mp = sys.cp; mp; mp = mp->next) {
520 if (mp->format == FORMAT_RAW) {
521 if (mp->width == 64)
522 outp += sprintf(outp, "\t%18.18s", mp->name);
523 else
524 outp += sprintf(outp, "\t%10.10s", mp->name);
525 } else {
526 outp += sprintf(outp, "\t%-7.7s", mp->name);
527 }
528 }
529
812db3f7 530 if (DO_BIC(BIC_PkgTmp))
3d109de2 531 outp += sprintf(outp, "\tPkgTmp");
889facbe 532
812db3f7 533 if (DO_BIC(BIC_GFX_rc6))
3d109de2 534 outp += sprintf(outp, "\tGFX%%rc6");
fdf676e5 535
812db3f7 536 if (DO_BIC(BIC_GFXMHz))
3d109de2 537 outp += sprintf(outp, "\tGFXMHz");
27d47356 538
0b2bb692 539 if (do_skl_residency) {
3d109de2
LB		 540 outp += sprintf(outp, "\tTotl%%C0");
541 outp += sprintf(outp, "\tAny%%C0");
542 outp += sprintf(outp, "\tGFX%%C0");
543 outp += sprintf(outp, "\tCPUGFX%%");
0b2bb692
LB		 544 }
545
0f47c08d 546 if (DO_BIC(BIC_Pkgpc2))
3d109de2 547 outp += sprintf(outp, "\tPkg%%pc2");
0f47c08d 548 if (DO_BIC(BIC_Pkgpc3))
3d109de2 549 outp += sprintf(outp, "\tPkg%%pc3");
0f47c08d 550 if (DO_BIC(BIC_Pkgpc6))
3d109de2 551 outp += sprintf(outp, "\tPkg%%pc6");
0f47c08d 552 if (DO_BIC(BIC_Pkgpc7))
3d109de2 553 outp += sprintf(outp, "\tPkg%%pc7");
0f47c08d 554 if (DO_BIC(BIC_Pkgpc8))
3d109de2 555 outp += sprintf(outp, "\tPkg%%pc8");
0f47c08d 556 if (DO_BIC(BIC_Pkgpc9))
3d109de2 557 outp += sprintf(outp, "\tPkg%%pc9");
0f47c08d 558 if (DO_BIC(BIC_Pkgpc10))
3d109de2 559 outp += sprintf(outp, "\tPk%%pc10");
103a8fea 560
5c56be9a 561 if (do_rapl && !rapl_joules) {
812db3f7 562 if (DO_BIC(BIC_PkgWatt))
3d109de2 563 outp += sprintf(outp, "\tPkgWatt");
812db3f7 564 if (DO_BIC(BIC_CorWatt))
3d109de2 565 outp += sprintf(outp, "\tCorWatt");
812db3f7 566 if (DO_BIC(BIC_GFXWatt))
3d109de2 567 outp += sprintf(outp, "\tGFXWatt");
812db3f7 568 if (DO_BIC(BIC_RAMWatt))
3d109de2 569 outp += sprintf(outp, "\tRAMWatt");
812db3f7 570 if (DO_BIC(BIC_PKG__))
3d109de2 571 outp += sprintf(outp, "\tPKG_%%");
812db3f7 572 if (DO_BIC(BIC_RAM__))
3d109de2 573 outp += sprintf(outp, "\tRAM_%%");
d7899447 574 } else if (do_rapl && rapl_joules) {
812db3f7 575 if (DO_BIC(BIC_Pkg_J))
3d109de2 576 outp += sprintf(outp, "\tPkg_J");
812db3f7 577 if (DO_BIC(BIC_Cor_J))
3d109de2 578 outp += sprintf(outp, "\tCor_J");
812db3f7 579 if (DO_BIC(BIC_GFX_J))
3d109de2 580 outp += sprintf(outp, "\tGFX_J");
812db3f7 581 if (DO_BIC(BIC_RAM_J))
3d109de2 582 outp += sprintf(outp, "\tRAM_J");
812db3f7 583 if (DO_BIC(BIC_PKG__))
3d109de2 584 outp += sprintf(outp, "\tPKG_%%");
812db3f7 585 if (DO_BIC(BIC_RAM__))
3d109de2 586 outp += sprintf(outp, "\tRAM_%%");
5c56be9a 587 }
388e9c81
LB		 588 for (mp = sys.pp; mp; mp = mp->next) {
589 if (mp->format == FORMAT_RAW) {
590 if (mp->width == 64)
591 outp += sprintf(outp, "\t%18.18s", mp->name);
592 else
593 outp += sprintf(outp, "\t%10.10s", mp->name);
594 } else {
595 outp += sprintf(outp, "\t%-7.7s", mp->name);
596 }
597 }
598
c98d5d94 599 outp += sprintf(outp, "\n");
103a8fea
LB		 600}
601
c98d5d94
LB		 602int dump_counters(struct thread_data *t, struct core_data *c,
603 struct pkg_data *p)
103a8fea 604{
388e9c81
LB		 605 int i;
606 struct msr_counter *mp;
607
3b4d5c7f 608 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
c98d5d94
LB		 609
610 if (t) {
3b4d5c7f
AS		 611 outp += sprintf(outp, "CPU: %d flags 0x%x\n",
612 t->cpu_id, t->flags);
613 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
614 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
615 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
616 outp += sprintf(outp, "c1: %016llX\n", t->c1);
6886fee4 617
812db3f7 618 if (DO_BIC(BIC_IRQ))
562a2d37 619 outp += sprintf(outp, "IRQ: %08X\n", t->irq_count);
812db3f7 620 if (DO_BIC(BIC_SMI))
3b4d5c7f 621 outp += sprintf(outp, "SMI: %08X\n", t->smi_count);
388e9c81
LB		 622
623 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
624 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n",
625 i, mp->msr_num, t->counter[i]);
626 }
c98d5d94 627 }
103a8fea 628
c98d5d94 629 if (c) {
3b4d5c7f
AS		 630 outp += sprintf(outp, "core: %d\n", c->core_id);
631 outp += sprintf(outp, "c3: %016llX\n", c->c3);
632 outp += sprintf(outp, "c6: %016llX\n", c->c6);
633 outp += sprintf(outp, "c7: %016llX\n", c->c7);
634 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
388e9c81
LB		 635
636 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
637 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n",
638 i, mp->msr_num, c->counter[i]);
639 }
0539ba11 640 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us);
c98d5d94 641 }
103a8fea 642
c98d5d94 643 if (p) {
3b4d5c7f 644 outp += sprintf(outp, "package: %d\n", p->package_id);
0b2bb692
LB		 645
646 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
647 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
648 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
649 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
650
3b4d5c7f 651 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
0f47c08d 652 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 653 outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
0f47c08d 654 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 655 outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
0f47c08d 656 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 657 outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
3b4d5c7f
AS		 658 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
659 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
660 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
661 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg);
662 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores);
663 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx);
664 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram);
665 outp += sprintf(outp, "Throttle PKG: %0X\n",
666 p->rapl_pkg_perf_status);
667 outp += sprintf(outp, "Throttle RAM: %0X\n",
668 p->rapl_dram_perf_status);
669 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
388e9c81
LB		 670
671 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
672 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n",
673 i, mp->msr_num, p->counter[i]);
674 }
c98d5d94 675 }
3b4d5c7f
AS		 676
677 outp += sprintf(outp, "\n");
678
c98d5d94 679 return 0;
103a8fea
LB		 680}
681
e23da037
LB		 682/*
683 * column formatting convention & formats
e23da037 684 */
c98d5d94
LB		 685int format_counters(struct thread_data *t, struct core_data *c,
686 struct pkg_data *p)
103a8fea 687{
008d396e 688 double interval_float, tsc;
fc04cc67 689 char *fmt8;
388e9c81
LB		 690 int i;
691 struct msr_counter *mp;
103a8fea 692
c98d5d94
LB		 693 /* if showing only 1st thread in core and this isn't one, bail out */
694 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
695 return 0;
696
697 /* if showing only 1st thread in pkg and this isn't one, bail out */
698 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
699 return 0;
700
103a8fea
LB		 701 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0;
702
008d396e
LB		 703 tsc = t->tsc * tsc_tweak;
704
c98d5d94
LB		 705 /* topo columns, print blanks on 1st (average) line */
706 if (t == &average.threads) {
812db3f7 707 if (DO_BIC(BIC_Package))
3d109de2 708 outp += sprintf(outp, "\t-");
812db3f7 709 if (DO_BIC(BIC_Core))
3d109de2 710 outp += sprintf(outp, "\t-");
812db3f7 711 if (DO_BIC(BIC_CPU))
3d109de2 712 outp += sprintf(outp, "\t-");
103a8fea 713 } else {
812db3f7 714 if (DO_BIC(BIC_Package)) {
c98d5d94 715 if (p)
3d109de2 716 outp += sprintf(outp, "\t%d", p->package_id);
c98d5d94 717 else
3d109de2 718 outp += sprintf(outp, "\t-");
c98d5d94 719 }
812db3f7 720 if (DO_BIC(BIC_Core)) {
c98d5d94 721 if (c)
3d109de2 722 outp += sprintf(outp, "\t%d", c->core_id);
c98d5d94 723 else
3d109de2 724 outp += sprintf(outp, "\t-");
c98d5d94 725 }
812db3f7 726 if (DO_BIC(BIC_CPU))
3d109de2 727 outp += sprintf(outp, "\t%d", t->cpu_id);
103a8fea 728 }
fc04cc67 729
812db3f7 730 if (DO_BIC(BIC_Avg_MHz))
3d109de2 731 outp += sprintf(outp, "\t%.0f",
fc04cc67
LB		 732 1.0 / units * t->aperf / interval_float);
733
812db3f7 734 if (DO_BIC(BIC_Busy))
008d396e 735 outp += sprintf(outp, "\t%.2f", 100.0 * t->mperf/tsc);
103a8fea 736
812db3f7 737 if (DO_BIC(BIC_Bzy_MHz)) {
21ed5574 738 if (has_base_hz)
3d109de2 739 outp += sprintf(outp, "\t%.0f", base_hz / units * t->aperf / t->mperf);
21ed5574 740 else
3d109de2 741 outp += sprintf(outp, "\t%.0f",
008d396e 742 tsc / units * t->aperf / t->mperf / interval_float);
21ed5574 743 }
103a8fea 744
812db3f7
LB		 745 if (DO_BIC(BIC_TSC_MHz))
746 outp += sprintf(outp, "\t%.0f", 1.0 * t->tsc/units/interval_float);
103a8fea 747
562a2d37 748 /* IRQ */
812db3f7 749 if (DO_BIC(BIC_IRQ))
3d109de2 750 outp += sprintf(outp, "\t%d", t->irq_count);
562a2d37 751
1cc21f7b 752 /* SMI */
812db3f7 753 if (DO_BIC(BIC_SMI))
3d109de2 754 outp += sprintf(outp, "\t%d", t->smi_count);
1cc21f7b 755
678a3bd1 756 /* C1 */
812db3f7 757 if (DO_BIC(BIC_CPU_c1))
008d396e 758 outp += sprintf(outp, "\t%.2f", 100.0 * t->c1/tsc);
c98d5d94 759
678a3bd1 760 /* Added counters */
388e9c81
LB		 761 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
762 if (mp->format == FORMAT_RAW) {
763 if (mp->width == 32)
764 outp += sprintf(outp, "\t0x%08lx", (unsigned long) t->counter[i]);
765 else
766 outp += sprintf(outp, "\t0x%016llx", t->counter[i]);
767 } else if (mp->format == FORMAT_DELTA) {
678a3bd1 768 outp += sprintf(outp, "\t%lld", t->counter[i]);
388e9c81 769 } else if (mp->format == FORMAT_PERCENT) {
008d396e 770 outp += sprintf(outp, "\t%.2f", 100.0 * t->counter[i]/tsc);
388e9c81
LB		 771 }
772 }
773
678a3bd1
LB		 774 /* print per-core data only for 1st thread in core */
775 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
776 goto done;
777
812db3f7 778 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates)
008d396e 779 outp += sprintf(outp, "\t%.2f", 100.0 * c->c3/tsc);
812db3f7 780 if (DO_BIC(BIC_CPU_c6))
008d396e 781 outp += sprintf(outp, "\t%.2f", 100.0 * c->c6/tsc);
812db3f7 782 if (DO_BIC(BIC_CPU_c7))
008d396e 783 outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/tsc);
678a3bd1 784
0539ba11
LB		 785 /* Mod%c6 */
786 if (DO_BIC(BIC_Mod_c6))
008d396e 787 outp += sprintf(outp, "\t%.2f", 100.0 * c->mc6_us / tsc);
0539ba11 788
812db3f7 789 if (DO_BIC(BIC_CoreTmp))
3d109de2 790 outp += sprintf(outp, "\t%d", c->core_temp_c);
889facbe 791
388e9c81
LB		 792 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
793 if (mp->format == FORMAT_RAW) {
794 if (mp->width == 32)
795 outp += sprintf(outp, "\t0x%08lx", (unsigned long) c->counter[i]);
796 else
797 outp += sprintf(outp, "\t0x%016llx", c->counter[i]);
798 } else if (mp->format == FORMAT_DELTA) {
678a3bd1 799 outp += sprintf(outp, "\t%lld", c->counter[i]);
388e9c81 800 } else if (mp->format == FORMAT_PERCENT) {
008d396e 801 outp += sprintf(outp, "\t%.2f", 100.0 * c->counter[i]/tsc);
388e9c81
LB		 802 }
803 }
804
c98d5d94
LB		 805 /* print per-package data only for 1st core in package */
806 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
807 goto done;
808
0b2bb692 809 /* PkgTmp */
812db3f7 810 if (DO_BIC(BIC_PkgTmp))
3d109de2 811 outp += sprintf(outp, "\t%d", p->pkg_temp_c);
889facbe 812
fdf676e5 813 /* GFXrc6 */
812db3f7 814 if (DO_BIC(BIC_GFX_rc6)) {
ba3dec99 815 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */
3d109de2 816 outp += sprintf(outp, "\t**.**");
9185e988 817 } else {
3d109de2 818 outp += sprintf(outp, "\t%.2f",
9185e988
LB		 819 p->gfx_rc6_ms / 10.0 / interval_float);
820 }
821 }
fdf676e5 822
27d47356 823 /* GFXMHz */
812db3f7 824 if (DO_BIC(BIC_GFXMHz))
3d109de2 825 outp += sprintf(outp, "\t%d", p->gfx_mhz);
27d47356 826
0b2bb692
LB		 827 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
828 if (do_skl_residency) {
008d396e
LB		 829 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_wtd_core_c0/tsc);
830 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_core_c0/tsc);
831 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_gfxe_c0/tsc);
832 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_both_core_gfxe_c0/tsc);
0b2bb692
LB		 833 }
834
0f47c08d 835 if (DO_BIC(BIC_Pkgpc2))
008d396e 836 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc2/tsc);
0f47c08d 837 if (DO_BIC(BIC_Pkgpc3))
008d396e 838 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc3/tsc);
0f47c08d 839 if (DO_BIC(BIC_Pkgpc6))
008d396e 840 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc6/tsc);
0f47c08d 841 if (DO_BIC(BIC_Pkgpc7))
008d396e 842 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc7/tsc);
0f47c08d 843 if (DO_BIC(BIC_Pkgpc8))
008d396e 844 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc8/tsc);
0f47c08d 845 if (DO_BIC(BIC_Pkgpc9))
008d396e 846 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc9/tsc);
0f47c08d 847 if (DO_BIC(BIC_Pkgpc10))
008d396e 848 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc10/tsc);
889facbe
LB		 849
850 /*
851 * If measurement interval exceeds minimum RAPL Joule Counter range,
852 * indicate that results are suspect by printing "**" in fraction place.
853 */
fc04cc67 854 if (interval_float < rapl_joule_counter_range)
3d109de2 855 fmt8 = "\t%.2f";
fc04cc67 856 else
e975db5d 857 fmt8 = "%6.0f**";
889facbe 858
812db3f7
LB		 859 if (DO_BIC(BIC_PkgWatt))
860 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float);
861 if (DO_BIC(BIC_CorWatt))
862 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float);
863 if (DO_BIC(BIC_GFXWatt))
864 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float);
865 if (DO_BIC(BIC_RAMWatt))
866 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float);
867 if (DO_BIC(BIC_Pkg_J))
868 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units);
869 if (DO_BIC(BIC_Cor_J))
870 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units);
871 if (DO_BIC(BIC_GFX_J))
872 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units);
873 if (DO_BIC(BIC_RAM_J))
874 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units);
875 if (DO_BIC(BIC_PKG__))
876 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
877 if (DO_BIC(BIC_RAM__))
878 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
879
388e9c81
LB		 880 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
881 if (mp->format == FORMAT_RAW) {
882 if (mp->width == 32)
883 outp += sprintf(outp, "\t0x%08lx", (unsigned long) p->counter[i]);
884 else
885 outp += sprintf(outp, "\t0x%016llx", p->counter[i]);
886 } else if (mp->format == FORMAT_DELTA) {
678a3bd1 887 outp += sprintf(outp, "\t%lld", p->counter[i]);
388e9c81 888 } else if (mp->format == FORMAT_PERCENT) {
008d396e 889 outp += sprintf(outp, "\t%.2f", 100.0 * p->counter[i]/tsc);
388e9c81
LB		 890 }
891 }
892
c98d5d94 893done:
c98d5d94
LB		 894 outp += sprintf(outp, "\n");
895
896 return 0;
103a8fea
LB		 897}
898
b7d8c148 899void flush_output_stdout(void)
c98d5d94 900{
b7d8c148
LB		 901 FILE *filep;
902
903 if (outf == stderr)
904 filep = stdout;
905 else
906 filep = outf;
907
908 fputs(output_buffer, filep);
909 fflush(filep);
910
c98d5d94
LB		 911 outp = output_buffer;
912}
b7d8c148 913void flush_output_stderr(void)
c98d5d94 914{
b7d8c148
LB		 915 fputs(output_buffer, outf);
916 fflush(outf);
c98d5d94
LB		 917 outp = output_buffer;
918}
919void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 920{
e23da037 921 static int printed;
103a8fea 922
e23da037
LB		 923 if (!printed || !summary_only)
924 print_header();
103a8fea 925
c98d5d94
LB		 926 if (topo.num_cpus > 1)
927 format_counters(&average.threads, &average.cores,
928 &average.packages);
103a8fea 929
e23da037
LB		 930 printed = 1;
931
932 if (summary_only)
933 return;
934
c98d5d94 935 for_all_cpus(format_counters, t, c, p);
103a8fea
LB		 936}
937
889facbe
LB		 938#define DELTA_WRAP32(new, old) \
939 if (new > old) { \
940 old = new - old; \
941 } else { \
942 old = 0x100000000 + new - old; \
943 }
944
ba3dec99 945int
c98d5d94
LB		 946delta_package(struct pkg_data *new, struct pkg_data *old)
947{
388e9c81
LB		 948 int i;
949 struct msr_counter *mp;
0b2bb692
LB		 950
951 if (do_skl_residency) {
952 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
953 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
954 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
955 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
956 }
c98d5d94 957 old->pc2 = new->pc2 - old->pc2;
0f47c08d 958 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 959 old->pc3 = new->pc3 - old->pc3;
0f47c08d 960 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 961 old->pc6 = new->pc6 - old->pc6;
0f47c08d 962 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 963 old->pc7 = new->pc7 - old->pc7;
ca58710f
KCA		 964 old->pc8 = new->pc8 - old->pc8;
965 old->pc9 = new->pc9 - old->pc9;
966 old->pc10 = new->pc10 - old->pc10;
889facbe
LB		 967 old->pkg_temp_c = new->pkg_temp_c;
968
9185e988
LB		 969 /* flag an error when rc6 counter resets/wraps */
970 if (old->gfx_rc6_ms > new->gfx_rc6_ms)
971 old->gfx_rc6_ms = -1;
972 else
973 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
974
27d47356
LB		 975 old->gfx_mhz = new->gfx_mhz;
976
889facbe
LB		 977 DELTA_WRAP32(new->energy_pkg, old->energy_pkg);
978 DELTA_WRAP32(new->energy_cores, old->energy_cores);
979 DELTA_WRAP32(new->energy_gfx, old->energy_gfx);
980 DELTA_WRAP32(new->energy_dram, old->energy_dram);
981 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status);
982 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status);
ba3dec99 983
388e9c81
LB		 984 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
985 if (mp->format == FORMAT_RAW)
986 old->counter[i] = new->counter[i];
987 else
988 old->counter[i] = new->counter[i] - old->counter[i];
989 }
990
ba3dec99 991 return 0;
c98d5d94 992}
103a8fea 993
c98d5d94
LB		 994void
995delta_core(struct core_data *new, struct core_data *old)
103a8fea 996{
388e9c81
LB		 997 int i;
998 struct msr_counter *mp;
999
c98d5d94
LB		 1000 old->c3 = new->c3 - old->c3;
1001 old->c6 = new->c6 - old->c6;
1002 old->c7 = new->c7 - old->c7;
889facbe 1003 old->core_temp_c = new->core_temp_c;
0539ba11 1004 old->mc6_us = new->mc6_us - old->mc6_us;
388e9c81
LB		 1005
1006 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1007 if (mp->format == FORMAT_RAW)
1008 old->counter[i] = new->counter[i];
1009 else
1010 old->counter[i] = new->counter[i] - old->counter[i];
1011 }
c98d5d94 1012}
103a8fea 1013
c3ae331d
LB		 1014/*
1015 * old = new - old
1016 */
ba3dec99 1017int
c98d5d94
LB		 1018delta_thread(struct thread_data *new, struct thread_data *old,
1019 struct core_data *core_delta)
1020{
388e9c81
LB		 1021 int i;
1022 struct msr_counter *mp;
1023
c98d5d94
LB		 1024 old->tsc = new->tsc - old->tsc;
1025
1026 /* check for TSC < 1 Mcycles over interval */
b2c95d90
JT		 1027 if (old->tsc < (1000 * 1000))
1028 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
1029 "You can disable all c-states by booting with \"idle=poll\"\n"
1030 "or just the deep ones with \"processor.max_cstate=1\"");
103a8fea 1031
c98d5d94 1032 old->c1 = new->c1 - old->c1;
103a8fea 1033
812db3f7 1034 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) {
a729617c
LB		 1035 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
1036 old->aperf = new->aperf - old->aperf;
1037 old->mperf = new->mperf - old->mperf;
1038 } else {
ba3dec99 1039 return -1;
103a8fea 1040 }
c98d5d94 1041 }
103a8fea 1042
103a8fea 1043
144b44b1
LB		 1044 if (use_c1_residency_msr) {
1045 /*
1046 * Some models have a dedicated C1 residency MSR,
1047 * which should be more accurate than the derivation below.
1048 */
1049 } else {
1050 /*
1051 * As counter collection is not atomic,
1052 * it is possible for mperf's non-halted cycles + idle states
1053 * to exceed TSC's all cycles: show c1 = 0% in that case.
1054 */
1055 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc)
1056 old->c1 = 0;
1057 else {
1058 /* normal case, derive c1 */
008d396e 1059 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3
c98d5d94 1060 - core_delta->c6 - core_delta->c7;
144b44b1 1061 }
c98d5d94 1062 }
c3ae331d 1063
c98d5d94 1064 if (old->mperf == 0) {
b7d8c148
LB		 1065 if (debug > 1)
1066 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
c98d5d94 1067 old->mperf = 1; /* divide by 0 protection */
103a8fea 1068 }
c98d5d94 1069
812db3f7 1070 if (DO_BIC(BIC_IRQ))
562a2d37
LB		 1071 old->irq_count = new->irq_count - old->irq_count;
1072
812db3f7 1073 if (DO_BIC(BIC_SMI))
1ed51011 1074 old->smi_count = new->smi_count - old->smi_count;
ba3dec99 1075
388e9c81
LB		 1076 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1077 if (mp->format == FORMAT_RAW)
1078 old->counter[i] = new->counter[i];
1079 else
1080 old->counter[i] = new->counter[i] - old->counter[i];
1081 }
ba3dec99 1082 return 0;
c98d5d94
LB		 1083}
1084
1085int delta_cpu(struct thread_data *t, struct core_data *c,
1086 struct pkg_data *p, struct thread_data *t2,
1087 struct core_data *c2, struct pkg_data *p2)
1088{
ba3dec99
LB		 1089 int retval = 0;
1090
c98d5d94
LB		 1091 /* calculate core delta only for 1st thread in core */
1092 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE)
1093 delta_core(c, c2);
1094
1095 /* always calculate thread delta */
ba3dec99
LB		 1096 retval = delta_thread(t, t2, c2); /* c2 is core delta */
1097 if (retval)
1098 return retval;
c98d5d94
LB		 1099
1100 /* calculate package delta only for 1st core in package */
1101 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)
ba3dec99 1102 retval = delta_package(p, p2);
c98d5d94 1103
ba3dec99 1104 return retval;
103a8fea
LB		 1105}
1106
c98d5d94
LB		 1107void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1108{
388e9c81
LB		 1109 int i;
1110 struct msr_counter *mp;
1111
c98d5d94
LB		 1112 t->tsc = 0;
1113 t->aperf = 0;
1114 t->mperf = 0;
1115 t->c1 = 0;
1116
562a2d37
LB		 1117 t->irq_count = 0;
1118 t->smi_count = 0;
1119
c98d5d94
LB		 1120 /* tells format_counters to dump all fields from this set */
1121 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE;
1122
1123 c->c3 = 0;
1124 c->c6 = 0;
1125 c->c7 = 0;
0539ba11 1126 c->mc6_us = 0;
889facbe 1127 c->core_temp_c = 0;
c98d5d94 1128
0b2bb692
LB		 1129 p->pkg_wtd_core_c0 = 0;
1130 p->pkg_any_core_c0 = 0;
1131 p->pkg_any_gfxe_c0 = 0;
1132 p->pkg_both_core_gfxe_c0 = 0;
1133
c98d5d94 1134 p->pc2 = 0;
0f47c08d 1135 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 1136 p->pc3 = 0;
0f47c08d 1137 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 1138 p->pc6 = 0;
0f47c08d 1139 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 1140 p->pc7 = 0;
ca58710f
KCA		 1141 p->pc8 = 0;
1142 p->pc9 = 0;
1143 p->pc10 = 0;
889facbe
LB		 1144
1145 p->energy_pkg = 0;
1146 p->energy_dram = 0;
1147 p->energy_cores = 0;
1148 p->energy_gfx = 0;
1149 p->rapl_pkg_perf_status = 0;
1150 p->rapl_dram_perf_status = 0;
1151 p->pkg_temp_c = 0;
27d47356 1152
fdf676e5 1153 p->gfx_rc6_ms = 0;
27d47356 1154 p->gfx_mhz = 0;
388e9c81
LB		 1155 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next)
1156 t->counter[i] = 0;
1157
1158 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next)
1159 c->counter[i] = 0;
1160
1161 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next)
1162 p->counter[i] = 0;
c98d5d94
LB		 1163}
1164int sum_counters(struct thread_data *t, struct core_data *c,
1165 struct pkg_data *p)
103a8fea 1166{
388e9c81
LB		 1167 int i;
1168 struct msr_counter *mp;
1169
c98d5d94
LB		 1170 average.threads.tsc += t->tsc;
1171 average.threads.aperf += t->aperf;
1172 average.threads.mperf += t->mperf;
1173 average.threads.c1 += t->c1;
103a8fea 1174
562a2d37
LB		 1175 average.threads.irq_count += t->irq_count;
1176 average.threads.smi_count += t->smi_count;
1177
388e9c81
LB		 1178 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1179 if (mp->format == FORMAT_RAW)
1180 continue;
1181 average.threads.counter[i] += t->counter[i];
1182 }
1183
c98d5d94
LB		 1184 /* sum per-core values only for 1st thread in core */
1185 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1186 return 0;
103a8fea 1187
c98d5d94
LB		 1188 average.cores.c3 += c->c3;
1189 average.cores.c6 += c->c6;
1190 average.cores.c7 += c->c7;
0539ba11 1191 average.cores.mc6_us += c->mc6_us;
c98d5d94 1192
889facbe
LB		 1193 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
1194
388e9c81
LB		 1195 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1196 if (mp->format == FORMAT_RAW)
1197 continue;
1198 average.cores.counter[i] += c->counter[i];
1199 }
1200
c98d5d94
LB		 1201 /* sum per-pkg values only for 1st core in pkg */
1202 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1203 return 0;
1204
0b2bb692
LB		 1205 if (do_skl_residency) {
1206 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
1207 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
1208 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
1209 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
1210 }
1211
c98d5d94 1212 average.packages.pc2 += p->pc2;
0f47c08d 1213 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 1214 average.packages.pc3 += p->pc3;
0f47c08d 1215 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 1216 average.packages.pc6 += p->pc6;
0f47c08d 1217 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 1218 average.packages.pc7 += p->pc7;
ca58710f
KCA		 1219 average.packages.pc8 += p->pc8;
1220 average.packages.pc9 += p->pc9;
1221 average.packages.pc10 += p->pc10;
c98d5d94 1222
889facbe
LB		 1223 average.packages.energy_pkg += p->energy_pkg;
1224 average.packages.energy_dram += p->energy_dram;
1225 average.packages.energy_cores += p->energy_cores;
1226 average.packages.energy_gfx += p->energy_gfx;
1227
fdf676e5 1228 average.packages.gfx_rc6_ms = p->gfx_rc6_ms;
27d47356
LB		 1229 average.packages.gfx_mhz = p->gfx_mhz;
1230
889facbe
LB		 1231 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
1232
1233 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
1234 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
388e9c81
LB		 1235
1236 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1237 if (mp->format == FORMAT_RAW)
1238 continue;
1239 average.packages.counter[i] += p->counter[i];
1240 }
c98d5d94
LB		 1241 return 0;
1242}
1243/*
1244 * sum the counters for all cpus in the system
1245 * compute the weighted average
1246 */
1247void compute_average(struct thread_data *t, struct core_data *c,
1248 struct pkg_data *p)
1249{
388e9c81
LB		 1250 int i;
1251 struct msr_counter *mp;
1252
c98d5d94
LB		 1253 clear_counters(&average.threads, &average.cores, &average.packages);
1254
1255 for_all_cpus(sum_counters, t, c, p);
1256
1257 average.threads.tsc /= topo.num_cpus;
1258 average.threads.aperf /= topo.num_cpus;
1259 average.threads.mperf /= topo.num_cpus;
1260 average.threads.c1 /= topo.num_cpus;
1261
1262 average.cores.c3 /= topo.num_cores;
1263 average.cores.c6 /= topo.num_cores;
1264 average.cores.c7 /= topo.num_cores;
0539ba11 1265 average.cores.mc6_us /= topo.num_cores;
c98d5d94 1266
0b2bb692
LB		 1267 if (do_skl_residency) {
1268 average.packages.pkg_wtd_core_c0 /= topo.num_packages;
1269 average.packages.pkg_any_core_c0 /= topo.num_packages;
1270 average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
1271 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
1272 }
1273
c98d5d94 1274 average.packages.pc2 /= topo.num_packages;
0f47c08d 1275 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 1276 average.packages.pc3 /= topo.num_packages;
0f47c08d 1277 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 1278 average.packages.pc6 /= topo.num_packages;
0f47c08d 1279 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 1280 average.packages.pc7 /= topo.num_packages;
ca58710f
KCA		 1281
1282 average.packages.pc8 /= topo.num_packages;
1283 average.packages.pc9 /= topo.num_packages;
1284 average.packages.pc10 /= topo.num_packages;
388e9c81
LB		 1285
1286 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1287 if (mp->format == FORMAT_RAW)
1288 continue;
1289 average.threads.counter[i] /= topo.num_cpus;
1290 }
1291 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1292 if (mp->format == FORMAT_RAW)
1293 continue;
1294 average.cores.counter[i] /= topo.num_cores;
1295 }
1296 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1297 if (mp->format == FORMAT_RAW)
1298 continue;
1299 average.packages.counter[i] /= topo.num_packages;
1300 }
103a8fea
LB		 1301}
1302
c98d5d94 1303static unsigned long long rdtsc(void)
103a8fea 1304{
c98d5d94 1305 unsigned int low, high;
15aaa346 1306
c98d5d94 1307 asm volatile("rdtsc" : "=a" (low), "=d" (high));
15aaa346 1308
c98d5d94
LB		 1309 return low | ((unsigned long long)high) << 32;
1310}
15aaa346 1311
495c7654
LB		 1312/*
1313 * Open a file, and exit on failure
1314 */
1315FILE *fopen_or_die(const char *path, const char *mode)
1316{
1317 FILE *filep = fopen(path, mode);
1318
1319 if (!filep)
1320 err(1, "%s: open failed", path);
1321 return filep;
1322}
1323/*
1324 * snapshot_sysfs_counter()
1325 *
1326 * return snapshot of given counter
1327 */
1328unsigned long long snapshot_sysfs_counter(char *path)
1329{
1330 FILE *fp;
1331 int retval;
1332 unsigned long long counter;
1333
1334 fp = fopen_or_die(path, "r");
1335
1336 retval = fscanf(fp, "%lld", &counter);
1337 if (retval != 1)
1338 err(1, "snapshot_sysfs_counter(%s)", path);
1339
1340 fclose(fp);
1341
1342 return counter;
1343}
1344
1345int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp)
1346{
1347 if (mp->msr_num != 0) {
1348 if (get_msr(cpu, mp->msr_num, counterp))
1349 return -1;
1350 } else {
1351 *counterp = snapshot_sysfs_counter(mp->path);
1352 }
1353
1354 return 0;
1355}
1356
c98d5d94
LB		 1357/*
1358 * get_counters(...)
1359 * migrate to cpu
1360 * acquire and record local counters for that cpu
1361 */
1362int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1363{
1364 int cpu = t->cpu_id;
889facbe 1365 unsigned long long msr;
0102b067 1366 int aperf_mperf_retry_count = 0;
388e9c81
LB		 1367 struct msr_counter *mp;
1368 int i;
88c3281f 1369
e52966c0 1370 if (cpu_migrate(cpu)) {
b7d8c148 1371 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
c98d5d94 1372 return -1;
e52966c0 1373 }
15aaa346 1374
0102b067 1375retry:
c98d5d94
LB		 1376 t->tsc = rdtsc(); /* we are running on local CPU of interest */
1377
812db3f7 1378 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) {
0102b067
LB		 1379 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time;
1380
1381 /*
1382 * The TSC, APERF and MPERF must be read together for
1383 * APERF/MPERF and MPERF/TSC to give accurate results.
1384 *
1385 * Unfortunately, APERF and MPERF are read by
1386 * individual system call, so delays may occur
1387 * between them. If the time to read them
1388 * varies by a large amount, we re-read them.
1389 */
1390
1391 /*
1392 * This initial dummy APERF read has been seen to
1393 * reduce jitter in the subsequent reads.
1394 */
1395
1396 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
1397 return -3;
1398
1399 t->tsc = rdtsc(); /* re-read close to APERF */
1400
1401 tsc_before = t->tsc;
1402
9c63a650 1403 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
c98d5d94 1404 return -3;
0102b067
LB		 1405
1406 tsc_between = rdtsc();
1407
9c63a650 1408 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
c98d5d94 1409 return -4;
0102b067
LB		 1410
1411 tsc_after = rdtsc();
1412
1413 aperf_time = tsc_between - tsc_before;
1414 mperf_time = tsc_after - tsc_between;
1415
1416 /*
1417 * If the system call latency to read APERF and MPERF
1418 * differ by more than 2x, then try again.
1419 */
1420 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) {
1421 aperf_mperf_retry_count++;
1422 if (aperf_mperf_retry_count < 5)
1423 goto retry;
1424 else
1425 warnx("cpu%d jitter %lld %lld",
1426 cpu, aperf_time, mperf_time);
1427 }
1428 aperf_mperf_retry_count = 0;
1429
b2b34dfe
HC		 1430 t->aperf = t->aperf * aperf_mperf_multiplier;
1431 t->mperf = t->mperf * aperf_mperf_multiplier;
c98d5d94
LB		 1432 }
1433
812db3f7 1434 if (DO_BIC(BIC_IRQ))
562a2d37 1435 t->irq_count = irqs_per_cpu[cpu];
812db3f7 1436 if (DO_BIC(BIC_SMI)) {
1ed51011
LB		 1437 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
1438 return -5;
1439 t->smi_count = msr & 0xFFFFFFFF;
1440 }
0539ba11 1441 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) {
144b44b1
LB		 1442 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
1443 return -6;
1444 }
1445
388e9c81 1446 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
495c7654 1447 if (get_mp(cpu, mp, &t->counter[i]))
388e9c81
LB		 1448 return -10;
1449 }
1450
c98d5d94
LB		 1451 /* collect core counters only for 1st thread in core */
1452 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1453 return 0;
1454
812db3f7 1455 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) {
c98d5d94
LB		 1456 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
1457 return -6;
144b44b1
LB		 1458 }
1459
812db3f7 1460 if (DO_BIC(BIC_CPU_c6) && !do_knl_cstates) {
c98d5d94
LB		 1461 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
1462 return -7;
fb5d4327
DC		 1463 } else if (do_knl_cstates) {
1464 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
1465 return -7;
c98d5d94
LB		 1466 }
1467
812db3f7 1468 if (DO_BIC(BIC_CPU_c7))
c98d5d94
LB		 1469 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
1470 return -8;
1471
0539ba11
LB		 1472 if (DO_BIC(BIC_Mod_c6))
1473 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
1474 return -8;
1475
812db3f7 1476 if (DO_BIC(BIC_CoreTmp)) {
889facbe
LB		 1477 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
1478 return -9;
1479 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1480 }
1481
388e9c81 1482 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
495c7654 1483 if (get_mp(cpu, mp, &c->counter[i]))
388e9c81
LB		 1484 return -10;
1485 }
889facbe 1486
c98d5d94
LB		 1487 /* collect package counters only for 1st core in package */
1488 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1489 return 0;
1490
0b2bb692
LB		 1491 if (do_skl_residency) {
1492 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
1493 return -10;
1494 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
1495 return -11;
1496 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
1497 return -12;
1498 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
1499 return -13;
1500 }
0f47c08d 1501 if (DO_BIC(BIC_Pkgpc3))
c98d5d94
LB		 1502 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
1503 return -9;
0f47c08d 1504 if (DO_BIC(BIC_Pkgpc6)) {
0539ba11
LB		 1505 if (do_slm_cstates) {
1506 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6))
1507 return -10;
1508 } else {
1509 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
1510 return -10;
1511 }
1512 }
1513
0f47c08d 1514 if (DO_BIC(BIC_Pkgpc2))
c98d5d94
LB		 1515 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
1516 return -11;
0f47c08d 1517 if (DO_BIC(BIC_Pkgpc7))
c98d5d94
LB		 1518 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
1519 return -12;
0f47c08d 1520 if (DO_BIC(BIC_Pkgpc8))
ca58710f
KCA		 1521 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
1522 return -13;
0f47c08d 1523 if (DO_BIC(BIC_Pkgpc9))
ca58710f
KCA		 1524 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
1525 return -13;
0f47c08d 1526 if (DO_BIC(BIC_Pkgpc10))
ca58710f
KCA		 1527 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
1528 return -13;
0f47c08d 1529
889facbe
LB		 1530 if (do_rapl & RAPL_PKG) {
1531 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr))
1532 return -13;
1533 p->energy_pkg = msr & 0xFFFFFFFF;
1534 }
9148494c 1535 if (do_rapl & RAPL_CORES_ENERGY_STATUS) {
889facbe
LB		 1536 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr))
1537 return -14;
1538 p->energy_cores = msr & 0xFFFFFFFF;
1539 }
1540 if (do_rapl & RAPL_DRAM) {
1541 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
1542 return -15;
1543 p->energy_dram = msr & 0xFFFFFFFF;
1544 }
1545 if (do_rapl & RAPL_GFX) {
1546 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr))
1547 return -16;
1548 p->energy_gfx = msr & 0xFFFFFFFF;
1549 }
1550 if (do_rapl & RAPL_PKG_PERF_STATUS) {
1551 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr))
1552 return -16;
1553 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF;
1554 }
1555 if (do_rapl & RAPL_DRAM_PERF_STATUS) {
1556 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr))
1557 return -16;
1558 p->rapl_dram_perf_status = msr & 0xFFFFFFFF;
1559 }
812db3f7 1560 if (DO_BIC(BIC_PkgTmp)) {
889facbe
LB		 1561 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
1562 return -17;
1563 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1564 }
fdf676e5 1565
812db3f7 1566 if (DO_BIC(BIC_GFX_rc6))
fdf676e5
LB		 1567 p->gfx_rc6_ms = gfx_cur_rc6_ms;
1568
812db3f7 1569 if (DO_BIC(BIC_GFXMHz))
27d47356
LB		 1570 p->gfx_mhz = gfx_cur_mhz;
1571
388e9c81 1572 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
495c7654 1573 if (get_mp(cpu, mp, &p->counter[i]))
388e9c81
LB		 1574 return -10;
1575 }
1576
15aaa346 1577 return 0;
103a8fea
LB		 1578}
1579
ee7e38e3
LB		 1580/*
1581 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
1582 * If you change the values, note they are used both in comparisons
1583 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
1584 */
1585
1586#define PCLUKN 0 /* Unknown */
1587#define PCLRSV 1 /* Reserved */
1588#define PCL__0 2 /* PC0 */
1589#define PCL__1 3 /* PC1 */
1590#define PCL__2 4 /* PC2 */
1591#define PCL__3 5 /* PC3 */
1592#define PCL__4 6 /* PC4 */
1593#define PCL__6 7 /* PC6 */
1594#define PCL_6N 8 /* PC6 No Retention */
1595#define PCL_6R 9 /* PC6 Retention */
1596#define PCL__7 10 /* PC7 */
1597#define PCL_7S 11 /* PC7 Shrink */
0b2bb692
LB		 1598#define PCL__8 12 /* PC8 */
1599#define PCL__9 13 /* PC9 */
1600#define PCLUNL 14 /* Unlimited */
ee7e38e3
LB		 1601
1602int pkg_cstate_limit = PCLUKN;
1603char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
0b2bb692 1604 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"};
ee7e38e3 1605
e9257f5f
LB		 1606int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1607int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1608int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
0539ba11 1609int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7};
f2642888 1610int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
e9257f5f 1611int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
e4085d54 1612int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
d8ebb442 1613int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
ee7e38e3 1614
a2b7b749
LB		 1615
1616static void
1617calculate_tsc_tweak()
1618{
a2b7b749
LB		 1619 tsc_tweak = base_hz / tsc_hz;
1620}
1621
fcd17211
LB		 1622static void
1623dump_nhm_platform_info(void)
103a8fea
LB		 1624{
1625 unsigned long long msr;
1626 unsigned int ratio;
1627
ec0adc53 1628 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
103a8fea 1629
b7d8c148 1630 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
6574a5d5 1631
103a8fea 1632 ratio = (msr >> 40) & 0xFF;
710f273b 1633 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n",
103a8fea
LB		 1634 ratio, bclk, ratio * bclk);
1635
1636 ratio = (msr >> 8) & 0xFF;
710f273b 1637 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n",
103a8fea
LB		 1638 ratio, bclk, ratio * bclk);
1639
7ce7d5de 1640 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
b7d8c148 1641 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
bfae2052 1642 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
67920418 1643
fcd17211
LB		 1644 return;
1645}
1646
1647static void
1648dump_hsw_turbo_ratio_limits(void)
1649{
1650 unsigned long long msr;
1651 unsigned int ratio;
1652
7ce7d5de 1653 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
fcd17211 1654
b7d8c148 1655 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
fcd17211
LB		 1656
1657 ratio = (msr >> 8) & 0xFF;
1658 if (ratio)
710f273b 1659 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n",
fcd17211
LB		 1660 ratio, bclk, ratio * bclk);
1661
1662 ratio = (msr >> 0) & 0xFF;
1663 if (ratio)
710f273b 1664 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n",
fcd17211
LB		 1665 ratio, bclk, ratio * bclk);
1666 return;
1667}
1668
1669static void
1670dump_ivt_turbo_ratio_limits(void)
1671{
1672 unsigned long long msr;
1673 unsigned int ratio;
6574a5d5 1674
7ce7d5de 1675 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
6574a5d5 1676
b7d8c148 1677 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
6574a5d5
LB		 1678
1679 ratio = (msr >> 56) & 0xFF;
1680 if (ratio)
710f273b 1681 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n",
6574a5d5
LB		 1682 ratio, bclk, ratio * bclk);
1683
1684 ratio = (msr >> 48) & 0xFF;
1685 if (ratio)
710f273b 1686 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n",
6574a5d5
LB		 1687 ratio, bclk, ratio * bclk);
1688
1689 ratio = (msr >> 40) & 0xFF;
1690 if (ratio)
710f273b 1691 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n",
6574a5d5
LB		 1692 ratio, bclk, ratio * bclk);
1693
1694 ratio = (msr >> 32) & 0xFF;
1695 if (ratio)
710f273b 1696 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n",
6574a5d5
LB		 1697 ratio, bclk, ratio * bclk);
1698
1699 ratio = (msr >> 24) & 0xFF;
1700 if (ratio)
710f273b 1701 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n",
6574a5d5
LB		 1702 ratio, bclk, ratio * bclk);
1703
1704 ratio = (msr >> 16) & 0xFF;
1705 if (ratio)
710f273b 1706 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n",
6574a5d5
LB		 1707 ratio, bclk, ratio * bclk);
1708
1709 ratio = (msr >> 8) & 0xFF;
1710 if (ratio)
710f273b 1711 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n",
6574a5d5
LB		 1712 ratio, bclk, ratio * bclk);
1713
1714 ratio = (msr >> 0) & 0xFF;
1715 if (ratio)
710f273b 1716 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n",
6574a5d5 1717 ratio, bclk, ratio * bclk);
fcd17211
LB		 1718 return;
1719}
31e07522
LB		 1720int has_turbo_ratio_group_limits(int family, int model)
1721{
1722
1723 if (!genuine_intel)
1724 return 0;
1725
1726 switch (model) {
1727 case INTEL_FAM6_ATOM_GOLDMONT:
1728 case INTEL_FAM6_SKYLAKE_X:
1729 case INTEL_FAM6_ATOM_DENVERTON:
1730 return 1;
1731 }
1732 return 0;
1733}
6574a5d5 1734
fcd17211 1735static void
31e07522 1736dump_turbo_ratio_limits(int family, int model)
fcd17211 1737{
31e07522
LB		 1738 unsigned long long msr, core_counts;
1739 unsigned int ratio, group_size;
103a8fea 1740
7ce7d5de 1741 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
b7d8c148 1742 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
6574a5d5 1743
31e07522
LB		 1744 if (has_turbo_ratio_group_limits(family, model)) {
1745 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts);
1746 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts);
1747 } else {
1748 core_counts = 0x0807060504030201;
1749 }
1750
6574a5d5 1751 ratio = (msr >> 56) & 0xFF;
31e07522 1752 group_size = (core_counts >> 56) & 0xFF;
6574a5d5 1753 if (ratio)
31e07522
LB		 1754 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1755 ratio, bclk, ratio * bclk, group_size);
6574a5d5
LB		 1756
1757 ratio = (msr >> 48) & 0xFF;
31e07522 1758 group_size = (core_counts >> 48) & 0xFF;
6574a5d5 1759 if (ratio)
31e07522
LB		 1760 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1761 ratio, bclk, ratio * bclk, group_size);
6574a5d5
LB		 1762
1763 ratio = (msr >> 40) & 0xFF;
31e07522 1764 group_size = (core_counts >> 40) & 0xFF;
6574a5d5 1765 if (ratio)
31e07522
LB		 1766 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1767 ratio, bclk, ratio * bclk, group_size);
6574a5d5
LB		 1768
1769 ratio = (msr >> 32) & 0xFF;
31e07522 1770 group_size = (core_counts >> 32) & 0xFF;
6574a5d5 1771 if (ratio)
31e07522
LB		 1772 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1773 ratio, bclk, ratio * bclk, group_size);
6574a5d5 1774
103a8fea 1775 ratio = (msr >> 24) & 0xFF;
31e07522 1776 group_size = (core_counts >> 24) & 0xFF;
103a8fea 1777 if (ratio)
31e07522
LB		 1778 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1779 ratio, bclk, ratio * bclk, group_size);
103a8fea
LB		 1780
1781 ratio = (msr >> 16) & 0xFF;
31e07522 1782 group_size = (core_counts >> 16) & 0xFF;
103a8fea 1783 if (ratio)
31e07522
LB		 1784 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1785 ratio, bclk, ratio * bclk, group_size);
103a8fea
LB		 1786
1787 ratio = (msr >> 8) & 0xFF;
31e07522 1788 group_size = (core_counts >> 8) & 0xFF;
103a8fea 1789 if (ratio)
31e07522
LB		 1790 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1791 ratio, bclk, ratio * bclk, group_size);
103a8fea
LB		 1792
1793 ratio = (msr >> 0) & 0xFF;
31e07522 1794 group_size = (core_counts >> 0) & 0xFF;
103a8fea 1795 if (ratio)
31e07522
LB		 1796 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1797 ratio, bclk, ratio * bclk, group_size);
fcd17211
LB		 1798 return;
1799}
3a9a941d 1800
0f7887c4
LB		 1801static void
1802dump_atom_turbo_ratio_limits(void)
1803{
1804 unsigned long long msr;
1805 unsigned int ratio;
1806
1807 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr);
1808 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
1809
1810 ratio = (msr >> 0) & 0x3F;
1811 if (ratio)
1812 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n",
1813 ratio, bclk, ratio * bclk);
1814
1815 ratio = (msr >> 8) & 0x3F;
1816 if (ratio)
1817 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n",
1818 ratio, bclk, ratio * bclk);
1819
1820 ratio = (msr >> 16) & 0x3F;
1821 if (ratio)
1822 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n",
1823 ratio, bclk, ratio * bclk);
1824
1825 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr);
1826 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
1827
1828 ratio = (msr >> 24) & 0x3F;
1829 if (ratio)
1830 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n",
1831 ratio, bclk, ratio * bclk);
1832
1833 ratio = (msr >> 16) & 0x3F;
1834 if (ratio)
1835 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n",
1836 ratio, bclk, ratio * bclk);
1837
1838 ratio = (msr >> 8) & 0x3F;
1839 if (ratio)
1840 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n",
1841 ratio, bclk, ratio * bclk);
1842
1843 ratio = (msr >> 0) & 0x3F;
1844 if (ratio)
1845 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n",
1846 ratio, bclk, ratio * bclk);
1847}
1848
fb5d4327
DC		 1849static void
1850dump_knl_turbo_ratio_limits(void)
1851{
cbf97aba
HC		 1852 const unsigned int buckets_no = 7;
1853
fb5d4327 1854 unsigned long long msr;
cbf97aba
HC		 1855 int delta_cores, delta_ratio;
1856 int i, b_nr;
1857 unsigned int cores[buckets_no];
1858 unsigned int ratio[buckets_no];
fb5d4327 1859
ebf5926a 1860 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
fb5d4327 1861
b7d8c148 1862 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n",
bfae2052 1863 base_cpu, msr);
fb5d4327
DC		 1864
1865 /**
1866 * Turbo encoding in KNL is as follows:
cbf97aba
HC		 1867 * [0] -- Reserved
1868 * [7:1] -- Base value of number of active cores of bucket 1.
fb5d4327
DC		 1869 * [15:8] -- Base value of freq ratio of bucket 1.
1870 * [20:16] -- +ve delta of number of active cores of bucket 2.
1871 * i.e. active cores of bucket 2 =
1872 * active cores of bucket 1 + delta
1873 * [23:21] -- Negative delta of freq ratio of bucket 2.
1874 * i.e. freq ratio of bucket 2 =
1875 * freq ratio of bucket 1 - delta
1876 * [28:24]-- +ve delta of number of active cores of bucket 3.
1877 * [31:29]-- -ve delta of freq ratio of bucket 3.
1878 * [36:32]-- +ve delta of number of active cores of bucket 4.
1879 * [39:37]-- -ve delta of freq ratio of bucket 4.
1880 * [44:40]-- +ve delta of number of active cores of bucket 5.
1881 * [47:45]-- -ve delta of freq ratio of bucket 5.
1882 * [52:48]-- +ve delta of number of active cores of bucket 6.
1883 * [55:53]-- -ve delta of freq ratio of bucket 6.
1884 * [60:56]-- +ve delta of number of active cores of bucket 7.
1885 * [63:61]-- -ve delta of freq ratio of bucket 7.
1886 */
cbf97aba
HC		 1887
1888 b_nr = 0;
1889 cores[b_nr] = (msr & 0xFF) >> 1;
1890 ratio[b_nr] = (msr >> 8) & 0xFF;
1891
1892 for (i = 16; i < 64; i += 8) {
fb5d4327 1893 delta_cores = (msr >> i) & 0x1F;
cbf97aba
HC		 1894 delta_ratio = (msr >> (i + 5)) & 0x7;
1895
1896 cores[b_nr + 1] = cores[b_nr] + delta_cores;
1897 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
1898 b_nr++;
fb5d4327 1899 }
cbf97aba
HC		 1900
1901 for (i = buckets_no - 1; i >= 0; i--)
1902 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
b7d8c148 1903 fprintf(outf,
710f273b 1904 "%d * %.1f = %.1f MHz max turbo %d active cores\n",
cbf97aba 1905 ratio[i], bclk, ratio[i] * bclk, cores[i]);
fb5d4327
DC		 1906}
1907
fcd17211
LB		 1908static void
1909dump_nhm_cst_cfg(void)
1910{
1911 unsigned long long msr;
1912
1df2e55a 1913 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
fcd17211
LB		 1914
1915#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
1916#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
1917
1df2e55a 1918 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr);
fcd17211 1919
b7d8c148 1920 fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n",
fcd17211
LB		 1921 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
1922 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
1923 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
1924 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
1925 (msr & (1 << 15)) ? "" : "UN",
6c34f160 1926 (unsigned int)msr & 0xF,
fcd17211
LB		 1927 pkg_cstate_limit_strings[pkg_cstate_limit]);
1928 return;
103a8fea
LB		 1929}
1930
6fb3143b
LB		 1931static void
1932dump_config_tdp(void)
1933{
1934 unsigned long long msr;
1935
1936 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
b7d8c148 1937 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
685b535b 1938 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF);
6fb3143b
LB		 1939
1940 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
b7d8c148 1941 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
6fb3143b 1942 if (msr) {
685b535b
CY		 1943 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
1944 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
1945 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
1946 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF);
6fb3143b 1947 }
b7d8c148 1948 fprintf(outf, ")\n");
6fb3143b
LB		 1949
1950 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
b7d8c148 1951 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
6fb3143b 1952 if (msr) {
685b535b
CY		 1953 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
1954 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
1955 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
1956 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF);
6fb3143b 1957 }
b7d8c148 1958 fprintf(outf, ")\n");
6fb3143b
LB		 1959
1960 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
b7d8c148 1961 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
6fb3143b 1962 if ((msr) & 0x3)
b7d8c148
LB		 1963 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
1964 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
1965 fprintf(outf, ")\n");
36229897 1966
6fb3143b 1967 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
b7d8c148 1968 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
685b535b 1969 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF);
b7d8c148
LB		 1970 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
1971 fprintf(outf, ")\n");
6fb3143b 1972}
5a63426e
LB		 1973
1974unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
1975
1976void print_irtl(void)
1977{
1978 unsigned long long msr;
1979
1980 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
1981 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr);
1982 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1983 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1984
1985 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
1986 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr);
1987 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1988 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1989
1990 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
1991 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr);
1992 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1993 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1994
1995 if (!do_irtl_hsw)
1996 return;
1997
1998 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
1999 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr);
2000 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2001 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2002
2003 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
2004 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr);
2005 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2006 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2007
2008 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
2009 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr);
2010 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2011 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2012
2013}
36229897
LB		 2014void free_fd_percpu(void)
2015{
2016 int i;
2017
01a67adf 2018 for (i = 0; i < topo.max_cpu_num + 1; ++i) {
36229897
LB		 2019 if (fd_percpu[i] != 0)
2020 close(fd_percpu[i]);
2021 }
2022
2023 free(fd_percpu);
6fb3143b
LB		 2024}
2025
c98d5d94 2026void free_all_buffers(void)
103a8fea 2027{
c98d5d94
LB		 2028 CPU_FREE(cpu_present_set);
2029 cpu_present_set = NULL;
36229897 2030 cpu_present_setsize = 0;
103a8fea 2031
c98d5d94
LB		 2032 CPU_FREE(cpu_affinity_set);
2033 cpu_affinity_set = NULL;
2034 cpu_affinity_setsize = 0;
103a8fea 2035
c98d5d94
LB		 2036 free(thread_even);
2037 free(core_even);
2038 free(package_even);
103a8fea 2039
c98d5d94
LB		 2040 thread_even = NULL;
2041 core_even = NULL;
2042 package_even = NULL;
103a8fea 2043
c98d5d94
LB		 2044 free(thread_odd);
2045 free(core_odd);
2046 free(package_odd);
103a8fea 2047
c98d5d94
LB		 2048 thread_odd = NULL;
2049 core_odd = NULL;
2050 package_odd = NULL;
103a8fea 2051
c98d5d94
LB		 2052 free(output_buffer);
2053 output_buffer = NULL;
2054 outp = NULL;
36229897
LB		 2055
2056 free_fd_percpu();
562a2d37
LB		 2057
2058 free(irq_column_2_cpu);
2059 free(irqs_per_cpu);
103a8fea
LB		 2060}
2061
57a42a34 2062
c98d5d94 2063/*
95aebc44 2064 * Parse a file containing a single int.
c98d5d94 2065 */
95aebc44 2066int parse_int_file(const char *fmt, ...)
103a8fea 2067{
95aebc44
JT		 2068 va_list args;
2069 char path[PATH_MAX];
c98d5d94 2070 FILE *filep;
95aebc44 2071 int value;
103a8fea 2072
95aebc44
JT		 2073 va_start(args, fmt);
2074 vsnprintf(path, sizeof(path), fmt, args);
2075 va_end(args);
57a42a34 2076 filep = fopen_or_die(path, "r");
b2c95d90
JT		 2077 if (fscanf(filep, "%d", &value) != 1)
2078 err(1, "%s: failed to parse number from file", path);
c98d5d94 2079 fclose(filep);
95aebc44
JT		 2080 return value;
2081}
2082
2083/*
e275b388
DC		 2084 * get_cpu_position_in_core(cpu)
2085 * return the position of the CPU among its HT siblings in the core
2086 * return -1 if the sibling is not in list
95aebc44 2087 */
e275b388 2088int get_cpu_position_in_core(int cpu)
95aebc44 2089{
e275b388
DC		 2090 char path[64];
2091 FILE *filep;
2092 int this_cpu;
2093 char character;
2094 int i;
2095
2096 sprintf(path,
2097 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list",
2098 cpu);
2099 filep = fopen(path, "r");
2100 if (filep == NULL) {
2101 perror(path);
2102 exit(1);
2103 }
2104
2105 for (i = 0; i < topo.num_threads_per_core; i++) {
2106 fscanf(filep, "%d", &this_cpu);
2107 if (this_cpu == cpu) {
2108 fclose(filep);
2109 return i;
2110 }
2111
2112 /* Account for no separator after last thread*/
2113 if (i != (topo.num_threads_per_core - 1))
2114 fscanf(filep, "%c", &character);
2115 }
2116
2117 fclose(filep);
2118 return -1;
103a8fea
LB		 2119}
2120
c98d5d94
LB		 2121/*
2122 * cpu_is_first_core_in_package(cpu)
2123 * return 1 if given CPU is 1st core in package
2124 */
2125int cpu_is_first_core_in_package(int cpu)
103a8fea 2126{
95aebc44 2127 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
103a8fea
LB		 2128}
2129
2130int get_physical_package_id(int cpu)
2131{
95aebc44 2132 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
103a8fea
LB		 2133}
2134
2135int get_core_id(int cpu)
2136{
95aebc44 2137 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
103a8fea
LB		 2138}
2139
c98d5d94
LB		 2140int get_num_ht_siblings(int cpu)
2141{
2142 char path[80];
2143 FILE *filep;
e275b388
DC		 2144 int sib1;
2145 int matches = 0;
c98d5d94 2146 char character;
e275b388
DC		 2147 char str[100];
2148 char *ch;
c98d5d94
LB		 2149
2150 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu);
57a42a34 2151 filep = fopen_or_die(path, "r");
e275b388 2152
c98d5d94
LB		 2153 /*
2154 * file format:
e275b388
DC		 2155 * A ',' separated or '-' separated set of numbers
2156 * (eg 1-2 or 1,3,4,5)
c98d5d94 2157 */
e275b388
DC		 2158 fscanf(filep, "%d%c\n", &sib1, &character);
2159 fseek(filep, 0, SEEK_SET);
2160 fgets(str, 100, filep);
2161 ch = strchr(str, character);
2162 while (ch != NULL) {
2163 matches++;
2164 ch = strchr(ch+1, character);
2165 }
c98d5d94
LB		 2166
2167 fclose(filep);
e275b388 2168 return matches+1;
c98d5d94
LB		 2169}
2170
103a8fea 2171/*
c98d5d94
LB		 2172 * run func(thread, core, package) in topology order
2173 * skip non-present cpus
103a8fea
LB		 2174 */
2175
c98d5d94
LB		 2176int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *,
2177 struct pkg_data *, struct thread_data *, struct core_data *,
2178 struct pkg_data *), struct thread_data *thread_base,
2179 struct core_data *core_base, struct pkg_data *pkg_base,
2180 struct thread_data *thread_base2, struct core_data *core_base2,
2181 struct pkg_data *pkg_base2)
2182{
2183 int retval, pkg_no, core_no, thread_no;
2184
2185 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
2186 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
2187 for (thread_no = 0; thread_no <
2188 topo.num_threads_per_core; ++thread_no) {
2189 struct thread_data *t, *t2;
2190 struct core_data *c, *c2;
2191 struct pkg_data *p, *p2;
2192
2193 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
2194
2195 if (cpu_is_not_present(t->cpu_id))
2196 continue;
2197
2198 t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no);
2199
2200 c = GET_CORE(core_base, core_no, pkg_no);
2201 c2 = GET_CORE(core_base2, core_no, pkg_no);
2202
2203 p = GET_PKG(pkg_base, pkg_no);
2204 p2 = GET_PKG(pkg_base2, pkg_no);
2205
2206 retval = func(t, c, p, t2, c2, p2);
2207 if (retval)
2208 return retval;
2209 }
2210 }
2211 }
2212 return 0;
2213}
2214
2215/*
2216 * run func(cpu) on every cpu in /proc/stat
2217 * return max_cpu number
2218 */
2219int for_all_proc_cpus(int (func)(int))
103a8fea
LB		 2220{
2221 FILE *fp;
c98d5d94 2222 int cpu_num;
103a8fea
LB		 2223 int retval;
2224
57a42a34 2225 fp = fopen_or_die(proc_stat, "r");
103a8fea
LB		 2226
2227 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
b2c95d90
JT		 2228 if (retval != 0)
2229 err(1, "%s: failed to parse format", proc_stat);
103a8fea 2230
c98d5d94
LB		 2231 while (1) {
2232 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
103a8fea
LB		 2233 if (retval != 1)
2234 break;
2235
c98d5d94
LB		 2236 retval = func(cpu_num);
2237 if (retval) {
2238 fclose(fp);
2239 return(retval);
2240 }
103a8fea
LB		 2241 }
2242 fclose(fp);
c98d5d94 2243 return 0;
103a8fea
LB		 2244}
2245
2246void re_initialize(void)
2247{
c98d5d94
LB		 2248 free_all_buffers();
2249 setup_all_buffers();
2250 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus);
103a8fea
LB		 2251}
2252
c98d5d94 2253
103a8fea 2254/*
c98d5d94
LB		 2255 * count_cpus()
2256 * remember the last one seen, it will be the max
103a8fea 2257 */
c98d5d94 2258int count_cpus(int cpu)
103a8fea 2259{
c98d5d94
LB		 2260 if (topo.max_cpu_num < cpu)
2261 topo.max_cpu_num = cpu;
103a8fea 2262
c98d5d94
LB		 2263 topo.num_cpus += 1;
2264 return 0;
2265}
2266int mark_cpu_present(int cpu)
2267{
2268 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
15aaa346 2269 return 0;
103a8fea
LB		 2270}
2271
562a2d37
LB		 2272/*
2273 * snapshot_proc_interrupts()
2274 *
2275 * read and record summary of /proc/interrupts
2276 *
2277 * return 1 if config change requires a restart, else return 0
2278 */
2279int snapshot_proc_interrupts(void)
2280{
2281 static FILE *fp;
2282 int column, retval;
2283
2284 if (fp == NULL)
2285 fp = fopen_or_die("/proc/interrupts", "r");
2286 else
2287 rewind(fp);
2288
2289 /* read 1st line of /proc/interrupts to get cpu* name for each column */
2290 for (column = 0; column < topo.num_cpus; ++column) {
2291 int cpu_number;
2292
2293 retval = fscanf(fp, " CPU%d", &cpu_number);
2294 if (retval != 1)
2295 break;
2296
2297 if (cpu_number > topo.max_cpu_num) {
2298 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num);
2299 return 1;
2300 }
2301
2302 irq_column_2_cpu[column] = cpu_number;
2303 irqs_per_cpu[cpu_number] = 0;
2304 }
2305
2306 /* read /proc/interrupt count lines and sum up irqs per cpu */
2307 while (1) {
2308 int column;
2309 char buf[64];
2310
2311 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */
2312 if (retval != 1)
2313 break;
2314
2315 /* read the count per cpu */
2316 for (column = 0; column < topo.num_cpus; ++column) {
2317
2318 int cpu_number, irq_count;
2319
2320 retval = fscanf(fp, " %d", &irq_count);
2321 if (retval != 1)
2322 break;
2323
2324 cpu_number = irq_column_2_cpu[column];
2325 irqs_per_cpu[cpu_number] += irq_count;
2326
2327 }
2328
2329 while (getc(fp) != '\n')
2330 ; /* flush interrupt description */
2331
2332 }
2333 return 0;
2334}
fdf676e5
LB		 2335/*
2336 * snapshot_gfx_rc6_ms()
2337 *
2338 * record snapshot of
2339 * /sys/class/drm/card0/power/rc6_residency_ms
2340 *
2341 * return 1 if config change requires a restart, else return 0
2342 */
2343int snapshot_gfx_rc6_ms(void)
2344{
2345 FILE *fp;
2346 int retval;
2347
2348 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
2349
2350 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms);
2351 if (retval != 1)
2352 err(1, "GFX rc6");
2353
2354 fclose(fp);
2355
2356 return 0;
2357}
27d47356
LB		 2358/*
2359 * snapshot_gfx_mhz()
2360 *
2361 * record snapshot of
2362 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
2363 *
2364 * return 1 if config change requires a restart, else return 0
2365 */
2366int snapshot_gfx_mhz(void)
2367{
2368 static FILE *fp;
2369 int retval;
2370
2371 if (fp == NULL)
2372 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
2373 else
2374 rewind(fp);
2375
2376 retval = fscanf(fp, "%d", &gfx_cur_mhz);
2377 if (retval != 1)
2378 err(1, "GFX MHz");
2379
2380 return 0;
2381}
562a2d37
LB		 2382
2383/*
2384 * snapshot /proc and /sys files
2385 *
2386 * return 1 if configuration restart needed, else return 0
2387 */
2388int snapshot_proc_sysfs_files(void)
2389{
2390 if (snapshot_proc_interrupts())
2391 return 1;
2392
812db3f7 2393 if (DO_BIC(BIC_GFX_rc6))
fdf676e5
LB		 2394 snapshot_gfx_rc6_ms();
2395
812db3f7 2396 if (DO_BIC(BIC_GFXMHz))
27d47356
LB		 2397 snapshot_gfx_mhz();
2398
562a2d37
LB		 2399 return 0;
2400}
2401
103a8fea
LB		 2402void turbostat_loop()
2403{
c98d5d94 2404 int retval;
e52966c0 2405 int restarted = 0;
c98d5d94 2406
103a8fea 2407restart:
e52966c0
LB		 2408 restarted++;
2409
562a2d37 2410 snapshot_proc_sysfs_files();
c98d5d94 2411 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
d91bb17c
LB		 2412 if (retval < -1) {
2413 exit(retval);
2414 } else if (retval == -1) {
e52966c0
LB		 2415 if (restarted > 1) {
2416 exit(retval);
2417 }
c98d5d94
LB		 2418 re_initialize();
2419 goto restart;
2420 }
e52966c0 2421 restarted = 0;
103a8fea
LB		 2422 gettimeofday(&tv_even, (struct timezone *)NULL);
2423
2424 while (1) {
c98d5d94 2425 if (for_all_proc_cpus(cpu_is_not_present)) {
103a8fea
LB		 2426 re_initialize();
2427 goto restart;
2428 }
2a0609c0 2429 nanosleep(&interval_ts, NULL);
562a2d37
LB		 2430 if (snapshot_proc_sysfs_files())
2431 goto restart;
c98d5d94 2432 retval = for_all_cpus(get_counters, ODD_COUNTERS);
d91bb17c
LB		 2433 if (retval < -1) {
2434 exit(retval);
2435 } else if (retval == -1) {
15aaa346
LB		 2436 re_initialize();
2437 goto restart;
2438 }
103a8fea 2439 gettimeofday(&tv_odd, (struct timezone *)NULL);
103a8fea 2440 timersub(&tv_odd, &tv_even, &tv_delta);
ba3dec99
LB		 2441 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) {
2442 re_initialize();
2443 goto restart;
2444 }
c98d5d94
LB		 2445 compute_average(EVEN_COUNTERS);
2446 format_all_counters(EVEN_COUNTERS);
b7d8c148 2447 flush_output_stdout();
2a0609c0 2448 nanosleep(&interval_ts, NULL);
562a2d37
LB		 2449 if (snapshot_proc_sysfs_files())
2450 goto restart;
c98d5d94 2451 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
d91bb17c
LB		 2452 if (retval < -1) {
2453 exit(retval);
2454 } else if (retval == -1) {
103a8fea
LB		 2455 re_initialize();
2456 goto restart;
2457 }
103a8fea 2458 gettimeofday(&tv_even, (struct timezone *)NULL);
103a8fea 2459 timersub(&tv_even, &tv_odd, &tv_delta);
ba3dec99
LB		 2460 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) {
2461 re_initialize();
2462 goto restart;
2463 }
c98d5d94
LB		 2464 compute_average(ODD_COUNTERS);
2465 format_all_counters(ODD_COUNTERS);
b7d8c148 2466 flush_output_stdout();
103a8fea
LB		 2467 }
2468}
2469
2470void check_dev_msr()
2471{
2472 struct stat sb;
7ce7d5de 2473 char pathname[32];
103a8fea 2474
7ce7d5de
PB		 2475 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
2476 if (stat(pathname, &sb))
a21d38c8
LB		 2477 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
2478 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
103a8fea
LB		 2479}
2480
98481e79 2481void check_permissions()
103a8fea 2482{
98481e79
LB		 2483 struct __user_cap_header_struct cap_header_data;
2484 cap_user_header_t cap_header = &cap_header_data;
2485 struct __user_cap_data_struct cap_data_data;
2486 cap_user_data_t cap_data = &cap_data_data;
2487 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap);
2488 int do_exit = 0;
7ce7d5de 2489 char pathname[32];
98481e79
LB		 2490
2491 /* check for CAP_SYS_RAWIO */
2492 cap_header->pid = getpid();
2493 cap_header->version = _LINUX_CAPABILITY_VERSION;
2494 if (capget(cap_header, cap_data) < 0)
2495 err(-6, "capget(2) failed");
2496
2497 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) {
2498 do_exit++;
2499 warnx("capget(CAP_SYS_RAWIO) failed,"
2500 " try \"# setcap cap_sys_rawio=ep %s\"", progname);
2501 }
2502
2503 /* test file permissions */
7ce7d5de
PB		 2504 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
2505 if (euidaccess(pathname, R_OK)) {
98481e79
LB		 2506 do_exit++;
2507 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
2508 }
2509
2510 /* if all else fails, thell them to be root */
2511 if (do_exit)
2512 if (getuid() != 0)
d7899447 2513 warnx("... or simply run as root");
98481e79
LB		 2514
2515 if (do_exit)
2516 exit(-6);
103a8fea
LB		 2517}
2518
d7899447
LB		 2519/*
2520 * NHM adds support for additional MSRs:
2521 *
2522 * MSR_SMI_COUNT 0x00000034
2523 *
ec0adc53 2524 * MSR_PLATFORM_INFO 0x000000ce
1df2e55a 2525 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
d7899447 2526 *
cf4cbe53
LB		 2527 * MSR_MISC_PWR_MGMT 0x000001aa
2528 *
d7899447
LB		 2529 * MSR_PKG_C3_RESIDENCY 0x000003f8
2530 * MSR_PKG_C6_RESIDENCY 0x000003f9
2531 * MSR_CORE_C3_RESIDENCY 0x000003fc
2532 * MSR_CORE_C6_RESIDENCY 0x000003fd
2533 *
ee7e38e3 2534 * Side effect:
1df2e55a 2535 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL
33148d67 2536 * sets has_misc_feature_control
d7899447 2537 */
ee7e38e3 2538int probe_nhm_msrs(unsigned int family, unsigned int model)
103a8fea 2539{
ee7e38e3 2540 unsigned long long msr;
21ed5574 2541 unsigned int base_ratio;
ee7e38e3
LB		 2542 int *pkg_cstate_limits;
2543
103a8fea
LB		 2544 if (!genuine_intel)
2545 return 0;
2546
2547 if (family != 6)
2548 return 0;
2549
21ed5574
LB		 2550 bclk = discover_bclk(family, model);
2551
103a8fea 2552 switch (model) {
869ce69e
LB		 2553 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
2554 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
103a8fea 2555 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
869ce69e
LB		 2556 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */
2557 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */
2558 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
2559 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
ee7e38e3
LB		 2560 pkg_cstate_limits = nhm_pkg_cstate_limits;
2561 break;
869ce69e
LB		 2562 case INTEL_FAM6_SANDYBRIDGE: /* SNB */
2563 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */
2564 case INTEL_FAM6_IVYBRIDGE: /* IVB */
2565 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
ee7e38e3 2566 pkg_cstate_limits = snb_pkg_cstate_limits;
33148d67 2567 has_misc_feature_control = 1;
ee7e38e3 2568 break;
869ce69e
LB		 2569 case INTEL_FAM6_HASWELL_CORE: /* HSW */
2570 case INTEL_FAM6_HASWELL_X: /* HSX */
2571 case INTEL_FAM6_HASWELL_ULT: /* HSW */
2572 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
2573 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
2574 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
2575 case INTEL_FAM6_BROADWELL_X: /* BDX */
2576 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2577 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
2578 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
2579 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
2580 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
ee7e38e3 2581 pkg_cstate_limits = hsw_pkg_cstate_limits;
33148d67 2582 has_misc_feature_control = 1;
ee7e38e3 2583 break;
d8ebb442
LB		 2584 case INTEL_FAM6_SKYLAKE_X: /* SKX */
2585 pkg_cstate_limits = skx_pkg_cstate_limits;
33148d67 2586 has_misc_feature_control = 1;
d8ebb442 2587 break;
869ce69e 2588 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
cf4cbe53 2589 no_MSR_MISC_PWR_MGMT = 1;
869ce69e 2590 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
ee7e38e3
LB		 2591 pkg_cstate_limits = slv_pkg_cstate_limits;
2592 break;
869ce69e 2593 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */
ee7e38e3 2594 pkg_cstate_limits = amt_pkg_cstate_limits;
cf4cbe53 2595 no_MSR_MISC_PWR_MGMT = 1;
ee7e38e3 2596 break;
869ce69e 2597 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */
005c82d6 2598 case INTEL_FAM6_XEON_PHI_KNM:
ee7e38e3
LB		 2599 pkg_cstate_limits = phi_pkg_cstate_limits;
2600 break;
869ce69e 2601 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
ac01ac13 2602 case INTEL_FAM6_ATOM_GEMINI_LAKE:
869ce69e 2603 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
e4085d54
LB		 2604 pkg_cstate_limits = bxt_pkg_cstate_limits;
2605 break;
103a8fea
LB		 2606 default:
2607 return 0;
2608 }
1df2e55a 2609 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
e9257f5f 2610 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
ee7e38e3 2611
ec0adc53 2612 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
21ed5574
LB		 2613 base_ratio = (msr >> 8) & 0xFF;
2614
2615 base_hz = base_ratio * bclk * 1000000;
2616 has_base_hz = 1;
ee7e38e3 2617 return 1;
103a8fea 2618}
0f7887c4 2619/*
495c7654 2620 * SLV client has support for unique MSRs:
0f7887c4
LB		 2621 *
2622 * MSR_CC6_DEMOTION_POLICY_CONFIG
2623 * MSR_MC6_DEMOTION_POLICY_CONFIG
2624 */
2625
2626int has_slv_msrs(unsigned int family, unsigned int model)
2627{
2628 if (!genuine_intel)
2629 return 0;
2630
2631 switch (model) {
2632 case INTEL_FAM6_ATOM_SILVERMONT1:
2633 case INTEL_FAM6_ATOM_MERRIFIELD:
2634 case INTEL_FAM6_ATOM_MOOREFIELD:
2635 return 1;
2636 }
2637 return 0;
2638}
7170a374
LB		 2639int is_dnv(unsigned int family, unsigned int model)
2640{
2641
2642 if (!genuine_intel)
2643 return 0;
2644
2645 switch (model) {
2646 case INTEL_FAM6_ATOM_DENVERTON:
2647 return 1;
2648 }
2649 return 0;
2650}
ade0ebac
LB		 2651int is_bdx(unsigned int family, unsigned int model)
2652{
2653
2654 if (!genuine_intel)
2655 return 0;
2656
2657 switch (model) {
2658 case INTEL_FAM6_BROADWELL_X:
2659 case INTEL_FAM6_BROADWELL_XEON_D:
2660 return 1;
2661 }
2662 return 0;
2663}
34c76197
LB		 2664int is_skx(unsigned int family, unsigned int model)
2665{
2666
2667 if (!genuine_intel)
2668 return 0;
2669
2670 switch (model) {
2671 case INTEL_FAM6_SKYLAKE_X:
2672 return 1;
2673 }
2674 return 0;
2675}
0f7887c4 2676
31e07522 2677int has_turbo_ratio_limit(unsigned int family, unsigned int model)
d7899447 2678{
0f7887c4
LB		 2679 if (has_slv_msrs(family, model))
2680 return 0;
2681
d7899447
LB		 2682 switch (model) {
2683 /* Nehalem compatible, but do not include turbo-ratio limit support */
869ce69e
LB		 2684 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
2685 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
2686 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */
005c82d6 2687 case INTEL_FAM6_XEON_PHI_KNM:
d7899447
LB		 2688 return 0;
2689 default:
2690 return 1;
2691 }
2692}
0f7887c4
LB		 2693int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model)
2694{
2695 if (has_slv_msrs(family, model))
2696 return 1;
2697
2698 return 0;
2699}
6574a5d5
LB		 2700int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
2701{
2702 if (!genuine_intel)
2703 return 0;
2704
2705 if (family != 6)
2706 return 0;
2707
2708 switch (model) {
869ce69e
LB		 2709 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
2710 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
fcd17211
LB		 2711 return 1;
2712 default:
2713 return 0;
2714 }
2715}
2716int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model)
2717{
2718 if (!genuine_intel)
2719 return 0;
2720
2721 if (family != 6)
2722 return 0;
2723
2724 switch (model) {
869ce69e 2725 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
6574a5d5
LB		 2726 return 1;
2727 default:
2728 return 0;
2729 }
2730}
2731
fb5d4327
DC		 2732int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model)
2733{
2734 if (!genuine_intel)
2735 return 0;
2736
2737 if (family != 6)
2738 return 0;
2739
2740 switch (model) {
869ce69e 2741 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
005c82d6 2742 case INTEL_FAM6_XEON_PHI_KNM:
fb5d4327
DC		 2743 return 1;
2744 default:
2745 return 0;
2746 }
2747}
31e07522
LB		 2748int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model)
2749{
2750 if (!genuine_intel)
2751 return 0;
2752
2753 if (family != 6)
2754 return 0;
2755
2756 switch (model) {
2757 case INTEL_FAM6_ATOM_GOLDMONT:
2758 case INTEL_FAM6_SKYLAKE_X:
2759 return 1;
2760 default:
2761 return 0;
2762 }
2763}
6fb3143b
LB		 2764int has_config_tdp(unsigned int family, unsigned int model)
2765{
2766 if (!genuine_intel)
2767 return 0;
2768
2769 if (family != 6)
2770 return 0;
2771
2772 switch (model) {
869ce69e
LB		 2773 case INTEL_FAM6_IVYBRIDGE: /* IVB */
2774 case INTEL_FAM6_HASWELL_CORE: /* HSW */
2775 case INTEL_FAM6_HASWELL_X: /* HSX */
2776 case INTEL_FAM6_HASWELL_ULT: /* HSW */
2777 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
2778 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
2779 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
2780 case INTEL_FAM6_BROADWELL_X: /* BDX */
2781 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2782 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
2783 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
2784 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
2785 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
2786 case INTEL_FAM6_SKYLAKE_X: /* SKX */
2787
2788 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
005c82d6 2789 case INTEL_FAM6_XEON_PHI_KNM:
6fb3143b
LB		 2790 return 1;
2791 default:
2792 return 0;
2793 }
2794}
2795
fcd17211 2796static void
1b69317d 2797dump_cstate_pstate_config_info(unsigned int family, unsigned int model)
fcd17211
LB		 2798{
2799 if (!do_nhm_platform_info)
2800 return;
2801
2802 dump_nhm_platform_info();
2803
2804 if (has_hsw_turbo_ratio_limit(family, model))
2805 dump_hsw_turbo_ratio_limits();
2806
2807 if (has_ivt_turbo_ratio_limit(family, model))
2808 dump_ivt_turbo_ratio_limits();
2809
31e07522
LB		 2810 if (has_turbo_ratio_limit(family, model))
2811 dump_turbo_ratio_limits(family, model);
fcd17211 2812
0f7887c4
LB		 2813 if (has_atom_turbo_ratio_limit(family, model))
2814 dump_atom_turbo_ratio_limits();
2815
fb5d4327
DC		 2816 if (has_knl_turbo_ratio_limit(family, model))
2817 dump_knl_turbo_ratio_limits();
2818
6fb3143b
LB		 2819 if (has_config_tdp(family, model))
2820 dump_config_tdp();
2821
fcd17211
LB		 2822 dump_nhm_cst_cfg();
2823}
2824
2825
889facbe
LB		 2826/*
2827 * print_epb()
2828 * Decode the ENERGY_PERF_BIAS MSR
2829 */
2830int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2831{
2832 unsigned long long msr;
2833 char *epb_string;
2834 int cpu;
2835
2836 if (!has_epb)
2837 return 0;
2838
2839 cpu = t->cpu_id;
2840
2841 /* EPB is per-package */
2842 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2843 return 0;
2844
2845 if (cpu_migrate(cpu)) {
b7d8c148 2846 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 2847 return -1;
2848 }
2849
2850 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr))
2851 return 0;
2852
e9be7dd6 2853 switch (msr & 0xF) {
889facbe
LB		 2854 case ENERGY_PERF_BIAS_PERFORMANCE:
2855 epb_string = "performance";
2856 break;
2857 case ENERGY_PERF_BIAS_NORMAL:
2858 epb_string = "balanced";
2859 break;
2860 case ENERGY_PERF_BIAS_POWERSAVE:
2861 epb_string = "powersave";
2862 break;
2863 default:
2864 epb_string = "custom";
2865 break;
2866 }
b7d8c148 2867 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string);
889facbe
LB		 2868
2869 return 0;
2870}
7f5c258e
LB		 2871/*
2872 * print_hwp()
2873 * Decode the MSR_HWP_CAPABILITIES
2874 */
2875int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2876{
2877 unsigned long long msr;
2878 int cpu;
2879
2880 if (!has_hwp)
2881 return 0;
2882
2883 cpu = t->cpu_id;
2884
2885 /* MSR_HWP_CAPABILITIES is per-package */
2886 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2887 return 0;
2888
2889 if (cpu_migrate(cpu)) {
b7d8c148 2890 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
7f5c258e
LB		 2891 return -1;
2892 }
2893
2894 if (get_msr(cpu, MSR_PM_ENABLE, &msr))
2895 return 0;
2896
b7d8c148 2897 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n",
7f5c258e
LB		 2898 cpu, msr, (msr & (1 << 0)) ? "" : "No-");
2899
2900 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
2901 if ((msr & (1 << 0)) == 0)
2902 return 0;
2903
2904 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
2905 return 0;
2906
b7d8c148 2907 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
7f5c258e
LB		 2908 "(high 0x%x guar 0x%x eff 0x%x low 0x%x)\n",
2909 cpu, msr,
2910 (unsigned int)HWP_HIGHEST_PERF(msr),
2911 (unsigned int)HWP_GUARANTEED_PERF(msr),
2912 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr),
2913 (unsigned int)HWP_LOWEST_PERF(msr));
2914
2915 if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
2916 return 0;
2917
b7d8c148 2918 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
7f5c258e
LB		 2919 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x pkg 0x%x)\n",
2920 cpu, msr,
2921 (unsigned int)(((msr) >> 0) & 0xff),
2922 (unsigned int)(((msr) >> 8) & 0xff),
2923 (unsigned int)(((msr) >> 16) & 0xff),
2924 (unsigned int)(((msr) >> 24) & 0xff),
2925 (unsigned int)(((msr) >> 32) & 0xff3),
2926 (unsigned int)(((msr) >> 42) & 0x1));
2927
2928 if (has_hwp_pkg) {
2929 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
2930 return 0;
2931
b7d8c148 2932 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
7f5c258e
LB		 2933 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x)\n",
2934 cpu, msr,
2935 (unsigned int)(((msr) >> 0) & 0xff),
2936 (unsigned int)(((msr) >> 8) & 0xff),
2937 (unsigned int)(((msr) >> 16) & 0xff),
2938 (unsigned int)(((msr) >> 24) & 0xff),
2939 (unsigned int)(((msr) >> 32) & 0xff3));
2940 }
2941 if (has_hwp_notify) {
2942 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
2943 return 0;
2944
b7d8c148 2945 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
7f5c258e
LB		 2946 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
2947 cpu, msr,
2948 ((msr) & 0x1) ? "EN" : "Dis",
2949 ((msr) & 0x2) ? "EN" : "Dis");
2950 }
2951 if (get_msr(cpu, MSR_HWP_STATUS, &msr))
2952 return 0;
2953
b7d8c148 2954 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
7f5c258e
LB		 2955 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
2956 cpu, msr,
2957 ((msr) & 0x1) ? "" : "No-",
2958 ((msr) & 0x2) ? "" : "No-");
889facbe
LB		 2959
2960 return 0;
2961}
2962
3a9a941d
LB		 2963/*
2964 * print_perf_limit()
2965 */
2966int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2967{
2968 unsigned long long msr;
2969 int cpu;
2970
2971 cpu = t->cpu_id;
2972
2973 /* per-package */
2974 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2975 return 0;
2976
2977 if (cpu_migrate(cpu)) {
b7d8c148 2978 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3a9a941d
LB		 2979 return -1;
2980 }
2981
2982 if (do_core_perf_limit_reasons) {
2983 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 2984 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2985 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
e33cbe85 2986 (msr & 1 << 15) ? "bit15, " : "",
3a9a941d 2987 (msr & 1 << 14) ? "bit14, " : "",
e33cbe85
LB		 2988 (msr & 1 << 13) ? "Transitions, " : "",
2989 (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
2990 (msr & 1 << 11) ? "PkgPwrL2, " : "",
2991 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2992 (msr & 1 << 9) ? "CorePwr, " : "",
2993 (msr & 1 << 8) ? "Amps, " : "",
2994 (msr & 1 << 6) ? "VR-Therm, " : "",
2995 (msr & 1 << 5) ? "Auto-HWP, " : "",
2996 (msr & 1 << 4) ? "Graphics, " : "",
2997 (msr & 1 << 2) ? "bit2, " : "",
2998 (msr & 1 << 1) ? "ThermStatus, " : "",
2999 (msr & 1 << 0) ? "PROCHOT, " : "");
b7d8c148 3000 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
e33cbe85 3001 (msr & 1 << 31) ? "bit31, " : "",
3a9a941d 3002 (msr & 1 << 30) ? "bit30, " : "",
e33cbe85
LB		 3003 (msr & 1 << 29) ? "Transitions, " : "",
3004 (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
3005 (msr & 1 << 27) ? "PkgPwrL2, " : "",
3006 (msr & 1 << 26) ? "PkgPwrL1, " : "",
3007 (msr & 1 << 25) ? "CorePwr, " : "",
3008 (msr & 1 << 24) ? "Amps, " : "",
3009 (msr & 1 << 22) ? "VR-Therm, " : "",
3010 (msr & 1 << 21) ? "Auto-HWP, " : "",
3011 (msr & 1 << 20) ? "Graphics, " : "",
3012 (msr & 1 << 18) ? "bit18, " : "",
3013 (msr & 1 << 17) ? "ThermStatus, " : "",
3014 (msr & 1 << 16) ? "PROCHOT, " : "");
3a9a941d
LB		 3015
3016 }
3017 if (do_gfx_perf_limit_reasons) {
3018 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 3019 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
3020 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
3a9a941d
LB		 3021 (msr & 1 << 0) ? "PROCHOT, " : "",
3022 (msr & 1 << 1) ? "ThermStatus, " : "",
3023 (msr & 1 << 4) ? "Graphics, " : "",
3024 (msr & 1 << 6) ? "VR-Therm, " : "",
3025 (msr & 1 << 8) ? "Amps, " : "",
3026 (msr & 1 << 9) ? "GFXPwr, " : "",
3027 (msr & 1 << 10) ? "PkgPwrL1, " : "",
3028 (msr & 1 << 11) ? "PkgPwrL2, " : "");
b7d8c148 3029 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
3a9a941d
LB		 3030 (msr & 1 << 16) ? "PROCHOT, " : "",
3031 (msr & 1 << 17) ? "ThermStatus, " : "",
3032 (msr & 1 << 20) ? "Graphics, " : "",
3033 (msr & 1 << 22) ? "VR-Therm, " : "",
3034 (msr & 1 << 24) ? "Amps, " : "",
3035 (msr & 1 << 25) ? "GFXPwr, " : "",
3036 (msr & 1 << 26) ? "PkgPwrL1, " : "",
3037 (msr & 1 << 27) ? "PkgPwrL2, " : "");
3038 }
3039 if (do_ring_perf_limit_reasons) {
3040 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 3041 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
3042 fprintf(outf, " (Active: %s%s%s%s%s%s)",
3a9a941d
LB		 3043 (msr & 1 << 0) ? "PROCHOT, " : "",
3044 (msr & 1 << 1) ? "ThermStatus, " : "",
3045 (msr & 1 << 6) ? "VR-Therm, " : "",
3046 (msr & 1 << 8) ? "Amps, " : "",
3047 (msr & 1 << 10) ? "PkgPwrL1, " : "",
3048 (msr & 1 << 11) ? "PkgPwrL2, " : "");
b7d8c148 3049 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
3a9a941d
LB		 3050 (msr & 1 << 16) ? "PROCHOT, " : "",
3051 (msr & 1 << 17) ? "ThermStatus, " : "",
3052 (msr & 1 << 22) ? "VR-Therm, " : "",
3053 (msr & 1 << 24) ? "Amps, " : "",
3054 (msr & 1 << 26) ? "PkgPwrL1, " : "",
3055 (msr & 1 << 27) ? "PkgPwrL2, " : "");
3056 }
3057 return 0;
3058}
3059
889facbe
LB		 3060#define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
3061#define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
3062
1b69317d 3063double get_tdp(unsigned int model)
144b44b1
LB		 3064{
3065 unsigned long long msr;
3066
3067 if (do_rapl & RAPL_PKG_POWER_INFO)
7ce7d5de 3068 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
144b44b1
LB		 3069 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
3070
3071 switch (model) {
869ce69e
LB		 3072 case INTEL_FAM6_ATOM_SILVERMONT1:
3073 case INTEL_FAM6_ATOM_SILVERMONT2:
144b44b1
LB		 3074 return 30.0;
3075 default:
3076 return 135.0;
3077 }
3078}
3079
40ee8e3b
AS		 3080/*
3081 * rapl_dram_energy_units_probe()
3082 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
3083 */
3084static double
3085rapl_dram_energy_units_probe(int model, double rapl_energy_units)
3086{
3087 /* only called for genuine_intel, family 6 */
3088
3089 switch (model) {
869ce69e
LB		 3090 case INTEL_FAM6_HASWELL_X: /* HSX */
3091 case INTEL_FAM6_BROADWELL_X: /* BDX */
3092 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
3093 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
005c82d6 3094 case INTEL_FAM6_XEON_PHI_KNM:
40ee8e3b
AS		 3095 return (rapl_dram_energy_units = 15.3 / 1000000);
3096 default:
3097 return (rapl_energy_units);
3098 }
3099}
3100
144b44b1 3101
889facbe
LB		 3102/*
3103 * rapl_probe()
3104 *
144b44b1 3105 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
889facbe
LB		 3106 */
3107void rapl_probe(unsigned int family, unsigned int model)
3108{
3109 unsigned long long msr;
144b44b1 3110 unsigned int time_unit;
889facbe
LB		 3111 double tdp;
3112
3113 if (!genuine_intel)
3114 return;
3115
3116 if (family != 6)
3117 return;
3118
3119 switch (model) {
869ce69e
LB		 3120 case INTEL_FAM6_SANDYBRIDGE:
3121 case INTEL_FAM6_IVYBRIDGE:
3122 case INTEL_FAM6_HASWELL_CORE: /* HSW */
3123 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3124 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
3125 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
3126 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
144b44b1 3127 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
812db3f7
LB		 3128 if (rapl_joules) {
3129 BIC_PRESENT(BIC_Pkg_J);
3130 BIC_PRESENT(BIC_Cor_J);
3131 BIC_PRESENT(BIC_GFX_J);
3132 } else {
3133 BIC_PRESENT(BIC_PkgWatt);
3134 BIC_PRESENT(BIC_CorWatt);
3135 BIC_PRESENT(BIC_GFXWatt);
3136 }
889facbe 3137 break;
869ce69e 3138 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
ac01ac13 3139 case INTEL_FAM6_ATOM_GEMINI_LAKE:
e4085d54 3140 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
812db3f7
LB		 3141 if (rapl_joules)
3142 BIC_PRESENT(BIC_Pkg_J);
3143 else
3144 BIC_PRESENT(BIC_PkgWatt);
e4085d54 3145 break;
869ce69e
LB		 3146 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3147 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3148 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3149 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
0b2bb692 3150 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
812db3f7
LB		 3151 BIC_PRESENT(BIC_PKG__);
3152 BIC_PRESENT(BIC_RAM__);
3153 if (rapl_joules) {
3154 BIC_PRESENT(BIC_Pkg_J);
3155 BIC_PRESENT(BIC_Cor_J);
3156 BIC_PRESENT(BIC_RAM_J);
3157 } else {
3158 BIC_PRESENT(BIC_PkgWatt);
3159 BIC_PRESENT(BIC_CorWatt);
3160 BIC_PRESENT(BIC_RAMWatt);
3161 }
0b2bb692 3162 break;
869ce69e
LB		 3163 case INTEL_FAM6_HASWELL_X: /* HSX */
3164 case INTEL_FAM6_BROADWELL_X: /* BDX */
3165 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
3166 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3167 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
005c82d6 3168 case INTEL_FAM6_XEON_PHI_KNM:
0b2bb692 3169 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
812db3f7
LB		 3170 BIC_PRESENT(BIC_PKG__);
3171 BIC_PRESENT(BIC_RAM__);
3172 if (rapl_joules) {
3173 BIC_PRESENT(BIC_Pkg_J);
3174 BIC_PRESENT(BIC_RAM_J);
3175 } else {
3176 BIC_PRESENT(BIC_PkgWatt);
3177 BIC_PRESENT(BIC_RAMWatt);
3178 }
e6f9bb3c 3179 break;
869ce69e
LB		 3180 case INTEL_FAM6_SANDYBRIDGE_X:
3181 case INTEL_FAM6_IVYBRIDGE_X:
0b2bb692 3182 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
812db3f7
LB		 3183 BIC_PRESENT(BIC_PKG__);
3184 BIC_PRESENT(BIC_RAM__);
3185 if (rapl_joules) {
3186 BIC_PRESENT(BIC_Pkg_J);
3187 BIC_PRESENT(BIC_Cor_J);
3188 BIC_PRESENT(BIC_RAM_J);
3189 } else {
3190 BIC_PRESENT(BIC_PkgWatt);
3191 BIC_PRESENT(BIC_CorWatt);
3192 BIC_PRESENT(BIC_RAMWatt);
3193 }
144b44b1 3194 break;
869ce69e
LB		 3195 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
3196 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
9148494c 3197 do_rapl = RAPL_PKG | RAPL_CORES;
812db3f7
LB		 3198 if (rapl_joules) {
3199 BIC_PRESENT(BIC_Pkg_J);
3200 BIC_PRESENT(BIC_Cor_J);
3201 } else {
3202 BIC_PRESENT(BIC_PkgWatt);
3203 BIC_PRESENT(BIC_CorWatt);
3204 }
889facbe 3205 break;
869ce69e 3206 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
0f644909 3207 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
812db3f7
LB		 3208 BIC_PRESENT(BIC_PKG__);
3209 BIC_PRESENT(BIC_RAM__);
3210 if (rapl_joules) {
3211 BIC_PRESENT(BIC_Pkg_J);
3212 BIC_PRESENT(BIC_Cor_J);
3213 BIC_PRESENT(BIC_RAM_J);
3214 } else {
3215 BIC_PRESENT(BIC_PkgWatt);
3216 BIC_PRESENT(BIC_CorWatt);
3217 BIC_PRESENT(BIC_RAMWatt);
3218 }
0f644909 3219 break;
889facbe
LB		 3220 default:
3221 return;
3222 }
3223
3224 /* units on package 0, verify later other packages match */
7ce7d5de 3225 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
889facbe
LB		 3226 return;
3227
3228 rapl_power_units = 1.0 / (1 << (msr & 0xF));
869ce69e 3229 if (model == INTEL_FAM6_ATOM_SILVERMONT1)
144b44b1
LB		 3230 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
3231 else
3232 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
889facbe 3233
40ee8e3b
AS		 3234 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units);
3235
144b44b1
LB		 3236 time_unit = msr >> 16 & 0xF;
3237 if (time_unit == 0)
3238 time_unit = 0xA;
889facbe 3239
144b44b1 3240 rapl_time_units = 1.0 / (1 << (time_unit));
889facbe 3241
144b44b1 3242 tdp = get_tdp(model);
889facbe 3243
144b44b1 3244 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
96e47158 3245 if (!quiet)
b7d8c148 3246 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
889facbe
LB		 3247
3248 return;
3249}
3250
1b69317d 3251void perf_limit_reasons_probe(unsigned int family, unsigned int model)
3a9a941d
LB		 3252{
3253 if (!genuine_intel)
3254 return;
3255
3256 if (family != 6)
3257 return;
3258
3259 switch (model) {
869ce69e
LB		 3260 case INTEL_FAM6_HASWELL_CORE: /* HSW */
3261 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3262 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
3a9a941d 3263 do_gfx_perf_limit_reasons = 1;
869ce69e 3264 case INTEL_FAM6_HASWELL_X: /* HSX */
3a9a941d
LB		 3265 do_core_perf_limit_reasons = 1;
3266 do_ring_perf_limit_reasons = 1;
3267 default:
3268 return;
3269 }
3270}
3271
889facbe
LB		 3272int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3273{
3274 unsigned long long msr;
3275 unsigned int dts;
3276 int cpu;
3277
3278 if (!(do_dts || do_ptm))
3279 return 0;
3280
3281 cpu = t->cpu_id;
3282
3283 /* DTS is per-core, no need to print for each thread */
388e9c81 3284 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
889facbe
LB		 3285 return 0;
3286
3287 if (cpu_migrate(cpu)) {
b7d8c148 3288 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 3289 return -1;
3290 }
3291
3292 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) {
3293 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
3294 return 0;
3295
3296 dts = (msr >> 16) & 0x7F;
b7d8c148 3297 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n",
889facbe
LB		 3298 cpu, msr, tcc_activation_temp - dts);
3299
3300#ifdef THERM_DEBUG
3301 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
3302 return 0;
3303
3304 dts = (msr >> 16) & 0x7F;
3305 dts2 = (msr >> 8) & 0x7F;
b7d8c148 3306 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
889facbe
LB		 3307 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
3308#endif
3309 }
3310
3311
3312 if (do_dts) {
3313 unsigned int resolution;
3314
3315 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
3316 return 0;
3317
3318 dts = (msr >> 16) & 0x7F;
3319 resolution = (msr >> 27) & 0xF;
b7d8c148 3320 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
889facbe
LB		 3321 cpu, msr, tcc_activation_temp - dts, resolution);
3322
3323#ifdef THERM_DEBUG
3324 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
3325 return 0;
3326
3327 dts = (msr >> 16) & 0x7F;
3328 dts2 = (msr >> 8) & 0x7F;
b7d8c148 3329 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
889facbe
LB		 3330 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
3331#endif
3332 }
3333
3334 return 0;
3335}
36229897 3336
889facbe
LB		 3337void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
3338{
b7d8c148 3339 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n",
889facbe
LB		 3340 cpu, label,
3341 ((msr >> 15) & 1) ? "EN" : "DIS",
3342 ((msr >> 0) & 0x7FFF) * rapl_power_units,
3343 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
3344 (((msr >> 16) & 1) ? "EN" : "DIS"));
3345
3346 return;
3347}
3348
3349int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3350{
3351 unsigned long long msr;
3352 int cpu;
889facbe
LB		 3353
3354 if (!do_rapl)
3355 return 0;
3356
3357 /* RAPL counters are per package, so print only for 1st thread/package */
3358 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3359 return 0;
3360
3361 cpu = t->cpu_id;
3362 if (cpu_migrate(cpu)) {
b7d8c148 3363 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 3364 return -1;
3365 }
3366
3367 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
3368 return -1;
3369
96e47158
LB		 3370 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr,
3371 rapl_power_units, rapl_energy_units, rapl_time_units);
3372
144b44b1
LB		 3373 if (do_rapl & RAPL_PKG_POWER_INFO) {
3374
889facbe
LB		 3375 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
3376 return -5;
3377
3378
b7d8c148 3379 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
889facbe
LB		 3380 cpu, msr,
3381 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3382 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3383 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3384 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
3385
144b44b1
LB		 3386 }
3387 if (do_rapl & RAPL_PKG) {
3388
889facbe
LB		 3389 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
3390 return -9;
3391
b7d8c148 3392 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
96e47158 3393 cpu, msr, (msr >> 63) & 1 ? "" : "UN");
889facbe
LB		 3394
3395 print_power_limit_msr(cpu, msr, "PKG Limit #1");
b7d8c148 3396 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n",
889facbe
LB		 3397 cpu,
3398 ((msr >> 47) & 1) ? "EN" : "DIS",
3399 ((msr >> 32) & 0x7FFF) * rapl_power_units,
3400 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
3401 ((msr >> 48) & 1) ? "EN" : "DIS");
3402 }
3403
0b2bb692 3404 if (do_rapl & RAPL_DRAM_POWER_INFO) {
889facbe
LB		 3405 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
3406 return -6;
3407
b7d8c148 3408 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
889facbe
LB		 3409 cpu, msr,
3410 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3411 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3412 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3413 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
0b2bb692
LB		 3414 }
3415 if (do_rapl & RAPL_DRAM) {
889facbe
LB		 3416 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
3417 return -9;
b7d8c148 3418 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
96e47158 3419 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
889facbe
LB		 3420
3421 print_power_limit_msr(cpu, msr, "DRAM Limit");
3422 }
144b44b1 3423 if (do_rapl & RAPL_CORE_POLICY) {
96e47158
LB		 3424 if (get_msr(cpu, MSR_PP0_POLICY, &msr))
3425 return -7;
889facbe 3426
96e47158 3427 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
144b44b1 3428 }
9148494c 3429 if (do_rapl & RAPL_CORES_POWER_LIMIT) {
96e47158
LB		 3430 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
3431 return -9;
3432 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
3433 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
3434 print_power_limit_msr(cpu, msr, "Cores Limit");
889facbe
LB		 3435 }
3436 if (do_rapl & RAPL_GFX) {
96e47158
LB		 3437 if (get_msr(cpu, MSR_PP1_POLICY, &msr))
3438 return -8;
889facbe 3439
96e47158 3440 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
889facbe 3441
96e47158
LB		 3442 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
3443 return -9;
3444 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
3445 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
3446 print_power_limit_msr(cpu, msr, "GFX Limit");
889facbe
LB		 3447 }
3448 return 0;
3449}
3450
d7899447
LB		 3451/*
3452 * SNB adds support for additional MSRs:
3453 *
3454 * MSR_PKG_C7_RESIDENCY 0x000003fa
3455 * MSR_CORE_C7_RESIDENCY 0x000003fe
3456 * MSR_PKG_C2_RESIDENCY 0x0000060d
3457 */
103a8fea 3458
d7899447 3459int has_snb_msrs(unsigned int family, unsigned int model)
103a8fea
LB		 3460{
3461 if (!genuine_intel)
3462 return 0;
3463
3464 switch (model) {
869ce69e
LB		 3465 case INTEL_FAM6_SANDYBRIDGE:
3466 case INTEL_FAM6_SANDYBRIDGE_X:
3467 case INTEL_FAM6_IVYBRIDGE: /* IVB */
3468 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
3469 case INTEL_FAM6_HASWELL_CORE: /* HSW */
3470 case INTEL_FAM6_HASWELL_X: /* HSW */
3471 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3472 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
3473 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
3474 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
3475 case INTEL_FAM6_BROADWELL_X: /* BDX */
3476 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
3477 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3478 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3479 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3480 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3481 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3482 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
ac01ac13 3483 case INTEL_FAM6_ATOM_GEMINI_LAKE:
5bbac26e 3484 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
103a8fea
LB		 3485 return 1;
3486 }
3487 return 0;
3488}
3489
d7899447
LB		 3490/*
3491 * HSW adds support for additional MSRs:
3492 *
5a63426e
LB		 3493 * MSR_PKG_C8_RESIDENCY 0x00000630
3494 * MSR_PKG_C9_RESIDENCY 0x00000631
3495 * MSR_PKG_C10_RESIDENCY 0x00000632
3496 *
3497 * MSR_PKGC8_IRTL 0x00000633
3498 * MSR_PKGC9_IRTL 0x00000634
3499 * MSR_PKGC10_IRTL 0x00000635
3500 *
d7899447
LB		 3501 */
3502int has_hsw_msrs(unsigned int family, unsigned int model)
ca58710f
KCA		 3503{
3504 if (!genuine_intel)
3505 return 0;
3506
3507 switch (model) {
869ce69e
LB		 3508 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3509 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
3510 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3511 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3512 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3513 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3514 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
ac01ac13 3515 case INTEL_FAM6_ATOM_GEMINI_LAKE:
0b2bb692
LB		 3516 return 1;
3517 }
3518 return 0;
3519}
3520
3521/*
3522 * SKL adds support for additional MSRS:
3523 *
3524 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
3525 * MSR_PKG_ANY_CORE_C0_RES 0x00000659
3526 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
3527 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
3528 */
3529int has_skl_msrs(unsigned int family, unsigned int model)
3530{
3531 if (!genuine_intel)
3532 return 0;
3533
3534 switch (model) {
869ce69e
LB		 3535 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3536 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3537 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3538 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
ca58710f
KCA		 3539 return 1;
3540 }
3541 return 0;
3542}
3543
144b44b1
LB		 3544int is_slm(unsigned int family, unsigned int model)
3545{
3546 if (!genuine_intel)
3547 return 0;
3548 switch (model) {
869ce69e
LB		 3549 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
3550 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
144b44b1
LB		 3551 return 1;
3552 }
3553 return 0;
3554}
3555
fb5d4327
DC		 3556int is_knl(unsigned int family, unsigned int model)
3557{
3558 if (!genuine_intel)
3559 return 0;
3560 switch (model) {
869ce69e 3561 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
005c82d6 3562 case INTEL_FAM6_XEON_PHI_KNM:
fb5d4327
DC		 3563 return 1;
3564 }
3565 return 0;
3566}
3567
b2b34dfe
HC		 3568unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model)
3569{
3570 if (is_knl(family, model))
3571 return 1024;
3572 return 1;
3573}
3574
144b44b1
LB		 3575#define SLM_BCLK_FREQS 5
3576double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0};
3577
3578double slm_bclk(void)
3579{
3580 unsigned long long msr = 3;
3581 unsigned int i;
3582 double freq;
3583
7ce7d5de 3584 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
b7d8c148 3585 fprintf(outf, "SLM BCLK: unknown\n");
144b44b1
LB		 3586
3587 i = msr & 0xf;
3588 if (i >= SLM_BCLK_FREQS) {
b7d8c148 3589 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
0a91e551 3590 i = 3;
144b44b1
LB		 3591 }
3592 freq = slm_freq_table[i];
3593
96e47158 3594 if (!quiet)
8f6196c1 3595 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
144b44b1
LB		 3596
3597 return freq;
3598}
3599
103a8fea
LB		 3600double discover_bclk(unsigned int family, unsigned int model)
3601{
121b48bb 3602 if (has_snb_msrs(family, model) || is_knl(family, model))
103a8fea 3603 return 100.00;
144b44b1
LB		 3604 else if (is_slm(family, model))
3605 return slm_bclk();
103a8fea
LB		 3606 else
3607 return 133.33;
3608}
3609
889facbe
LB		 3610/*
3611 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
3612 * the Thermal Control Circuit (TCC) activates.
3613 * This is usually equal to tjMax.
3614 *
3615 * Older processors do not have this MSR, so there we guess,
3616 * but also allow cmdline over-ride with -T.
3617 *
3618 * Several MSR temperature values are in units of degrees-C
3619 * below this value, including the Digital Thermal Sensor (DTS),
3620 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
3621 */
3622int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3623{
3624 unsigned long long msr;
3625 unsigned int target_c_local;
3626 int cpu;
3627
3628 /* tcc_activation_temp is used only for dts or ptm */
3629 if (!(do_dts || do_ptm))
3630 return 0;
3631
3632 /* this is a per-package concept */
3633 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3634 return 0;
3635
3636 cpu = t->cpu_id;
3637 if (cpu_migrate(cpu)) {
b7d8c148 3638 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 3639 return -1;
3640 }
3641
3642 if (tcc_activation_temp_override != 0) {
3643 tcc_activation_temp = tcc_activation_temp_override;
b7d8c148 3644 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n",
889facbe
LB		 3645 cpu, tcc_activation_temp);
3646 return 0;
3647 }
3648
3649 /* Temperature Target MSR is Nehalem and newer only */
d7899447 3650 if (!do_nhm_platform_info)
889facbe
LB		 3651 goto guess;
3652
7ce7d5de 3653 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
889facbe
LB		 3654 goto guess;
3655
3482124a 3656 target_c_local = (msr >> 16) & 0xFF;
889facbe 3657
96e47158 3658 if (!quiet)
b7d8c148 3659 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n",
889facbe
LB		 3660 cpu, msr, target_c_local);
3661
3482124a 3662 if (!target_c_local)
889facbe
LB		 3663 goto guess;
3664
3665 tcc_activation_temp = target_c_local;
3666
3667 return 0;
3668
3669guess:
3670 tcc_activation_temp = TJMAX_DEFAULT;
b7d8c148 3671 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n",
889facbe
LB		 3672 cpu, tcc_activation_temp);
3673
3674 return 0;
3675}
69807a63 3676
aa8d8cc7
LB		 3677void decode_feature_control_msr(void)
3678{
3679 unsigned long long msr;
3680
3681 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr))
3682 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
3683 base_cpu, msr,
3684 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-",
3685 msr & (1 << 18) ? "SGX" : "");
3686}
3687
69807a63
LB		 3688void decode_misc_enable_msr(void)
3689{
3690 unsigned long long msr;
3691
3692 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
e6512624 3693 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",
69807a63 3694 base_cpu, msr,
e6512624
LB		 3695 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-",
3696 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-",
3697 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "No-" : "",
3698 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "",
3699 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : "");
69807a63
LB		 3700}
3701
33148d67
LB		 3702void decode_misc_feature_control(void)
3703{
3704 unsigned long long msr;
3705
3706 if (!has_misc_feature_control)
3707 return;
3708
3709 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr))
3710 fprintf(outf, "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n",
3711 base_cpu, msr,
3712 msr & (0 << 0) ? "No-" : "",
3713 msr & (1 << 0) ? "No-" : "",
3714 msr & (2 << 0) ? "No-" : "",
3715 msr & (3 << 0) ? "No-" : "");
3716}
f0057310
LB		 3717/*
3718 * Decode MSR_MISC_PWR_MGMT
3719 *
3720 * Decode the bits according to the Nehalem documentation
3721 * bit[0] seems to continue to have same meaning going forward
3722 * bit[1] less so...
3723 */
3724void decode_misc_pwr_mgmt_msr(void)
3725{
3726 unsigned long long msr;
3727
3728 if (!do_nhm_platform_info)
3729 return;
3730
cf4cbe53
LB		 3731 if (no_MSR_MISC_PWR_MGMT)
3732 return;
3733
f0057310 3734 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
ddadb8ad 3735 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
f0057310
LB		 3736 base_cpu, msr,
3737 msr & (1 << 0) ? "DIS" : "EN",
ddadb8ad
SP		 3738 msr & (1 << 1) ? "EN" : "DIS",
3739 msr & (1 << 8) ? "EN" : "DIS");
f0057310 3740}
71616c8e
LB		 3741/*
3742 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG
3743 *
3744 * This MSRs are present on Silvermont processors,
3745 * Intel Atom processor E3000 series (Baytrail), and friends.
3746 */
3747void decode_c6_demotion_policy_msr(void)
3748{
3749 unsigned long long msr;
3750
3751 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
3752 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n",
3753 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
3754
3755 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
3756 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n",
3757 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
3758}
7f5c258e 3759
fcd17211 3760void process_cpuid()
103a8fea 3761{
61a87ba7 3762 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level;
103a8fea 3763 unsigned int fms, family, model, stepping;
b3a34e93 3764 unsigned int has_turbo;
103a8fea
LB		 3765
3766 eax = ebx = ecx = edx = 0;
3767
5aea2f7f 3768 __cpuid(0, max_level, ebx, ecx, edx);
103a8fea
LB		 3769
3770 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e)
3771 genuine_intel = 1;
3772
96e47158 3773 if (!quiet)
b7d8c148 3774 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ",
103a8fea
LB		 3775 (char *)&ebx, (char *)&edx, (char *)&ecx);
3776
5aea2f7f 3777 __cpuid(1, fms, ebx, ecx, edx);
103a8fea
LB		 3778 family = (fms >> 8) & 0xf;
3779 model = (fms >> 4) & 0xf;
3780 stepping = fms & 0xf;
3781 if (family == 6 || family == 0xf)
3782 model += ((fms >> 16) & 0xf) << 4;
3783
96e47158 3784 if (!quiet) {
b7d8c148 3785 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n",
103a8fea 3786 max_level, family, model, stepping, family, model, stepping);
aa8d8cc7 3787 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s\n",
69807a63
LB		 3788 ecx & (1 << 0) ? "SSE3" : "-",
3789 ecx & (1 << 3) ? "MONITOR" : "-",
aa8d8cc7 3790 ecx & (1 << 6) ? "SMX" : "-",
69807a63
LB		 3791 ecx & (1 << 7) ? "EIST" : "-",
3792 ecx & (1 << 8) ? "TM2" : "-",
3793 edx & (1 << 4) ? "TSC" : "-",
3794 edx & (1 << 5) ? "MSR" : "-",
3795 edx & (1 << 22) ? "ACPI-TM" : "-",
3796 edx & (1 << 29) ? "TM" : "-");
3797 }
103a8fea 3798
b2c95d90
JT		 3799 if (!(edx & (1 << 5)))
3800 errx(1, "CPUID: no MSR");
103a8fea
LB		 3801
3802 /*
3803 * check max extended function levels of CPUID.
3804 * This is needed to check for invariant TSC.
3805 * This check is valid for both Intel and AMD.
3806 */
3807 ebx = ecx = edx = 0;
5aea2f7f 3808 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx);
103a8fea 3809
61a87ba7 3810 if (max_extended_level >= 0x80000007) {
103a8fea 3811
d7899447
LB		 3812 /*
3813 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
3814 * this check is valid for both Intel and AMD
3815 */
5aea2f7f 3816 __cpuid(0x80000007, eax, ebx, ecx, edx);
d7899447
LB		 3817 has_invariant_tsc = edx & (1 << 8);
3818 }
103a8fea
LB		 3819
3820 /*
3821 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
3822 * this check is valid for both Intel and AMD
3823 */
3824
5aea2f7f 3825 __cpuid(0x6, eax, ebx, ecx, edx);
8209e054 3826 has_aperf = ecx & (1 << 0);
812db3f7
LB		 3827 if (has_aperf) {
3828 BIC_PRESENT(BIC_Avg_MHz);
3829 BIC_PRESENT(BIC_Busy);
3830 BIC_PRESENT(BIC_Bzy_MHz);
3831 }
889facbe 3832 do_dts = eax & (1 << 0);
812db3f7
LB		 3833 if (do_dts)
3834 BIC_PRESENT(BIC_CoreTmp);
b3a34e93 3835 has_turbo = eax & (1 << 1);
889facbe 3836 do_ptm = eax & (1 << 6);
812db3f7
LB		 3837 if (do_ptm)
3838 BIC_PRESENT(BIC_PkgTmp);
7f5c258e
LB		 3839 has_hwp = eax & (1 << 7);
3840 has_hwp_notify = eax & (1 << 8);
3841 has_hwp_activity_window = eax & (1 << 9);
3842 has_hwp_epp = eax & (1 << 10);
3843 has_hwp_pkg = eax & (1 << 11);
889facbe
LB		 3844 has_epb = ecx & (1 << 3);
3845
96e47158 3846 if (!quiet)
b3a34e93 3847 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, "
7f5c258e
LB		 3848 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
3849 has_aperf ? "" : "No-",
b3a34e93 3850 has_turbo ? "" : "No-",
7f5c258e
LB		 3851 do_dts ? "" : "No-",
3852 do_ptm ? "" : "No-",
3853 has_hwp ? "" : "No-",
3854 has_hwp_notify ? "" : "No-",
3855 has_hwp_activity_window ? "" : "No-",
3856 has_hwp_epp ? "" : "No-",
3857 has_hwp_pkg ? "" : "No-",
3858 has_epb ? "" : "No-");
103a8fea 3859
96e47158 3860 if (!quiet)
69807a63
LB		 3861 decode_misc_enable_msr();
3862
33148d67 3863
96e47158 3864 if (max_level >= 0x7 && !quiet) {
aa8d8cc7 3865 int has_sgx;
103a8fea 3866
aa8d8cc7
LB		 3867 ecx = 0;
3868
3869 __cpuid_count(0x7, 0, eax, ebx, ecx, edx);
3870
3871 has_sgx = ebx & (1 << 2);
3872 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-");
3873
3874 if (has_sgx)
3875 decode_feature_control_msr();
3876 }
3877
61a87ba7 3878 if (max_level >= 0x15) {
8a5bdf41
LB		 3879 unsigned int eax_crystal;
3880 unsigned int ebx_tsc;
3881
3882 /*
3883 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
3884 */
3885 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
5aea2f7f 3886 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx);
8a5bdf41
LB		 3887
3888 if (ebx_tsc != 0) {
3889
96e47158 3890 if (!quiet && (ebx != 0))
b7d8c148 3891 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
8a5bdf41
LB		 3892 eax_crystal, ebx_tsc, crystal_hz);
3893
3894 if (crystal_hz == 0)
3895 switch(model) {
869ce69e
LB		 3896 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3897 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3898 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3899 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
e8efbc80
LB		 3900 crystal_hz = 24000000; /* 24.0 MHz */
3901 break;
869ce69e 3902 case INTEL_FAM6_SKYLAKE_X: /* SKX */
7268d407 3903 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
ec53e594
LB		 3904 crystal_hz = 25000000; /* 25.0 MHz */
3905 break;
869ce69e 3906 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
ac01ac13 3907 case INTEL_FAM6_ATOM_GEMINI_LAKE:
e8efbc80 3908 crystal_hz = 19200000; /* 19.2 MHz */
8a5bdf41
LB		 3909 break;
3910 default:
3911 crystal_hz = 0;
3912 }
3913
3914 if (crystal_hz) {
3915 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal;
96e47158 3916 if (!quiet)
b7d8c148 3917 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
8a5bdf41
LB		 3918 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal);
3919 }
3920 }
3921 }
61a87ba7
LB		 3922 if (max_level >= 0x16) {
3923 unsigned int base_mhz, max_mhz, bus_mhz, edx;
3924
3925 /*
3926 * CPUID 16H Base MHz, Max MHz, Bus MHz
3927 */
3928 base_mhz = max_mhz = bus_mhz = edx = 0;
3929
5aea2f7f 3930 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx);
96e47158 3931 if (!quiet)
b7d8c148 3932 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
61a87ba7
LB		 3933 base_mhz, max_mhz, bus_mhz);
3934 }
8a5bdf41 3935
b2b34dfe
HC		 3936 if (has_aperf)
3937 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
3938
812db3f7
LB		 3939 BIC_PRESENT(BIC_IRQ);
3940 BIC_PRESENT(BIC_TSC_MHz);
3941
3942 if (probe_nhm_msrs(family, model)) {
3943 do_nhm_platform_info = 1;
3944 BIC_PRESENT(BIC_CPU_c1);
3945 BIC_PRESENT(BIC_CPU_c3);
3946 BIC_PRESENT(BIC_CPU_c6);
3947 BIC_PRESENT(BIC_SMI);
3948 }
d7899447 3949 do_snb_cstates = has_snb_msrs(family, model);
812db3f7
LB		 3950
3951 if (do_snb_cstates)
3952 BIC_PRESENT(BIC_CPU_c7);
3953
5a63426e 3954 do_irtl_snb = has_snb_msrs(family, model);
0f47c08d
LB		 3955 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2))
3956 BIC_PRESENT(BIC_Pkgpc2);
3957 if (pkg_cstate_limit >= PCL__3)
3958 BIC_PRESENT(BIC_Pkgpc3);
3959 if (pkg_cstate_limit >= PCL__6)
3960 BIC_PRESENT(BIC_Pkgpc6);
3961 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7))
3962 BIC_PRESENT(BIC_Pkgpc7);
0539ba11 3963 if (has_slv_msrs(family, model)) {
0f47c08d
LB		 3964 BIC_NOT_PRESENT(BIC_Pkgpc2);
3965 BIC_NOT_PRESENT(BIC_Pkgpc3);
3966 BIC_PRESENT(BIC_Pkgpc6);
3967 BIC_NOT_PRESENT(BIC_Pkgpc7);
0539ba11
LB		 3968 BIC_PRESENT(BIC_Mod_c6);
3969 use_c1_residency_msr = 1;
3970 }
7170a374
LB		 3971 if (is_dnv(family, model)) {
3972 BIC_PRESENT(BIC_CPU_c1);
3973 BIC_NOT_PRESENT(BIC_CPU_c3);
3974 BIC_NOT_PRESENT(BIC_Pkgpc3);
3975 BIC_NOT_PRESENT(BIC_CPU_c7);
3976 BIC_NOT_PRESENT(BIC_Pkgpc7);
3977 use_c1_residency_msr = 1;
3978 }
34c76197
LB		 3979 if (is_skx(family, model)) {
3980 BIC_NOT_PRESENT(BIC_CPU_c3);
3981 BIC_NOT_PRESENT(BIC_Pkgpc3);
3982 BIC_NOT_PRESENT(BIC_CPU_c7);
3983 BIC_NOT_PRESENT(BIC_Pkgpc7);
3984 }
ade0ebac
LB		 3985 if (is_bdx(family, model)) {
3986 BIC_NOT_PRESENT(BIC_CPU_c7);
3987 BIC_NOT_PRESENT(BIC_Pkgpc7);
3988 }
0f47c08d
LB		 3989 if (has_hsw_msrs(family, model)) {
3990 BIC_PRESENT(BIC_Pkgpc8);
3991 BIC_PRESENT(BIC_Pkgpc9);
3992 BIC_PRESENT(BIC_Pkgpc10);
3993 }
5a63426e 3994 do_irtl_hsw = has_hsw_msrs(family, model);
0b2bb692 3995 do_skl_residency = has_skl_msrs(family, model);
144b44b1 3996 do_slm_cstates = is_slm(family, model);
fb5d4327 3997 do_knl_cstates = is_knl(family, model);
103a8fea 3998
96e47158 3999 if (!quiet)
f0057310
LB		 4000 decode_misc_pwr_mgmt_msr();
4001
96e47158 4002 if (!quiet && has_slv_msrs(family, model))
71616c8e
LB		 4003 decode_c6_demotion_policy_msr();
4004
889facbe 4005 rapl_probe(family, model);
3a9a941d 4006 perf_limit_reasons_probe(family, model);
889facbe 4007
96e47158 4008 if (!quiet)
1b69317d 4009 dump_cstate_pstate_config_info(family, model);
fcd17211 4010
a2b7b749
LB		 4011 if (has_skl_msrs(family, model))
4012 calculate_tsc_tweak();
4013
812db3f7
LB		 4014 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK))
4015 BIC_PRESENT(BIC_GFX_rc6);
fdf676e5 4016
812db3f7
LB		 4017 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK))
4018 BIC_PRESENT(BIC_GFXMHz);
27d47356 4019
96e47158 4020 if (!quiet)
33148d67
LB		 4021 decode_misc_feature_control();
4022
889facbe 4023 return;
103a8fea
LB		 4024}
4025
d8af6f5f 4026void help()
103a8fea 4027{
b7d8c148 4028 fprintf(outf,
d8af6f5f
LB		 4029 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
4030 "\n"
4031 "Turbostat forks the specified COMMAND and prints statistics\n"
4032 "when COMMAND completes.\n"
4033 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
4034 "to print statistics, until interrupted.\n"
388e9c81
LB		 4035 "--add add a counter\n"
4036 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n"
96e47158 4037 "--quiet skip decoding system configuration header\n"
d8af6f5f
LB		 4038 "--interval sec Override default 5-second measurement interval\n"
4039 "--help print this help message\n"
b7d8c148 4040 "--out file create or truncate \"file\" for all output\n"
d8af6f5f
LB		 4041 "--version print version information\n"
4042 "\n"
4043 "For more help, run \"man turbostat\"\n");
103a8fea
LB		 4044}
4045
4046
4047/*
4048 * in /dev/cpu/ return success for names that are numbers
4049 * ie. filter out ".", "..", "microcode".
4050 */
4051int dir_filter(const struct dirent *dirp)
4052{
4053 if (isdigit(dirp->d_name[0]))
4054 return 1;
4055 else
4056 return 0;
4057}
4058
4059int open_dev_cpu_msr(int dummy1)
4060{
4061 return 0;
4062}
4063
c98d5d94
LB		 4064void topology_probe()
4065{
4066 int i;
4067 int max_core_id = 0;
4068 int max_package_id = 0;
4069 int max_siblings = 0;
4070 struct cpu_topology {
4071 int core_id;
4072 int physical_package_id;
4073 } *cpus;
4074
4075 /* Initialize num_cpus, max_cpu_num */
4076 topo.num_cpus = 0;
4077 topo.max_cpu_num = 0;
4078 for_all_proc_cpus(count_cpus);
4079 if (!summary_only && topo.num_cpus > 1)
812db3f7 4080 BIC_PRESENT(BIC_CPU);
c98d5d94 4081
d8af6f5f 4082 if (debug > 1)
b7d8c148 4083 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
c98d5d94
LB		 4084
4085 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology));
b2c95d90
JT		 4086 if (cpus == NULL)
4087 err(1, "calloc cpus");
c98d5d94
LB		 4088
4089 /*
4090 * Allocate and initialize cpu_present_set
4091 */
4092 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
b2c95d90
JT		 4093 if (cpu_present_set == NULL)
4094 err(3, "CPU_ALLOC");
c98d5d94
LB		 4095 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
4096 CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
4097 for_all_proc_cpus(mark_cpu_present);
4098
4099 /*
4100 * Allocate and initialize cpu_affinity_set
4101 */
4102 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
b2c95d90
JT		 4103 if (cpu_affinity_set == NULL)
4104 err(3, "CPU_ALLOC");
c98d5d94
LB		 4105 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
4106 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
4107
4108
4109 /*
4110 * For online cpus
4111 * find max_core_id, max_package_id
4112 */
4113 for (i = 0; i <= topo.max_cpu_num; ++i) {
4114 int siblings;
4115
4116 if (cpu_is_not_present(i)) {
d8af6f5f 4117 if (debug > 1)
b7d8c148 4118 fprintf(outf, "cpu%d NOT PRESENT\n", i);
c98d5d94
LB		 4119 continue;
4120 }
4121 cpus[i].core_id = get_core_id(i);
4122 if (cpus[i].core_id > max_core_id)
4123 max_core_id = cpus[i].core_id;
4124
4125 cpus[i].physical_package_id = get_physical_package_id(i);
4126 if (cpus[i].physical_package_id > max_package_id)
4127 max_package_id = cpus[i].physical_package_id;
4128
4129 siblings = get_num_ht_siblings(i);
4130 if (siblings > max_siblings)
4131 max_siblings = siblings;
d8af6f5f 4132 if (debug > 1)
b7d8c148 4133 fprintf(outf, "cpu %d pkg %d core %d\n",
c98d5d94
LB		 4134 i, cpus[i].physical_package_id, cpus[i].core_id);
4135 }
4136 topo.num_cores_per_pkg = max_core_id + 1;
d8af6f5f 4137 if (debug > 1)
b7d8c148 4138 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n",
c98d5d94 4139 max_core_id, topo.num_cores_per_pkg);
0f47c08d 4140 if (!summary_only && topo.num_cores_per_pkg > 1)
812db3f7 4141 BIC_PRESENT(BIC_Core);
c98d5d94
LB		 4142
4143 topo.num_packages = max_package_id + 1;
d8af6f5f 4144 if (debug > 1)
b7d8c148 4145 fprintf(outf, "max_package_id %d, sizing for %d packages\n",
c98d5d94 4146 max_package_id, topo.num_packages);
1cc21f7b 4147 if (debug && !summary_only && topo.num_packages > 1)
812db3f7 4148 BIC_PRESENT(BIC_Package);
c98d5d94
LB		 4149
4150 topo.num_threads_per_core = max_siblings;
d8af6f5f 4151 if (debug > 1)
b7d8c148 4152 fprintf(outf, "max_siblings %d\n", max_siblings);
c98d5d94
LB		 4153
4154 free(cpus);
4155}
4156
4157void
4158allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p)
4159{
4160 int i;
4161
4162 *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg *
678a3bd1 4163 topo.num_packages, sizeof(struct thread_data));
c98d5d94
LB		 4164 if (*t == NULL)
4165 goto error;
4166
4167 for (i = 0; i < topo.num_threads_per_core *
4168 topo.num_cores_per_pkg * topo.num_packages; i++)
4169 (*t)[i].cpu_id = -1;
4170
4171 *c = calloc(topo.num_cores_per_pkg * topo.num_packages,
678a3bd1 4172 sizeof(struct core_data));
c98d5d94
LB		 4173 if (*c == NULL)
4174 goto error;
4175
4176 for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++)
4177 (*c)[i].core_id = -1;
4178
678a3bd1 4179 *p = calloc(topo.num_packages, sizeof(struct pkg_data));
c98d5d94
LB		 4180 if (*p == NULL)
4181 goto error;
4182
4183 for (i = 0; i < topo.num_packages; i++)
4184 (*p)[i].package_id = i;
4185
4186 return;
4187error:
b2c95d90 4188 err(1, "calloc counters");
c98d5d94
LB		 4189}
4190/*
4191 * init_counter()
4192 *
4193 * set cpu_id, core_num, pkg_num
4194 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
4195 *
4196 * increment topo.num_cores when 1st core in pkg seen
4197 */
4198void init_counter(struct thread_data *thread_base, struct core_data *core_base,
4199 struct pkg_data *pkg_base, int thread_num, int core_num,
4200 int pkg_num, int cpu_id)
4201{
4202 struct thread_data *t;
4203 struct core_data *c;
4204 struct pkg_data *p;
4205
4206 t = GET_THREAD(thread_base, thread_num, core_num, pkg_num);
4207 c = GET_CORE(core_base, core_num, pkg_num);
4208 p = GET_PKG(pkg_base, pkg_num);
4209
4210 t->cpu_id = cpu_id;
4211 if (thread_num == 0) {
4212 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE;
4213 if (cpu_is_first_core_in_package(cpu_id))
4214 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE;
4215 }
4216
4217 c->core_id = core_num;
4218 p->package_id = pkg_num;
4219}
4220
4221
4222int initialize_counters(int cpu_id)
4223{
4224 int my_thread_id, my_core_id, my_package_id;
4225
4226 my_package_id = get_physical_package_id(cpu_id);
4227 my_core_id = get_core_id(cpu_id);
e275b388
DC		 4228 my_thread_id = get_cpu_position_in_core(cpu_id);
4229 if (!my_thread_id)
c98d5d94 4230 topo.num_cores++;
c98d5d94
LB		 4231
4232 init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
4233 init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
4234 return 0;
4235}
4236
4237void allocate_output_buffer()
4238{
3b4d5c7f 4239 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024);
c98d5d94 4240 outp = output_buffer;
b2c95d90
JT		 4241 if (outp == NULL)
4242 err(-1, "calloc output buffer");
c98d5d94 4243}
36229897
LB		 4244void allocate_fd_percpu(void)
4245{
01a67adf 4246 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
36229897
LB		 4247 if (fd_percpu == NULL)
4248 err(-1, "calloc fd_percpu");
4249}
562a2d37
LB		 4250void allocate_irq_buffers(void)
4251{
4252 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int));
4253 if (irq_column_2_cpu == NULL)
4254 err(-1, "calloc %d", topo.num_cpus);
c98d5d94 4255
01a67adf 4256 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int));
562a2d37 4257 if (irqs_per_cpu == NULL)
01a67adf 4258 err(-1, "calloc %d", topo.max_cpu_num + 1);
562a2d37 4259}
c98d5d94
LB		 4260void setup_all_buffers(void)
4261{
4262 topology_probe();
562a2d37 4263 allocate_irq_buffers();
36229897 4264 allocate_fd_percpu();
c98d5d94
LB		 4265 allocate_counters(&thread_even, &core_even, &package_even);
4266 allocate_counters(&thread_odd, &core_odd, &package_odd);
4267 allocate_output_buffer();
4268 for_all_proc_cpus(initialize_counters);
4269}
3b4d5c7f 4270
7ce7d5de
PB		 4271void set_base_cpu(void)
4272{
4273 base_cpu = sched_getcpu();
4274 if (base_cpu < 0)
4275 err(-ENODEV, "No valid cpus found");
4276
4277 if (debug > 1)
b7d8c148 4278 fprintf(outf, "base_cpu = %d\n", base_cpu);
7ce7d5de
PB		 4279}
4280
103a8fea
LB		 4281void turbostat_init()
4282{
7ce7d5de
PB		 4283 setup_all_buffers();
4284 set_base_cpu();
103a8fea 4285 check_dev_msr();
98481e79 4286 check_permissions();
fcd17211 4287 process_cpuid();
103a8fea 4288
103a8fea 4289
96e47158 4290 if (!quiet)
7f5c258e
LB		 4291 for_all_cpus(print_hwp, ODD_COUNTERS);
4292
96e47158 4293 if (!quiet)
889facbe
LB		 4294 for_all_cpus(print_epb, ODD_COUNTERS);
4295
96e47158 4296 if (!quiet)
3a9a941d
LB		 4297 for_all_cpus(print_perf_limit, ODD_COUNTERS);
4298
96e47158 4299 if (!quiet)
889facbe
LB		 4300 for_all_cpus(print_rapl, ODD_COUNTERS);
4301
4302 for_all_cpus(set_temperature_target, ODD_COUNTERS);
4303
96e47158 4304 if (!quiet)
889facbe 4305 for_all_cpus(print_thermal, ODD_COUNTERS);
5a63426e 4306
96e47158 4307 if (!quiet && do_irtl_snb)
5a63426e 4308 print_irtl();
103a8fea
LB		 4309}
4310
4311int fork_it(char **argv)
4312{
103a8fea 4313 pid_t child_pid;
d91bb17c 4314 int status;
d15cf7c1 4315
d91bb17c
LB		 4316 status = for_all_cpus(get_counters, EVEN_COUNTERS);
4317 if (status)
4318 exit(status);
c98d5d94
LB		 4319 /* clear affinity side-effect of get_counters() */
4320 sched_setaffinity(0, cpu_present_setsize, cpu_present_set);
103a8fea
LB		 4321 gettimeofday(&tv_even, (struct timezone *)NULL);
4322
4323 child_pid = fork();
4324 if (!child_pid) {
4325 /* child */
4326 execvp(argv[0], argv);
4327 } else {
103a8fea
LB		 4328
4329 /* parent */
b2c95d90
JT		 4330 if (child_pid == -1)
4331 err(1, "fork");
103a8fea
LB		 4332
4333 signal(SIGINT, SIG_IGN);
4334 signal(SIGQUIT, SIG_IGN);
b2c95d90
JT		 4335 if (waitpid(child_pid, &status, 0) == -1)
4336 err(status, "waitpid");
103a8fea 4337 }
c98d5d94
LB		 4338 /*
4339 * n.b. fork_it() does not check for errors from for_all_cpus()
4340 * because re-starting is problematic when forking
4341 */
4342 for_all_cpus(get_counters, ODD_COUNTERS);
103a8fea 4343 gettimeofday(&tv_odd, (struct timezone *)NULL);
103a8fea 4344 timersub(&tv_odd, &tv_even, &tv_delta);
ba3dec99
LB		 4345 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS))
4346 fprintf(outf, "%s: Counter reset detected\n", progname);
4347 else {
4348 compute_average(EVEN_COUNTERS);
4349 format_all_counters(EVEN_COUNTERS);
4350 }
103a8fea 4351
b7d8c148
LB		 4352 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0);
4353
4354 flush_output_stderr();
103a8fea 4355
d91bb17c 4356 return status;
103a8fea
LB		 4357}
4358
3b4d5c7f
AS		 4359int get_and_dump_counters(void)
4360{
4361 int status;
4362
4363 status = for_all_cpus(get_counters, ODD_COUNTERS);
4364 if (status)
4365 return status;
4366
4367 status = for_all_cpus(dump_counters, ODD_COUNTERS);
4368 if (status)
4369 return status;
4370
b7d8c148 4371 flush_output_stdout();
3b4d5c7f
AS		 4372
4373 return status;
4374}
4375
d8af6f5f 4376void print_version() {
0539ba11 4377 fprintf(outf, "turbostat version 4.17 10 Jan 2017"
d8af6f5f
LB		 4378 " - Len Brown <lenb@kernel.org>\n");
4379}
4380
495c7654
LB		 4381int add_counter(unsigned int msr_num, char *path, char *name,
4382 unsigned int width, enum counter_scope scope,
4383 enum counter_type type, enum counter_format format)
388e9c81
LB		 4384{
4385 struct msr_counter *msrp;
4386
4387 msrp = calloc(1, sizeof(struct msr_counter));
4388 if (msrp == NULL) {
4389 perror("calloc");
4390 exit(1);
4391 }
4392
4393 msrp->msr_num = msr_num;
4394 strncpy(msrp->name, name, NAME_BYTES);
495c7654
LB		 4395 if (path)
4396 strncpy(msrp->path, path, PATH_BYTES);
388e9c81
LB		 4397 msrp->width = width;
4398 msrp->type = type;
4399 msrp->format = format;
4400
4401 switch (scope) {
4402
4403 case SCOPE_CPU:
388e9c81
LB		 4404 msrp->next = sys.tp;
4405 sys.tp = msrp;
678a3bd1
LB		 4406 sys.added_thread_counters++;
4407 if (sys.added_thread_counters > MAX_ADDED_COUNTERS) {
4408 fprintf(stderr, "exceeded max %d added thread counters\n",
4409 MAX_ADDED_COUNTERS);
4410 exit(-1);
4411 }
388e9c81
LB		 4412 break;
4413
4414 case SCOPE_CORE:
388e9c81
LB		 4415 msrp->next = sys.cp;
4416 sys.cp = msrp;
678a3bd1
LB		 4417 sys.added_core_counters++;
4418 if (sys.added_core_counters > MAX_ADDED_COUNTERS) {
4419 fprintf(stderr, "exceeded max %d added core counters\n",
4420 MAX_ADDED_COUNTERS);
4421 exit(-1);
4422 }
388e9c81
LB		 4423 break;
4424
4425 case SCOPE_PACKAGE:
388e9c81
LB		 4426 msrp->next = sys.pp;
4427 sys.pp = msrp;
678a3bd1
LB		 4428 sys.added_package_counters++;
4429 if (sys.added_package_counters > MAX_ADDED_COUNTERS) {
4430 fprintf(stderr, "exceeded max %d added package counters\n",
4431 MAX_ADDED_COUNTERS);
4432 exit(-1);
4433 }
388e9c81
LB		 4434 break;
4435 }
4436
4437 return 0;
4438}
4439
4440void parse_add_command(char *add_command)
4441{
4442 int msr_num = 0;
495c7654 4443 char *path = NULL;
0f47c08d 4444 char name_buffer[NAME_BYTES] = "";
388e9c81
LB		 4445 int width = 64;
4446 int fail = 0;
4447 enum counter_scope scope = SCOPE_CPU;
4448 enum counter_type type = COUNTER_CYCLES;
4449 enum counter_format format = FORMAT_DELTA;
4450
4451 while (add_command) {
4452
4453 if (sscanf(add_command, "msr0x%x", &msr_num) == 1)
4454 goto next;
4455
4456 if (sscanf(add_command, "msr%d", &msr_num) == 1)
4457 goto next;
4458
495c7654
LB		 4459 if (*add_command == '/') {
4460 path = add_command;
4461 goto next;
4462 }
4463
388e9c81
LB		 4464 if (sscanf(add_command, "u%d", &width) == 1) {
4465 if ((width == 32) || (width == 64))
4466 goto next;
4467 width = 64;
4468 }
4469 if (!strncmp(add_command, "cpu", strlen("cpu"))) {
4470 scope = SCOPE_CPU;
4471 goto next;
4472 }
4473 if (!strncmp(add_command, "core", strlen("core"))) {
4474 scope = SCOPE_CORE;
4475 goto next;
4476 }
4477 if (!strncmp(add_command, "package", strlen("package"))) {
4478 scope = SCOPE_PACKAGE;
4479 goto next;
4480 }
4481 if (!strncmp(add_command, "cycles", strlen("cycles"))) {
4482 type = COUNTER_CYCLES;
4483 goto next;
4484 }
4485 if (!strncmp(add_command, "seconds", strlen("seconds"))) {
4486 type = COUNTER_SECONDS;
4487 goto next;
4488 }
4489 if (!strncmp(add_command, "raw", strlen("raw"))) {
4490 format = FORMAT_RAW;
4491 goto next;
4492 }
4493 if (!strncmp(add_command, "delta", strlen("delta"))) {
4494 format = FORMAT_DELTA;
4495 goto next;
4496 }
4497 if (!strncmp(add_command, "percent", strlen("percent"))) {
4498 format = FORMAT_PERCENT;
4499 goto next;
4500 }
4501
4502 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */
4503 char *eos;
4504
4505 eos = strchr(name_buffer, ',');
4506 if (eos)
4507 *eos = '\0';
4508 goto next;
4509 }
4510
4511next:
4512 add_command = strchr(add_command, ',');
495c7654
LB		 4513 if (add_command) {
4514 *add_command = '\0';
388e9c81 4515 add_command++;
495c7654 4516 }
388e9c81
LB		 4517
4518 }
495c7654
LB		 4519 if ((msr_num == 0) && (path == NULL)) {
4520 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n");
388e9c81
LB		 4521 fail++;
4522 }
4523
4524 /* generate default column header */
4525 if (*name_buffer == '\0') {
4526 if (format == FORMAT_RAW) {
4527 if (width == 32)
4528 sprintf(name_buffer, "msr%d", msr_num);
4529 else
4530 sprintf(name_buffer, "MSR%d", msr_num);
4531 } else if (format == FORMAT_DELTA) {
4532 if (width == 32)
4533 sprintf(name_buffer, "cnt%d", msr_num);
4534 else
4535 sprintf(name_buffer, "CNT%d", msr_num);
4536 } else if (format == FORMAT_PERCENT) {
4537 if (width == 32)
4538 sprintf(name_buffer, "msr%d%%", msr_num);
4539 else
4540 sprintf(name_buffer, "MSR%d%%", msr_num);
4541 }
4542 }
4543
495c7654 4544 if (add_counter(msr_num, path, name_buffer, width, scope, type, format))
388e9c81
LB		 4545 fail++;
4546
4547 if (fail) {
4548 help();
4549 exit(1);
4550 }
4551}
812db3f7
LB		 4552/*
4553 * HIDE_LIST - hide this list of counters, show the rest [default]
4554 * SHOW_LIST - show this list of counters, hide the rest
4555 */
4556enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST;
4557
4558int shown;
4559/*
4560 * parse_show_hide() - process cmdline to set default counter action
4561 */
4562void parse_show_hide(char *optarg, enum show_hide_mode new_mode)
4563{
4564 /*
4565 * --show: show only those specified
4566 * The 1st invocation will clear and replace the enabled mask
4567 * subsequent invocations can add to it.
4568 */
4569 if (new_mode == SHOW_LIST) {
4570 if (shown == 0)
4571 bic_enabled = bic_lookup(optarg);
4572 else
4573 bic_enabled |= bic_lookup(optarg);
4574 shown = 1;
4575
4576 return;
4577 }
4578
4579 /*
4580 * --hide: do not show those specified
4581 * multiple invocations simply clear more bits in enabled mask
4582 */
4583 bic_enabled &= ~bic_lookup(optarg);
4584}
4585
103a8fea
LB		 4586void cmdline(int argc, char **argv)
4587{
4588 int opt;
d8af6f5f
LB		 4589 int option_index = 0;
4590 static struct option long_options[] = {
388e9c81 4591 {"add", required_argument, 0, 'a'},
d8af6f5f 4592 {"Dump", no_argument, 0, 'D'},
96e47158 4593 {"debug", no_argument, 0, 'd'}, /* internal, not documented */
d8af6f5f
LB		 4594 {"interval", required_argument, 0, 'i'},
4595 {"help", no_argument, 0, 'h'},
812db3f7 4596 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help
d8af6f5f 4597 {"Joules", no_argument, 0, 'J'},
b7d8c148 4598 {"out", required_argument, 0, 'o'},
d8af6f5f
LB		 4599 {"Package", no_argument, 0, 'p'},
4600 {"processor", no_argument, 0, 'p'},
96e47158 4601 {"quiet", no_argument, 0, 'q'},
812db3f7 4602 {"show", required_argument, 0, 's'},
d8af6f5f
LB		 4603 {"Summary", no_argument, 0, 'S'},
4604 {"TCC", required_argument, 0, 'T'},
4605 {"version", no_argument, 0, 'v' },
4606 {0, 0, 0, 0 }
4607 };
103a8fea
LB		 4608
4609 progname = argv[0];
4610
96e47158 4611 while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:PpqST:v",
d8af6f5f 4612 long_options, &option_index)) != -1) {
103a8fea 4613 switch (opt) {
388e9c81
LB		 4614 case 'a':
4615 parse_add_command(optarg);
4616 break;
d8af6f5f 4617 case 'D':
3b4d5c7f
AS		 4618 dump_only++;
4619 break;
d8af6f5f
LB		 4620 case 'd':
4621 debug++;
103a8fea 4622 break;
812db3f7
LB		 4623 case 'H':
4624 parse_show_hide(optarg, HIDE_LIST);
4625 break;
d8af6f5f
LB		 4626 case 'h':
4627 default:
4628 help();
4629 exit(1);
103a8fea 4630 case 'i':
2a0609c0
LB		 4631 {
4632 double interval = strtod(optarg, NULL);
4633
4634 if (interval < 0.001) {
b7d8c148 4635 fprintf(outf, "interval %f seconds is too small\n",
2a0609c0
LB		 4636 interval);
4637 exit(2);
4638 }
4639
4640 interval_ts.tv_sec = interval;
4641 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
4642 }
103a8fea 4643 break;
d8af6f5f
LB		 4644 case 'J':
4645 rapl_joules++;
8e180f3c 4646 break;
b7d8c148
LB		 4647 case 'o':
4648 outf = fopen_or_die(optarg, "w");
4649 break;
d8af6f5f
LB		 4650 case 'P':
4651 show_pkg_only++;
4652 break;
4653 case 'p':
4654 show_core_only++;
103a8fea 4655 break;
96e47158
LB		 4656 case 'q':
4657 quiet = 1;
4658 break;
812db3f7
LB		 4659 case 's':
4660 parse_show_hide(optarg, SHOW_LIST);
4661 break;
d8af6f5f
LB		 4662 case 'S':
4663 summary_only++;
889facbe
LB		 4664 break;
4665 case 'T':
4666 tcc_activation_temp_override = atoi(optarg);
4667 break;
d8af6f5f
LB		 4668 case 'v':
4669 print_version();
4670 exit(0);
5c56be9a 4671 break;
103a8fea
LB		 4672 }
4673 }
4674}
4675
4676int main(int argc, char **argv)
4677{
b7d8c148
LB		 4678 outf = stderr;
4679
103a8fea
LB		 4680 cmdline(argc, argv);
4681
96e47158 4682 if (!quiet)
d8af6f5f 4683 print_version();
103a8fea
LB		 4684
4685 turbostat_init();
4686
3b4d5c7f
AS		 4687 /* dump counters and exit */
4688 if (dump_only)
4689 return get_and_dump_counters();
4690
103a8fea
LB		 4691 /*
4692 * if any params left, it must be a command to fork
4693 */
4694 if (argc - optind)
4695 return fork_it(argv + optind);
4696 else
4697 turbostat_loop();
4698
4699 return 0;
4700}
Linux 6.x block layer and io_uring tree(s)