Commit | Line | Data |
---|---|---|
cdb29a8f JY |
1 | [ |
2 | { | |
09625cff | 3 | "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", |
09625cff IR |
4 | "EventCode": "0x51", |
5 | "EventName": "L1D.REPLACEMENT", | |
09625cff IR |
6 | "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", |
7 | "SampleAfterValue": "100003", | |
09625cff | 8 | "UMask": "0x1" |
cdb29a8f JY |
9 | }, |
10 | { | |
09625cff | 11 | "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", |
09625cff IR |
12 | "EventCode": "0x48", |
13 | "EventName": "L1D_PEND_MISS.FB_FULL", | |
bd035250 | 14 | "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", |
09625cff | 15 | "SampleAfterValue": "1000003", |
09625cff | 16 | "UMask": "0x2" |
cdb29a8f JY |
17 | }, |
18 | { | |
bd035250 | 19 | "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.", |
09625cff IR |
20 | "CounterMask": "1", |
21 | "EdgeDetect": "1", | |
22 | "EventCode": "0x48", | |
23 | "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", | |
bd035250 | 24 | "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", |
09625cff | 25 | "SampleAfterValue": "1000003", |
09625cff | 26 | "UMask": "0x2" |
cdb29a8f JY |
27 | }, |
28 | { | |
09625cff | 29 | "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", |
09625cff IR |
30 | "EventCode": "0x48", |
31 | "EventName": "L1D_PEND_MISS.L2_STALL", | |
09625cff IR |
32 | "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", |
33 | "SampleAfterValue": "1000003", | |
09625cff | 34 | "UMask": "0x4" |
cdb29a8f JY |
35 | }, |
36 | { | |
09625cff | 37 | "BriefDescription": "Number of L1D misses that are outstanding", |
09625cff IR |
38 | "EventCode": "0x48", |
39 | "EventName": "L1D_PEND_MISS.PENDING", | |
09625cff IR |
40 | "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", |
41 | "SampleAfterValue": "1000003", | |
09625cff | 42 | "UMask": "0x1" |
cdb29a8f JY |
43 | }, |
44 | { | |
09625cff | 45 | "BriefDescription": "Cycles with L1D load Misses outstanding.", |
09625cff IR |
46 | "CounterMask": "1", |
47 | "EventCode": "0x48", | |
48 | "EventName": "L1D_PEND_MISS.PENDING_CYCLES", | |
09625cff IR |
49 | "PublicDescription": "Counts duration of L1D miss outstanding in cycles.", |
50 | "SampleAfterValue": "1000003", | |
09625cff | 51 | "UMask": "0x1" |
cdb29a8f JY |
52 | }, |
53 | { | |
09625cff | 54 | "BriefDescription": "L2 cache lines filling L2", |
09625cff IR |
55 | "EventCode": "0xF1", |
56 | "EventName": "L2_LINES_IN.ALL", | |
09625cff IR |
57 | "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", |
58 | "SampleAfterValue": "100003", | |
09625cff IR |
59 | "UMask": "0x1f" |
60 | }, | |
61 | { | |
62 | "BriefDescription": "Cache lines that are evicted by L2 cache when triggered by an L2 cache fill.", | |
09625cff IR |
63 | "EventCode": "0xF2", |
64 | "EventName": "L2_LINES_OUT.NON_SILENT", | |
09625cff | 65 | "PublicDescription": "Counts the number of lines that are evicted by the L2 cache due to L2 cache fills. Evicted lines are delivered to the L3, which may or may not cache them, according to system load and priorities.", |
cdb29a8f | 66 | "SampleAfterValue": "200003", |
09625cff | 67 | "UMask": "0x2" |
cdb29a8f JY |
68 | }, |
69 | { | |
09625cff | 70 | "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.", |
09625cff IR |
71 | "EventCode": "0xF2", |
72 | "EventName": "L2_LINES_OUT.SILENT", | |
09625cff | 73 | "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", |
cdb29a8f | 74 | "SampleAfterValue": "200003", |
09625cff | 75 | "UMask": "0x1" |
cdb29a8f JY |
76 | }, |
77 | { | |
09625cff | 78 | "BriefDescription": "L2 code requests", |
cdb29a8f | 79 | "EventCode": "0x24", |
09625cff | 80 | "EventName": "L2_RQSTS.ALL_CODE_RD", |
09625cff | 81 | "PublicDescription": "Counts the total number of L2 code requests.", |
cdb29a8f | 82 | "SampleAfterValue": "200003", |
09625cff | 83 | "UMask": "0xe4" |
cdb29a8f JY |
84 | }, |
85 | { | |
86 | "BriefDescription": "Demand Data Read requests", | |
cdb29a8f JY |
87 | "EventCode": "0x24", |
88 | "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", | |
cdb29a8f JY |
89 | "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", |
90 | "SampleAfterValue": "200003", | |
cdb29a8f JY |
91 | "UMask": "0xe1" |
92 | }, | |
09625cff IR |
93 | { |
94 | "BriefDescription": "Demand requests that miss L2 cache", | |
09625cff IR |
95 | "EventCode": "0x24", |
96 | "EventName": "L2_RQSTS.ALL_DEMAND_MISS", | |
09625cff IR |
97 | "PublicDescription": "Counts demand requests that miss L2 cache.", |
98 | "SampleAfterValue": "200003", | |
09625cff IR |
99 | "UMask": "0x27" |
100 | }, | |
cdb29a8f JY |
101 | { |
102 | "BriefDescription": "RFO requests to L2 cache", | |
cdb29a8f JY |
103 | "EventCode": "0x24", |
104 | "EventName": "L2_RQSTS.ALL_RFO", | |
cdb29a8f JY |
105 | "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", |
106 | "SampleAfterValue": "200003", | |
cdb29a8f JY |
107 | "UMask": "0xe2" |
108 | }, | |
109 | { | |
09625cff | 110 | "BriefDescription": "L2 cache hits when fetching instructions, code reads.", |
cdb29a8f | 111 | "EventCode": "0x24", |
09625cff | 112 | "EventName": "L2_RQSTS.CODE_RD_HIT", |
09625cff | 113 | "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", |
cdb29a8f | 114 | "SampleAfterValue": "200003", |
09625cff | 115 | "UMask": "0xc4" |
cdb29a8f JY |
116 | }, |
117 | { | |
09625cff | 118 | "BriefDescription": "L2 cache misses when fetching instructions", |
09625cff IR |
119 | "EventCode": "0x24", |
120 | "EventName": "L2_RQSTS.CODE_RD_MISS", | |
09625cff IR |
121 | "PublicDescription": "Counts L2 cache misses when fetching instructions.", |
122 | "SampleAfterValue": "200003", | |
09625cff | 123 | "UMask": "0x24" |
cdb29a8f JY |
124 | }, |
125 | { | |
09625cff | 126 | "BriefDescription": "Demand Data Read requests that hit L2 cache", |
09625cff IR |
127 | "EventCode": "0x24", |
128 | "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", | |
09625cff IR |
129 | "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", |
130 | "SampleAfterValue": "200003", | |
09625cff | 131 | "UMask": "0xc1" |
cdb29a8f JY |
132 | }, |
133 | { | |
09625cff | 134 | "BriefDescription": "Demand Data Read miss L2, no rejects", |
09625cff IR |
135 | "EventCode": "0x24", |
136 | "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", | |
09625cff IR |
137 | "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", |
138 | "SampleAfterValue": "200003", | |
09625cff | 139 | "UMask": "0x21" |
cdb29a8f JY |
140 | }, |
141 | { | |
09625cff | 142 | "BriefDescription": "RFO requests that hit L2 cache", |
09625cff IR |
143 | "EventCode": "0x24", |
144 | "EventName": "L2_RQSTS.RFO_HIT", | |
09625cff IR |
145 | "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", |
146 | "SampleAfterValue": "200003", | |
09625cff | 147 | "UMask": "0xc2" |
cdb29a8f JY |
148 | }, |
149 | { | |
09625cff | 150 | "BriefDescription": "RFO requests that miss L2 cache", |
09625cff IR |
151 | "EventCode": "0x24", |
152 | "EventName": "L2_RQSTS.RFO_MISS", | |
09625cff IR |
153 | "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", |
154 | "SampleAfterValue": "200003", | |
09625cff | 155 | "UMask": "0x22" |
cdb29a8f JY |
156 | }, |
157 | { | |
09625cff | 158 | "BriefDescription": "SW prefetch requests that hit L2 cache.", |
09625cff IR |
159 | "EventCode": "0x24", |
160 | "EventName": "L2_RQSTS.SWPF_HIT", | |
09625cff IR |
161 | "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", |
162 | "SampleAfterValue": "200003", | |
09625cff | 163 | "UMask": "0xc8" |
cdb29a8f JY |
164 | }, |
165 | { | |
09625cff | 166 | "BriefDescription": "SW prefetch requests that miss L2 cache.", |
09625cff IR |
167 | "EventCode": "0x24", |
168 | "EventName": "L2_RQSTS.SWPF_MISS", | |
09625cff IR |
169 | "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", |
170 | "SampleAfterValue": "200003", | |
09625cff | 171 | "UMask": "0x28" |
cdb29a8f JY |
172 | }, |
173 | { | |
09625cff | 174 | "BriefDescription": "L2 writebacks that access L2 cache", |
09625cff IR |
175 | "EventCode": "0xF0", |
176 | "EventName": "L2_TRANS.L2_WB", | |
09625cff IR |
177 | "PublicDescription": "Counts L2 writebacks that access L2 cache.", |
178 | "SampleAfterValue": "200003", | |
09625cff | 179 | "UMask": "0x40" |
cdb29a8f JY |
180 | }, |
181 | { | |
09625cff | 182 | "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", |
09625cff IR |
183 | "EventCode": "0x2e", |
184 | "EventName": "LONGEST_LAT_CACHE.MISS", | |
09625cff IR |
185 | "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", |
186 | "SampleAfterValue": "100003", | |
09625cff | 187 | "UMask": "0x41" |
cdb29a8f JY |
188 | }, |
189 | { | |
09625cff | 190 | "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", |
09625cff IR |
191 | "EventCode": "0x2e", |
192 | "EventName": "LONGEST_LAT_CACHE.REFERENCE", | |
09625cff IR |
193 | "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", |
194 | "SampleAfterValue": "100003", | |
09625cff | 195 | "UMask": "0x4f" |
cdb29a8f JY |
196 | }, |
197 | { | |
d214d0c2 | 198 | "BriefDescription": "Retired load instructions.", |
09625cff IR |
199 | "Data_LA": "1", |
200 | "EventCode": "0xd0", | |
201 | "EventName": "MEM_INST_RETIRED.ALL_LOADS", | |
202 | "PEBS": "1", | |
d214d0c2 | 203 | "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", |
09625cff IR |
204 | "SampleAfterValue": "1000003", |
205 | "UMask": "0x81" | |
cdb29a8f JY |
206 | }, |
207 | { | |
d214d0c2 | 208 | "BriefDescription": "Retired store instructions.", |
cdb29a8f JY |
209 | "Data_LA": "1", |
210 | "EventCode": "0xd0", | |
09625cff | 211 | "EventName": "MEM_INST_RETIRED.ALL_STORES", |
cdb29a8f | 212 | "PEBS": "1", |
d214d0c2 | 213 | "PublicDescription": "Counts all retired store instructions.", |
09625cff IR |
214 | "SampleAfterValue": "1000003", |
215 | "UMask": "0x82" | |
cdb29a8f JY |
216 | }, |
217 | { | |
09625cff | 218 | "BriefDescription": "All retired memory instructions.", |
cdb29a8f JY |
219 | "Data_LA": "1", |
220 | "EventCode": "0xd0", | |
09625cff | 221 | "EventName": "MEM_INST_RETIRED.ANY", |
cdb29a8f | 222 | "PEBS": "1", |
09625cff IR |
223 | "PublicDescription": "Counts all retired memory instructions - loads and stores.", |
224 | "SampleAfterValue": "1000003", | |
225 | "UMask": "0x83" | |
cdb29a8f JY |
226 | }, |
227 | { | |
228 | "BriefDescription": "Retired load instructions with locked access.", | |
cdb29a8f JY |
229 | "Data_LA": "1", |
230 | "EventCode": "0xd0", | |
231 | "EventName": "MEM_INST_RETIRED.LOCK_LOADS", | |
232 | "PEBS": "1", | |
cdb29a8f JY |
233 | "PublicDescription": "Counts retired load instructions with locked access.", |
234 | "SampleAfterValue": "100007", | |
235 | "UMask": "0x21" | |
236 | }, | |
237 | { | |
238 | "BriefDescription": "Retired load instructions that split across a cacheline boundary.", | |
cdb29a8f JY |
239 | "Data_LA": "1", |
240 | "EventCode": "0xd0", | |
241 | "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", | |
242 | "PEBS": "1", | |
cdb29a8f JY |
243 | "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", |
244 | "SampleAfterValue": "100003", | |
245 | "UMask": "0x41" | |
246 | }, | |
247 | { | |
248 | "BriefDescription": "Retired store instructions that split across a cacheline boundary.", | |
cdb29a8f JY |
249 | "Data_LA": "1", |
250 | "EventCode": "0xd0", | |
251 | "EventName": "MEM_INST_RETIRED.SPLIT_STORES", | |
cdb29a8f | 252 | "PEBS": "1", |
cdb29a8f JY |
253 | "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.", |
254 | "SampleAfterValue": "100003", | |
255 | "UMask": "0x42" | |
256 | }, | |
257 | { | |
09625cff | 258 | "BriefDescription": "Retired load instructions that miss the STLB.", |
cdb29a8f JY |
259 | "Data_LA": "1", |
260 | "EventCode": "0xd0", | |
09625cff | 261 | "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", |
cdb29a8f | 262 | "PEBS": "1", |
09625cff IR |
263 | "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).", |
264 | "SampleAfterValue": "100003", | |
265 | "UMask": "0x11" | |
cdb29a8f JY |
266 | }, |
267 | { | |
09625cff | 268 | "BriefDescription": "Retired store instructions that miss the STLB.", |
cdb29a8f JY |
269 | "Data_LA": "1", |
270 | "EventCode": "0xd0", | |
09625cff | 271 | "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", |
cdb29a8f | 272 | "PEBS": "1", |
09625cff IR |
273 | "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).", |
274 | "SampleAfterValue": "100003", | |
275 | "UMask": "0x12" | |
cdb29a8f JY |
276 | }, |
277 | { | |
09625cff | 278 | "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", |
cdb29a8f | 279 | "Data_LA": "1", |
09625cff IR |
280 | "EventCode": "0xd2", |
281 | "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", | |
cdb29a8f | 282 | "PEBS": "1", |
09625cff IR |
283 | "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.", |
284 | "SampleAfterValue": "20011", | |
09625cff | 285 | "UMask": "0x4" |
cdb29a8f JY |
286 | }, |
287 | { | |
09625cff | 288 | "BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", |
cdb29a8f | 289 | "Data_LA": "1", |
f8e23ad1 | 290 | "Deprecated": "1", |
09625cff IR |
291 | "EventCode": "0xd2", |
292 | "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", | |
cdb29a8f | 293 | "PEBS": "1", |
09625cff | 294 | "SampleAfterValue": "20011", |
cdb29a8f JY |
295 | "UMask": "0x2" |
296 | }, | |
297 | { | |
09625cff | 298 | "BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", |
cdb29a8f | 299 | "Data_LA": "1", |
f8e23ad1 | 300 | "Deprecated": "1", |
09625cff IR |
301 | "EventCode": "0xd2", |
302 | "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", | |
cdb29a8f | 303 | "PEBS": "1", |
09625cff | 304 | "SampleAfterValue": "20011", |
cdb29a8f JY |
305 | "UMask": "0x4" |
306 | }, | |
307 | { | |
09625cff | 308 | "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", |
cdb29a8f | 309 | "Data_LA": "1", |
09625cff IR |
310 | "EventCode": "0xd2", |
311 | "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", | |
cdb29a8f | 312 | "PEBS": "1", |
09625cff IR |
313 | "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", |
314 | "SampleAfterValue": "20011", | |
315 | "UMask": "0x1" | |
cdb29a8f JY |
316 | }, |
317 | { | |
09625cff | 318 | "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", |
cdb29a8f | 319 | "Data_LA": "1", |
09625cff IR |
320 | "EventCode": "0xd2", |
321 | "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", | |
cdb29a8f | 322 | "PEBS": "1", |
09625cff IR |
323 | "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.", |
324 | "SampleAfterValue": "100003", | |
325 | "UMask": "0x8" | |
cdb29a8f JY |
326 | }, |
327 | { | |
09625cff | 328 | "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", |
cdb29a8f | 329 | "Data_LA": "1", |
09625cff IR |
330 | "EventCode": "0xd2", |
331 | "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", | |
cdb29a8f | 332 | "PEBS": "1", |
09625cff IR |
333 | "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", |
334 | "SampleAfterValue": "20011", | |
09625cff | 335 | "UMask": "0x2" |
cdb29a8f JY |
336 | }, |
337 | { | |
09625cff | 338 | "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", |
cdb29a8f | 339 | "Data_LA": "1", |
09625cff IR |
340 | "EventCode": "0xd3", |
341 | "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", | |
cdb29a8f | 342 | "PEBS": "1", |
09625cff | 343 | "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.", |
cdb29a8f | 344 | "SampleAfterValue": "100007", |
09625cff | 345 | "UMask": "0x1" |
cdb29a8f JY |
346 | }, |
347 | { | |
09625cff | 348 | "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from remote dram", |
cdb29a8f | 349 | "Data_LA": "1", |
09625cff IR |
350 | "EventCode": "0xd3", |
351 | "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", | |
cdb29a8f | 352 | "PEBS": "1", |
09625cff IR |
353 | "SampleAfterValue": "100007", |
354 | "UMask": "0x2" | |
cdb29a8f JY |
355 | }, |
356 | { | |
09625cff | 357 | "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache", |
cdb29a8f | 358 | "Data_LA": "1", |
09625cff IR |
359 | "EventCode": "0xd3", |
360 | "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", | |
cdb29a8f | 361 | "PEBS": "1", |
09625cff IR |
362 | "PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache.", |
363 | "SampleAfterValue": "100007", | |
364 | "UMask": "0x8" | |
cdb29a8f JY |
365 | }, |
366 | { | |
09625cff | 367 | "BriefDescription": "Retired load instructions whose data sources was remote HITM", |
cdb29a8f | 368 | "Data_LA": "1", |
09625cff IR |
369 | "EventCode": "0xd3", |
370 | "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", | |
cdb29a8f | 371 | "PEBS": "1", |
09625cff IR |
372 | "PublicDescription": "Retired load instructions whose data sources was remote HITM.", |
373 | "SampleAfterValue": "100007", | |
374 | "UMask": "0x4" | |
cdb29a8f JY |
375 | }, |
376 | { | |
f8e23ad1 | 377 | "BriefDescription": "Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", |
cdb29a8f | 378 | "Data_LA": "1", |
09625cff IR |
379 | "EventCode": "0xd3", |
380 | "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", | |
cdb29a8f | 381 | "PEBS": "1", |
f8e23ad1 | 382 | "PublicDescription": "Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).", |
09625cff IR |
383 | "SampleAfterValue": "100007", |
384 | "UMask": "0x10" | |
cdb29a8f JY |
385 | }, |
386 | { | |
09625cff | 387 | "BriefDescription": "Retired instructions with at least 1 uncacheable load or Bus Lock.", |
cdb29a8f | 388 | "Data_LA": "1", |
09625cff IR |
389 | "EventCode": "0xd4", |
390 | "EventName": "MEM_LOAD_MISC_RETIRED.UC", | |
cdb29a8f | 391 | "PEBS": "1", |
09625cff IR |
392 | "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).", |
393 | "SampleAfterValue": "100007", | |
cdb29a8f JY |
394 | "UMask": "0x4" |
395 | }, | |
396 | { | |
09625cff | 397 | "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", |
cdb29a8f | 398 | "Data_LA": "1", |
09625cff IR |
399 | "EventCode": "0xd1", |
400 | "EventName": "MEM_LOAD_RETIRED.FB_HIT", | |
cdb29a8f | 401 | "PEBS": "1", |
09625cff IR |
402 | "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", |
403 | "SampleAfterValue": "100007", | |
404 | "UMask": "0x40" | |
cdb29a8f JY |
405 | }, |
406 | { | |
09625cff | 407 | "BriefDescription": "Retired load instructions with L1 cache hits as data sources", |
cdb29a8f | 408 | "Data_LA": "1", |
09625cff IR |
409 | "EventCode": "0xd1", |
410 | "EventName": "MEM_LOAD_RETIRED.L1_HIT", | |
cdb29a8f | 411 | "PEBS": "1", |
09625cff IR |
412 | "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", |
413 | "SampleAfterValue": "1000003", | |
414 | "UMask": "0x1" | |
cdb29a8f JY |
415 | }, |
416 | { | |
09625cff | 417 | "BriefDescription": "Retired load instructions missed L1 cache as data sources", |
cdb29a8f | 418 | "Data_LA": "1", |
09625cff IR |
419 | "EventCode": "0xd1", |
420 | "EventName": "MEM_LOAD_RETIRED.L1_MISS", | |
cdb29a8f | 421 | "PEBS": "1", |
09625cff IR |
422 | "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", |
423 | "SampleAfterValue": "200003", | |
424 | "UMask": "0x8" | |
cdb29a8f JY |
425 | }, |
426 | { | |
09625cff | 427 | "BriefDescription": "Retired load instructions with L2 cache hits as data sources", |
cdb29a8f | 428 | "Data_LA": "1", |
09625cff IR |
429 | "EventCode": "0xd1", |
430 | "EventName": "MEM_LOAD_RETIRED.L2_HIT", | |
cdb29a8f | 431 | "PEBS": "1", |
09625cff IR |
432 | "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.", |
433 | "SampleAfterValue": "200003", | |
cdb29a8f JY |
434 | "UMask": "0x2" |
435 | }, | |
436 | { | |
09625cff | 437 | "BriefDescription": "Retired load instructions missed L2 cache as data sources", |
cdb29a8f | 438 | "Data_LA": "1", |
09625cff IR |
439 | "EventCode": "0xd1", |
440 | "EventName": "MEM_LOAD_RETIRED.L2_MISS", | |
cdb29a8f | 441 | "PEBS": "1", |
09625cff IR |
442 | "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.", |
443 | "SampleAfterValue": "100021", | |
444 | "UMask": "0x10" | |
445 | }, | |
446 | { | |
447 | "BriefDescription": "Retired load instructions with L3 cache hits as data sources", | |
09625cff IR |
448 | "Data_LA": "1", |
449 | "EventCode": "0xd1", | |
450 | "EventName": "MEM_LOAD_RETIRED.L3_HIT", | |
451 | "PEBS": "1", | |
09625cff IR |
452 | "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", |
453 | "SampleAfterValue": "100021", | |
cdb29a8f JY |
454 | "UMask": "0x4" |
455 | }, | |
456 | { | |
09625cff | 457 | "BriefDescription": "Retired load instructions missed L3 cache as data sources", |
cdb29a8f | 458 | "Data_LA": "1", |
09625cff IR |
459 | "EventCode": "0xd1", |
460 | "EventName": "MEM_LOAD_RETIRED.L3_MISS", | |
cdb29a8f | 461 | "PEBS": "1", |
09625cff IR |
462 | "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", |
463 | "SampleAfterValue": "50021", | |
464 | "UMask": "0x20" | |
cdb29a8f JY |
465 | }, |
466 | { | |
f8e23ad1 | 467 | "BriefDescription": "Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", |
cdb29a8f | 468 | "Data_LA": "1", |
09625cff IR |
469 | "EventCode": "0xd1", |
470 | "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM", | |
cdb29a8f | 471 | "PEBS": "1", |
f8e23ad1 | 472 | "PublicDescription": "Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).", |
09625cff IR |
473 | "SampleAfterValue": "100003", |
474 | "UMask": "0x80" | |
cdb29a8f | 475 | }, |
f25db21b IR |
476 | { |
477 | "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", | |
f25db21b IR |
478 | "EventCode": "0xB7, 0xBB", |
479 | "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", | |
480 | "MSRIndex": "0x1a6,0x1a7", | |
481 | "MSRValue": "0x3F803C0004", | |
f25db21b IR |
482 | "SampleAfterValue": "100003", |
483 | "UMask": "0x1" | |
484 | }, | |
485 | { | |
486 | "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", | |
f25db21b IR |
487 | "EventCode": "0xB7, 0xBB", |
488 | "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", | |
489 | "MSRIndex": "0x1a6,0x1a7", | |
490 | "MSRValue": "0x10003C0004", | |
f25db21b IR |
491 | "SampleAfterValue": "100003", |
492 | "UMask": "0x1" | |
493 | }, | |
cdb29a8f | 494 | { |
09625cff | 495 | "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", |
09625cff IR |
496 | "EventCode": "0xB7, 0xBB", |
497 | "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM", | |
498 | "MSRIndex": "0x1a6,0x1a7", | |
499 | "MSRValue": "0x1008000004", | |
09625cff IR |
500 | "SampleAfterValue": "100003", |
501 | "UMask": "0x1" | |
502 | }, | |
503 | { | |
504 | "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", | |
09625cff IR |
505 | "EventCode": "0xB7, 0xBB", |
506 | "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD", | |
507 | "MSRIndex": "0x1a6,0x1a7", | |
508 | "MSRValue": "0x808000004", | |
09625cff IR |
509 | "SampleAfterValue": "100003", |
510 | "UMask": "0x1" | |
511 | }, | |
f25db21b IR |
512 | { |
513 | "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.", | |
f25db21b IR |
514 | "EventCode": "0xB7, 0xBB", |
515 | "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", | |
516 | "MSRIndex": "0x1a6,0x1a7", | |
517 | "MSRValue": "0x3F803C0001", | |
f25db21b IR |
518 | "SampleAfterValue": "100003", |
519 | "UMask": "0x1" | |
520 | }, | |
521 | { | |
522 | "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", | |
f25db21b IR |
523 | "EventCode": "0xB7, 0xBB", |
524 | "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", | |
525 | "MSRIndex": "0x1a6,0x1a7", | |
526 | "MSRValue": "0x10003C0001", | |
f25db21b IR |
527 | "SampleAfterValue": "100003", |
528 | "UMask": "0x1" | |
529 | }, | |
530 | { | |
531 | "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.", | |
f25db21b IR |
532 | "EventCode": "0xB7, 0xBB", |
533 | "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", | |
534 | "MSRIndex": "0x1a6,0x1a7", | |
535 | "MSRValue": "0x4003C0001", | |
f25db21b IR |
536 | "SampleAfterValue": "100003", |
537 | "UMask": "0x1" | |
538 | }, | |
539 | { | |
540 | "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", | |
f25db21b IR |
541 | "EventCode": "0xB7, 0xBB", |
542 | "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", | |
543 | "MSRIndex": "0x1a6,0x1a7", | |
544 | "MSRValue": "0x8003C0001", | |
f25db21b IR |
545 | "SampleAfterValue": "100003", |
546 | "UMask": "0x1" | |
547 | }, | |
09625cff IR |
548 | { |
549 | "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", | |
09625cff IR |
550 | "EventCode": "0xB7, 0xBB", |
551 | "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM", | |
552 | "MSRIndex": "0x1a6,0x1a7", | |
553 | "MSRValue": "0x1030000001", | |
09625cff IR |
554 | "SampleAfterValue": "100003", |
555 | "UMask": "0x1" | |
556 | }, | |
557 | { | |
558 | "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", | |
09625cff IR |
559 | "EventCode": "0xB7, 0xBB", |
560 | "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", | |
561 | "MSRIndex": "0x1a6,0x1a7", | |
562 | "MSRValue": "0x830000001", | |
09625cff IR |
563 | "SampleAfterValue": "100003", |
564 | "UMask": "0x1" | |
565 | }, | |
566 | { | |
567 | "BriefDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", | |
09625cff IR |
568 | "EventCode": "0xB7, 0xBB", |
569 | "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM", | |
570 | "MSRIndex": "0x1a6,0x1a7", | |
571 | "MSRValue": "0x1008000001", | |
09625cff IR |
572 | "SampleAfterValue": "100003", |
573 | "UMask": "0x1" | |
574 | }, | |
575 | { | |
576 | "BriefDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", | |
09625cff IR |
577 | "EventCode": "0xB7, 0xBB", |
578 | "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD", | |
579 | "MSRIndex": "0x1a6,0x1a7", | |
580 | "MSRValue": "0x808000001", | |
09625cff IR |
581 | "SampleAfterValue": "100003", |
582 | "UMask": "0x1" | |
583 | }, | |
f25db21b IR |
584 | { |
585 | "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", | |
f25db21b IR |
586 | "EventCode": "0xB7, 0xBB", |
587 | "EventName": "OCR.DEMAND_RFO.L3_HIT", | |
588 | "MSRIndex": "0x1a6,0x1a7", | |
589 | "MSRValue": "0x3F803C0002", | |
f25db21b IR |
590 | "SampleAfterValue": "100003", |
591 | "UMask": "0x1" | |
592 | }, | |
593 | { | |
594 | "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", | |
f25db21b IR |
595 | "EventCode": "0xB7, 0xBB", |
596 | "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", | |
597 | "MSRIndex": "0x1a6,0x1a7", | |
598 | "MSRValue": "0x10003C0002", | |
f25db21b IR |
599 | "SampleAfterValue": "100003", |
600 | "UMask": "0x1" | |
601 | }, | |
09625cff IR |
602 | { |
603 | "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", | |
09625cff IR |
604 | "EventCode": "0xB7, 0xBB", |
605 | "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM", | |
606 | "MSRIndex": "0x1a6,0x1a7", | |
607 | "MSRValue": "0x1008000002", | |
09625cff IR |
608 | "SampleAfterValue": "100003", |
609 | "UMask": "0x1" | |
610 | }, | |
611 | { | |
612 | "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", | |
09625cff IR |
613 | "EventCode": "0xB7, 0xBB", |
614 | "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD", | |
615 | "MSRIndex": "0x1a6,0x1a7", | |
616 | "MSRValue": "0x808000002", | |
09625cff IR |
617 | "SampleAfterValue": "100003", |
618 | "UMask": "0x1" | |
619 | }, | |
f25db21b IR |
620 | { |
621 | "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", | |
f25db21b IR |
622 | "EventCode": "0xB7, 0xBB", |
623 | "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT", | |
624 | "MSRIndex": "0x1a6,0x1a7", | |
625 | "MSRValue": "0x3F803C0400", | |
f25db21b IR |
626 | "SampleAfterValue": "100003", |
627 | "UMask": "0x1" | |
628 | }, | |
629 | { | |
630 | "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.", | |
f25db21b IR |
631 | "EventCode": "0xB7, 0xBB", |
632 | "EventName": "OCR.HWPF_L3.L3_HIT", | |
633 | "MSRIndex": "0x1a6,0x1a7", | |
634 | "MSRValue": "0x80082380", | |
f25db21b IR |
635 | "SampleAfterValue": "100003", |
636 | "UMask": "0x1" | |
637 | }, | |
638 | { | |
639 | "BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.", | |
f25db21b IR |
640 | "EventCode": "0xB7, 0xBB", |
641 | "EventName": "OCR.PREFETCHES.L3_HIT", | |
642 | "MSRIndex": "0x1a6,0x1a7", | |
643 | "MSRValue": "0x3F803C27F0", | |
f25db21b IR |
644 | "SampleAfterValue": "100003", |
645 | "UMask": "0x1" | |
646 | }, | |
647 | { | |
d214d0c2 | 648 | "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", |
f25db21b IR |
649 | "EventCode": "0xB7, 0xBB", |
650 | "EventName": "OCR.READS_TO_CORE.L3_HIT", | |
651 | "MSRIndex": "0x1a6,0x1a7", | |
652 | "MSRValue": "0x3F003C0477", | |
f25db21b IR |
653 | "SampleAfterValue": "100003", |
654 | "UMask": "0x1" | |
655 | }, | |
656 | { | |
d214d0c2 | 657 | "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", |
f25db21b IR |
658 | "EventCode": "0xB7, 0xBB", |
659 | "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", | |
660 | "MSRIndex": "0x1a6,0x1a7", | |
661 | "MSRValue": "0x10003C0477", | |
f25db21b IR |
662 | "SampleAfterValue": "100003", |
663 | "UMask": "0x1" | |
664 | }, | |
665 | { | |
d214d0c2 | 666 | "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.", |
f25db21b IR |
667 | "EventCode": "0xB7, 0xBB", |
668 | "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", | |
669 | "MSRIndex": "0x1a6,0x1a7", | |
670 | "MSRValue": "0x4003C0477", | |
f25db21b IR |
671 | "SampleAfterValue": "100003", |
672 | "UMask": "0x1" | |
673 | }, | |
674 | { | |
d214d0c2 | 675 | "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", |
f25db21b IR |
676 | "EventCode": "0xB7, 0xBB", |
677 | "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", | |
678 | "MSRIndex": "0x1a6,0x1a7", | |
679 | "MSRValue": "0x8003C0477", | |
f25db21b IR |
680 | "SampleAfterValue": "100003", |
681 | "UMask": "0x1" | |
682 | }, | |
683 | { | |
d214d0c2 | 684 | "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).", |
f25db21b IR |
685 | "EventCode": "0xB7, 0xBB", |
686 | "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD", | |
687 | "MSRIndex": "0x1a6,0x1a7", | |
688 | "MSRValue": "0x1830000477", | |
f25db21b IR |
689 | "SampleAfterValue": "100003", |
690 | "UMask": "0x1" | |
691 | }, | |
09625cff | 692 | { |
d214d0c2 | 693 | "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", |
09625cff IR |
694 | "EventCode": "0xB7, 0xBB", |
695 | "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM", | |
696 | "MSRIndex": "0x1a6,0x1a7", | |
697 | "MSRValue": "0x1030000477", | |
09625cff IR |
698 | "SampleAfterValue": "100003", |
699 | "UMask": "0x1" | |
700 | }, | |
701 | { | |
d214d0c2 | 702 | "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", |
09625cff IR |
703 | "EventCode": "0xB7, 0xBB", |
704 | "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", | |
705 | "MSRIndex": "0x1a6,0x1a7", | |
706 | "MSRValue": "0x830000477", | |
09625cff IR |
707 | "SampleAfterValue": "100003", |
708 | "UMask": "0x1" | |
709 | }, | |
710 | { | |
d214d0c2 | 711 | "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", |
09625cff IR |
712 | "EventCode": "0xB7, 0xBB", |
713 | "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM", | |
714 | "MSRIndex": "0x1a6,0x1a7", | |
715 | "MSRValue": "0x1008000477", | |
09625cff IR |
716 | "SampleAfterValue": "100003", |
717 | "UMask": "0x1" | |
718 | }, | |
719 | { | |
d214d0c2 | 720 | "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", |
09625cff IR |
721 | "EventCode": "0xB7, 0xBB", |
722 | "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD", | |
723 | "MSRIndex": "0x1a6,0x1a7", | |
724 | "MSRValue": "0x808000477", | |
09625cff IR |
725 | "SampleAfterValue": "100003", |
726 | "UMask": "0x1" | |
727 | }, | |
f25db21b IR |
728 | { |
729 | "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.", | |
f25db21b IR |
730 | "EventCode": "0xB7, 0xBB", |
731 | "EventName": "OCR.STREAMING_WR.L3_HIT", | |
732 | "MSRIndex": "0x1a6,0x1a7", | |
733 | "MSRValue": "0x80080800", | |
f25db21b IR |
734 | "SampleAfterValue": "100003", |
735 | "UMask": "0x1" | |
736 | }, | |
09625cff IR |
737 | { |
738 | "BriefDescription": "Demand and prefetch data reads", | |
09625cff IR |
739 | "EventCode": "0xB0", |
740 | "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", | |
09625cff IR |
741 | "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", |
742 | "SampleAfterValue": "100003", | |
09625cff | 743 | "UMask": "0x8" |
cdb29a8f JY |
744 | }, |
745 | { | |
09625cff | 746 | "BriefDescription": "Counts memory transactions sent to the uncore.", |
09625cff IR |
747 | "EventCode": "0xB0", |
748 | "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", | |
09625cff | 749 | "PublicDescription": "Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses.", |
cdb29a8f | 750 | "SampleAfterValue": "100003", |
09625cff | 751 | "UMask": "0x80" |
cdb29a8f JY |
752 | }, |
753 | { | |
09625cff | 754 | "BriefDescription": "Counts cacheable and non-cacheable code reads to the core.", |
09625cff IR |
755 | "EventCode": "0xb0", |
756 | "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", | |
09625cff IR |
757 | "PublicDescription": "Counts both cacheable and non-cacheable code reads to the core.", |
758 | "SampleAfterValue": "100003", | |
09625cff IR |
759 | "UMask": "0x2" |
760 | }, | |
761 | { | |
762 | "BriefDescription": "Demand Data Read requests sent to uncore", | |
09625cff IR |
763 | "EventCode": "0xb0", |
764 | "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", | |
09625cff IR |
765 | "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", |
766 | "SampleAfterValue": "100003", | |
cdb29a8f JY |
767 | "UMask": "0x1" |
768 | }, | |
769 | { | |
09625cff | 770 | "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", |
09625cff IR |
771 | "EventCode": "0xb0", |
772 | "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", | |
09625cff IR |
773 | "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", |
774 | "SampleAfterValue": "100003", | |
09625cff IR |
775 | "UMask": "0x4" |
776 | }, | |
777 | { | |
778 | "BriefDescription": "For every cycle, increments by the number of outstanding data read requests pending.", | |
09625cff IR |
779 | "EventCode": "0x60", |
780 | "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", | |
09625cff IR |
781 | "PublicDescription": "For every cycle, increments by the number of outstanding data read requests pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", |
782 | "SampleAfterValue": "1000003", | |
09625cff IR |
783 | "UMask": "0x8" |
784 | }, | |
785 | { | |
786 | "BriefDescription": "Cycles where at least 1 outstanding data read request is pending.", | |
09625cff IR |
787 | "CounterMask": "1", |
788 | "EventCode": "0x60", | |
789 | "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", | |
09625cff IR |
790 | "PublicDescription": "Cycles where at least 1 outstanding data read request is pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", |
791 | "SampleAfterValue": "1000003", | |
09625cff IR |
792 | "UMask": "0x8" |
793 | }, | |
794 | { | |
795 | "BriefDescription": "Cycles with outstanding code read requests pending.", | |
09625cff IR |
796 | "CounterMask": "1", |
797 | "EventCode": "0x60", | |
798 | "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", | |
09625cff IR |
799 | "PublicDescription": "Cycles with outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", |
800 | "SampleAfterValue": "1000003", | |
09625cff IR |
801 | "UMask": "0x2" |
802 | }, | |
803 | { | |
804 | "BriefDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.", | |
09625cff IR |
805 | "CounterMask": "1", |
806 | "EventCode": "0x60", | |
807 | "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", | |
09625cff IR |
808 | "PublicDescription": "Cycles where at least 1 outstanding Demand RFO request is pending. RFOs are initiated by a core as part of a data store operation. Demand RFO requests include RFOs, locks, and ItoM transactions. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", |
809 | "SampleAfterValue": "1000003", | |
09625cff IR |
810 | "UMask": "0x4" |
811 | }, | |
812 | { | |
813 | "BriefDescription": "For every cycle, increments by the number of outstanding code read requests pending.", | |
09625cff IR |
814 | "EventCode": "0x60", |
815 | "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", | |
09625cff IR |
816 | "PublicDescription": "For every cycle, increments by the number of outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", |
817 | "SampleAfterValue": "1000003", | |
cdb29a8f JY |
818 | "UMask": "0x2" |
819 | }, | |
09625cff IR |
820 | { |
821 | "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.", | |
09625cff IR |
822 | "EventCode": "0x60", |
823 | "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", | |
09625cff IR |
824 | "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", |
825 | "SampleAfterValue": "1000003", | |
09625cff IR |
826 | "UMask": "0x1" |
827 | }, | |
cdb29a8f JY |
828 | { |
829 | "BriefDescription": "Cycles the queue waiting for offcore responses is full.", | |
cdb29a8f JY |
830 | "EventCode": "0xf4", |
831 | "EventName": "SQ_MISC.SQ_FULL", | |
cdb29a8f JY |
832 | "PublicDescription": "Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries.", |
833 | "SampleAfterValue": "100003", | |
cdb29a8f | 834 | "UMask": "0x4" |
f25db21b IR |
835 | }, |
836 | { | |
837 | "BriefDescription": "Number of PREFETCHNTA instructions executed.", | |
f25db21b IR |
838 | "EventCode": "0x32", |
839 | "EventName": "SW_PREFETCH_ACCESS.NTA", | |
f25db21b IR |
840 | "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", |
841 | "SampleAfterValue": "100003", | |
f25db21b IR |
842 | "UMask": "0x1" |
843 | }, | |
844 | { | |
845 | "BriefDescription": "Number of PREFETCHW instructions executed.", | |
f25db21b IR |
846 | "EventCode": "0x32", |
847 | "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", | |
f25db21b IR |
848 | "PublicDescription": "Counts the number of PREFETCHW instructions executed.", |
849 | "SampleAfterValue": "100003", | |
f25db21b IR |
850 | "UMask": "0x8" |
851 | }, | |
852 | { | |
853 | "BriefDescription": "Number of PREFETCHT0 instructions executed.", | |
f25db21b IR |
854 | "EventCode": "0x32", |
855 | "EventName": "SW_PREFETCH_ACCESS.T0", | |
f25db21b IR |
856 | "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", |
857 | "SampleAfterValue": "100003", | |
f25db21b IR |
858 | "UMask": "0x2" |
859 | }, | |
860 | { | |
861 | "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", | |
f25db21b IR |
862 | "EventCode": "0x32", |
863 | "EventName": "SW_PREFETCH_ACCESS.T1_T2", | |
f25db21b IR |
864 | "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", |
865 | "SampleAfterValue": "100003", | |
f25db21b | 866 | "UMask": "0x4" |
cdb29a8f | 867 | } |
cbeee6ca | 868 | ] |