projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 27b565b1 AK |
1 | [ |
| 2 | { | |
| 27b565b1 | 3 | "BriefDescription": "Unhalted core cycles when the thread is in ring 0", |
| 6a8ec0b6 | 4 | "Counter": "0,1,2,3", |
| 34cb72ef | 5 | "EventCode": "0x5C", |
| 27b565b1 AK |
6 | "EventName": "CPL_CYCLES.RING0", |
| 7 | "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", | |
| 8 | "SampleAfterValue": "2000003", | |
| 34cb72ef | 9 | "UMask": "0x1" |
| 27b565b1 | 10 | }, |
| 27b565b1 | 11 | { |
| 27b565b1 | 12 | "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", |
| 6a8ec0b6 | 13 | "Counter": "0,1,2,3", |
| 27b565b1 | 14 | "CounterMask": "1", |
| 34cb72ef IR |
15 | "EdgeDetect": "1", |
| 16 | "EventCode": "0x5C", | |
| 17 | "EventName": "CPL_CYCLES.RING0_TRANS", | |
| 27b565b1 AK |
18 | "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", |
| 19 | "SampleAfterValue": "100007", | |
| 34cb72ef | 20 | "UMask": "0x1" |
| 27b565b1 | 21 | }, |
| fae0a4df | 22 | { |
| fae0a4df | 23 | "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", |
| 6a8ec0b6 | 24 | "Counter": "0,1,2,3", |
| 34cb72ef | 25 | "EventCode": "0x5C", |
| fae0a4df AK |
26 | "EventName": "CPL_CYCLES.RING123", |
| 27 | "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", | |
| 28 | "SampleAfterValue": "2000003", | |
| 34cb72ef | 29 | "UMask": "0x2" |
| fae0a4df | 30 | }, |
| 27b565b1 | 31 | { |
| 27b565b1 | 32 | "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", |
| 6a8ec0b6 | 33 | "Counter": "0,1,2,3", |
| 34cb72ef | 34 | "EventCode": "0x63", |
| 27b565b1 AK |
35 | "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", |
| 36 | "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", | |
| 37 | "SampleAfterValue": "2000003", | |
| 34cb72ef | 38 | "UMask": "0x1" |
| 27b565b1 | 39 | } |
| ef908a19 | 40 | ] |