[linux-block.git] / tools / objtool / arch / x86 / decode.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2015 Josh Poimboeuf <jpoimboe@redhat.com>
 */

#include <stdio.h>
#include <stdlib.h>

#define unlikely(cond) (cond)
#include <asm/insn.h>
#include "../../../arch/x86/lib/inat.c"
#include "../../../arch/x86/lib/insn.c"

#define CONFIG_64BIT 1
#include <asm/nops.h>

#include <asm/orc_types.h>
#include <objtool/check.h>
#include <objtool/elf.h>
#include <objtool/arch.h>
#include <objtool/warn.h>
#include <objtool/endianness.h>
#include <objtool/builtin.h>
#include <arch/elf.h>

int arch_ftrace_match(char *name)
{
	return !strcmp(name, "__fentry__");
}

static int is_x86_64(const struct elf *elf)
{
	switch (elf->ehdr.e_machine) {
	case EM_X86_64:
		return 1;
	case EM_386:
		return 0;
	default:
		WARN("unexpected ELF machine type %d", elf->ehdr.e_machine);
		return -1;
	}
}

bool arch_callee_saved_reg(unsigned char reg)
{
	switch (reg) {
	case CFI_BP:
	case CFI_BX:
	case CFI_R12:
	case CFI_R13:
	case CFI_R14:
	case CFI_R15:
		return true;

	case CFI_AX:
	case CFI_CX:
	case CFI_DX:
	case CFI_SI:
	case CFI_DI:
	case CFI_SP:
	case CFI_R8:
	case CFI_R9:
	case CFI_R10:
	case CFI_R11:
	case CFI_RA:
	default:
		return false;
	}
}

unsigned long arch_dest_reloc_offset(int addend)
{
	return addend + 4;
}

unsigned long arch_jump_destination(struct instruction *insn)
{
	return insn->offset + insn->len + insn->immediate;
}

bool arch_pc_relative_reloc(struct reloc *reloc)
{
	/*
	 * All relocation types where P (the address of the target)
	 * is included in the computation.
	 */
	switch (reloc_type(reloc)) {
	case R_X86_64_PC8:
	case R_X86_64_PC16:
	case R_X86_64_PC32:
	case R_X86_64_PC64:

	case R_X86_64_PLT32:
	case R_X86_64_GOTPC32:
	case R_X86_64_GOTPCREL:
		return true;

	default:
		break;
	}

	return false;
}

#define ADD_OP(op) \
	if (!(op = calloc(1, sizeof(*op)))) \
		return -1; \
	else for (*ops_list = op, ops_list = &op->next; op; op = NULL)

/*
 * Helpers to decode ModRM/SIB:
 *
 * r/m| AX  CX  DX  BX |  SP |  BP |  SI  DI |
 *    | R8  R9 R10 R11 | R12 | R13 | R14 R15 |
 * Mod+----------------+-----+-----+---------+
 * 00 |    [r/m]       |[SIB]|[IP+]|  [r/m]  |
 * 01 |  [r/m + d8]    |[S+d]|   [r/m + d8]  |
 * 10 |  [r/m + d32]   |[S+D]|   [r/m + d32] |
 * 11 |                   r/ m               |
 */

#define mod_is_mem()	(modrm_mod != 3)
#define mod_is_reg()	(modrm_mod == 3)

#define is_RIP()   ((modrm_rm & 7) == CFI_BP && modrm_mod == 0)
#define have_SIB() ((modrm_rm & 7) == CFI_SP && mod_is_mem())

#define rm_is(reg) (have_SIB() ? \
		    sib_base == (reg) && sib_index == CFI_SP : \
		    modrm_rm == (reg))

#define rm_is_mem(reg)	(mod_is_mem() && !is_RIP() && rm_is(reg))
#define rm_is_reg(reg)	(mod_is_reg() && modrm_rm == (reg))

static bool has_notrack_prefix(struct insn *insn)
{
	int i;

	for (i = 0; i < insn->prefixes.nbytes; i++) {
		if (insn->prefixes.bytes[i] == 0x3e)
			return true;
	}

	return false;
}

int arch_decode_instruction(struct objtool_file *file, const struct section *sec,
			    unsigned long offset, unsigned int maxlen,
			    struct instruction *insn)
{
	struct stack_op **ops_list = &insn->stack_ops;
	const struct elf *elf = file->elf;
	struct insn ins;
	int x86_64, ret;
	unsigned char op1, op2, op3, prefix,
		      rex = 0, rex_b = 0, rex_r = 0, rex_w = 0, rex_x = 0,
		      modrm = 0, modrm_mod = 0, modrm_rm = 0, modrm_reg = 0,
		      sib = 0, /* sib_scale = 0, */ sib_index = 0, sib_base = 0;
	struct stack_op *op = NULL;
	struct symbol *sym;
	u64 imm;

	x86_64 = is_x86_64(elf);
	if (x86_64 == -1)
		return -1;

	ret = insn_decode(&ins, sec->data->d_buf + offset, maxlen,
			  x86_64 ? INSN_MODE_64 : INSN_MODE_32);
	if (ret < 0) {
		WARN("can't decode instruction at %s:0x%lx", sec->name, offset);
		return -1;
	}

	insn->len = ins.length;
	insn->type = INSN_OTHER;

	if (ins.vex_prefix.nbytes)
		return 0;

	prefix = ins.prefixes.bytes[0];

	op1 = ins.opcode.bytes[0];
	op2 = ins.opcode.bytes[1];
	op3 = ins.opcode.bytes[2];

	if (ins.rex_prefix.nbytes) {
		rex = ins.rex_prefix.bytes[0];
		rex_w = X86_REX_W(rex) >> 3;
		rex_r = X86_REX_R(rex) >> 2;
		rex_x = X86_REX_X(rex) >> 1;
		rex_b = X86_REX_B(rex);
	}

	if (ins.modrm.nbytes) {
		modrm = ins.modrm.bytes[0];
		modrm_mod = X86_MODRM_MOD(modrm);
		modrm_reg = X86_MODRM_REG(modrm) + 8*rex_r;
		modrm_rm  = X86_MODRM_RM(modrm)  + 8*rex_b;
	}

	if (ins.sib.nbytes) {
		sib = ins.sib.bytes[0];
		/* sib_scale = X86_SIB_SCALE(sib); */
		sib_index = X86_SIB_INDEX(sib) + 8*rex_x;
		sib_base  = X86_SIB_BASE(sib)  + 8*rex_b;
	}

	switch (op1) {

	case 0x1:
	case 0x29:
		if (rex_w && rm_is_reg(CFI_SP)) {

			/* add/sub reg, %rsp */
			ADD_OP(op) {
				op->src.type = OP_SRC_ADD;
				op->src.reg = modrm_reg;
				op->dest.type = OP_DEST_REG;
				op->dest.reg = CFI_SP;
			}
		}
		break;

	case 0x50 ... 0x57:

		/* push reg */
		ADD_OP(op) {
			op->src.type = OP_SRC_REG;
			op->src.reg = (op1 & 0x7) + 8*rex_b;
			op->dest.type = OP_DEST_PUSH;
		}

		break;

	case 0x58 ... 0x5f:

		/* pop reg */
		ADD_OP(op) {
			op->src.type = OP_SRC_POP;
			op->dest.type = OP_DEST_REG;
			op->dest.reg = (op1 & 0x7) + 8*rex_b;
		}

		break;

	case 0x68:
	case 0x6a:
		/* push immediate */
		ADD_OP(op) {
			op->src.type = OP_SRC_CONST;
			op->dest.type = OP_DEST_PUSH;
		}
		break;

	case 0x70 ... 0x7f:
		insn->type = INSN_JUMP_CONDITIONAL;
		break;

	case 0x80 ... 0x83:
		/*
		 * 1000 00sw : mod OP r/m : immediate
		 *
		 * s - sign extend immediate
		 * w - imm8 / imm32
		 *
		 * OP: 000 ADD    100 AND
		 *     001 OR     101 SUB
		 *     010 ADC    110 XOR
		 *     011 SBB    111 CMP
		 */

		/* 64bit only */
		if (!rex_w)
			break;

		/* %rsp target only */
		if (!rm_is_reg(CFI_SP))
			break;

		imm = ins.immediate.value;
		if (op1 & 2) { /* sign extend */
			if (op1 & 1) { /* imm32 */
				imm <<= 32;
				imm = (s64)imm >> 32;
			} else { /* imm8 */
				imm <<= 56;
				imm = (s64)imm >> 56;
			}
		}

		switch (modrm_reg & 7) {
		case 5:
			imm = -imm;
			/* fallthrough */
		case 0:
			/* add/sub imm, %rsp */
			ADD_OP(op) {
				op->src.type = OP_SRC_ADD;
				op->src.reg = CFI_SP;
				op->src.offset = imm;
				op->dest.type = OP_DEST_REG;
				op->dest.reg = CFI_SP;
			}
			break;

		case 4:
			/* and imm, %rsp */
			ADD_OP(op) {
				op->src.type = OP_SRC_AND;
				op->src.reg = CFI_SP;
				op->src.offset = ins.immediate.value;
				op->dest.type = OP_DEST_REG;
				op->dest.reg = CFI_SP;
			}
			break;

		default:
			/* WARN ? */
			break;
		}

		break;

	case 0x89:
		if (!rex_w)
			break;

		if (modrm_reg == CFI_SP) {

			if (mod_is_reg()) {
				/* mov %rsp, reg */
				ADD_OP(op) {
					op->src.type = OP_SRC_REG;
					op->src.reg = CFI_SP;
					op->dest.type = OP_DEST_REG;
					op->dest.reg = modrm_rm;
				}
				break;

			} else {
				/* skip RIP relative displacement */
				if (is_RIP())
					break;

				/* skip nontrivial SIB */
				if (have_SIB()) {
					modrm_rm = sib_base;
					if (sib_index != CFI_SP)
						break;
				}

				/* mov %rsp, disp(%reg) */
				ADD_OP(op) {
					op->src.type = OP_SRC_REG;
					op->src.reg = CFI_SP;
					op->dest.type = OP_DEST_REG_INDIRECT;
					op->dest.reg = modrm_rm;
					op->dest.offset = ins.displacement.value;
				}
				break;
			}

			break;
		}

		if (rm_is_reg(CFI_SP)) {

			/* mov reg, %rsp */
			ADD_OP(op) {
				op->src.type = OP_SRC_REG;
				op->src.reg = modrm_reg;
				op->dest.type = OP_DEST_REG;
				op->dest.reg = CFI_SP;
			}
			break;
		}

		/* fallthrough */
	case 0x88:
		if (!rex_w)
			break;

		if (rm_is_mem(CFI_BP)) {

			/* mov reg, disp(%rbp) */
			ADD_OP(op) {
				op->src.type = OP_SRC_REG;
				op->src.reg = modrm_reg;
				op->dest.type = OP_DEST_REG_INDIRECT;
				op->dest.reg = CFI_BP;
				op->dest.offset = ins.displacement.value;
			}
			break;
		}

		if (rm_is_mem(CFI_SP)) {

			/* mov reg, disp(%rsp) */
			ADD_OP(op) {
				op->src.type = OP_SRC_REG;
				op->src.reg = modrm_reg;
				op->dest.type = OP_DEST_REG_INDIRECT;
				op->dest.reg = CFI_SP;
				op->dest.offset = ins.displacement.value;
			}
			break;
		}

		break;

	case 0x8b:
		if (!rex_w)
			break;

		if (rm_is_mem(CFI_BP)) {

			/* mov disp(%rbp), reg */
			ADD_OP(op) {
				op->src.type = OP_SRC_REG_INDIRECT;
				op->src.reg = CFI_BP;
				op->src.offset = ins.displacement.value;
				op->dest.type = OP_DEST_REG;
				op->dest.reg = modrm_reg;
			}
			break;
		}

		if (rm_is_mem(CFI_SP)) {

			/* mov disp(%rsp), reg */
			ADD_OP(op) {
				op->src.type = OP_SRC_REG_INDIRECT;
				op->src.reg = CFI_SP;
				op->src.offset = ins.displacement.value;
				op->dest.type = OP_DEST_REG;
				op->dest.reg = modrm_reg;
			}
			break;
		}

		break;

	case 0x8d:
		if (mod_is_reg()) {
			WARN("invalid LEA encoding at %s:0x%lx", sec->name, offset);
			break;
		}

		/* skip non 64bit ops */
		if (!rex_w)
			break;

		/* skip RIP relative displacement */
		if (is_RIP())
			break;

		/* skip nontrivial SIB */
		if (have_SIB()) {
			modrm_rm = sib_base;
			if (sib_index != CFI_SP)
				break;
		}

		/* lea disp(%src), %dst */
		ADD_OP(op) {
			op->src.offset = ins.displacement.value;
			if (!op->src.offset) {
				/* lea (%src), %dst */
				op->src.type = OP_SRC_REG;
			} else {
				/* lea disp(%src), %dst */
				op->src.type = OP_SRC_ADD;
			}
			op->src.reg = modrm_rm;
			op->dest.type = OP_DEST_REG;
			op->dest.reg = modrm_reg;
		}
		break;

	case 0x8f:
		/* pop to mem */
		ADD_OP(op) {
			op->src.type = OP_SRC_POP;
			op->dest.type = OP_DEST_MEM;
		}
		break;

	case 0x90:
		insn->type = INSN_NOP;
		break;

	case 0x9c:
		/* pushf */
		ADD_OP(op) {
			op->src.type = OP_SRC_CONST;
			op->dest.type = OP_DEST_PUSHF;
		}
		break;

	case 0x9d:
		/* popf */
		ADD_OP(op) {
			op->src.type = OP_SRC_POPF;
			op->dest.type = OP_DEST_MEM;
		}
		break;

	case 0x0f:

		if (op2 == 0x01) {

			if (modrm == 0xca)
				insn->type = INSN_CLAC;
			else if (modrm == 0xcb)
				insn->type = INSN_STAC;

		} else if (op2 >= 0x80 && op2 <= 0x8f) {

			insn->type = INSN_JUMP_CONDITIONAL;

		} else if (op2 == 0x05 || op2 == 0x07 || op2 == 0x34 ||
			   op2 == 0x35) {

			/* sysenter, sysret */
			insn->type = INSN_CONTEXT_SWITCH;

		} else if (op2 == 0x0b || op2 == 0xb9) {

			/* ud2 */
			insn->type = INSN_BUG;

		} else if (op2 == 0x0d || op2 == 0x1f) {

			/* nopl/nopw */
			insn->type = INSN_NOP;

		} else if (op2 == 0x1e) {

			if (prefix == 0xf3 && (modrm == 0xfa || modrm == 0xfb))
				insn->type = INSN_ENDBR;


		} else if (op2 == 0x38 && op3 == 0xf8) {
			if (ins.prefixes.nbytes == 1 &&
			    ins.prefixes.bytes[0] == 0xf2) {
				/* ENQCMD cannot be used in the kernel. */
				WARN("ENQCMD instruction at %s:%lx", sec->name,
				     offset);
			}

		} else if (op2 == 0xa0 || op2 == 0xa8) {

			/* push fs/gs */
			ADD_OP(op) {
				op->src.type = OP_SRC_CONST;
				op->dest.type = OP_DEST_PUSH;
			}

		} else if (op2 == 0xa1 || op2 == 0xa9) {

			/* pop fs/gs */
			ADD_OP(op) {
				op->src.type = OP_SRC_POP;
				op->dest.type = OP_DEST_MEM;
			}
		}

		break;

	case 0xc9:
		/*
		 * leave
		 *
		 * equivalent to:
		 * mov bp, sp
		 * pop bp
		 */
		ADD_OP(op) {
			op->src.type = OP_SRC_REG;
			op->src.reg = CFI_BP;
			op->dest.type = OP_DEST_REG;
			op->dest.reg = CFI_SP;
		}
		ADD_OP(op) {
			op->src.type = OP_SRC_POP;
			op->dest.type = OP_DEST_REG;
			op->dest.reg = CFI_BP;
		}
		break;

	case 0xcc:
		/* int3 */
		insn->type = INSN_TRAP;
		break;

	case 0xe3:
		/* jecxz/jrcxz */
		insn->type = INSN_JUMP_CONDITIONAL;
		break;

	case 0xe9:
	case 0xeb:
		insn->type = INSN_JUMP_UNCONDITIONAL;
		break;

	case 0xc2:
	case 0xc3:
		insn->type = INSN_RETURN;
		break;

	case 0xc7: /* mov imm, r/m */
		if (!opts.noinstr)
			break;

		if (ins.length == 3+4+4 && !strncmp(sec->name, ".init.text", 10)) {
			struct reloc *immr, *disp;
			struct symbol *func;
			int idx;

			immr = find_reloc_by_dest(elf, (void *)sec, offset+3);
			disp = find_reloc_by_dest(elf, (void *)sec, offset+7);

			if (!immr || strcmp(immr->sym->name, "pv_ops"))
				break;

			idx = (reloc_addend(immr) + 8) / sizeof(void *);

			func = disp->sym;
			if (disp->sym->type == STT_SECTION)
				func = find_symbol_by_offset(disp->sym->sec, reloc_addend(disp));
			if (!func) {
				WARN("no func for pv_ops[]");
				return -1;
			}

			objtool_pv_add(file, idx, func);
		}

		break;

	case 0xcf: /* iret */
		/*
		 * Handle sync_core(), which has an IRET to self.
		 * All other IRET are in STT_NONE entry code.
		 */
		sym = find_symbol_containing(sec, offset);
		if (sym && sym->type == STT_FUNC) {
			ADD_OP(op) {
				/* add $40, %rsp */
				op->src.type = OP_SRC_ADD;
				op->src.reg = CFI_SP;
				op->src.offset = 5*8;
				op->dest.type = OP_DEST_REG;
				op->dest.reg = CFI_SP;
			}
			break;
		}

		/* fallthrough */

	case 0xca: /* retf */
	case 0xcb: /* retf */
		insn->type = INSN_CONTEXT_SWITCH;
		break;

	case 0xe0: /* loopne */
	case 0xe1: /* loope */
	case 0xe2: /* loop */
		insn->type = INSN_JUMP_CONDITIONAL;
		break;

	case 0xe8:
		insn->type = INSN_CALL;
		/*
		 * For the impact on the stack, a CALL behaves like
		 * a PUSH of an immediate value (the return address).
		 */
		ADD_OP(op) {
			op->src.type = OP_SRC_CONST;
			op->dest.type = OP_DEST_PUSH;
		}
		break;

	case 0xfc:
		insn->type = INSN_CLD;
		break;

	case 0xfd:
		insn->type = INSN_STD;
		break;

	case 0xff:
		if (modrm_reg == 2 || modrm_reg == 3) {

			insn->type = INSN_CALL_DYNAMIC;
			if (has_notrack_prefix(&ins))
				WARN("notrack prefix found at %s:0x%lx", sec->name, offset);

		} else if (modrm_reg == 4) {

			insn->type = INSN_JUMP_DYNAMIC;
			if (has_notrack_prefix(&ins))
				WARN("notrack prefix found at %s:0x%lx", sec->name, offset);

		} else if (modrm_reg == 5) {

			/* jmpf */
			insn->type = INSN_CONTEXT_SWITCH;

		} else if (modrm_reg == 6) {

			/* push from mem */
			ADD_OP(op) {
				op->src.type = OP_SRC_CONST;
				op->dest.type = OP_DEST_PUSH;
			}
		}

		break;

	default:
		break;
	}

	insn->immediate = ins.immediate.nbytes ? ins.immediate.value : 0;

	return 0;
}

void arch_initial_func_cfi_state(struct cfi_init_state *state)
{
	int i;

	for (i = 0; i < CFI_NUM_REGS; i++) {
		state->regs[i].base = CFI_UNDEFINED;
		state->regs[i].offset = 0;
	}

	/* initial CFA (call frame address) */
	state->cfa.base = CFI_SP;
	state->cfa.offset = 8;

	/* initial RA (return address) */
	state->regs[CFI_RA].base = CFI_CFA;
	state->regs[CFI_RA].offset = -8;
}

const char *arch_nop_insn(int len)
{
	static const char nops[5][5] = {
		{ BYTES_NOP1 },
		{ BYTES_NOP2 },
		{ BYTES_NOP3 },
		{ BYTES_NOP4 },
		{ BYTES_NOP5 },
	};

	if (len < 1 || len > 5) {
		WARN("invalid NOP size: %d\n", len);
		return NULL;
	}

	return nops[len-1];
}

#define BYTE_RET	0xC3

const char *arch_ret_insn(int len)
{
	static const char ret[5][5] = {
		{ BYTE_RET },
		{ BYTE_RET, 0xcc },
		{ BYTE_RET, 0xcc, BYTES_NOP1 },
		{ BYTE_RET, 0xcc, BYTES_NOP2 },
		{ BYTE_RET, 0xcc, BYTES_NOP3 },
	};

	if (len < 1 || len > 5) {
		WARN("invalid RET size: %d\n", len);
		return NULL;
	}

	return ret[len-1];
}

int arch_decode_hint_reg(u8 sp_reg, int *base)
{
	switch (sp_reg) {
	case ORC_REG_UNDEFINED:
		*base = CFI_UNDEFINED;
		break;
	case ORC_REG_SP:
		*base = CFI_SP;
		break;
	case ORC_REG_BP:
		*base = CFI_BP;
		break;
	case ORC_REG_SP_INDIRECT:
		*base = CFI_SP_INDIRECT;
		break;
	case ORC_REG_R10:
		*base = CFI_R10;
		break;
	case ORC_REG_R13:
		*base = CFI_R13;
		break;
	case ORC_REG_DI:
		*base = CFI_DI;
		break;
	case ORC_REG_DX:
		*base = CFI_DX;
		break;
	default:
		return -1;
	}

	return 0;
}

bool arch_is_retpoline(struct symbol *sym)
{
	return !strncmp(sym->name, "__x86_indirect_", 15);
}

bool arch_is_rethunk(struct symbol *sym)
{
	return !strcmp(sym->name, "__x86_return_thunk") ||
	       !strcmp(sym->name, "srso_untrain_ret") ||
	       !strcmp(sym->name, "srso_safe_ret") ||
	       !strcmp(sym->name, "__ret");
}
Commit	Line	Data
1ccea77e	1	// SPDX-License-Identifier: GPL-2.0-or-later
442f04c3 JP	2	/*
442f04c3 JP	3	* Copyright (C) 2015 Josh Poimboeuf <jpoimboe@redhat.com>
442f04c3 JP	4	*/
	5
	6	#include <stdio.h>
	7	#include <stdlib.h>
	8
	9	#define unlikely(cond) (cond)
6a77cff8	10	#include <asm/insn.h>
d046b725 JP	11	#include "../../../arch/x86/lib/inat.c"
d046b725 JP	12	#include "../../../arch/x86/lib/insn.c"
442f04c3	13
301cddc2 PZ	14	#define CONFIG_64BIT 1
	15	#include <asm/nops.h>
	16
edea9e6b	17	#include <asm/orc_types.h>
7786032e VG	18	#include <objtool/check.h>
	19	#include <objtool/elf.h>
	20	#include <objtool/arch.h>
	21	#include <objtool/warn.h>
f66c05d6	22	#include <objtool/endianness.h>
db2b0c5d	23	#include <objtool/builtin.h>
9bc0bb50	24	#include <arch/elf.h>
442f04c3	25
4ca993d4 SV	26	int arch_ftrace_match(char *name)
	27	{
	28	return !strcmp(name, "__fentry__");
	29	}
	30
0c98be81	31	static int is_x86_64(const struct elf *elf)
442f04c3 JP	32	{
	33	switch (elf->ehdr.e_machine) {
	34	case EM_X86_64:
	35	return 1;
	36	case EM_386:
	37	return 0;
	38	default:
	39	WARN("unexpected ELF machine type %d", elf->ehdr.e_machine);
	40	return -1;
	41	}
	42	}
	43
baa41469 JP	44	bool arch_callee_saved_reg(unsigned char reg)
	45	{
	46	switch (reg) {
	47	case CFI_BP:
	48	case CFI_BX:
	49	case CFI_R12:
	50	case CFI_R13:
	51	case CFI_R14:
	52	case CFI_R15:
	53	return true;
	54
	55	case CFI_AX:
	56	case CFI_CX:
	57	case CFI_DX:
	58	case CFI_SI:
	59	case CFI_DI:
	60	case CFI_SP:
	61	case CFI_R8:
	62	case CFI_R9:
	63	case CFI_R10:
	64	case CFI_R11:
	65	case CFI_RA:
	66	default:
	67	return false;
	68	}
	69	}
	70
f1974222	71	unsigned long arch_dest_reloc_offset(int addend)
bfb08f22 RG	72	{
	73	return addend + 4;
	74	}
	75
	76	unsigned long arch_jump_destination(struct instruction *insn)
	77	{
	78	return insn->offset + insn->len + insn->immediate;
	79	}
	80
61c6065e PZ	81	bool arch_pc_relative_reloc(struct reloc *reloc)
	82	{
	83	/*
	84	* All relocation types where P (the address of the target)
	85	* is included in the computation.
	86	*/
fcee899d	87	switch (reloc_type(reloc)) {
61c6065e PZ	88	case R_X86_64_PC8:
	89	case R_X86_64_PC16:
	90	case R_X86_64_PC32:
	91	case R_X86_64_PC64:
	92
	93	case R_X86_64_PLT32:
	94	case R_X86_64_GOTPC32:
	95	case R_X86_64_GOTPCREL:
	96	return true;
	97
	98	default:
	99	break;
	100	}
	101
	102	return false;
	103	}
	104
7d989fca PZ	105	#define ADD_OP(op) \
	106	if (!(op = calloc(1, sizeof(*op)))) \
	107	return -1; \
3ee88df1	108	else for (*ops_list = op, ops_list = &op->next; op; op = NULL)
7d989fca	109
78df6245 PZ	110	/*
	111	* Helpers to decode ModRM/SIB:
	112	*
	113	* r/m\| AX CX DX BX \| SP \| BP \| SI DI \|
	114	* \| R8 R9 R10 R11 \| R12 \| R13 \| R14 R15 \|
	115	* Mod+----------------+-----+-----+---------+
	116	* 00 \| [r/m] \|[SIB]\|[IP+]\| [r/m] \|
	117	* 01 \| [r/m + d8] \|[S+d]\| [r/m + d8] \|
	118	* 10 \| [r/m + d32] \|[S+D]\| [r/m + d32] \|
	119	* 11 \| r/ m \|
78df6245	120	*/
36d92e43 PZ	121
	122	#define mod_is_mem() (modrm_mod != 3)
	123	#define mod_is_reg() (modrm_mod == 3)
	124
78df6245	125	#define is_RIP() ((modrm_rm & 7) == CFI_BP && modrm_mod == 0)
36d92e43	126	#define have_SIB() ((modrm_rm & 7) == CFI_SP && mod_is_mem())
78df6245 PZ	127
	128	#define rm_is(reg) (have_SIB() ? \
	129	sib_base == (reg) && sib_index == CFI_SP : \
	130	modrm_rm == (reg))
	131
36d92e43 PZ	132	#define rm_is_mem(reg) (mod_is_mem() && !is_RIP() && rm_is(reg))
	133	#define rm_is_reg(reg) (mod_is_reg() && modrm_rm == (reg))
	134
7d209d13 PZ	135	static bool has_notrack_prefix(struct insn *insn)
	136	{
	137	int i;
	138
	139	for (i = 0; i < insn->prefixes.nbytes; i++) {
	140	if (insn->prefixes.bytes[i] == 0x3e)
	141	return true;
	142	}
	143
	144	return false;
	145	}
	146
db2b0c5d	147	int arch_decode_instruction(struct objtool_file file, const struct section sec,
442f04c3	148	unsigned long offset, unsigned int maxlen,
20a55463	149	struct instruction *insn)
442f04c3	150	{
3ee88df1	151	struct stack_op **ops_list = &insn->stack_ops;
db2b0c5d	152	const struct elf *elf = file->elf;
20a55463	153	struct insn ins;
03b2cd72	154	int x86_64, ret;
7d209d13	155	unsigned char op1, op2, op3, prefix,
2ee0c363 PZ	156	rex = 0, rex_b = 0, rex_r = 0, rex_w = 0, rex_x = 0,
2ee0c363 PZ	157	modrm = 0, modrm_mod = 0, modrm_rm = 0, modrm_reg = 0,
78df6245	158	sib = 0, /* sib_scale = 0, */ sib_index = 0, sib_base = 0;
7d989fca	159	struct stack_op *op = NULL;
b490f453	160	struct symbol *sym;
961d83b9	161	u64 imm;
442f04c3 JP	162
	163	x86_64 = is_x86_64(elf);
	164	if (x86_64 == -1)
	165	return -1;
	166
20a55463	167	ret = insn_decode(&ins, sec->data->d_buf + offset, maxlen,
c7e41b09 BP	168	x86_64 ? INSN_MODE_64 : INSN_MODE_32);
c7e41b09 BP	169	if (ret < 0) {
0c98be81	170	WARN("can't decode instruction at %s:0x%lx", sec->name, offset);
442f04c3 JP	171	return -1;
	172	}
	173
20a55463 PZ	174	insn->len = ins.length;
20a55463 PZ	175	insn->type = INSN_OTHER;
442f04c3	176
20a55463	177	if (ins.vex_prefix.nbytes)
442f04c3 JP	178	return 0;
442f04c3 JP	179
20a55463	180	prefix = ins.prefixes.bytes[0];
7d209d13	181
20a55463 PZ	182	op1 = ins.opcode.bytes[0];
	183	op2 = ins.opcode.bytes[1];
	184	op3 = ins.opcode.bytes[2];
442f04c3	185
20a55463 PZ	186	if (ins.rex_prefix.nbytes) {
20a55463 PZ	187	rex = ins.rex_prefix.bytes[0];
baa41469 JP	188	rex_w = X86_REX_W(rex) >> 3;
baa41469 JP	189	rex_r = X86_REX_R(rex) >> 2;
dd88a0a0	190	rex_x = X86_REX_X(rex) >> 1;
baa41469 JP	191	rex_b = X86_REX_B(rex);
	192	}
	193
20a55463 PZ	194	if (ins.modrm.nbytes) {
20a55463 PZ	195	modrm = ins.modrm.bytes[0];
baa41469	196	modrm_mod = X86_MODRM_MOD(modrm);
16ef7f15 PZ	197	modrm_reg = X86_MODRM_REG(modrm) + 8*rex_r;
16ef7f15 PZ	198	modrm_rm = X86_MODRM_RM(modrm) + 8*rex_b;
baa41469 JP	199	}
baa41469 JP	200
20a55463 PZ	201	if (ins.sib.nbytes) {
20a55463 PZ	202	sib = ins.sib.bytes[0];
78df6245	203	/* sib_scale = X86_SIB_SCALE(sib); */
16ef7f15 PZ	204	sib_index = X86_SIB_INDEX(sib) + 8*rex_x;
16ef7f15 PZ	205	sib_base = X86_SIB_BASE(sib) + 8*rex_b;
16ef7f15	206	}
baa41469	207
442f04c3	208	switch (op1) {
baa41469 JP	209
	210	case 0x1:
	211	case 0x29:
36d92e43	212	if (rex_w && rm_is_reg(CFI_SP)) {
baa41469 JP	213
baa41469 JP	214	/* add/sub reg, %rsp */
7d989fca PZ	215	ADD_OP(op) {
7d989fca PZ	216	op->src.type = OP_SRC_ADD;
16ef7f15	217	op->src.reg = modrm_reg;
7d989fca PZ	218	op->dest.type = OP_DEST_REG;
	219	op->dest.reg = CFI_SP;
	220	}
baa41469 JP	221	}
	222	break;
	223
	224	case 0x50 ... 0x57:
	225
	226	/* push reg */
7d989fca PZ	227	ADD_OP(op) {
7d989fca PZ	228	op->src.type = OP_SRC_REG;
16ef7f15	229	op->src.reg = (op1 & 0x7) + 8*rex_b;
7d989fca PZ	230	op->dest.type = OP_DEST_PUSH;
7d989fca PZ	231	}
baa41469	232
442f04c3 JP	233	break;
442f04c3 JP	234
baa41469 JP	235	case 0x58 ... 0x5f:
	236
	237	/* pop reg */
7d989fca PZ	238	ADD_OP(op) {
	239	op->src.type = OP_SRC_POP;
	240	op->dest.type = OP_DEST_REG;
16ef7f15	241	op->dest.reg = (op1 & 0x7) + 8*rex_b;
7d989fca	242	}
baa41469 JP	243
	244	break;
	245
	246	case 0x68:
	247	case 0x6a:
	248	/* push immediate */
7d989fca PZ	249	ADD_OP(op) {
	250	op->src.type = OP_SRC_CONST;
	251	op->dest.type = OP_DEST_PUSH;
	252	}
442f04c3 JP	253	break;
	254
	255	case 0x70 ... 0x7f:
20a55463	256	insn->type = INSN_JUMP_CONDITIONAL;
442f04c3 JP	257	break;
442f04c3 JP	258
961d83b9 PZ	259	case 0x80 ... 0x83:
	260	/*
	261	* 1000 00sw : mod OP r/m : immediate
	262	*
	263	* s - sign extend immediate
	264	* w - imm8 / imm32
	265	*
	266	* OP: 000 ADD 100 AND
	267	* 001 OR 101 SUB
	268	* 010 ADC 110 XOR
	269	* 011 SBB 111 CMP
	270	*/
	271
	272	/* 64bit only */
	273	if (!rex_w)
	274	break;
	275
	276	/* %rsp target only */
36d92e43	277	if (!rm_is_reg(CFI_SP))
baa41469 JP	278	break;
baa41469 JP	279
20a55463	280	imm = ins.immediate.value;
961d83b9 PZ	281	if (op1 & 2) { /* sign extend */
	282	if (op1 & 1) { /* imm32 */
	283	imm <<= 32;
	284	imm = (s64)imm >> 32;
	285	} else { /* imm8 */
	286	imm <<= 56;
	287	imm = (s64)imm >> 56;
	288	}
	289	}
	290
	291	switch (modrm_reg & 7) {
	292	case 5:
	293	imm = -imm;
	294	/* fallthrough */
	295	case 0:
	296	/* add/sub imm, %rsp */
	297	ADD_OP(op) {
	298	op->src.type = OP_SRC_ADD;
	299	op->src.reg = CFI_SP;
	300	op->src.offset = imm;
	301	op->dest.type = OP_DEST_REG;
	302	op->dest.reg = CFI_SP;
	303	}
	304	break;
	305
	306	case 4:
baa41469	307	/* and imm, %rsp */
7d989fca PZ	308	ADD_OP(op) {
	309	op->src.type = OP_SRC_AND;
	310	op->src.reg = CFI_SP;
20a55463	311	op->src.offset = ins.immediate.value;
7d989fca PZ	312	op->dest.type = OP_DEST_REG;
	313	op->dest.reg = CFI_SP;
	314	}
baa41469	315	break;
baa41469	316
961d83b9 PZ	317	default:
961d83b9 PZ	318	/* WARN ? */
baa41469	319	break;
7d989fca	320	}
961d83b9	321
baa41469 JP	322	break;
baa41469 JP	323
442f04c3	324	case 0x89:
78df6245 PZ	325	if (!rex_w)
	326	break;
	327
	328	if (modrm_reg == CFI_SP) {
2a512829	329
36d92e43	330	if (mod_is_reg()) {
2a512829 PZ	331	/* mov %rsp, reg */
	332	ADD_OP(op) {
	333	op->src.type = OP_SRC_REG;
	334	op->src.reg = CFI_SP;
	335	op->dest.type = OP_DEST_REG;
16ef7f15	336	op->dest.reg = modrm_rm;
2a512829 PZ	337	}
	338	break;
	339
	340	} else {
2a512829	341	/* skip RIP relative displacement */
78df6245	342	if (is_RIP())
2a512829 PZ	343	break;
2a512829 PZ	344
78df6245 PZ	345	/* skip nontrivial SIB */
	346	if (have_SIB()) {
	347	modrm_rm = sib_base;
	348	if (sib_index != CFI_SP)
	349	break;
	350	}
	351
2a512829 PZ	352	/* mov %rsp, disp(%reg) */
	353	ADD_OP(op) {
	354	op->src.type = OP_SRC_REG;
	355	op->src.reg = CFI_SP;
	356	op->dest.type = OP_DEST_REG_INDIRECT;
16ef7f15	357	op->dest.reg = modrm_rm;
20a55463	358	op->dest.offset = ins.displacement.value;
2a512829 PZ	359	}
2a512829 PZ	360	break;
7d989fca	361	}
2a512829	362
baa41469 JP	363	break;
baa41469 JP	364	}
dd88a0a0	365
36d92e43	366	if (rm_is_reg(CFI_SP)) {
dd88a0a0 JP	367
dd88a0a0 JP	368	/* mov reg, %rsp */
7d989fca PZ	369	ADD_OP(op) {
7d989fca PZ	370	op->src.type = OP_SRC_REG;
16ef7f15	371	op->src.reg = modrm_reg;
7d989fca PZ	372	op->dest.type = OP_DEST_REG;
	373	op->dest.reg = CFI_SP;
	374	}
dd88a0a0 JP	375	break;
	376	}
	377
baa41469 JP	378	/* fallthrough */
baa41469 JP	379	case 0x88:
78df6245 PZ	380	if (!rex_w)
	381	break;
	382
36d92e43	383	if (rm_is_mem(CFI_BP)) {
baa41469 JP	384
baa41469 JP	385	/* mov reg, disp(%rbp) */
7d989fca PZ	386	ADD_OP(op) {
7d989fca PZ	387	op->src.type = OP_SRC_REG;
16ef7f15	388	op->src.reg = modrm_reg;
7d989fca PZ	389	op->dest.type = OP_DEST_REG_INDIRECT;
7d989fca PZ	390	op->dest.reg = CFI_BP;
20a55463	391	op->dest.offset = ins.displacement.value;
7d989fca	392	}
2a512829 PZ	393	break;
2a512829 PZ	394	}
baa41469	395
36d92e43	396	if (rm_is_mem(CFI_SP)) {
baa41469 JP	397
baa41469 JP	398	/* mov reg, disp(%rsp) */
7d989fca PZ	399	ADD_OP(op) {
7d989fca PZ	400	op->src.type = OP_SRC_REG;
16ef7f15	401	op->src.reg = modrm_reg;
7d989fca PZ	402	op->dest.type = OP_DEST_REG_INDIRECT;
7d989fca PZ	403	op->dest.reg = CFI_SP;
20a55463	404	op->dest.offset = ins.displacement.value;
7d989fca	405	}
2a512829	406	break;
baa41469 JP	407	}
	408
	409	break;
	410
	411	case 0x8b:
16ef7f15 PZ	412	if (!rex_w)
	413	break;
	414
36d92e43	415	if (rm_is_mem(CFI_BP)) {
baa41469 JP	416
baa41469 JP	417	/* mov disp(%rbp), reg */
7d989fca PZ	418	ADD_OP(op) {
	419	op->src.type = OP_SRC_REG_INDIRECT;
	420	op->src.reg = CFI_BP;
20a55463	421	op->src.offset = ins.displacement.value;
7d989fca	422	op->dest.type = OP_DEST_REG;
16ef7f15	423	op->dest.reg = modrm_reg;
7d989fca	424	}
16ef7f15 PZ	425	break;
16ef7f15 PZ	426	}
baa41469	427
36d92e43	428	if (rm_is_mem(CFI_SP)) {
baa41469 JP	429
baa41469 JP	430	/* mov disp(%rsp), reg */
7d989fca PZ	431	ADD_OP(op) {
	432	op->src.type = OP_SRC_REG_INDIRECT;
	433	op->src.reg = CFI_SP;
20a55463	434	op->src.offset = ins.displacement.value;
7d989fca	435	op->dest.type = OP_DEST_REG;
16ef7f15	436	op->dest.reg = modrm_reg;
7d989fca	437	}
16ef7f15	438	break;
baa41469 JP	439	}
baa41469 JP	440
442f04c3 JP	441	break;
442f04c3 JP	442
2cc17fda	443	case 0x8d:
36d92e43	444	if (mod_is_reg()) {
2ee0c363 PZ	445	WARN("invalid LEA encoding at %s:0x%lx", sec->name, offset);
	446	break;
	447	}
5b8de48e	448
2ee0c363 PZ	449	/* skip non 64bit ops */
	450	if (!rex_w)
	451	break;
baa41469	452
2ee0c363	453	/* skip RIP relative displacement */
78df6245	454	if (is_RIP())
2ee0c363	455	break;
baa41469	456
78df6245 PZ	457	/* skip nontrivial SIB */
	458	if (have_SIB()) {
	459	modrm_rm = sib_base;
	460	if (sib_index != CFI_SP)
	461	break;
	462	}
baa41469	463
2ee0c363 PZ	464	/* lea disp(%src), %dst */
2ee0c363 PZ	465	ADD_OP(op) {
20a55463	466	op->src.offset = ins.displacement.value;
2ee0c363 PZ	467	if (!op->src.offset) {
	468	/* lea (%src), %dst */
	469	op->src.type = OP_SRC_REG;
	470	} else {
	471	/* lea disp(%src), %dst */
7d989fca	472	op->src.type = OP_SRC_ADD;
7d989fca	473	}
16ef7f15	474	op->src.reg = modrm_rm;
2ee0c363	475	op->dest.type = OP_DEST_REG;
16ef7f15	476	op->dest.reg = modrm_reg;
baa41469	477	}
baa41469 JP	478	break;
	479
	480	case 0x8f:
	481	/* pop to mem */
7d989fca PZ	482	ADD_OP(op) {
	483	op->src.type = OP_SRC_POP;
	484	op->dest.type = OP_DEST_MEM;
	485	}
2cc17fda JP	486	break;
2cc17fda JP	487
442f04c3	488	case 0x90:
20a55463	489	insn->type = INSN_NOP;
442f04c3 JP	490	break;
442f04c3 JP	491
baa41469 JP	492	case 0x9c:
baa41469 JP	493	/* pushf */
7d989fca PZ	494	ADD_OP(op) {
	495	op->src.type = OP_SRC_CONST;
	496	op->dest.type = OP_DEST_PUSHF;
	497	}
baa41469 JP	498	break;
	499
	500	case 0x9d:
	501	/* popf */
7d989fca PZ	502	ADD_OP(op) {
	503	op->src.type = OP_SRC_POPF;
	504	op->dest.type = OP_DEST_MEM;
	505	}
baa41469 JP	506	break;
baa41469 JP	507
442f04c3	508	case 0x0f:
baa41469	509
ea24213d PZ	510	if (op2 == 0x01) {
	511
	512	if (modrm == 0xca)
20a55463	513	insn->type = INSN_CLAC;
ea24213d	514	else if (modrm == 0xcb)
20a55463	515	insn->type = INSN_STAC;
ea24213d PZ	516
ea24213d PZ	517	} else if (op2 >= 0x80 && op2 <= 0x8f) {
649ea4d5	518
20a55463	519	insn->type = INSN_JUMP_CONDITIONAL;
649ea4d5 JP	520
	521	} else if (op2 == 0x05 \|\| op2 == 0x07 \|\| op2 == 0x34 \|\|
	522	op2 == 0x35) {
baa41469	523
442f04c3	524	/* sysenter, sysret */
20a55463	525	insn->type = INSN_CONTEXT_SWITCH;
baa41469	526
649ea4d5 JP	527	} else if (op2 == 0x0b \|\| op2 == 0xb9) {
	528
	529	/* ud2 */
20a55463	530	insn->type = INSN_BUG;
649ea4d5 JP	531
649ea4d5 JP	532	} else if (op2 == 0x0d \|\| op2 == 0x1f) {
baa41469	533
442f04c3	534	/* nopl/nopw */
20a55463	535	insn->type = INSN_NOP;
baa41469	536
7d209d13 PZ	537	} else if (op2 == 0x1e) {
	538
	539	if (prefix == 0xf3 && (modrm == 0xfa \|\| modrm == 0xfb))
20a55463	540	insn->type = INSN_ENDBR;
7d209d13 PZ	541
7d209d13 PZ	542
227a0655	543	} else if (op2 == 0x38 && op3 == 0xf8) {
20a55463 PZ	544	if (ins.prefixes.nbytes == 1 &&
20a55463 PZ	545	ins.prefixes.bytes[0] == 0xf2) {
227a0655 FY	546	/* ENQCMD cannot be used in the kernel. */
	547	WARN("ENQCMD instruction at %s:%lx", sec->name,
	548	offset);
	549	}
	550
649ea4d5	551	} else if (op2 == 0xa0 \|\| op2 == 0xa8) {
baa41469 JP	552
baa41469 JP	553	/* push fs/gs */
7d989fca PZ	554	ADD_OP(op) {
	555	op->src.type = OP_SRC_CONST;
	556	op->dest.type = OP_DEST_PUSH;
	557	}
baa41469 JP	558
	559	} else if (op2 == 0xa1 \|\| op2 == 0xa9) {
	560
	561	/* pop fs/gs */
7d989fca PZ	562	ADD_OP(op) {
	563	op->src.type = OP_SRC_POP;
	564	op->dest.type = OP_DEST_MEM;
	565	}
baa41469	566	}
442f04c3 JP	567
	568	break;
	569
baa41469 JP	570	case 0xc9:
	571	/*
	572	* leave
	573	*
	574	* equivalent to:
	575	* mov bp, sp
	576	* pop bp
	577	*/
ffc7e74f PZ	578	ADD_OP(op) {
	579	op->src.type = OP_SRC_REG;
	580	op->src.reg = CFI_BP;
	581	op->dest.type = OP_DEST_REG;
	582	op->dest.reg = CFI_SP;
	583	}
	584	ADD_OP(op) {
	585	op->src.type = OP_SRC_POP;
	586	op->dest.type = OP_DEST_REG;
	587	op->dest.reg = CFI_BP;
	588	}
442f04c3 JP	589	break;
442f04c3 JP	590
1cc1e4c8 PZ	591	case 0xcc:
1cc1e4c8 PZ	592	/* int3 */
20a55463	593	insn->type = INSN_TRAP;
1cc1e4c8 PZ	594	break;
1cc1e4c8 PZ	595
baa41469 JP	596	case 0xe3:
baa41469 JP	597	/* jecxz/jrcxz */
20a55463	598	insn->type = INSN_JUMP_CONDITIONAL;
442f04c3 JP	599	break;
	600
	601	case 0xe9:
	602	case 0xeb:
20a55463	603	insn->type = INSN_JUMP_UNCONDITIONAL;
442f04c3 JP	604	break;
	605
	606	case 0xc2:
	607	case 0xc3:
20a55463	608	insn->type = INSN_RETURN;
442f04c3 JP	609	break;
442f04c3 JP	610
db2b0c5d	611	case 0xc7: /* mov imm, r/m */
2daf7fab	612	if (!opts.noinstr)
db2b0c5d PZ	613	break;
db2b0c5d PZ	614
20a55463	615	if (ins.length == 3+4+4 && !strncmp(sec->name, ".init.text", 10)) {
db2b0c5d PZ	616	struct reloc immr, disp;
	617	struct symbol *func;
	618	int idx;
	619
	620	immr = find_reloc_by_dest(elf, (void *)sec, offset+3);
	621	disp = find_reloc_by_dest(elf, (void *)sec, offset+7);
	622
	623	if (!immr \|\| strcmp(immr->sym->name, "pv_ops"))
	624	break;
	625
0696b6e3	626	idx = (reloc_addend(immr) + 8) / sizeof(void *);
db2b0c5d PZ	627
	628	func = disp->sym;
	629	if (disp->sym->type == STT_SECTION)
0696b6e3	630	func = find_symbol_by_offset(disp->sym->sec, reloc_addend(disp));
db2b0c5d PZ	631	if (!func) {
	632	WARN("no func for pv_ops[]");
	633	return -1;
	634	}
	635
	636	objtool_pv_add(file, idx, func);
	637	}
	638
	639	break;
	640
b7460462	641	case 0xcf: /* iret */
b490f453 MB	642	/*
	643	* Handle sync_core(), which has an IRET to self.
	644	* All other IRET are in STT_NONE entry code.
	645	*/
	646	sym = find_symbol_containing(sec, offset);
	647	if (sym && sym->type == STT_FUNC) {
	648	ADD_OP(op) {
	649	/* add $40, %rsp */
	650	op->src.type = OP_SRC_ADD;
	651	op->src.reg = CFI_SP;
	652	op->src.offset = 5*8;
	653	op->dest.type = OP_DEST_REG;
	654	op->dest.reg = CFI_SP;
	655	}
	656	break;
7d989fca	657	}
b490f453 MB	658
b490f453 MB	659	/* fallthrough */
b7460462	660
442f04c3 JP	661	case 0xca: /* retf */
442f04c3 JP	662	case 0xcb: /* retf */
20a55463	663	insn->type = INSN_CONTEXT_SWITCH;
442f04c3 JP	664	break;
442f04c3 JP	665
7a7621df PZ	666	case 0xe0: /* loopne */
	667	case 0xe1: /* loope */
	668	case 0xe2: /* loop */
20a55463	669	insn->type = INSN_JUMP_CONDITIONAL;
7a7621df PZ	670	break;
7a7621df PZ	671
442f04c3	672	case 0xe8:
20a55463	673	insn->type = INSN_CALL;
8aa8eb2a AC	674	/*
	675	* For the impact on the stack, a CALL behaves like
	676	* a PUSH of an immediate value (the return address).
	677	*/
	678	ADD_OP(op) {
	679	op->src.type = OP_SRC_CONST;
	680	op->dest.type = OP_DEST_PUSH;
	681	}
442f04c3 JP	682	break;
442f04c3 JP	683
2f0f9e9a	684	case 0xfc:
20a55463	685	insn->type = INSN_CLD;
2f0f9e9a PZ	686	break;
	687
	688	case 0xfd:
20a55463	689	insn->type = INSN_STD;
2f0f9e9a PZ	690	break;
2f0f9e9a PZ	691
442f04c3	692	case 0xff:
7d209d13	693	if (modrm_reg == 2 \|\| modrm_reg == 3) {
baa41469	694
20a55463 PZ	695	insn->type = INSN_CALL_DYNAMIC;
20a55463 PZ	696	if (has_notrack_prefix(&ins))
7d209d13	697	WARN("notrack prefix found at %s:0x%lx", sec->name, offset);
baa41469	698
7d209d13	699	} else if (modrm_reg == 4) {
baa41469	700
20a55463 PZ	701	insn->type = INSN_JUMP_DYNAMIC;
20a55463 PZ	702	if (has_notrack_prefix(&ins))
7d209d13	703	WARN("notrack prefix found at %s:0x%lx", sec->name, offset);
baa41469	704
7d209d13	705	} else if (modrm_reg == 5) {
baa41469 JP	706
baa41469 JP	707	/* jmpf */
20a55463	708	insn->type = INSN_CONTEXT_SWITCH;
442f04c3	709
7d209d13	710	} else if (modrm_reg == 6) {
baa41469 JP	711
baa41469 JP	712	/* push from mem */
7d989fca PZ	713	ADD_OP(op) {
	714	op->src.type = OP_SRC_CONST;
	715	op->dest.type = OP_DEST_PUSH;
	716	}
baa41469 JP	717	}
baa41469 JP	718
442f04c3 JP	719	break;
	720
	721	default:
	722	break;
	723	}
	724
20a55463	725	insn->immediate = ins.immediate.nbytes ? ins.immediate.value : 0;
442f04c3 JP	726
	727	return 0;
	728	}
baa41469	729
a3608f59	730	void arch_initial_func_cfi_state(struct cfi_init_state *state)
baa41469 JP	731	{
	732	int i;
	733
	734	for (i = 0; i < CFI_NUM_REGS; i++) {
	735	state->regs[i].base = CFI_UNDEFINED;
	736	state->regs[i].offset = 0;
	737	}
	738
	739	/* initial CFA (call frame address) */
	740	state->cfa.base = CFI_SP;
	741	state->cfa.offset = 8;
	742
	743	/* initial RA (return address) */
b735bd3e JP	744	state->regs[CFI_RA].base = CFI_CFA;
b735bd3e JP	745	state->regs[CFI_RA].offset = -8;
baa41469	746	}
0f1441b4 PZ	747
	748	const char *arch_nop_insn(int len)
	749	{
	750	static const char nops[5][5] = {
301cddc2 PZ	751	{ BYTES_NOP1 },
	752	{ BYTES_NOP2 },
	753	{ BYTES_NOP3 },
	754	{ BYTES_NOP4 },
	755	{ BYTES_NOP5 },
0f1441b4 PZ	756	};
	757
	758	if (len < 1 \|\| len > 5) {
	759	WARN("invalid NOP size: %d\n", len);
	760	return NULL;
	761	}
	762
	763	return nops[len-1];
	764	}
edea9e6b	765
f56dae88 PZ	766	#define BYTE_RET 0xC3
	767
	768	const char *arch_ret_insn(int len)
	769	{
	770	static const char ret[5][5] = {
	771	{ BYTE_RET },
1cc1e4c8 PZ	772	{ BYTE_RET, 0xcc },
	773	{ BYTE_RET, 0xcc, BYTES_NOP1 },
	774	{ BYTE_RET, 0xcc, BYTES_NOP2 },
	775	{ BYTE_RET, 0xcc, BYTES_NOP3 },
f56dae88 PZ	776	};
	777
	778	if (len < 1 \|\| len > 5) {
	779	WARN("invalid RET size: %d\n", len);
	780	return NULL;
	781	}
	782
	783	return ret[len-1];
	784	}
	785
8b946cc3	786	int arch_decode_hint_reg(u8 sp_reg, int *base)
edea9e6b	787	{
edea9e6b JT	788	switch (sp_reg) {
edea9e6b JT	789	case ORC_REG_UNDEFINED:
8b946cc3	790	*base = CFI_UNDEFINED;
edea9e6b JT	791	break;
edea9e6b JT	792	case ORC_REG_SP:
8b946cc3	793	*base = CFI_SP;
edea9e6b JT	794	break;
edea9e6b JT	795	case ORC_REG_BP:
8b946cc3	796	*base = CFI_BP;
edea9e6b JT	797	break;
edea9e6b JT	798	case ORC_REG_SP_INDIRECT:
8b946cc3	799	*base = CFI_SP_INDIRECT;
edea9e6b JT	800	break;
edea9e6b JT	801	case ORC_REG_R10:
8b946cc3	802	*base = CFI_R10;
edea9e6b JT	803	break;
edea9e6b JT	804	case ORC_REG_R13:
8b946cc3	805	*base = CFI_R13;
edea9e6b JT	806	break;
edea9e6b JT	807	case ORC_REG_DI:
8b946cc3	808	*base = CFI_DI;
edea9e6b JT	809	break;
edea9e6b JT	810	case ORC_REG_DX:
8b946cc3	811	*base = CFI_DX;
edea9e6b JT	812	break;
	813	default:
	814	return -1;
	815	}
	816
	817	return 0;
	818	}
530b4ddd PZ	819
	820	bool arch_is_retpoline(struct symbol *sym)
	821	{
	822	return !strncmp(sym->name, "__x86_indirect_", 15);
	823	}
d9e9d230 PZ	824
	825	bool arch_is_rethunk(struct symbol *sym)
	826	{
fb3bd914 BPA	827	return !strcmp(sym->name, "__x86_return_thunk") \|\|
	828	!strcmp(sym->name, "srso_untrain_ret") \|\|
	829	!strcmp(sym->name, "srso_safe_ret") \|\|
	830	!strcmp(sym->name, "__ret");
d9e9d230	831	}