projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 444e2ff3 ACM |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | #ifndef _ASM_X86_MSR_INDEX_H | |
| 3 | #define _ASM_X86_MSR_INDEX_H | |
| 4 | ||
| 5 | #include <linux/bits.h> | |
| 6 | ||
| a66558dc | 7 | /* CPU model specific register (MSR) numbers. */ |
| 444e2ff3 ACM |
8 | |
| 9 | /* x86-64 specific MSRs */ | |
| 10 | #define MSR_EFER 0xc0000080 /* extended feature register */ | |
| 11 | #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ | |
| 12 | #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ | |
| 13 | #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ | |
| 14 | #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ | |
| 15 | #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ | |
| 16 | #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ | |
| 17 | #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ | |
| 18 | #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ | |
| 19 | ||
| 20 | /* EFER bits: */ | |
| 21 | #define _EFER_SCE 0 /* SYSCALL/SYSRET */ | |
| 22 | #define _EFER_LME 8 /* Long mode enable */ | |
| 23 | #define _EFER_LMA 10 /* Long mode active (read-only) */ | |
| 24 | #define _EFER_NX 11 /* No execute enable */ | |
| 25 | #define _EFER_SVME 12 /* Enable virtualization */ | |
| 26 | #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ | |
| 27 | #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ | |
| 3ee7cb4f | 28 | #define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ |
| 444e2ff3 ACM |
29 | |
| 30 | #define EFER_SCE (1<<_EFER_SCE) | |
| 31 | #define EFER_LME (1<<_EFER_LME) | |
| 32 | #define EFER_LMA (1<<_EFER_LMA) | |
| 33 | #define EFER_NX (1<<_EFER_NX) | |
| 34 | #define EFER_SVME (1<<_EFER_SVME) | |
| 35 | #define EFER_LMSLE (1<<_EFER_LMSLE) | |
| 36 | #define EFER_FFXSR (1<<_EFER_FFXSR) | |
| 3ee7cb4f | 37 | #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) |
| 444e2ff3 ACM |
38 | |
| 39 | /* Intel MSRs. Some also available on other CPUs */ | |
| 40 | ||
| bab1a501 ACM |
41 | #define MSR_TEST_CTRL 0x00000033 |
| 42 | #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 | |
| 43 | #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) | |
| 44 | ||
| 444e2ff3 ACM |
45 | #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ |
| 46 | #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ | |
| 47 | #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ | |
| 48 | #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ | |
| 49 | #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ | |
| 50 | #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ | |
| 4ad3278d PG |
51 | #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ |
| 52 | #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) | |
| 444e2ff3 | 53 | |
| 3ee7cb4f ACM |
54 | /* A mask for bits which the kernel toggles when controlling mitigations */ |
| 55 | #define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ | |
| 56 | | SPEC_CTRL_RRSBA_DIS_S) | |
| 57 | ||
| 444e2ff3 ACM |
58 | #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ |
| 59 | #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ | |
| 60 | ||
| 61 | #define MSR_PPIN_CTL 0x0000004e | |
| 62 | #define MSR_PPIN 0x0000004f | |
| 63 | ||
| 64 | #define MSR_IA32_PERFCTR0 0x000000c1 | |
| 65 | #define MSR_IA32_PERFCTR1 0x000000c2 | |
| 66 | #define MSR_FSB_FREQ 0x000000cd | |
| 67 | #define MSR_PLATFORM_INFO 0x000000ce | |
| 68 | #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 | |
| 69 | #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) | |
| 70 | ||
| 71 | #define MSR_IA32_UMWAIT_CONTROL 0xe1 | |
| 72 | #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) | |
| 73 | #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) | |
| 74 | /* | |
| 75 | * The time field is bit[31:2], but representing a 32bit value with | |
| 76 | * bit[1:0] zero. | |
| 77 | */ | |
| 78 | #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) | |
| 79 | ||
| bab1a501 ACM |
80 | /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ |
| 81 | #define MSR_IA32_CORE_CAPS 0x000000cf | |
| 9dde6cad ACM |
82 | #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2 |
| 83 | #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT) | |
| bab1a501 ACM |
84 | #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 |
| 85 | #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) | |
| 86 | ||
| 444e2ff3 ACM |
87 | #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 |
| 88 | #define NHM_C3_AUTO_DEMOTE (1UL << 25) | |
| 89 | #define NHM_C1_AUTO_DEMOTE (1UL << 26) | |
| 90 | #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) | |
| 91 | #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) | |
| 92 | #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) | |
| 93 | ||
| 94 | #define MSR_MTRRcap 0x000000fe | |
| 95 | ||
| 96 | #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a | |
| 97 | #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ | |
| 98 | #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ | |
| 91d248c3 | 99 | #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ |
| 444e2ff3 ACM |
100 | #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ |
| 101 | #define ARCH_CAP_SSB_NO BIT(4) /* | |
| 102 | * Not susceptible to Speculative Store Bypass | |
| 103 | * attack, so no Speculative Store Bypass | |
| 104 | * control required. | |
| 105 | */ | |
| 106 | #define ARCH_CAP_MDS_NO BIT(5) /* | |
| 107 | * Not susceptible to | |
| 108 | * Microarchitectural Data | |
| 109 | * Sampling (MDS) vulnerabilities. | |
| 110 | */ | |
| 8122b047 ACM |
111 | #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* |
| 112 | * The processor is not susceptible to a | |
| 113 | * machine check error due to modifying the | |
| 114 | * code page size along with either the | |
| 115 | * physical address or cache type | |
| 116 | * without TLB invalidation. | |
| 117 | */ | |
| 118 | #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ | |
| 119 | #define ARCH_CAP_TAA_NO BIT(8) /* | |
| 120 | * Not susceptible to | |
| 121 | * TSX Async Abort (TAA) vulnerabilities. | |
| 122 | */ | |
| 51802186 PG |
123 | #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* |
| 124 | * Not susceptible to SBDR and SSDP | |
| 125 | * variants of Processor MMIO stale data | |
| 126 | * vulnerabilities. | |
| 127 | */ | |
| 128 | #define ARCH_CAP_FBSDP_NO BIT(14) /* | |
| 129 | * Not susceptible to FBSDP variant of | |
| 130 | * Processor MMIO stale data | |
| 131 | * vulnerabilities. | |
| 132 | */ | |
| 133 | #define ARCH_CAP_PSDP_NO BIT(15) /* | |
| 134 | * Not susceptible to PSDP variant of | |
| 135 | * Processor MMIO stale data | |
| 136 | * vulnerabilities. | |
| 137 | */ | |
| 138 | #define ARCH_CAP_FB_CLEAR BIT(17) /* | |
| 139 | * VERW clears CPU fill buffer | |
| 140 | * even on MDS_NO CPUs. | |
| 141 | */ | |
| 027bbb88 PG |
142 | #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* |
| 143 | * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] | |
| 144 | * bit available to control VERW | |
| 145 | * behavior. | |
| 146 | */ | |
| 4ad3278d PG |
147 | #define ARCH_CAP_RRSBA BIT(19) /* |
| 148 | * Indicates RET may use predictors | |
| 149 | * other than the RSB. With eIBRS | |
| 150 | * enabled predictions in kernel mode | |
| 151 | * are restricted to targets in | |
| 152 | * kernel. | |
| 153 | */ | |
| 2b129932 DS |
154 | #define ARCH_CAP_PBRSB_NO BIT(24) /* |
| 155 | * Not susceptible to Post-Barrier | |
| 156 | * Return Stack Buffer Predictions. | |
| 157 | */ | |
| 444e2ff3 | 158 | |
| a3a36565 ACM |
159 | #define ARCH_CAP_XAPIC_DISABLE BIT(21) /* |
| 160 | * IA32_XAPIC_DISABLE_STATUS MSR | |
| 161 | * supported | |
| 162 | */ | |
| 163 | ||
| 444e2ff3 ACM |
164 | #define MSR_IA32_FLUSH_CMD 0x0000010b |
| 165 | #define L1D_FLUSH BIT(0) /* | |
| 166 | * Writeback and invalidate the | |
| 167 | * L1 data cache. | |
| 168 | */ | |
| 169 | ||
| 170 | #define MSR_IA32_BBL_CR_CTL 0x00000119 | |
| 171 | #define MSR_IA32_BBL_CR_CTL3 0x0000011e | |
| 172 | ||
| 8122b047 ACM |
173 | #define MSR_IA32_TSX_CTRL 0x00000122 |
| 174 | #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ | |
| 175 | #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ | |
| 176 | ||
| 25ca7e5c | 177 | #define MSR_IA32_MCU_OPT_CTRL 0x00000123 |
| 400331f8 PG |
178 | #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ |
| 179 | #define RTM_ALLOW BIT(1) /* TSX development mode */ | |
| 027bbb88 | 180 | #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ |
| 25ca7e5c | 181 | |
| 444e2ff3 ACM |
182 | #define MSR_IA32_SYSENTER_CS 0x00000174 |
| 183 | #define MSR_IA32_SYSENTER_ESP 0x00000175 | |
| 184 | #define MSR_IA32_SYSENTER_EIP 0x00000176 | |
| 185 | ||
| 186 | #define MSR_IA32_MCG_CAP 0x00000179 | |
| 187 | #define MSR_IA32_MCG_STATUS 0x0000017a | |
| 188 | #define MSR_IA32_MCG_CTL 0x0000017b | |
| e9bde94f | 189 | #define MSR_ERROR_CONTROL 0x0000017f |
| 444e2ff3 ACM |
190 | #define MSR_IA32_MCG_EXT_CTL 0x000004d0 |
| 191 | ||
| 192 | #define MSR_OFFCORE_RSP_0 0x000001a6 | |
| 193 | #define MSR_OFFCORE_RSP_1 0x000001a7 | |
| 194 | #define MSR_TURBO_RATIO_LIMIT 0x000001ad | |
| 195 | #define MSR_TURBO_RATIO_LIMIT1 0x000001ae | |
| 196 | #define MSR_TURBO_RATIO_LIMIT2 0x000001af | |
| 197 | ||
| 3ee7cb4f ACM |
198 | #define MSR_SNOOP_RSP_0 0x00001328 |
| 199 | #define MSR_SNOOP_RSP_1 0x00001329 | |
| 200 | ||
| 444e2ff3 ACM |
201 | #define MSR_LBR_SELECT 0x000001c8 |
| 202 | #define MSR_LBR_TOS 0x000001c9 | |
| f815fe51 ACM |
203 | |
| 204 | #define MSR_IA32_POWER_CTL 0x000001fc | |
| 205 | #define MSR_IA32_POWER_CTL_BIT_EE 19 | |
| 206 | ||
| 9dde6cad ACM |
207 | /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ |
| 208 | #define MSR_INTEGRITY_CAPS 0x000002d9 | |
| 34e82891 YS |
209 | #define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2 |
| 210 | #define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT) | |
| 9dde6cad ACM |
211 | #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 |
| 212 | #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) | |
| 213 | ||
| 444e2ff3 ACM |
214 | #define MSR_LBR_NHM_FROM 0x00000680 |
| 215 | #define MSR_LBR_NHM_TO 0x000006c0 | |
| 216 | #define MSR_LBR_CORE_FROM 0x00000040 | |
| 217 | #define MSR_LBR_CORE_TO 0x00000060 | |
| 218 | ||
| 219 | #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ | |
| 220 | #define LBR_INFO_MISPRED BIT_ULL(63) | |
| 221 | #define LBR_INFO_IN_TX BIT_ULL(62) | |
| 222 | #define LBR_INFO_ABORT BIT_ULL(61) | |
| f815fe51 | 223 | #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) |
| 444e2ff3 | 224 | #define LBR_INFO_CYCLES 0xffff |
| f815fe51 ACM |
225 | #define LBR_INFO_BR_TYPE_OFFSET 56 |
| 226 | #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) | |
| 227 | ||
| 228 | #define MSR_ARCH_LBR_CTL 0x000014ce | |
| 229 | #define ARCH_LBR_CTL_LBREN BIT(0) | |
| 230 | #define ARCH_LBR_CTL_CPL_OFFSET 1 | |
| 231 | #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) | |
| 232 | #define ARCH_LBR_CTL_STACK_OFFSET 3 | |
| 233 | #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) | |
| 234 | #define ARCH_LBR_CTL_FILTER_OFFSET 16 | |
| 235 | #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) | |
| 236 | #define MSR_ARCH_LBR_DEPTH 0x000014cf | |
| 237 | #define MSR_ARCH_LBR_FROM_0 0x00001500 | |
| 238 | #define MSR_ARCH_LBR_TO_0 0x00001600 | |
| 239 | #define MSR_ARCH_LBR_INFO_0 0x00001200 | |
| 444e2ff3 ACM |
240 | |
| 241 | #define MSR_IA32_PEBS_ENABLE 0x000003f1 | |
| 242 | #define MSR_PEBS_DATA_CFG 0x000003f2 | |
| 243 | #define MSR_IA32_DS_AREA 0x00000600 | |
| 244 | #define MSR_IA32_PERF_CAPABILITIES 0x00000345 | |
| b3172585 ACM |
245 | #define PERF_CAP_METRICS_IDX 15 |
| 246 | #define PERF_CAP_PT_IDX 16 | |
| 247 | ||
| 444e2ff3 | 248 | #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 |
| 7f7f86a7 ACM |
249 | #define PERF_CAP_PEBS_TRAP BIT_ULL(6) |
| 250 | #define PERF_CAP_ARCH_REG BIT_ULL(7) | |
| 251 | #define PERF_CAP_PEBS_FORMAT 0xf00 | |
| 252 | #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) | |
| 253 | #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ | |
| 254 | PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) | |
| 444e2ff3 ACM |
255 | |
| 256 | #define MSR_IA32_RTIT_CTL 0x00000570 | |
| 257 | #define RTIT_CTL_TRACEEN BIT(0) | |
| 258 | #define RTIT_CTL_CYCLEACC BIT(1) | |
| 259 | #define RTIT_CTL_OS BIT(2) | |
| 260 | #define RTIT_CTL_USR BIT(3) | |
| 261 | #define RTIT_CTL_PWR_EVT_EN BIT(4) | |
| 262 | #define RTIT_CTL_FUP_ON_PTW BIT(5) | |
| 263 | #define RTIT_CTL_FABRIC_EN BIT(6) | |
| 264 | #define RTIT_CTL_CR3EN BIT(7) | |
| 265 | #define RTIT_CTL_TOPA BIT(8) | |
| 266 | #define RTIT_CTL_MTC_EN BIT(9) | |
| 267 | #define RTIT_CTL_TSC_EN BIT(10) | |
| 268 | #define RTIT_CTL_DISRETC BIT(11) | |
| 269 | #define RTIT_CTL_PTW_EN BIT(12) | |
| 270 | #define RTIT_CTL_BRANCH_EN BIT(13) | |
| 672b259f ACM |
271 | #define RTIT_CTL_EVENT_EN BIT(31) |
| 272 | #define RTIT_CTL_NOTNT BIT_ULL(55) | |
| 444e2ff3 ACM |
273 | #define RTIT_CTL_MTC_RANGE_OFFSET 14 |
| 274 | #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) | |
| 275 | #define RTIT_CTL_CYC_THRESH_OFFSET 19 | |
| 276 | #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) | |
| 277 | #define RTIT_CTL_PSB_FREQ_OFFSET 24 | |
| 278 | #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) | |
| 279 | #define RTIT_CTL_ADDR0_OFFSET 32 | |
| 280 | #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) | |
| 281 | #define RTIT_CTL_ADDR1_OFFSET 36 | |
| 282 | #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) | |
| 283 | #define RTIT_CTL_ADDR2_OFFSET 40 | |
| 284 | #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) | |
| 285 | #define RTIT_CTL_ADDR3_OFFSET 44 | |
| 286 | #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) | |
| 287 | #define MSR_IA32_RTIT_STATUS 0x00000571 | |
| 288 | #define RTIT_STATUS_FILTEREN BIT(0) | |
| 289 | #define RTIT_STATUS_CONTEXTEN BIT(1) | |
| 290 | #define RTIT_STATUS_TRIGGEREN BIT(2) | |
| 291 | #define RTIT_STATUS_BUFFOVF BIT(3) | |
| 292 | #define RTIT_STATUS_ERROR BIT(4) | |
| 293 | #define RTIT_STATUS_STOPPED BIT(5) | |
| 294 | #define RTIT_STATUS_BYTECNT_OFFSET 32 | |
| 295 | #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) | |
| 296 | #define MSR_IA32_RTIT_ADDR0_A 0x00000580 | |
| 297 | #define MSR_IA32_RTIT_ADDR0_B 0x00000581 | |
| 298 | #define MSR_IA32_RTIT_ADDR1_A 0x00000582 | |
| 299 | #define MSR_IA32_RTIT_ADDR1_B 0x00000583 | |
| 300 | #define MSR_IA32_RTIT_ADDR2_A 0x00000584 | |
| 301 | #define MSR_IA32_RTIT_ADDR2_B 0x00000585 | |
| 302 | #define MSR_IA32_RTIT_ADDR3_A 0x00000586 | |
| 303 | #define MSR_IA32_RTIT_ADDR3_B 0x00000587 | |
| 304 | #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 | |
| 305 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 | |
| 306 | #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 | |
| 307 | ||
| 308 | #define MSR_MTRRfix64K_00000 0x00000250 | |
| 309 | #define MSR_MTRRfix16K_80000 0x00000258 | |
| 310 | #define MSR_MTRRfix16K_A0000 0x00000259 | |
| 311 | #define MSR_MTRRfix4K_C0000 0x00000268 | |
| 312 | #define MSR_MTRRfix4K_C8000 0x00000269 | |
| 313 | #define MSR_MTRRfix4K_D0000 0x0000026a | |
| 314 | #define MSR_MTRRfix4K_D8000 0x0000026b | |
| 315 | #define MSR_MTRRfix4K_E0000 0x0000026c | |
| 316 | #define MSR_MTRRfix4K_E8000 0x0000026d | |
| 317 | #define MSR_MTRRfix4K_F0000 0x0000026e | |
| 318 | #define MSR_MTRRfix4K_F8000 0x0000026f | |
| 319 | #define MSR_MTRRdefType 0x000002ff | |
| 320 | ||
| 321 | #define MSR_IA32_CR_PAT 0x00000277 | |
| 322 | ||
| 323 | #define MSR_IA32_DEBUGCTLMSR 0x000001d9 | |
| 324 | #define MSR_IA32_LASTBRANCHFROMIP 0x000001db | |
| 325 | #define MSR_IA32_LASTBRANCHTOIP 0x000001dc | |
| 326 | #define MSR_IA32_LASTINTFROMIP 0x000001dd | |
| 327 | #define MSR_IA32_LASTINTTOIP 0x000001de | |
| 328 | ||
| 32b734e0 ACM |
329 | #define MSR_IA32_PASID 0x00000d93 |
| 330 | #define MSR_IA32_PASID_VALID BIT_ULL(31) | |
| 331 | ||
| 444e2ff3 ACM |
332 | /* DEBUGCTLMSR bits (others vary by model): */ |
| 333 | #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ | |
| 334 | #define DEBUGCTLMSR_BTF_SHIFT 1 | |
| 335 | #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ | |
| b3172585 | 336 | #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) |
| 444e2ff3 ACM |
337 | #define DEBUGCTLMSR_TR (1UL << 6) |
| 338 | #define DEBUGCTLMSR_BTS (1UL << 7) | |
| 339 | #define DEBUGCTLMSR_BTINT (1UL << 8) | |
| 340 | #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) | |
| 341 | #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) | |
| 342 | #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) | |
| 343 | #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) | |
| 344 | #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 | |
| 345 | #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) | |
| 346 | ||
| 347 | #define MSR_PEBS_FRONTEND 0x000003f7 | |
| 348 | ||
| 444e2ff3 ACM |
349 | #define MSR_IA32_MC0_CTL 0x00000400 |
| 350 | #define MSR_IA32_MC0_STATUS 0x00000401 | |
| 351 | #define MSR_IA32_MC0_ADDR 0x00000402 | |
| 352 | #define MSR_IA32_MC0_MISC 0x00000403 | |
| 353 | ||
| 354 | /* C-state Residency Counters */ | |
| 355 | #define MSR_PKG_C3_RESIDENCY 0x000003f8 | |
| 356 | #define MSR_PKG_C6_RESIDENCY 0x000003f9 | |
| 357 | #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa | |
| 358 | #define MSR_PKG_C7_RESIDENCY 0x000003fa | |
| 359 | #define MSR_CORE_C3_RESIDENCY 0x000003fc | |
| 360 | #define MSR_CORE_C6_RESIDENCY 0x000003fd | |
| 361 | #define MSR_CORE_C7_RESIDENCY 0x000003fe | |
| 362 | #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff | |
| 363 | #define MSR_PKG_C2_RESIDENCY 0x0000060d | |
| 364 | #define MSR_PKG_C8_RESIDENCY 0x00000630 | |
| 365 | #define MSR_PKG_C9_RESIDENCY 0x00000631 | |
| 366 | #define MSR_PKG_C10_RESIDENCY 0x00000632 | |
| 367 | ||
| 368 | /* Interrupt Response Limit */ | |
| 369 | #define MSR_PKGC3_IRTL 0x0000060a | |
| 370 | #define MSR_PKGC6_IRTL 0x0000060b | |
| 371 | #define MSR_PKGC7_IRTL 0x0000060c | |
| 372 | #define MSR_PKGC8_IRTL 0x00000633 | |
| 373 | #define MSR_PKGC9_IRTL 0x00000634 | |
| 374 | #define MSR_PKGC10_IRTL 0x00000635 | |
| 375 | ||
| 376 | /* Run Time Average Power Limiting (RAPL) Interface */ | |
| 377 | ||
| 9dde6cad | 378 | #define MSR_VR_CURRENT_CONFIG 0x00000601 |
| 444e2ff3 ACM |
379 | #define MSR_RAPL_POWER_UNIT 0x00000606 |
| 380 | ||
| 381 | #define MSR_PKG_POWER_LIMIT 0x00000610 | |
| 382 | #define MSR_PKG_ENERGY_STATUS 0x00000611 | |
| 383 | #define MSR_PKG_PERF_STATUS 0x00000613 | |
| 384 | #define MSR_PKG_POWER_INFO 0x00000614 | |
| 385 | ||
| 386 | #define MSR_DRAM_POWER_LIMIT 0x00000618 | |
| 387 | #define MSR_DRAM_ENERGY_STATUS 0x00000619 | |
| 388 | #define MSR_DRAM_PERF_STATUS 0x0000061b | |
| 389 | #define MSR_DRAM_POWER_INFO 0x0000061c | |
| 390 | ||
| 391 | #define MSR_PP0_POWER_LIMIT 0x00000638 | |
| 392 | #define MSR_PP0_ENERGY_STATUS 0x00000639 | |
| 393 | #define MSR_PP0_POLICY 0x0000063a | |
| 394 | #define MSR_PP0_PERF_STATUS 0x0000063b | |
| 395 | ||
| 396 | #define MSR_PP1_POWER_LIMIT 0x00000640 | |
| 397 | #define MSR_PP1_ENERGY_STATUS 0x00000641 | |
| 398 | #define MSR_PP1_POLICY 0x00000642 | |
| 399 | ||
| 3b1f47d6 | 400 | #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 |
| e9bde94f ACM |
401 | #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a |
| 402 | #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b | |
| 3b1f47d6 | 403 | |
| 444e2ff3 ACM |
404 | /* Config TDP MSRs */ |
| 405 | #define MSR_CONFIG_TDP_NOMINAL 0x00000648 | |
| 406 | #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 | |
| 407 | #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A | |
| 408 | #define MSR_CONFIG_TDP_CONTROL 0x0000064B | |
| 409 | #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C | |
| 410 | ||
| 411 | #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D | |
| 7f7f86a7 | 412 | #define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650 |
| 444e2ff3 ACM |
413 | |
| 414 | #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 | |
| 415 | #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 | |
| 416 | #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A | |
| 417 | #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B | |
| 418 | ||
| 419 | #define MSR_CORE_C1_RES 0x00000660 | |
| 420 | #define MSR_MODULE_C6_RES_MS 0x00000664 | |
| 421 | ||
| 422 | #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 | |
| 423 | #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 | |
| 424 | ||
| 425 | #define MSR_ATOM_CORE_RATIOS 0x0000066a | |
| 426 | #define MSR_ATOM_CORE_VIDS 0x0000066b | |
| 427 | #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c | |
| 428 | #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d | |
| 429 | ||
| 444e2ff3 ACM |
430 | #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 |
| 431 | #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 | |
| 432 | #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 | |
| 433 | ||
| 672b259f ACM |
434 | /* Control-flow Enforcement Technology MSRs */ |
| 435 | #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ | |
| 436 | #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ | |
| 437 | #define CET_SHSTK_EN BIT_ULL(0) | |
| 438 | #define CET_WRSS_EN BIT_ULL(1) | |
| 439 | #define CET_ENDBR_EN BIT_ULL(2) | |
| 440 | #define CET_LEG_IW_EN BIT_ULL(3) | |
| 441 | #define CET_NO_TRACK_EN BIT_ULL(4) | |
| 442 | #define CET_SUPPRESS_DISABLE BIT_ULL(5) | |
| 443 | #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) | |
| 444 | #define CET_SUPPRESS BIT_ULL(10) | |
| 445 | #define CET_WAIT_ENDBR BIT_ULL(11) | |
| 446 | ||
| 447 | #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ | |
| 448 | #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ | |
| 449 | #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ | |
| 450 | #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ | |
| 451 | #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ | |
| 452 | ||
| 444e2ff3 ACM |
453 | /* Hardware P state interface */ |
| 454 | #define MSR_PPERF 0x0000064e | |
| 455 | #define MSR_PERF_LIMIT_REASONS 0x0000064f | |
| 456 | #define MSR_PM_ENABLE 0x00000770 | |
| 457 | #define MSR_HWP_CAPABILITIES 0x00000771 | |
| 458 | #define MSR_HWP_REQUEST_PKG 0x00000772 | |
| 459 | #define MSR_HWP_INTERRUPT 0x00000773 | |
| 460 | #define MSR_HWP_REQUEST 0x00000774 | |
| 461 | #define MSR_HWP_STATUS 0x00000777 | |
| 462 | ||
| 463 | /* CPUID.6.EAX */ | |
| 464 | #define HWP_BASE_BIT (1<<7) | |
| 465 | #define HWP_NOTIFICATIONS_BIT (1<<8) | |
| 466 | #define HWP_ACTIVITY_WINDOW_BIT (1<<9) | |
| 467 | #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) | |
| 468 | #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) | |
| 469 | ||
| 470 | /* IA32_HWP_CAPABILITIES */ | |
| 471 | #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) | |
| 472 | #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) | |
| 473 | #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) | |
| 474 | #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) | |
| 475 | ||
| 476 | /* IA32_HWP_REQUEST */ | |
| 477 | #define HWP_MIN_PERF(x) (x & 0xff) | |
| 478 | #define HWP_MAX_PERF(x) ((x & 0xff) << 8) | |
| 479 | #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) | |
| 480 | #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) | |
| 481 | #define HWP_EPP_PERFORMANCE 0x00 | |
| 482 | #define HWP_EPP_BALANCE_PERFORMANCE 0x80 | |
| 483 | #define HWP_EPP_BALANCE_POWERSAVE 0xC0 | |
| 484 | #define HWP_EPP_POWERSAVE 0xFF | |
| 485 | #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) | |
| 486 | #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) | |
| 487 | ||
| 488 | /* IA32_HWP_STATUS */ | |
| 489 | #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) | |
| 490 | #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) | |
| 491 | ||
| 492 | /* IA32_HWP_INTERRUPT */ | |
| 493 | #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) | |
| 494 | #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) | |
| 495 | ||
| 496 | #define MSR_AMD64_MC0_MASK 0xc0010044 | |
| 497 | ||
| 498 | #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) | |
| 499 | #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) | |
| 500 | #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) | |
| 501 | #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) | |
| 502 | ||
| 503 | #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) | |
| 504 | ||
| 505 | /* These are consecutive and not in the normal 4er MCE bank block */ | |
| 506 | #define MSR_IA32_MC0_CTL2 0x00000280 | |
| 507 | #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) | |
| 508 | ||
| 509 | #define MSR_P6_PERFCTR0 0x000000c1 | |
| 510 | #define MSR_P6_PERFCTR1 0x000000c2 | |
| 511 | #define MSR_P6_EVNTSEL0 0x00000186 | |
| 512 | #define MSR_P6_EVNTSEL1 0x00000187 | |
| 513 | ||
| 514 | #define MSR_KNC_PERFCTR0 0x00000020 | |
| 515 | #define MSR_KNC_PERFCTR1 0x00000021 | |
| 516 | #define MSR_KNC_EVNTSEL0 0x00000028 | |
| 517 | #define MSR_KNC_EVNTSEL1 0x00000029 | |
| 518 | ||
| 519 | /* Alternative perfctr range with full access. */ | |
| 520 | #define MSR_IA32_PMC0 0x000004c1 | |
| 521 | ||
| 522 | /* Auto-reload via MSR instead of DS area */ | |
| 523 | #define MSR_RELOAD_PMC0 0x000014c1 | |
| 524 | #define MSR_RELOAD_FIXED_CTR0 0x00001309 | |
| 525 | ||
| 526 | /* | |
| 527 | * AMD64 MSRs. Not complete. See the architecture manual for a more | |
| 528 | * complete list. | |
| 529 | */ | |
| 530 | #define MSR_AMD64_PATCH_LEVEL 0x0000008b | |
| 531 | #define MSR_AMD64_TSC_RATIO 0xc0000104 | |
| 532 | #define MSR_AMD64_NB_CFG 0xc001001f | |
| 444e2ff3 ACM |
533 | #define MSR_AMD64_PATCH_LOADER 0xc0010020 |
| 534 | #define MSR_AMD_PERF_CTL 0xc0010062 | |
| 535 | #define MSR_AMD_PERF_STATUS 0xc0010063 | |
| 536 | #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 | |
| 537 | #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 | |
| 538 | #define MSR_AMD64_OSVW_STATUS 0xc0010141 | |
| 8122b047 ACM |
539 | #define MSR_AMD_PPIN_CTL 0xc00102f0 |
| 540 | #define MSR_AMD_PPIN 0xc00102f1 | |
| f815fe51 | 541 | #define MSR_AMD64_CPUID_FN_1 0xc0011004 |
| 444e2ff3 ACM |
542 | #define MSR_AMD64_LS_CFG 0xc0011020 |
| 543 | #define MSR_AMD64_DC_CFG 0xc0011022 | |
| 2632daeb BP |
544 | |
| 545 | #define MSR_AMD64_DE_CFG 0xc0011029 | |
| a66558dc | 546 | #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 |
| 2632daeb | 547 | #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) |
| 8cdd4aef | 548 | #define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9 |
| 2632daeb | 549 | |
| 444e2ff3 ACM |
550 | #define MSR_AMD64_BU_CFG2 0xc001102a |
| 551 | #define MSR_AMD64_IBSFETCHCTL 0xc0011030 | |
| 552 | #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 | |
| 553 | #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 | |
| 554 | #define MSR_AMD64_IBSFETCH_REG_COUNT 3 | |
| 555 | #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) | |
| 556 | #define MSR_AMD64_IBSOPCTL 0xc0011033 | |
| 557 | #define MSR_AMD64_IBSOPRIP 0xc0011034 | |
| 558 | #define MSR_AMD64_IBSOPDATA 0xc0011035 | |
| 559 | #define MSR_AMD64_IBSOPDATA2 0xc0011036 | |
| 560 | #define MSR_AMD64_IBSOPDATA3 0xc0011037 | |
| 561 | #define MSR_AMD64_IBSDCLINAD 0xc0011038 | |
| 562 | #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 | |
| 563 | #define MSR_AMD64_IBSOP_REG_COUNT 7 | |
| 564 | #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) | |
| 565 | #define MSR_AMD64_IBSCTL 0xc001103a | |
| 566 | #define MSR_AMD64_IBSBRTARGET 0xc001103b | |
| 32b734e0 | 567 | #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c |
| 444e2ff3 ACM |
568 | #define MSR_AMD64_IBSOPDATA4 0xc001103d |
| 569 | #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ | |
| 5b061a32 | 570 | #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b |
| fde66824 | 571 | #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e |
| 32b734e0 | 572 | #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 |
| 444e2ff3 ACM |
573 | #define MSR_AMD64_SEV 0xc0010131 |
| 574 | #define MSR_AMD64_SEV_ENABLED_BIT 0 | |
| 32b734e0 | 575 | #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 |
| 9dde6cad | 576 | #define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 |
| 444e2ff3 | 577 | #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) |
| 32b734e0 | 578 | #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) |
| 9dde6cad | 579 | #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) |
| 444e2ff3 | 580 | |
| 3ef9fec0 ACM |
581 | /* SNP feature bits enabled by the hypervisor */ |
| 582 | #define MSR_AMD64_SNP_VTOM BIT_ULL(3) | |
| 583 | #define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(4) | |
| 584 | #define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(5) | |
| 585 | #define MSR_AMD64_SNP_ALT_INJ BIT_ULL(6) | |
| 586 | #define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(7) | |
| 587 | #define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(8) | |
| 588 | #define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(9) | |
| 589 | #define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(10) | |
| 590 | #define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(11) | |
| 591 | #define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(12) | |
| 592 | #define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(14) | |
| 593 | #define MSR_AMD64_SNP_VMSA_REG_PROTECTION BIT_ULL(16) | |
| 594 | #define MSR_AMD64_SNP_SMT_PROTECTION BIT_ULL(17) | |
| 595 | ||
| 596 | /* SNP feature bits reserved for future use. */ | |
| 597 | #define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13) | |
| 598 | #define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15) | |
| 599 | #define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, 18) | |
| 600 | ||
| 444e2ff3 ACM |
601 | #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f |
| 602 | ||
| e652ab64 ACM |
603 | /* AMD Collaborative Processor Performance Control MSRs */ |
| 604 | #define MSR_AMD_CPPC_CAP1 0xc00102b0 | |
| 605 | #define MSR_AMD_CPPC_ENABLE 0xc00102b1 | |
| 606 | #define MSR_AMD_CPPC_CAP2 0xc00102b2 | |
| 607 | #define MSR_AMD_CPPC_REQ 0xc00102b3 | |
| 608 | #define MSR_AMD_CPPC_STATUS 0xc00102b4 | |
| 609 | ||
| 610 | #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) | |
| 611 | #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) | |
| 612 | #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) | |
| 613 | #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) | |
| 614 | ||
| 615 | #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) | |
| 616 | #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) | |
| 617 | #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) | |
| 618 | #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) | |
| 619 | ||
| 9dde6cad ACM |
620 | /* AMD Performance Counter Global Status and Control MSRs */ |
| 621 | #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 | |
| 622 | #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 | |
| 623 | #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 | |
| 624 | ||
| a3a36565 ACM |
625 | /* AMD Last Branch Record MSRs */ |
| 626 | #define MSR_AMD64_LBR_SELECT 0xc000010e | |
| 627 | ||
| 444e2ff3 ACM |
628 | /* Fam 17h MSRs */ |
| 629 | #define MSR_F17H_IRPERF 0xc00000e9 | |
| 630 | ||
| 91d248c3 ACM |
631 | #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 |
| 632 | #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) | |
| 633 | ||
| 444e2ff3 ACM |
634 | /* Fam 16h MSRs */ |
| 635 | #define MSR_F16H_L2I_PERF_CTL 0xc0010230 | |
| 636 | #define MSR_F16H_L2I_PERF_CTR 0xc0010231 | |
| 637 | #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 | |
| 638 | #define MSR_F16H_DR2_ADDR_MASK 0xc001101a | |
| 639 | #define MSR_F16H_DR3_ADDR_MASK 0xc001101b | |
| 640 | #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 | |
| 641 | ||
| 642 | /* Fam 15h MSRs */ | |
| f815fe51 ACM |
643 | #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a |
| 644 | #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b | |
| 444e2ff3 ACM |
645 | #define MSR_F15H_PERF_CTL 0xc0010200 |
| 646 | #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL | |
| 647 | #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) | |
| 648 | #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) | |
| 649 | #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) | |
| 650 | #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) | |
| 651 | #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) | |
| 652 | ||
| 653 | #define MSR_F15H_PERF_CTR 0xc0010201 | |
| 654 | #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR | |
| 655 | #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) | |
| 656 | #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) | |
| 657 | #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) | |
| 658 | #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) | |
| 659 | #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) | |
| 660 | ||
| 661 | #define MSR_F15H_NB_PERF_CTL 0xc0010240 | |
| 662 | #define MSR_F15H_NB_PERF_CTR 0xc0010241 | |
| 663 | #define MSR_F15H_PTSC 0xc0010280 | |
| 664 | #define MSR_F15H_IC_CFG 0xc0011021 | |
| 665 | #define MSR_F15H_EX_CFG 0xc001102c | |
| 666 | ||
| 667 | /* Fam 10h MSRs */ | |
| 668 | #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 | |
| 669 | #define FAM10H_MMIO_CONF_ENABLE (1<<0) | |
| 670 | #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf | |
| 671 | #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 | |
| 672 | #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL | |
| 673 | #define FAM10H_MMIO_CONF_BASE_SHIFT 20 | |
| 674 | #define MSR_FAM10H_NODE_ID 0xc001100c | |
| 444e2ff3 ACM |
675 | |
| 676 | /* K8 MSRs */ | |
| 677 | #define MSR_K8_TOP_MEM1 0xc001001a | |
| 678 | #define MSR_K8_TOP_MEM2 0xc001001d | |
| 059e5c32 BS |
679 | #define MSR_AMD64_SYSCFG 0xc0010010 |
| 680 | #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 | |
| 681 | #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) | |
| 444e2ff3 ACM |
682 | #define MSR_K8_INT_PENDING_MSG 0xc0010055 |
| 683 | /* C1E active bits in int pending message */ | |
| 684 | #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 | |
| 685 | #define MSR_K8_TSEG_ADDR 0xc0010112 | |
| 686 | #define MSR_K8_TSEG_MASK 0xc0010113 | |
| 687 | #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ | |
| 688 | #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ | |
| 689 | #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ | |
| 690 | ||
| 691 | /* K7 MSRs */ | |
| 692 | #define MSR_K7_EVNTSEL0 0xc0010000 | |
| 693 | #define MSR_K7_PERFCTR0 0xc0010004 | |
| 694 | #define MSR_K7_EVNTSEL1 0xc0010001 | |
| 695 | #define MSR_K7_PERFCTR1 0xc0010005 | |
| 696 | #define MSR_K7_EVNTSEL2 0xc0010002 | |
| 697 | #define MSR_K7_PERFCTR2 0xc0010006 | |
| 698 | #define MSR_K7_EVNTSEL3 0xc0010003 | |
| 699 | #define MSR_K7_PERFCTR3 0xc0010007 | |
| 700 | #define MSR_K7_CLK_CTL 0xc001001b | |
| 701 | #define MSR_K7_HWCR 0xc0010015 | |
| 702 | #define MSR_K7_HWCR_SMMLOCK_BIT 0 | |
| 703 | #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) | |
| d8e3ee2e ACM |
704 | #define MSR_K7_HWCR_IRPERF_EN_BIT 30 |
| 705 | #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) | |
| 444e2ff3 ACM |
706 | #define MSR_K7_FID_VID_CTL 0xc0010041 |
| 707 | #define MSR_K7_FID_VID_STATUS 0xc0010042 | |
| 708 | ||
| 709 | /* K6 MSRs */ | |
| 710 | #define MSR_K6_WHCR 0xc0000082 | |
| 711 | #define MSR_K6_UWCCR 0xc0000085 | |
| 712 | #define MSR_K6_EPMR 0xc0000086 | |
| 713 | #define MSR_K6_PSOR 0xc0000087 | |
| 714 | #define MSR_K6_PFIR 0xc0000088 | |
| 715 | ||
| 716 | /* Centaur-Hauls/IDT defined MSRs. */ | |
| 717 | #define MSR_IDT_FCR1 0x00000107 | |
| 718 | #define MSR_IDT_FCR2 0x00000108 | |
| 719 | #define MSR_IDT_FCR3 0x00000109 | |
| 720 | #define MSR_IDT_FCR4 0x0000010a | |
| 721 | ||
| 722 | #define MSR_IDT_MCR0 0x00000110 | |
| 723 | #define MSR_IDT_MCR1 0x00000111 | |
| 724 | #define MSR_IDT_MCR2 0x00000112 | |
| 725 | #define MSR_IDT_MCR3 0x00000113 | |
| 726 | #define MSR_IDT_MCR4 0x00000114 | |
| 727 | #define MSR_IDT_MCR5 0x00000115 | |
| 728 | #define MSR_IDT_MCR6 0x00000116 | |
| 729 | #define MSR_IDT_MCR7 0x00000117 | |
| 730 | #define MSR_IDT_MCR_CTRL 0x00000120 | |
| 731 | ||
| 732 | /* VIA Cyrix defined MSRs*/ | |
| 733 | #define MSR_VIA_FCR 0x00001107 | |
| 734 | #define MSR_VIA_LONGHAUL 0x0000110a | |
| 735 | #define MSR_VIA_RNG 0x0000110b | |
| 736 | #define MSR_VIA_BCR2 0x00001147 | |
| 737 | ||
| 738 | /* Transmeta defined MSRs */ | |
| 739 | #define MSR_TMTA_LONGRUN_CTRL 0x80868010 | |
| 740 | #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 | |
| 741 | #define MSR_TMTA_LRTI_READOUT 0x80868018 | |
| 742 | #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a | |
| 743 | ||
| 744 | /* Intel defined MSRs. */ | |
| 745 | #define MSR_IA32_P5_MC_ADDR 0x00000000 | |
| 746 | #define MSR_IA32_P5_MC_TYPE 0x00000001 | |
| 747 | #define MSR_IA32_TSC 0x00000010 | |
| 748 | #define MSR_IA32_PLATFORM_ID 0x00000017 | |
| 749 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a | |
| 750 | #define MSR_EBC_FREQUENCY_ID 0x0000002c | |
| 751 | #define MSR_SMI_COUNT 0x00000034 | |
| f6505c88 SC |
752 | |
| 753 | /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ | |
| 754 | #define MSR_IA32_FEAT_CTL 0x0000003a | |
| 755 | #define FEAT_CTL_LOCKED BIT(0) | |
| 756 | #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) | |
| 757 | #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) | |
| e9bde94f ACM |
758 | #define FEAT_CTL_SGX_LC_ENABLED BIT(17) |
| 759 | #define FEAT_CTL_SGX_ENABLED BIT(18) | |
| f6505c88 SC |
760 | #define FEAT_CTL_LMCE_ENABLED BIT(20) |
| 761 | ||
| 444e2ff3 ACM |
762 | #define MSR_IA32_TSC_ADJUST 0x0000003b |
| 763 | #define MSR_IA32_BNDCFGS 0x00000d90 | |
| 764 | ||
| 765 | #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc | |
| 766 | ||
| 3442b5e0 ACM |
767 | #define MSR_IA32_XFD 0x000001c4 |
| 768 | #define MSR_IA32_XFD_ERR 0x000001c5 | |
| 444e2ff3 ACM |
769 | #define MSR_IA32_XSS 0x00000da0 |
| 770 | ||
| 444e2ff3 ACM |
771 | #define MSR_IA32_APICBASE 0x0000001b |
| 772 | #define MSR_IA32_APICBASE_BSP (1<<8) | |
| 773 | #define MSR_IA32_APICBASE_ENABLE (1<<11) | |
| 774 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) | |
| 775 | ||
| 444e2ff3 ACM |
776 | #define MSR_IA32_UCODE_WRITE 0x00000079 |
| 777 | #define MSR_IA32_UCODE_REV 0x0000008b | |
| 778 | ||
| e9bde94f ACM |
779 | /* Intel SGX Launch Enclave Public Key Hash MSRs */ |
| 780 | #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C | |
| 781 | #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D | |
| 782 | #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E | |
| 783 | #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F | |
| 784 | ||
| 444e2ff3 ACM |
785 | #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b |
| 786 | #define MSR_IA32_SMBASE 0x0000009e | |
| 787 | ||
| 788 | #define MSR_IA32_PERF_STATUS 0x00000198 | |
| 789 | #define MSR_IA32_PERF_CTL 0x00000199 | |
| 790 | #define INTEL_PERF_CTL_MASK 0xffff | |
| 791 | ||
| 9dde6cad ACM |
792 | /* AMD Branch Sampling configuration */ |
| 793 | #define MSR_AMD_DBG_EXTN_CFG 0xc000010f | |
| 794 | #define MSR_AMD_SAMP_BR_FROM 0xc0010300 | |
| 795 | ||
| a3a36565 ACM |
796 | #define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6) |
| 797 | ||
| 444e2ff3 ACM |
798 | #define MSR_IA32_MPERF 0x000000e7 |
| 799 | #define MSR_IA32_APERF 0x000000e8 | |
| 800 | ||
| 801 | #define MSR_IA32_THERM_CONTROL 0x0000019a | |
| 802 | #define MSR_IA32_THERM_INTERRUPT 0x0000019b | |
| 803 | ||
| 804 | #define THERM_INT_HIGH_ENABLE (1 << 0) | |
| 805 | #define THERM_INT_LOW_ENABLE (1 << 1) | |
| 806 | #define THERM_INT_PLN_ENABLE (1 << 24) | |
| 807 | ||
| 808 | #define MSR_IA32_THERM_STATUS 0x0000019c | |
| 809 | ||
| 810 | #define THERM_STATUS_PROCHOT (1 << 0) | |
| 811 | #define THERM_STATUS_POWER_LIMIT (1 << 10) | |
| 812 | ||
| 813 | #define MSR_THERM2_CTL 0x0000019d | |
| 814 | ||
| 815 | #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) | |
| 816 | ||
| 817 | #define MSR_IA32_MISC_ENABLE 0x000001a0 | |
| 818 | ||
| 819 | #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 | |
| 820 | ||
| 821 | #define MSR_MISC_FEATURE_CONTROL 0x000001a4 | |
| 822 | #define MSR_MISC_PWR_MGMT 0x000001aa | |
| 823 | ||
| 824 | #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 | |
| 825 | #define ENERGY_PERF_BIAS_PERFORMANCE 0 | |
| 826 | #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 | |
| 827 | #define ENERGY_PERF_BIAS_NORMAL 6 | |
| a66558dc | 828 | #define ENERGY_PERF_BIAS_NORMAL_POWERSAVE 7 |
| 444e2ff3 ACM |
829 | #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 |
| 830 | #define ENERGY_PERF_BIAS_POWERSAVE 15 | |
| 831 | ||
| 832 | #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 | |
| 833 | ||
| 834 | #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) | |
| 835 | #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) | |
| 61726144 | 836 | #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) |
| 444e2ff3 ACM |
837 | |
| 838 | #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 | |
| 839 | ||
| 840 | #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) | |
| 841 | #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) | |
| 842 | #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) | |
| 61726144 | 843 | #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) |
| 444e2ff3 ACM |
844 | |
| 845 | /* Thermal Thresholds Support */ | |
| 846 | #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) | |
| 847 | #define THERM_SHIFT_THRESHOLD0 8 | |
| 848 | #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) | |
| 849 | #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) | |
| 850 | #define THERM_SHIFT_THRESHOLD1 16 | |
| 851 | #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) | |
| 852 | #define THERM_STATUS_THRESHOLD0 (1 << 6) | |
| 853 | #define THERM_LOG_THRESHOLD0 (1 << 7) | |
| 854 | #define THERM_STATUS_THRESHOLD1 (1 << 8) | |
| 855 | #define THERM_LOG_THRESHOLD1 (1 << 9) | |
| 856 | ||
| 857 | /* MISC_ENABLE bits: architectural */ | |
| 858 | #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 | |
| 859 | #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) | |
| 860 | #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 | |
| 861 | #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) | |
| 862 | #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 | |
| 863 | #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) | |
| 864 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 | |
| 865 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) | |
| 866 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 | |
| 867 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) | |
| 868 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 | |
| 869 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) | |
| 870 | #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 | |
| 871 | #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) | |
| 872 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 | |
| 873 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) | |
| 874 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 | |
| 875 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) | |
| 876 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 | |
| 877 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) | |
| 878 | ||
| 879 | /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ | |
| 880 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 | |
| 881 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) | |
| 882 | #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 | |
| 883 | #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) | |
| 884 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 | |
| 885 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) | |
| 886 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 | |
| 887 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) | |
| 888 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 | |
| 889 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) | |
| 890 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 | |
| 891 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) | |
| 892 | #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 | |
| 893 | #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) | |
| 894 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 | |
| 895 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) | |
| 896 | #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 | |
| 897 | #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) | |
| 898 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 | |
| 899 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) | |
| 900 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 | |
| 901 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) | |
| 902 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 | |
| 903 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) | |
| 904 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 | |
| 905 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) | |
| 906 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 | |
| 907 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) | |
| 908 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 | |
| 909 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) | |
| 910 | ||
| 911 | /* MISC_FEATURES_ENABLES non-architectural features */ | |
| 912 | #define MSR_MISC_FEATURES_ENABLES 0x00000140 | |
| 913 | ||
| 914 | #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 | |
| 915 | #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) | |
| 916 | #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 | |
| 917 | ||
| 918 | #define MSR_IA32_TSC_DEADLINE 0x000006E0 | |
| 919 | ||
| 920 | ||
| 921 | #define MSR_TSX_FORCE_ABORT 0x0000010F | |
| 922 | ||
| 923 | #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 | |
| 924 | #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) | |
| 04df0dc1 ACM |
925 | #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 |
| 926 | #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) | |
| 927 | #define MSR_TFA_SDV_ENABLE_RTM_BIT 2 | |
| 928 | #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) | |
| 444e2ff3 ACM |
929 | |
| 930 | /* P4/Xeon+ specific */ | |
| 931 | #define MSR_IA32_MCG_EAX 0x00000180 | |
| 932 | #define MSR_IA32_MCG_EBX 0x00000181 | |
| 933 | #define MSR_IA32_MCG_ECX 0x00000182 | |
| 934 | #define MSR_IA32_MCG_EDX 0x00000183 | |
| 935 | #define MSR_IA32_MCG_ESI 0x00000184 | |
| 936 | #define MSR_IA32_MCG_EDI 0x00000185 | |
| 937 | #define MSR_IA32_MCG_EBP 0x00000186 | |
| 938 | #define MSR_IA32_MCG_ESP 0x00000187 | |
| 939 | #define MSR_IA32_MCG_EFLAGS 0x00000188 | |
| 940 | #define MSR_IA32_MCG_EIP 0x00000189 | |
| 941 | #define MSR_IA32_MCG_RESERVED 0x0000018a | |
| 942 | ||
| 943 | /* Pentium IV performance counter MSRs */ | |
| 944 | #define MSR_P4_BPU_PERFCTR0 0x00000300 | |
| 945 | #define MSR_P4_BPU_PERFCTR1 0x00000301 | |
| 946 | #define MSR_P4_BPU_PERFCTR2 0x00000302 | |
| 947 | #define MSR_P4_BPU_PERFCTR3 0x00000303 | |
| 948 | #define MSR_P4_MS_PERFCTR0 0x00000304 | |
| 949 | #define MSR_P4_MS_PERFCTR1 0x00000305 | |
| 950 | #define MSR_P4_MS_PERFCTR2 0x00000306 | |
| 951 | #define MSR_P4_MS_PERFCTR3 0x00000307 | |
| 952 | #define MSR_P4_FLAME_PERFCTR0 0x00000308 | |
| 953 | #define MSR_P4_FLAME_PERFCTR1 0x00000309 | |
| 954 | #define MSR_P4_FLAME_PERFCTR2 0x0000030a | |
| 955 | #define MSR_P4_FLAME_PERFCTR3 0x0000030b | |
| 956 | #define MSR_P4_IQ_PERFCTR0 0x0000030c | |
| 957 | #define MSR_P4_IQ_PERFCTR1 0x0000030d | |
| 958 | #define MSR_P4_IQ_PERFCTR2 0x0000030e | |
| 959 | #define MSR_P4_IQ_PERFCTR3 0x0000030f | |
| 960 | #define MSR_P4_IQ_PERFCTR4 0x00000310 | |
| 961 | #define MSR_P4_IQ_PERFCTR5 0x00000311 | |
| 962 | #define MSR_P4_BPU_CCCR0 0x00000360 | |
| 963 | #define MSR_P4_BPU_CCCR1 0x00000361 | |
| 964 | #define MSR_P4_BPU_CCCR2 0x00000362 | |
| 965 | #define MSR_P4_BPU_CCCR3 0x00000363 | |
| 966 | #define MSR_P4_MS_CCCR0 0x00000364 | |
| 967 | #define MSR_P4_MS_CCCR1 0x00000365 | |
| 968 | #define MSR_P4_MS_CCCR2 0x00000366 | |
| 969 | #define MSR_P4_MS_CCCR3 0x00000367 | |
| 970 | #define MSR_P4_FLAME_CCCR0 0x00000368 | |
| 971 | #define MSR_P4_FLAME_CCCR1 0x00000369 | |
| 972 | #define MSR_P4_FLAME_CCCR2 0x0000036a | |
| 973 | #define MSR_P4_FLAME_CCCR3 0x0000036b | |
| 974 | #define MSR_P4_IQ_CCCR0 0x0000036c | |
| 975 | #define MSR_P4_IQ_CCCR1 0x0000036d | |
| 976 | #define MSR_P4_IQ_CCCR2 0x0000036e | |
| 977 | #define MSR_P4_IQ_CCCR3 0x0000036f | |
| 978 | #define MSR_P4_IQ_CCCR4 0x00000370 | |
| 979 | #define MSR_P4_IQ_CCCR5 0x00000371 | |
| 980 | #define MSR_P4_ALF_ESCR0 0x000003ca | |
| 981 | #define MSR_P4_ALF_ESCR1 0x000003cb | |
| 982 | #define MSR_P4_BPU_ESCR0 0x000003b2 | |
| 983 | #define MSR_P4_BPU_ESCR1 0x000003b3 | |
| 984 | #define MSR_P4_BSU_ESCR0 0x000003a0 | |
| 985 | #define MSR_P4_BSU_ESCR1 0x000003a1 | |
| 986 | #define MSR_P4_CRU_ESCR0 0x000003b8 | |
| 987 | #define MSR_P4_CRU_ESCR1 0x000003b9 | |
| 988 | #define MSR_P4_CRU_ESCR2 0x000003cc | |
| 989 | #define MSR_P4_CRU_ESCR3 0x000003cd | |
| 990 | #define MSR_P4_CRU_ESCR4 0x000003e0 | |
| 991 | #define MSR_P4_CRU_ESCR5 0x000003e1 | |
| 992 | #define MSR_P4_DAC_ESCR0 0x000003a8 | |
| 993 | #define MSR_P4_DAC_ESCR1 0x000003a9 | |
| 994 | #define MSR_P4_FIRM_ESCR0 0x000003a4 | |
| 995 | #define MSR_P4_FIRM_ESCR1 0x000003a5 | |
| 996 | #define MSR_P4_FLAME_ESCR0 0x000003a6 | |
| 997 | #define MSR_P4_FLAME_ESCR1 0x000003a7 | |
| 998 | #define MSR_P4_FSB_ESCR0 0x000003a2 | |
| 999 | #define MSR_P4_FSB_ESCR1 0x000003a3 | |
| 1000 | #define MSR_P4_IQ_ESCR0 0x000003ba | |
| 1001 | #define MSR_P4_IQ_ESCR1 0x000003bb | |
| 1002 | #define MSR_P4_IS_ESCR0 0x000003b4 | |
| 1003 | #define MSR_P4_IS_ESCR1 0x000003b5 | |
| 1004 | #define MSR_P4_ITLB_ESCR0 0x000003b6 | |
| 1005 | #define MSR_P4_ITLB_ESCR1 0x000003b7 | |
| 1006 | #define MSR_P4_IX_ESCR0 0x000003c8 | |
| 1007 | #define MSR_P4_IX_ESCR1 0x000003c9 | |
| 1008 | #define MSR_P4_MOB_ESCR0 0x000003aa | |
| 1009 | #define MSR_P4_MOB_ESCR1 0x000003ab | |
| 1010 | #define MSR_P4_MS_ESCR0 0x000003c0 | |
| 1011 | #define MSR_P4_MS_ESCR1 0x000003c1 | |
| 1012 | #define MSR_P4_PMH_ESCR0 0x000003ac | |
| 1013 | #define MSR_P4_PMH_ESCR1 0x000003ad | |
| 1014 | #define MSR_P4_RAT_ESCR0 0x000003bc | |
| 1015 | #define MSR_P4_RAT_ESCR1 0x000003bd | |
| 1016 | #define MSR_P4_SAAT_ESCR0 0x000003ae | |
| 1017 | #define MSR_P4_SAAT_ESCR1 0x000003af | |
| 1018 | #define MSR_P4_SSU_ESCR0 0x000003be | |
| 1019 | #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ | |
| 1020 | ||
| 1021 | #define MSR_P4_TBPU_ESCR0 0x000003c2 | |
| 1022 | #define MSR_P4_TBPU_ESCR1 0x000003c3 | |
| 1023 | #define MSR_P4_TC_ESCR0 0x000003c4 | |
| 1024 | #define MSR_P4_TC_ESCR1 0x000003c5 | |
| 1025 | #define MSR_P4_U2L_ESCR0 0x000003b0 | |
| 1026 | #define MSR_P4_U2L_ESCR1 0x000003b1 | |
| 1027 | ||
| 1028 | #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 | |
| 1029 | ||
| 1030 | /* Intel Core-based CPU performance counters */ | |
| 1031 | #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 | |
| 1032 | #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a | |
| 1033 | #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b | |
| 32b734e0 | 1034 | #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c |
| 444e2ff3 ACM |
1035 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d |
| 1036 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e | |
| 1037 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f | |
| 1038 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 | |
| 1039 | ||
| 32b734e0 ACM |
1040 | #define MSR_PERF_METRICS 0x00000329 |
| 1041 | ||
| 444e2ff3 ACM |
1042 | /* PERF_GLOBAL_OVF_CTL bits */ |
| 1043 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 | |
| 1044 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) | |
| 1045 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 | |
| 1046 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) | |
| 1047 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 | |
| 1048 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) | |
| 1049 | ||
| 1050 | /* Geode defined MSRs */ | |
| 1051 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 | |
| 1052 | ||
| 1053 | /* Intel VT MSRs */ | |
| 1054 | #define MSR_IA32_VMX_BASIC 0x00000480 | |
| 1055 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 | |
| 1056 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 | |
| 1057 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 | |
| 1058 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 | |
| 1059 | #define MSR_IA32_VMX_MISC 0x00000485 | |
| 1060 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 | |
| 1061 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 | |
| 1062 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 | |
| 1063 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 | |
| 1064 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a | |
| 1065 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b | |
| 1066 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c | |
| 1067 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d | |
| 1068 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e | |
| 1069 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f | |
| 1070 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 | |
| 1071 | #define MSR_IA32_VMX_VMFUNC 0x00000491 | |
| 7f7f86a7 | 1072 | #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 |
| 444e2ff3 ACM |
1073 | |
| 1074 | /* VMX_BASIC bits and bitmasks */ | |
| 1075 | #define VMX_BASIC_VMCS_SIZE_SHIFT 32 | |
| 1076 | #define VMX_BASIC_TRUE_CTLS (1ULL << 55) | |
| 1077 | #define VMX_BASIC_64 0x0001000000000000LLU | |
| 1078 | #define VMX_BASIC_MEM_TYPE_SHIFT 50 | |
| 1079 | #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU | |
| 1080 | #define VMX_BASIC_MEM_TYPE_WB 6LLU | |
| 1081 | #define VMX_BASIC_INOUT 0x0040000000000000LLU | |
| 1082 | ||
| a66558dc ACM |
1083 | /* Resctrl MSRs: */ |
| 1084 | /* - Intel: */ | |
| 1085 | #define MSR_IA32_L3_QOS_CFG 0xc81 | |
| 1086 | #define MSR_IA32_L2_QOS_CFG 0xc82 | |
| 1087 | #define MSR_IA32_QM_EVTSEL 0xc8d | |
| 1088 | #define MSR_IA32_QM_CTR 0xc8e | |
| 1089 | #define MSR_IA32_PQR_ASSOC 0xc8f | |
| 1090 | #define MSR_IA32_L3_CBM_BASE 0xc90 | |
| 1091 | #define MSR_IA32_L2_CBM_BASE 0xd10 | |
| 1092 | #define MSR_IA32_MBA_THRTL_BASE 0xd50 | |
| 1093 | ||
| 1094 | /* - AMD: */ | |
| 1095 | #define MSR_IA32_MBA_BW_BASE 0xc0000200 | |
| 3ee7cb4f ACM |
1096 | #define MSR_IA32_SMBA_BW_BASE 0xc0000280 |
| 1097 | #define MSR_IA32_EVT_CFG_BASE 0xc0000400 | |
| a66558dc | 1098 | |
| 444e2ff3 ACM |
1099 | /* MSR_IA32_VMX_MISC bits */ |
| 1100 | #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) | |
| 1101 | #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) | |
| 1102 | #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F | |
| 1103 | /* AMD-V MSRs */ | |
| 1104 | ||
| 1105 | #define MSR_VM_CR 0xc0010114 | |
| 1106 | #define MSR_VM_IGNNE 0xc0010115 | |
| 1107 | #define MSR_VM_HSAVE_PA 0xc0010117 | |
| 1108 | ||
| 61726144 ACM |
1109 | /* Hardware Feedback Interface */ |
| 1110 | #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 | |
| 1111 | #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 | |
| 1112 | ||
| a3a36565 ACM |
1113 | /* x2APIC locked status */ |
| 1114 | #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD | |
| 1115 | #define LEGACY_XAPIC_DISABLED BIT(0) /* | |
| 1116 | * x2APIC mode is locked and | |
| 1117 | * disabling x2APIC will cause | |
| 1118 | * a #GP | |
| 1119 | */ | |
| 1120 | ||
| 444e2ff3 | 1121 | #endif /* _ASM_X86_MSR_INDEX_H */ |