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7d7d1bf1 ACM |
1 | #ifndef _ASM_X86_DISABLED_FEATURES_H |
2 | #define _ASM_X86_DISABLED_FEATURES_H | |
3 | ||
4 | /* These features, although they might be available in a CPU | |
5 | * will not be used because the compile options to support | |
6 | * them are not present. | |
7 | * | |
8 | * This code allows them to be checked and disabled at | |
9 | * compile time without an explicit #ifdef. Use | |
10 | * cpu_feature_enabled(). | |
11 | */ | |
12 | ||
13 | #ifdef CONFIG_X86_INTEL_MPX | |
14 | # define DISABLE_MPX 0 | |
15 | #else | |
16 | # define DISABLE_MPX (1<<(X86_FEATURE_MPX & 31)) | |
17 | #endif | |
18 | ||
0b44cfb8 IM |
19 | #ifdef CONFIG_X86_INTEL_UMIP |
20 | # define DISABLE_UMIP 0 | |
21 | #else | |
22 | # define DISABLE_UMIP (1<<(X86_FEATURE_UMIP & 31)) | |
23 | #endif | |
24 | ||
7d7d1bf1 ACM |
25 | #ifdef CONFIG_X86_64 |
26 | # define DISABLE_VME (1<<(X86_FEATURE_VME & 31)) | |
27 | # define DISABLE_K6_MTRR (1<<(X86_FEATURE_K6_MTRR & 31)) | |
28 | # define DISABLE_CYRIX_ARR (1<<(X86_FEATURE_CYRIX_ARR & 31)) | |
29 | # define DISABLE_CENTAUR_MCR (1<<(X86_FEATURE_CENTAUR_MCR & 31)) | |
549a3976 | 30 | # define DISABLE_PCID 0 |
7d7d1bf1 ACM |
31 | #else |
32 | # define DISABLE_VME 0 | |
33 | # define DISABLE_K6_MTRR 0 | |
34 | # define DISABLE_CYRIX_ARR 0 | |
35 | # define DISABLE_CENTAUR_MCR 0 | |
549a3976 | 36 | # define DISABLE_PCID (1<<(X86_FEATURE_PCID & 31)) |
7d7d1bf1 ACM |
37 | #endif /* CONFIG_X86_64 */ |
38 | ||
39 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS | |
40 | # define DISABLE_PKU 0 | |
41 | # define DISABLE_OSPKE 0 | |
42 | #else | |
43 | # define DISABLE_PKU (1<<(X86_FEATURE_PKU & 31)) | |
44 | # define DISABLE_OSPKE (1<<(X86_FEATURE_OSPKE & 31)) | |
45 | #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ | |
46 | ||
6e30437b IM |
47 | #ifdef CONFIG_X86_5LEVEL |
48 | # define DISABLE_LA57 0 | |
49 | #else | |
50 | # define DISABLE_LA57 (1<<(X86_FEATURE_LA57 & 31)) | |
51 | #endif | |
52 | ||
7d7d1bf1 ACM |
53 | /* |
54 | * Make sure to add features to the correct mask | |
55 | */ | |
56 | #define DISABLED_MASK0 (DISABLE_VME) | |
57 | #define DISABLED_MASK1 0 | |
58 | #define DISABLED_MASK2 0 | |
59 | #define DISABLED_MASK3 (DISABLE_CYRIX_ARR|DISABLE_CENTAUR_MCR|DISABLE_K6_MTRR) | |
549a3976 | 60 | #define DISABLED_MASK4 (DISABLE_PCID) |
7d7d1bf1 ACM |
61 | #define DISABLED_MASK5 0 |
62 | #define DISABLED_MASK6 0 | |
63 | #define DISABLED_MASK7 0 | |
64 | #define DISABLED_MASK8 0 | |
65 | #define DISABLED_MASK9 (DISABLE_MPX) | |
66 | #define DISABLED_MASK10 0 | |
67 | #define DISABLED_MASK11 0 | |
68 | #define DISABLED_MASK12 0 | |
69 | #define DISABLED_MASK13 0 | |
70 | #define DISABLED_MASK14 0 | |
71 | #define DISABLED_MASK15 0 | |
0b44cfb8 | 72 | #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP) |
840b49ba ACM |
73 | #define DISABLED_MASK17 0 |
74 | #define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) | |
7d7d1bf1 ACM |
75 | |
76 | #endif /* _ASM_X86_DISABLED_FEATURES_H */ |