[linux-2.6-block.git] / tools / arch / arm64 / include / asm / cputype.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2012 ARM Ltd.
 */
#ifndef __ASM_CPUTYPE_H
#define __ASM_CPUTYPE_H

#define INVALID_HWID		ULONG_MAX

#define MPIDR_UP_BITMASK	(0x1 << 30)
#define MPIDR_MT_BITMASK	(0x1 << 24)
#define MPIDR_HWID_BITMASK	UL(0xff00ffffff)

#define MPIDR_LEVEL_BITS_SHIFT	3
#define MPIDR_LEVEL_BITS	(1 << MPIDR_LEVEL_BITS_SHIFT)
#define MPIDR_LEVEL_MASK	((1 << MPIDR_LEVEL_BITS) - 1)

#define MPIDR_LEVEL_SHIFT(level) \
	(((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)

#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
	((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)

#define MIDR_REVISION_MASK	0xf
#define MIDR_REVISION(midr)	((midr) & MIDR_REVISION_MASK)
#define MIDR_PARTNUM_SHIFT	4
#define MIDR_PARTNUM_MASK	(0xfff << MIDR_PARTNUM_SHIFT)
#define MIDR_PARTNUM(midr)	\
	(((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
#define MIDR_ARCHITECTURE_SHIFT	16
#define MIDR_ARCHITECTURE_MASK	(0xf << MIDR_ARCHITECTURE_SHIFT)
#define MIDR_ARCHITECTURE(midr)	\
	(((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
#define MIDR_VARIANT_SHIFT	20
#define MIDR_VARIANT_MASK	(0xf << MIDR_VARIANT_SHIFT)
#define MIDR_VARIANT(midr)	\
	(((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
#define MIDR_IMPLEMENTOR_SHIFT	24
#define MIDR_IMPLEMENTOR_MASK	(0xffU << MIDR_IMPLEMENTOR_SHIFT)
#define MIDR_IMPLEMENTOR(midr)	\
	(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)

#define MIDR_CPU_MODEL(imp, partnum) \
	((_AT(u32, imp)		<< MIDR_IMPLEMENTOR_SHIFT) | \
	(0xf			<< MIDR_ARCHITECTURE_SHIFT) | \
	((partnum)		<< MIDR_PARTNUM_SHIFT))

#define MIDR_CPU_VAR_REV(var, rev) \
	(((var)	<< MIDR_VARIANT_SHIFT) | (rev))

#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
			     MIDR_ARCHITECTURE_MASK)

#define ARM_CPU_IMP_ARM			0x41
#define ARM_CPU_IMP_APM			0x50
#define ARM_CPU_IMP_CAVIUM		0x43
#define ARM_CPU_IMP_BRCM		0x42
#define ARM_CPU_IMP_QCOM		0x51
#define ARM_CPU_IMP_NVIDIA		0x4E
#define ARM_CPU_IMP_FUJITSU		0x46
#define ARM_CPU_IMP_HISI		0x48
#define ARM_CPU_IMP_APPLE		0x61
#define ARM_CPU_IMP_AMPERE		0xC0
#define ARM_CPU_IMP_MICROSOFT		0x6D

#define ARM_CPU_PART_AEM_V8		0xD0F
#define ARM_CPU_PART_FOUNDATION		0xD00
#define ARM_CPU_PART_CORTEX_A57		0xD07
#define ARM_CPU_PART_CORTEX_A72		0xD08
#define ARM_CPU_PART_CORTEX_A53		0xD03
#define ARM_CPU_PART_CORTEX_A73		0xD09
#define ARM_CPU_PART_CORTEX_A75		0xD0A
#define ARM_CPU_PART_CORTEX_A35		0xD04
#define ARM_CPU_PART_CORTEX_A55		0xD05
#define ARM_CPU_PART_CORTEX_A76		0xD0B
#define ARM_CPU_PART_NEOVERSE_N1	0xD0C
#define ARM_CPU_PART_CORTEX_A77		0xD0D
#define ARM_CPU_PART_NEOVERSE_V1	0xD40
#define ARM_CPU_PART_CORTEX_A78		0xD41
#define ARM_CPU_PART_CORTEX_A78AE	0xD42
#define ARM_CPU_PART_CORTEX_X1		0xD44
#define ARM_CPU_PART_CORTEX_A510	0xD46
#define ARM_CPU_PART_CORTEX_A520	0xD80
#define ARM_CPU_PART_CORTEX_A710	0xD47
#define ARM_CPU_PART_CORTEX_A715	0xD4D
#define ARM_CPU_PART_CORTEX_X2		0xD48
#define ARM_CPU_PART_NEOVERSE_N2	0xD49
#define ARM_CPU_PART_CORTEX_A78C	0xD4B
#define ARM_CPU_PART_NEOVERSE_V2	0xD4F
#define ARM_CPU_PART_CORTEX_X4		0xD82
#define ARM_CPU_PART_NEOVERSE_V3	0xD84

#define APM_CPU_PART_XGENE		0x000
#define APM_CPU_VAR_POTENZA		0x00

#define CAVIUM_CPU_PART_THUNDERX	0x0A1
#define CAVIUM_CPU_PART_THUNDERX_81XX	0x0A2
#define CAVIUM_CPU_PART_THUNDERX_83XX	0x0A3
#define CAVIUM_CPU_PART_THUNDERX2	0x0AF
/* OcteonTx2 series */
#define CAVIUM_CPU_PART_OCTX2_98XX	0x0B1
#define CAVIUM_CPU_PART_OCTX2_96XX	0x0B2
#define CAVIUM_CPU_PART_OCTX2_95XX	0x0B3
#define CAVIUM_CPU_PART_OCTX2_95XXN	0x0B4
#define CAVIUM_CPU_PART_OCTX2_95XXMM	0x0B5
#define CAVIUM_CPU_PART_OCTX2_95XXO	0x0B6

#define BRCM_CPU_PART_BRAHMA_B53	0x100
#define BRCM_CPU_PART_VULCAN		0x516

#define QCOM_CPU_PART_FALKOR_V1		0x800
#define QCOM_CPU_PART_FALKOR		0xC00
#define QCOM_CPU_PART_KRYO		0x200
#define QCOM_CPU_PART_KRYO_2XX_GOLD	0x800
#define QCOM_CPU_PART_KRYO_2XX_SILVER	0x801
#define QCOM_CPU_PART_KRYO_3XX_SILVER	0x803
#define QCOM_CPU_PART_KRYO_4XX_GOLD	0x804
#define QCOM_CPU_PART_KRYO_4XX_SILVER	0x805

#define NVIDIA_CPU_PART_DENVER		0x003
#define NVIDIA_CPU_PART_CARMEL		0x004

#define FUJITSU_CPU_PART_A64FX		0x001

#define HISI_CPU_PART_TSV110		0xD01

#define APPLE_CPU_PART_M1_ICESTORM	0x022
#define APPLE_CPU_PART_M1_FIRESTORM	0x023
#define APPLE_CPU_PART_M1_ICESTORM_PRO	0x024
#define APPLE_CPU_PART_M1_FIRESTORM_PRO	0x025
#define APPLE_CPU_PART_M1_ICESTORM_MAX	0x028
#define APPLE_CPU_PART_M1_FIRESTORM_MAX	0x029
#define APPLE_CPU_PART_M2_BLIZZARD	0x032
#define APPLE_CPU_PART_M2_AVALANCHE	0x033
#define APPLE_CPU_PART_M2_BLIZZARD_PRO	0x034
#define APPLE_CPU_PART_M2_AVALANCHE_PRO	0x035
#define APPLE_CPU_PART_M2_BLIZZARD_MAX	0x038
#define APPLE_CPU_PART_M2_AVALANCHE_MAX	0x039

#define AMPERE_CPU_PART_AMPERE1		0xAC3

#define MICROSOFT_CPU_PART_AZURE_COBALT_100	0xD49 /* Based on r0p0 of ARM Neoverse N2 */

#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
#define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
#define MIDR_CORTEX_A76	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
#define MIDR_CORTEX_A77	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
#define MIDR_NEOVERSE_V1	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1)
#define MIDR_CORTEX_A78	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)
#define MIDR_CORTEX_A78AE	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)
#define MIDR_CORTEX_X1	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
#define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520)
#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715)
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
#define MIDR_CORTEX_A78C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
#define MIDR_OCTX2_98XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_98XX)
#define MIDR_OCTX2_96XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_96XX)
#define MIDR_OCTX2_95XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XX)
#define MIDR_OCTX2_95XXN MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXN)
#define MIDR_OCTX2_95XXMM MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXMM)
#define MIDR_OCTX2_95XXO MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXO)
#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
#define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD)
#define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)
#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)
#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)
#define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)
#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
#define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)
#define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)
#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)
#define MIDR_APPLE_M2_BLIZZARD MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD)
#define MIDR_APPLE_M2_AVALANCHE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE)
#define MIDR_APPLE_M2_BLIZZARD_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_PRO)
#define MIDR_APPLE_M2_AVALANCHE_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO)
#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)

/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
#define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX
#define MIDR_FUJITSU_ERRATUM_010001_MASK	(~MIDR_CPU_VAR_REV(1, 0))
#define TCR_CLEAR_FUJITSU_ERRATUM_010001	(TCR_NFD1 | TCR_NFD0)

#ifndef __ASSEMBLY__

#include <asm/sysreg.h>

#define read_cpuid(reg)			read_sysreg_s(SYS_ ## reg)

/*
 * Represent a range of MIDR values for a given CPU model and a
 * range of variant/revision values.
 *
 * @model	- CPU model as defined by MIDR_CPU_MODEL
 * @rv_min	- Minimum value for the revision/variant as defined by
 *		  MIDR_CPU_VAR_REV
 * @rv_max	- Maximum value for the variant/revision for the range.
 */
struct midr_range {
	u32 model;
	u32 rv_min;
	u32 rv_max;
};

#define MIDR_RANGE(m, v_min, r_min, v_max, r_max)		\
	{							\
		.model = m,					\
		.rv_min = MIDR_CPU_VAR_REV(v_min, r_min),	\
		.rv_max = MIDR_CPU_VAR_REV(v_max, r_max),	\
	}

#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
#define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)
#define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)

static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,
					   u32 rv_max)
{
	u32 _model = midr & MIDR_CPU_MODEL_MASK;
	u32 rv = midr & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK);

	return _model == model && rv >= rv_min && rv <= rv_max;
}

static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)
{
	return midr_is_cpu_model_range(midr, range->model,
				       range->rv_min, range->rv_max);
}

static inline bool
is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
{
	while (ranges->model)
		if (is_midr_in_range(midr, ranges++))
			return true;
	return false;
}

/*
 * The CPU ID never changes at run time, so we might as well tell the
 * compiler that it's constant.  Use this function to read the CPU ID
 * rather than directly reading processor_id or read_cpuid() directly.
 */
static inline u32 __attribute_const__ read_cpuid_id(void)
{
	return read_cpuid(MIDR_EL1);
}

static inline u64 __attribute_const__ read_cpuid_mpidr(void)
{
	return read_cpuid(MPIDR_EL1);
}

static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
{
	return MIDR_IMPLEMENTOR(read_cpuid_id());
}

static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
{
	return MIDR_PARTNUM(read_cpuid_id());
}

static inline u32 __attribute_const__ read_cpuid_cachetype(void)
{
	return read_cpuid(CTR_EL0);
}
#endif /* __ASSEMBLY__ */

#endif
Commit	Line	Data
1314376d AS	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2	/*
	3	* Copyright (C) 2012 ARM Ltd.
	4	*/
	5	#ifndef __ASM_CPUTYPE_H
	6	#define __ASM_CPUTYPE_H
	7
	8	#define INVALID_HWID ULONG_MAX
	9
	10	#define MPIDR_UP_BITMASK (0x1 << 30)
	11	#define MPIDR_MT_BITMASK (0x1 << 24)
	12	#define MPIDR_HWID_BITMASK UL(0xff00ffffff)
	13
	14	#define MPIDR_LEVEL_BITS_SHIFT 3
	15	#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
	16	#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
	17
	18	#define MPIDR_LEVEL_SHIFT(level) \
	19	(((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
	20
	21	#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
	22	((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
	23
	24	#define MIDR_REVISION_MASK 0xf
	25	#define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
	26	#define MIDR_PARTNUM_SHIFT 4
	27	#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
	28	#define MIDR_PARTNUM(midr) \
	29	(((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
	30	#define MIDR_ARCHITECTURE_SHIFT 16
	31	#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
	32	#define MIDR_ARCHITECTURE(midr) \
	33	(((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
	34	#define MIDR_VARIANT_SHIFT 20
	35	#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
	36	#define MIDR_VARIANT(midr) \
	37	(((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
	38	#define MIDR_IMPLEMENTOR_SHIFT 24
37402d5d	39	#define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT)
1314376d AS	40	#define MIDR_IMPLEMENTOR(midr) \
	41	(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
	42
	43	#define MIDR_CPU_MODEL(imp, partnum) \
8c51e8f4	44	((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) \| \
1314376d AS	45	(0xf << MIDR_ARCHITECTURE_SHIFT) \| \
	46	((partnum) << MIDR_PARTNUM_SHIFT))
	47
	48	#define MIDR_CPU_VAR_REV(var, rev) \
	49	(((var) << MIDR_VARIANT_SHIFT) \| (rev))
	50
	51	#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK \| MIDR_PARTNUM_MASK \| \
	52	MIDR_ARCHITECTURE_MASK)
	53
	54	#define ARM_CPU_IMP_ARM 0x41
	55	#define ARM_CPU_IMP_APM 0x50
	56	#define ARM_CPU_IMP_CAVIUM 0x43
	57	#define ARM_CPU_IMP_BRCM 0x42
	58	#define ARM_CPU_IMP_QCOM 0x51
	59	#define ARM_CPU_IMP_NVIDIA 0x4E
	60	#define ARM_CPU_IMP_FUJITSU 0x46
	61	#define ARM_CPU_IMP_HISI 0x48
	62	#define ARM_CPU_IMP_APPLE 0x61
ffc1df3d	63	#define ARM_CPU_IMP_AMPERE 0xC0
1cebd7f7	64	#define ARM_CPU_IMP_MICROSOFT 0x6D
1314376d AS	65
	66	#define ARM_CPU_PART_AEM_V8 0xD0F
	67	#define ARM_CPU_PART_FOUNDATION 0xD00
	68	#define ARM_CPU_PART_CORTEX_A57 0xD07
	69	#define ARM_CPU_PART_CORTEX_A72 0xD08
	70	#define ARM_CPU_PART_CORTEX_A53 0xD03
	71	#define ARM_CPU_PART_CORTEX_A73 0xD09
	72	#define ARM_CPU_PART_CORTEX_A75 0xD0A
	73	#define ARM_CPU_PART_CORTEX_A35 0xD04
	74	#define ARM_CPU_PART_CORTEX_A55 0xD05
	75	#define ARM_CPU_PART_CORTEX_A76 0xD0B
	76	#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
	77	#define ARM_CPU_PART_CORTEX_A77 0xD0D
	78	#define ARM_CPU_PART_NEOVERSE_V1 0xD40
	79	#define ARM_CPU_PART_CORTEX_A78 0xD41
278aaba2	80	#define ARM_CPU_PART_CORTEX_A78AE 0xD42
1314376d AS	81	#define ARM_CPU_PART_CORTEX_X1 0xD44
1314376d AS	82	#define ARM_CPU_PART_CORTEX_A510 0xD46
fad8afdc	83	#define ARM_CPU_PART_CORTEX_A520 0xD80
1314376d	84	#define ARM_CPU_PART_CORTEX_A710 0xD47
8c51e8f4	85	#define ARM_CPU_PART_CORTEX_A715 0xD4D
1314376d AS	86	#define ARM_CPU_PART_CORTEX_X2 0xD48
	87	#define ARM_CPU_PART_NEOVERSE_N2 0xD49
	88	#define ARM_CPU_PART_CORTEX_A78C 0xD4B
dc6abbbd ACM	89	#define ARM_CPU_PART_NEOVERSE_V2 0xD4F
	90	#define ARM_CPU_PART_CORTEX_X4 0xD82
	91	#define ARM_CPU_PART_NEOVERSE_V3 0xD84
1314376d	92
fad8afdc NK	93	#define APM_CPU_PART_XGENE 0x000
fad8afdc NK	94	#define APM_CPU_VAR_POTENZA 0x00
1314376d AS	95
	96	#define CAVIUM_CPU_PART_THUNDERX 0x0A1
	97	#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
	98	#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
	99	#define CAVIUM_CPU_PART_THUNDERX2 0x0AF
	100	/* OcteonTx2 series */
	101	#define CAVIUM_CPU_PART_OCTX2_98XX 0x0B1
	102	#define CAVIUM_CPU_PART_OCTX2_96XX 0x0B2
	103	#define CAVIUM_CPU_PART_OCTX2_95XX 0x0B3
	104	#define CAVIUM_CPU_PART_OCTX2_95XXN 0x0B4
	105	#define CAVIUM_CPU_PART_OCTX2_95XXMM 0x0B5
	106	#define CAVIUM_CPU_PART_OCTX2_95XXO 0x0B6
	107
	108	#define BRCM_CPU_PART_BRAHMA_B53 0x100
	109	#define BRCM_CPU_PART_VULCAN 0x516
	110
	111	#define QCOM_CPU_PART_FALKOR_V1 0x800
	112	#define QCOM_CPU_PART_FALKOR 0xC00
	113	#define QCOM_CPU_PART_KRYO 0x200
	114	#define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800
	115	#define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801
	116	#define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803
	117	#define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804
	118	#define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805
	119
	120	#define NVIDIA_CPU_PART_DENVER 0x003
	121	#define NVIDIA_CPU_PART_CARMEL 0x004
	122
	123	#define FUJITSU_CPU_PART_A64FX 0x001
	124
	125	#define HISI_CPU_PART_TSV110 0xD01
	126
	127	#define APPLE_CPU_PART_M1_ICESTORM 0x022
	128	#define APPLE_CPU_PART_M1_FIRESTORM 0x023
37402d5d ACM	129	#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024
	130	#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025
	131	#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
	132	#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
8c51e8f4 ACM	133	#define APPLE_CPU_PART_M2_BLIZZARD 0x032
8c51e8f4 ACM	134	#define APPLE_CPU_PART_M2_AVALANCHE 0x033
963293ff ACM	135	#define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034
	136	#define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035
	137	#define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038
	138	#define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039
1314376d	139
ffc1df3d ACM	140	#define AMPERE_CPU_PART_AMPERE1 0xAC3
ffc1df3d ACM	141
1cebd7f7 NK	142	#define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */
1cebd7f7 NK	143
1314376d AS	144	#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
	145	#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
	146	#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
	147	#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
	148	#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
	149	#define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
	150	#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
	151	#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
	152	#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
	153	#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
	154	#define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1)
	155	#define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)
278aaba2	156	#define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)
1314376d AS	157	#define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
1314376d AS	158	#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
fad8afdc	159	#define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520)
1314376d	160	#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
8c51e8f4	161	#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715)
1314376d AS	162	#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
	163	#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
	164	#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
dc6abbbd ACM	165	#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
	166	#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
	167	#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
1314376d AS	168	#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
	169	#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
	170	#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
	171	#define MIDR_OCTX2_98XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_98XX)
	172	#define MIDR_OCTX2_96XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_96XX)
	173	#define MIDR_OCTX2_95XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XX)
	174	#define MIDR_OCTX2_95XXN MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXN)
	175	#define MIDR_OCTX2_95XXMM MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXMM)
	176	#define MIDR_OCTX2_95XXO MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXO)
	177	#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
	178	#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
	179	#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
	180	#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
	181	#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
	182	#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
	183	#define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD)
	184	#define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)
	185	#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)
	186	#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)
	187	#define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)
	188	#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
	189	#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
	190	#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
	191	#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
	192	#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
	193	#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
37402d5d ACM	194	#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
	195	#define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)
	196	#define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)
	197	#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)
8c51e8f4 ACM	198	#define MIDR_APPLE_M2_BLIZZARD MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD)
8c51e8f4 ACM	199	#define MIDR_APPLE_M2_AVALANCHE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE)
963293ff ACM	200	#define MIDR_APPLE_M2_BLIZZARD_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_PRO)
	201	#define MIDR_APPLE_M2_AVALANCHE_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO)
	202	#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
	203	#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
ffc1df3d	204	#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
1cebd7f7	205	#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)
1314376d AS	206
	207	/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
	208	#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
	209	#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
	210	#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 \| TCR_NFD0)
	211
	212	#ifndef __ASSEMBLY__
	213
37402d5d	214	#include <asm/sysreg.h>
1314376d AS	215
	216	#define read_cpuid(reg) read_sysreg_s(SYS_ ## reg)
	217
	218	/*
	219	* Represent a range of MIDR values for a given CPU model and a
	220	* range of variant/revision values.
	221	*
	222	* @model - CPU model as defined by MIDR_CPU_MODEL
	223	* @rv_min - Minimum value for the revision/variant as defined by
	224	* MIDR_CPU_VAR_REV
	225	* @rv_max - Maximum value for the variant/revision for the range.
	226	*/
	227	struct midr_range {
	228	u32 model;
	229	u32 rv_min;
	230	u32 rv_max;
	231	};
	232
	233	#define MIDR_RANGE(m, v_min, r_min, v_max, r_max) \
	234	{ \
	235	.model = m, \
	236	.rv_min = MIDR_CPU_VAR_REV(v_min, r_min), \
	237	.rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \
	238	}
	239
	240	#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
	241	#define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)
	242	#define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
	243
	244	static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,
	245	u32 rv_max)
	246	{
	247	u32 _model = midr & MIDR_CPU_MODEL_MASK;
	248	u32 rv = midr & (MIDR_REVISION_MASK \| MIDR_VARIANT_MASK);
	249
	250	return _model == model && rv >= rv_min && rv <= rv_max;
	251	}
	252
	253	static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)
	254	{
	255	return midr_is_cpu_model_range(midr, range->model,
	256	range->rv_min, range->rv_max);
	257	}
	258
	259	static inline bool
	260	is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
	261	{
	262	while (ranges->model)
	263	if (is_midr_in_range(midr, ranges++))
	264	return true;
	265	return false;
	266	}
	267
	268	/*
	269	* The CPU ID never changes at run time, so we might as well tell the
	270	* compiler that it's constant. Use this function to read the CPU ID
	271	* rather than directly reading processor_id or read_cpuid() directly.
	272	*/
	273	static inline u32 __attribute_const__ read_cpuid_id(void)
	274	{
	275	return read_cpuid(MIDR_EL1);
	276	}
	277
	278	static inline u64 __attribute_const__ read_cpuid_mpidr(void)
279	{
280	return read_cpuid(MPIDR_EL1);
281	}
282
283	static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
284	{
285	return MIDR_IMPLEMENTOR(read_cpuid_id());
286	}
287
288	static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
289	{
290	return MIDR_PARTNUM(read_cpuid_id());
291	}
292
293	static inline u32 __attribute_const__ read_cpuid_cachetype(void)
294	{
295	return read_cpuid(CTR_EL0);
296	}
297	#endif /* __ASSEMBLY__ */
298
299	#endif