[linux-2.6-block.git] / sound / x86 / intel_hdmi_lpe_audio.h

/*
 *   intel_hdmi_lpe_audio.h - Intel HDMI LPE audio driver
 *
 *  Copyright (C) 2016 Intel Corp
 *  Authors:	Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
 *		Ramesh Babu K V <ramesh.babu@intel.com>
 *		Vaibhav Agarwal <vaibhav.agarwal@intel.com>
 *		Jerome Anand <jerome.anand@intel.com>
 *		Aravind Siddappaji <aravindx.siddappaji@intel.com>
 *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; version 2 of the License.
 *
 *  This program is distributed in the hope that it will be useful, but
 *  WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  General Public License for more details.
 *
 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 */
#ifndef __INTEL_HDMI_LPE_AUDIO_H
#define __INTEL_HDMI_LPE_AUDIO_H

#define HAD_MIN_CHANNEL		2
#define HAD_MAX_CHANNEL		8
#define HAD_NUM_OF_RING_BUFS	4

/* max 20bit address, aligned to 64 */
#define HAD_MAX_BUFFER		((1024 * 1024 - 1) & ~0x3f)
#define HAD_DEFAULT_BUFFER	(600 * 1024) /* default prealloc size */
#define HAD_MAX_PERIODS		256	/* arbitrary, but should suffice */
#define HAD_MIN_PERIODS		1
#define HAD_MAX_PERIOD_BYTES	((HAD_MAX_BUFFER / HAD_MIN_PERIODS) & ~0x3f)
#define HAD_MIN_PERIOD_BYTES	1024	/* might be smaller */
#define HAD_FIFO_SIZE		0 /* fifo not being used */
#define MAX_SPEAKERS		8

#define AUD_SAMPLE_RATE_32	32000
#define AUD_SAMPLE_RATE_44_1	44100
#define AUD_SAMPLE_RATE_48	48000
#define AUD_SAMPLE_RATE_88_2	88200
#define AUD_SAMPLE_RATE_96	96000
#define AUD_SAMPLE_RATE_176_4	176400
#define AUD_SAMPLE_RATE_192	192000

#define HAD_MIN_RATE		AUD_SAMPLE_RATE_32
#define HAD_MAX_RATE		AUD_SAMPLE_RATE_192

#define DIS_SAMPLE_RATE_25_2	25200
#define DIS_SAMPLE_RATE_27	27000
#define DIS_SAMPLE_RATE_54	54000
#define DIS_SAMPLE_RATE_74_25	74250
#define DIS_SAMPLE_RATE_148_5	148500
#define HAD_REG_WIDTH		0x08
#define HAD_MAX_DIP_WORDS		16

/* DP Link Rates */
#define DP_2_7_GHZ			270000
#define DP_1_62_GHZ			162000

/* Maud Values */
#define AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL		1988
#define AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL		2740
#define AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL		2982
#define AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL		5480
#define AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL		5965
#define AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL		10961
#define HAD_MAX_RATE_DP_2_7_MAUD_VAL			11930
#define AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL		3314
#define AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL		4567
#define AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL		4971
#define AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL		9134
#define AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL		9942
#define AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL		18268
#define HAD_MAX_RATE_DP_1_62_MAUD_VAL			19884

/* Naud Value */
#define DP_NAUD_VAL					32768

/* HDMI Controller register offsets - audio domain common */
/* Base address for below regs = 0x65000 */
enum hdmi_ctrl_reg_offset_common {
	AUDIO_HDMI_CONFIG_A = 0x000,
	AUDIO_HDMI_CONFIG_B = 0x800,
	AUDIO_HDMI_CONFIG_C = 0x900,
};
/* HDMI controller register offsets */
enum hdmi_ctrl_reg_offset {
	AUD_CONFIG		= 0x0,
	AUD_CH_STATUS_0		= 0x08,
	AUD_CH_STATUS_1		= 0x0C,
	AUD_HDMI_CTS		= 0x10,
	AUD_N_ENABLE		= 0x14,
	AUD_SAMPLE_RATE		= 0x18,
	AUD_BUF_CONFIG		= 0x20,
	AUD_BUF_CH_SWAP		= 0x24,
	AUD_BUF_A_ADDR		= 0x40,
	AUD_BUF_A_LENGTH	= 0x44,
	AUD_BUF_B_ADDR		= 0x48,
	AUD_BUF_B_LENGTH	= 0x4c,
	AUD_BUF_C_ADDR		= 0x50,
	AUD_BUF_C_LENGTH	= 0x54,
	AUD_BUF_D_ADDR		= 0x58,
	AUD_BUF_D_LENGTH	= 0x5c,
	AUD_CNTL_ST		= 0x60,
	AUD_HDMI_STATUS		= 0x64, /* v2 */
	AUD_HDMIW_INFOFR	= 0x68, /* v2 */
};

/* Audio configuration */
union aud_cfg {
	struct {
		u32 aud_en:1;
		u32 layout:1;		/* LAYOUT[01], see below */
		u32 fmt:2;
		u32 num_ch:3;
		u32 set:1;
		u32 flat:1;
		u32 val_bit:1;
		u32 user_bit:1;
		u32 underrun:1;		/* 0: send null packets,
					 * 1: send silence stream
					 */
		u32 packet_mode:1;	/* 0: 32bit container, 1: 16bit */
		u32 left_align:1;	/* 0: MSB bits 0-23, 1: bits 8-31 */
		u32 bogus_sample:1;	/* bogus sample for odd channels */
		u32 dp_modei:1;		/* 0: HDMI, 1: DP */
		u32 rsvd:16;
	} regx;
	u32 regval;
};

#define AUD_CONFIG_VALID_BIT			(1 << 9)
#define AUD_CONFIG_DP_MODE			(1 << 15)
#define AUD_CONFIG_CH_MASK	0x70
#define LAYOUT0			0		/* interleaved stereo */
#define LAYOUT1			1		/* for channels > 2 */

/* Audio Channel Status 0 Attributes */
union aud_ch_status_0 {
	struct {
		u32 ch_status:1;
		u32 lpcm_id:1;
		u32 cp_info:1;
		u32 format:3;
		u32 mode:2;
		u32 ctg_code:8;
		u32 src_num:4;
		u32 ch_num:4;
		u32 samp_freq:4;	/* CH_STATUS_MAP_XXX */
		u32 clk_acc:2;
		u32 rsvd:2;
	} regx;
	u32 regval;
};

/* samp_freq values - Sampling rate as per IEC60958 Ver 3 */
#define CH_STATUS_MAP_32KHZ	0x3
#define CH_STATUS_MAP_44KHZ	0x0
#define CH_STATUS_MAP_48KHZ	0x2
#define CH_STATUS_MAP_88KHZ	0x8
#define CH_STATUS_MAP_96KHZ	0xA
#define CH_STATUS_MAP_176KHZ	0xC
#define CH_STATUS_MAP_192KHZ	0xE

/* Audio Channel Status 1 Attributes */
union aud_ch_status_1 {
	struct {
		u32 max_wrd_len:1;
		u32 wrd_len:3;
		u32 rsvd:28;
	} regx;
	u32 regval;
};

#define MAX_SMPL_WIDTH_20	0x0
#define MAX_SMPL_WIDTH_24	0x1
#define SMPL_WIDTH_16BITS	0x1
#define SMPL_WIDTH_24BITS	0x5

/* CTS register */
union aud_hdmi_cts {
	struct {
		u32 cts_val:24;
		u32 en_cts_prog:1;
		u32 rsvd:7;
	} regx;
	u32 regval;
};

/* N register */
union aud_hdmi_n_enable {
	struct {
		u32 n_val:24;
		u32 en_n_prog:1;
		u32 rsvd:7;
	} regx;
	u32 regval;
};

/* Audio Buffer configurations */
union aud_buf_config {
	struct {
		u32 audio_fifo_watermark:8;
		u32 dma_fifo_watermark:3;
		u32 rsvd0:5;
		u32 aud_delay:8;
		u32 rsvd1:8;
	} regx;
	u32 regval;
};

#define FIFO_THRESHOLD		0xFE
#define DMA_FIFO_THRESHOLD	0x7

/* Audio Sample Swapping offset */
union aud_buf_ch_swap {
	struct {
		u32 first_0:3;
		u32 second_0:3;
		u32 first_1:3;
		u32 second_1:3;
		u32 first_2:3;
		u32 second_2:3;
		u32 first_3:3;
		u32 second_3:3;
		u32 rsvd:8;
	} regx;
	u32 regval;
};

#define SWAP_LFE_CENTER		0x00fac4c8	/* octal 76543210 */

/* Address for Audio Buffer */
union aud_buf_addr {
	struct {
		u32 valid:1;
		u32 intr_en:1;
		u32 rsvd:4;
		u32 addr:26;
	} regx;
	u32 regval;
};

#define AUD_BUF_VALID		(1U << 0)
#define AUD_BUF_INTR_EN		(1U << 1)

/* Length of Audio Buffer */
union aud_buf_len {
	struct {
		u32 buf_len:20;
		u32 rsvd:12;
	} regx;
	u32 regval;
};

/* Audio Control State Register offset */
union aud_ctrl_st {
	struct {
		u32 ram_addr:4;
		u32 eld_ack:1;
		u32 eld_addr:4;
		u32 eld_buf_size:5;
		u32 eld_valid:1;
		u32 cp_ready:1;
		u32 dip_freq:2;
		u32 dip_idx:3;
		u32 dip_en_sta:4;
		u32 rsvd:7;
	} regx;
	u32 regval;
};

/* Audio HDMI Widget Data Island Packet offset */
union aud_info_frame1 {
	struct {
		u32 pkt_type:8;
		u32 ver_num:8;
		u32 len:5;
		u32 rsvd:11;
	} regx;
	u32 regval;
};

#define HDMI_INFO_FRAME_WORD1	0x000a0184
#define DP_INFO_FRAME_WORD1	0x00441b84

/* DIP frame 2 */
union aud_info_frame2 {
	struct {
		u32 chksum:8;
		u32 chnl_cnt:3;
		u32 rsvd0:1;
		u32 coding_type:4;
		u32 smpl_size:2;
		u32 smpl_freq:3;
		u32 rsvd1:3;
		u32 format:8;
	} regx;
	u32 regval;
};

/* DIP frame 3 */
union aud_info_frame3 {
	struct {
		u32 chnl_alloc:8;
		u32 rsvd0:3;
		u32 lsv:4;
		u32 dm_inh:1;
		u32 rsvd1:16;
	} regx;
	u32 regval;
};

#define VALID_DIP_WORDS		3

/* AUD_HDMI_STATUS bits */
#define HDMI_AUDIO_UNDERRUN		(1U << 31)
#define HDMI_AUDIO_BUFFER_DONE		(1U << 29)

/* AUD_HDMI_STATUS register mask */
#define AUD_HDMI_STATUS_MASK_UNDERRUN	0xC0000000
#define AUD_HDMI_STATUS_MASK_SRDBG	0x00000002
#define AUD_HDMI_STATUSG_MASK_FUNCRST	0x00000001

#endif
Commit	Line	Data
287599cf JA	1	/*
	2	* intel_hdmi_lpe_audio.h - Intel HDMI LPE audio driver
	3	*
	4	* Copyright (C) 2016 Intel Corp
	5	* Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
	6	* Ramesh Babu K V <ramesh.babu@intel.com>
	7	* Vaibhav Agarwal <vaibhav.agarwal@intel.com>
	8	* Jerome Anand <jerome.anand@intel.com>
	9	* Aravind Siddappaji <aravindx.siddappaji@intel.com>
	10	* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; version 2 of the License.
	15	*
	16	* This program is distributed in the hope that it will be useful, but
	17	* WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	19	* General Public License for more details.
	20	*
	21	* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	22	*/
	23	#ifndef __INTEL_HDMI_LPE_AUDIO_H
	24	#define __INTEL_HDMI_LPE_AUDIO_H
	25
287599cf JA	26	#define HAD_MIN_CHANNEL 2
	27	#define HAD_MAX_CHANNEL 8
	28	#define HAD_NUM_OF_RING_BUFS 4
	29
e1b239f3 TI	30	/* max 20bit address, aligned to 64 */
	31	#define HAD_MAX_BUFFER ((1024 * 1024 - 1) & ~0x3f)
	32	#define HAD_DEFAULT_BUFFER (600 * 1024) /* default prealloc size */
	33	#define HAD_MAX_PERIODS 256 /* arbitrary, but should suffice */
8d48c016	34	#define HAD_MIN_PERIODS 1
e1b239f3 TI	35	#define HAD_MAX_PERIOD_BYTES ((HAD_MAX_BUFFER / HAD_MIN_PERIODS) & ~0x3f)
e1b239f3 TI	36	#define HAD_MIN_PERIOD_BYTES 1024 /* might be smaller */
287599cf JA	37	#define HAD_FIFO_SIZE 0 /* fifo not being used */
	38	#define MAX_SPEAKERS 8
	39
	40	#define AUD_SAMPLE_RATE_32 32000
	41	#define AUD_SAMPLE_RATE_44_1 44100
	42	#define AUD_SAMPLE_RATE_48 48000
	43	#define AUD_SAMPLE_RATE_88_2 88200
	44	#define AUD_SAMPLE_RATE_96 96000
	45	#define AUD_SAMPLE_RATE_176_4 176400
	46	#define AUD_SAMPLE_RATE_192 192000
	47
	48	#define HAD_MIN_RATE AUD_SAMPLE_RATE_32
	49	#define HAD_MAX_RATE AUD_SAMPLE_RATE_192
	50
	51	#define DIS_SAMPLE_RATE_25_2 25200
	52	#define DIS_SAMPLE_RATE_27 27000
	53	#define DIS_SAMPLE_RATE_54 54000
	54	#define DIS_SAMPLE_RATE_74_25 74250
	55	#define DIS_SAMPLE_RATE_148_5 148500
	56	#define HAD_REG_WIDTH 0x08
287599cf	57	#define HAD_MAX_DIP_WORDS 16
287599cf	58
964ca808 PLB	59	/* DP Link Rates */
	60	#define DP_2_7_GHZ 270000
	61	#define DP_1_62_GHZ 162000
	62
	63	/* Maud Values */
	64	#define AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL 1988
	65	#define AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL 2740
	66	#define AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL 2982
	67	#define AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL 5480
	68	#define AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL 5965
	69	#define AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL 10961
	70	#define HAD_MAX_RATE_DP_2_7_MAUD_VAL 11930
	71	#define AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL 3314
	72	#define AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL 4567
	73	#define AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL 4971
	74	#define AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL 9134
	75	#define AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL 9942
	76	#define AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL 18268
	77	#define HAD_MAX_RATE_DP_1_62_MAUD_VAL 19884
	78
	79	/* Naud Value */
	80	#define DP_NAUD_VAL 32768
	81
287599cf JA	82	/* HDMI Controller register offsets - audio domain common */
	83	/* Base address for below regs = 0x65000 */
	84	enum hdmi_ctrl_reg_offset_common {
03c34377	85	AUDIO_HDMI_CONFIG_A = 0x000,
287599cf JA	86	AUDIO_HDMI_CONFIG_B = 0x800,
	87	AUDIO_HDMI_CONFIG_C = 0x900,
	88	};
	89	/* HDMI controller register offsets */
4151ee84	90	enum hdmi_ctrl_reg_offset {
287599cf JA	91	AUD_CONFIG = 0x0,
	92	AUD_CH_STATUS_0 = 0x08,
	93	AUD_CH_STATUS_1 = 0x0C,
	94	AUD_HDMI_CTS = 0x10,
	95	AUD_N_ENABLE = 0x14,
	96	AUD_SAMPLE_RATE = 0x18,
	97	AUD_BUF_CONFIG = 0x20,
	98	AUD_BUF_CH_SWAP = 0x24,
	99	AUD_BUF_A_ADDR = 0x40,
	100	AUD_BUF_A_LENGTH = 0x44,
	101	AUD_BUF_B_ADDR = 0x48,
	102	AUD_BUF_B_LENGTH = 0x4c,
	103	AUD_BUF_C_ADDR = 0x50,
	104	AUD_BUF_C_LENGTH = 0x54,
	105	AUD_BUF_D_ADDR = 0x58,
	106	AUD_BUF_D_LENGTH = 0x5c,
	107	AUD_CNTL_ST = 0x60,
4151ee84 TI	108	AUD_HDMI_STATUS = 0x64, /* v2 */
4151ee84 TI	109	AUD_HDMIW_INFOFR = 0x68, /* v2 */
287599cf JA	110	};
287599cf JA	111
7ceba75f	112	/* Audio configuration */
287599cf	113	union aud_cfg {
287599cf JA	114	struct {
287599cf JA	115	u32 aud_en:1;
77531bee	116	u32 layout:1; /* LAYOUT[01], see below */
287599cf JA	117	u32 fmt:2;
	118	u32 num_ch:3;
	119	u32 set:1;
	120	u32 flat:1;
	121	u32 val_bit:1;
	122	u32 user_bit:1;
77531bee TI	123	u32 underrun:1; /* 0: send null packets,
	124	* 1: send silence stream
	125	*/
	126	u32 packet_mode:1; /* 0: 32bit container, 1: 16bit */
	127	u32 left_align:1; /* 0: MSB bits 0-23, 1: bits 8-31 */
	128	u32 bogus_sample:1; /* bogus sample for odd channels */
	129	u32 dp_modei:1; /* 0: HDMI, 1: DP */
287599cf	130	u32 rsvd:16;
7ceba75f TI	131	} regx;
7ceba75f TI	132	u32 regval;
287599cf JA	133	};
287599cf JA	134
03c34377 TI	135	#define AUD_CONFIG_VALID_BIT (1 << 9)
03c34377 TI	136	#define AUD_CONFIG_DP_MODE (1 << 15)
77531bee TI	137	#define AUD_CONFIG_CH_MASK 0x70
	138	#define LAYOUT0 0 /* interleaved stereo */
	139	#define LAYOUT1 1 /* for channels > 2 */
03c34377	140
7ceba75f	141	/* Audio Channel Status 0 Attributes */
287599cf JA	142	union aud_ch_status_0 {
	143	struct {
	144	u32 ch_status:1;
	145	u32 lpcm_id:1;
	146	u32 cp_info:1;
	147	u32 format:3;
	148	u32 mode:2;
	149	u32 ctg_code:8;
	150	u32 src_num:4;
	151	u32 ch_num:4;
77531bee	152	u32 samp_freq:4; /* CH_STATUS_MAP_XXX */
287599cf JA	153	u32 clk_acc:2;
287599cf JA	154	u32 rsvd:2;
7ceba75f TI	155	} regx;
7ceba75f TI	156	u32 regval;
287599cf JA	157	};
287599cf JA	158
77531bee TI	159	/* samp_freq values - Sampling rate as per IEC60958 Ver 3 */
	160	#define CH_STATUS_MAP_32KHZ 0x3
	161	#define CH_STATUS_MAP_44KHZ 0x0
	162	#define CH_STATUS_MAP_48KHZ 0x2
	163	#define CH_STATUS_MAP_88KHZ 0x8
	164	#define CH_STATUS_MAP_96KHZ 0xA
	165	#define CH_STATUS_MAP_176KHZ 0xC
	166	#define CH_STATUS_MAP_192KHZ 0xE
	167
7ceba75f	168	/* Audio Channel Status 1 Attributes */
287599cf JA	169	union aud_ch_status_1 {
	170	struct {
	171	u32 max_wrd_len:1;
	172	u32 wrd_len:3;
	173	u32 rsvd:28;
7ceba75f TI	174	} regx;
7ceba75f TI	175	u32 regval;
287599cf JA	176	};
287599cf JA	177
77531bee TI	178	#define MAX_SMPL_WIDTH_20 0x0
	179	#define MAX_SMPL_WIDTH_24 0x1
	180	#define SMPL_WIDTH_16BITS 0x1
	181	#define SMPL_WIDTH_24BITS 0x5
	182
7ceba75f	183	/* CTS register */
287599cf	184	union aud_hdmi_cts {
287599cf JA	185	struct {
	186	u32 cts_val:24;
	187	u32 en_cts_prog:1;
	188	u32 rsvd:7;
7ceba75f TI	189	} regx;
7ceba75f TI	190	u32 regval;
287599cf JA	191	};
287599cf JA	192
7ceba75f	193	/* N register */
287599cf	194	union aud_hdmi_n_enable {
287599cf JA	195	struct {
	196	u32 n_val:24;
	197	u32 en_n_prog:1;
	198	u32 rsvd:7;
7ceba75f TI	199	} regx;
7ceba75f TI	200	u32 regval;
287599cf JA	201	};
287599cf JA	202
7ceba75f	203	/* Audio Buffer configurations */
287599cf	204	union aud_buf_config {
287599cf JA	205	struct {
	206	u32 audio_fifo_watermark:8;
	207	u32 dma_fifo_watermark:3;
	208	u32 rsvd0:5;
	209	u32 aud_delay:8;
	210	u32 rsvd1:8;
7ceba75f TI	211	} regx;
7ceba75f TI	212	u32 regval;
287599cf JA	213	};
287599cf JA	214
77531bee TI	215	#define FIFO_THRESHOLD 0xFE
	216	#define DMA_FIFO_THRESHOLD 0x7
	217
7ceba75f	218	/* Audio Sample Swapping offset */
287599cf JA	219	union aud_buf_ch_swap {
	220	struct {
	221	u32 first_0:3;
	222	u32 second_0:3;
	223	u32 first_1:3;
	224	u32 second_1:3;
	225	u32 first_2:3;
	226	u32 second_2:3;
	227	u32 first_3:3;
	228	u32 second_3:3;
	229	u32 rsvd:8;
7ceba75f TI	230	} regx;
7ceba75f TI	231	u32 regval;
287599cf JA	232	};
287599cf JA	233
77531bee TI	234	#define SWAP_LFE_CENTER 0x00fac4c8 /* octal 76543210 */
77531bee TI	235
7ceba75f	236	/* Address for Audio Buffer */
287599cf JA	237	union aud_buf_addr {
	238	struct {
	239	u32 valid:1;
	240	u32 intr_en:1;
	241	u32 rsvd:4;
	242	u32 addr:26;
7ceba75f TI	243	} regx;
7ceba75f TI	244	u32 regval;
287599cf JA	245	};
287599cf JA	246
e1b239f3 TI	247	#define AUD_BUF_VALID (1U << 0)
	248	#define AUD_BUF_INTR_EN (1U << 1)
	249
7ceba75f	250	/* Length of Audio Buffer */
287599cf JA	251	union aud_buf_len {
	252	struct {
	253	u32 buf_len:20;
	254	u32 rsvd:12;
7ceba75f TI	255	} regx;
7ceba75f TI	256	u32 regval;
287599cf JA	257	};
287599cf JA	258
7ceba75f	259	/* Audio Control State Register offset */
287599cf JA	260	union aud_ctrl_st {
	261	struct {
	262	u32 ram_addr:4;
	263	u32 eld_ack:1;
	264	u32 eld_addr:4;
	265	u32 eld_buf_size:5;
	266	u32 eld_valid:1;
	267	u32 cp_ready:1;
	268	u32 dip_freq:2;
	269	u32 dip_idx:3;
	270	u32 dip_en_sta:4;
	271	u32 rsvd:7;
7ceba75f TI	272	} regx;
7ceba75f TI	273	u32 regval;
287599cf JA	274	};
287599cf JA	275
7ceba75f	276	/* Audio HDMI Widget Data Island Packet offset */
287599cf JA	277	union aud_info_frame1 {
	278	struct {
	279	u32 pkt_type:8;
	280	u32 ver_num:8;
	281	u32 len:5;
	282	u32 rsvd:11;
7ceba75f TI	283	} regx;
7ceba75f TI	284	u32 regval;
287599cf JA	285	};
287599cf JA	286
77531bee TI	287	#define HDMI_INFO_FRAME_WORD1 0x000a0184
	288	#define DP_INFO_FRAME_WORD1 0x00441b84
	289
7ceba75f	290	/* DIP frame 2 */
287599cf JA	291	union aud_info_frame2 {
	292	struct {
	293	u32 chksum:8;
	294	u32 chnl_cnt:3;
	295	u32 rsvd0:1;
	296	u32 coding_type:4;
	297	u32 smpl_size:2;
	298	u32 smpl_freq:3;
	299	u32 rsvd1:3;
	300	u32 format:8;
7ceba75f TI	301	} regx;
7ceba75f TI	302	u32 regval;
287599cf JA	303	};
287599cf JA	304
7ceba75f	305	/* DIP frame 3 */
287599cf JA	306	union aud_info_frame3 {
	307	struct {
	308	u32 chnl_alloc:8;
	309	u32 rsvd0:3;
	310	u32 lsv:4;
	311	u32 dm_inh:1;
	312	u32 rsvd1:16;
7ceba75f TI	313	} regx;
7ceba75f TI	314	u32 regval;
287599cf JA	315	};
287599cf JA	316
77531bee TI	317	#define VALID_DIP_WORDS 3
77531bee TI	318
03c34377 TI	319	/* AUD_HDMI_STATUS bits */
	320	#define HDMI_AUDIO_UNDERRUN (1U << 31)
	321	#define HDMI_AUDIO_BUFFER_DONE (1U << 29)
287599cf	322
03c34377	323	/* AUD_HDMI_STATUS register mask */
77531bee TI	324	#define AUD_HDMI_STATUS_MASK_UNDERRUN 0xC0000000
	325	#define AUD_HDMI_STATUS_MASK_SRDBG 0x00000002
	326	#define AUD_HDMI_STATUSG_MASK_FUNCRST 0x00000001
287599cf	327
287599cf	328	#endif