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5dab11d8 JA |
1 | /* |
2 | * intel_hdmi_audio.c - Intel HDMI audio driver | |
3 | * | |
4 | * Copyright (C) 2016 Intel Corp | |
5 | * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com> | |
6 | * Ramesh Babu K V <ramesh.babu@intel.com> | |
7 | * Vaibhav Agarwal <vaibhav.agarwal@intel.com> | |
8 | * Jerome Anand <jerome.anand@intel.com> | |
9 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; version 2 of the License. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
21 | * ALSA driver for Intel HDMI audio | |
22 | */ | |
23 | ||
03c34377 | 24 | #include <linux/types.h> |
5dab11d8 JA |
25 | #include <linux/platform_device.h> |
26 | #include <linux/io.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/module.h> | |
da864809 | 29 | #include <linux/interrupt.h> |
03c34377 | 30 | #include <linux/pm_runtime.h> |
5dab11d8 | 31 | #include <asm/cacheflush.h> |
5dab11d8 | 32 | #include <sound/core.h> |
03c34377 TI |
33 | #include <sound/asoundef.h> |
34 | #include <sound/pcm.h> | |
5dab11d8 JA |
35 | #include <sound/pcm_params.h> |
36 | #include <sound/initval.h> | |
37 | #include <sound/control.h> | |
03c34377 | 38 | #include <drm/drm_edid.h> |
da864809 | 39 | #include <drm/intel_lpe_audio.h> |
5dab11d8 JA |
40 | #include "intel_hdmi_audio.h" |
41 | ||
5dab11d8 JA |
42 | /*standard module options for ALSA. This module supports only one card*/ |
43 | static int hdmi_card_index = SNDRV_DEFAULT_IDX1; | |
44 | static char *hdmi_card_id = SNDRV_DEFAULT_STR1; | |
5dab11d8 JA |
45 | |
46 | module_param_named(index, hdmi_card_index, int, 0444); | |
47 | MODULE_PARM_DESC(index, | |
48 | "Index value for INTEL Intel HDMI Audio controller."); | |
49 | module_param_named(id, hdmi_card_id, charp, 0444); | |
50 | MODULE_PARM_DESC(id, | |
51 | "ID string for INTEL Intel HDMI Audio controller."); | |
52 | ||
53 | /* | |
54 | * ELD SA bits in the CEA Speaker Allocation data block | |
55 | */ | |
4a5ddb2c | 56 | static const int eld_speaker_allocation_bits[] = { |
5dab11d8 JA |
57 | [0] = FL | FR, |
58 | [1] = LFE, | |
59 | [2] = FC, | |
60 | [3] = RL | RR, | |
61 | [4] = RC, | |
62 | [5] = FLC | FRC, | |
63 | [6] = RLC | RRC, | |
64 | /* the following are not defined in ELD yet */ | |
65 | [7] = 0, | |
66 | }; | |
67 | ||
68 | /* | |
69 | * This is an ordered list! | |
70 | * | |
71 | * The preceding ones have better chances to be selected by | |
72 | * hdmi_channel_allocation(). | |
73 | */ | |
74 | static struct cea_channel_speaker_allocation channel_allocations[] = { | |
75 | /* channel: 7 6 5 4 3 2 1 0 */ | |
76 | { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, | |
77 | /* 2.1 */ | |
78 | { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, | |
79 | /* Dolby Surround */ | |
80 | { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, | |
81 | /* surround40 */ | |
82 | { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, | |
83 | /* surround41 */ | |
84 | { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, | |
85 | /* surround50 */ | |
86 | { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, | |
87 | /* surround51 */ | |
88 | { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, | |
89 | /* 6.1 */ | |
90 | { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, | |
91 | /* surround71 */ | |
92 | { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, | |
93 | ||
94 | { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, | |
95 | { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, | |
96 | { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, | |
97 | { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, | |
98 | { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, | |
99 | { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, | |
100 | { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, | |
101 | { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, | |
102 | { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, | |
103 | { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, | |
104 | { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, | |
105 | { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, | |
106 | { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, | |
107 | { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, | |
108 | { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, | |
109 | { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, | |
110 | { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, | |
111 | { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, | |
112 | { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, | |
113 | { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, | |
114 | { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, | |
115 | { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, | |
116 | { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, | |
117 | }; | |
118 | ||
4a5ddb2c | 119 | static const struct channel_map_table map_tables[] = { |
5dab11d8 JA |
120 | { SNDRV_CHMAP_FL, 0x00, FL }, |
121 | { SNDRV_CHMAP_FR, 0x01, FR }, | |
122 | { SNDRV_CHMAP_RL, 0x04, RL }, | |
123 | { SNDRV_CHMAP_RR, 0x05, RR }, | |
124 | { SNDRV_CHMAP_LFE, 0x02, LFE }, | |
125 | { SNDRV_CHMAP_FC, 0x03, FC }, | |
126 | { SNDRV_CHMAP_RLC, 0x06, RLC }, | |
127 | { SNDRV_CHMAP_RRC, 0x07, RRC }, | |
128 | {} /* terminator */ | |
129 | }; | |
130 | ||
131 | /* hardware capability structure */ | |
132 | static const struct snd_pcm_hardware snd_intel_hadstream = { | |
133 | .info = (SNDRV_PCM_INFO_INTERLEAVED | | |
134 | SNDRV_PCM_INFO_DOUBLE | | |
135 | SNDRV_PCM_INFO_MMAP| | |
136 | SNDRV_PCM_INFO_MMAP_VALID | | |
137 | SNDRV_PCM_INFO_BATCH), | |
138 | .formats = (SNDRV_PCM_FMTBIT_S24 | | |
139 | SNDRV_PCM_FMTBIT_U24), | |
140 | .rates = SNDRV_PCM_RATE_32000 | | |
141 | SNDRV_PCM_RATE_44100 | | |
142 | SNDRV_PCM_RATE_48000 | | |
143 | SNDRV_PCM_RATE_88200 | | |
144 | SNDRV_PCM_RATE_96000 | | |
145 | SNDRV_PCM_RATE_176400 | | |
146 | SNDRV_PCM_RATE_192000, | |
147 | .rate_min = HAD_MIN_RATE, | |
148 | .rate_max = HAD_MAX_RATE, | |
149 | .channels_min = HAD_MIN_CHANNEL, | |
150 | .channels_max = HAD_MAX_CHANNEL, | |
151 | .buffer_bytes_max = HAD_MAX_BUFFER, | |
152 | .period_bytes_min = HAD_MIN_PERIOD_BYTES, | |
153 | .period_bytes_max = HAD_MAX_PERIOD_BYTES, | |
154 | .periods_min = HAD_MIN_PERIODS, | |
155 | .periods_max = HAD_MAX_PERIODS, | |
156 | .fifo_size = HAD_FIFO_SIZE, | |
157 | }; | |
158 | ||
313d9f28 TI |
159 | /* Get the active PCM substream; |
160 | * Call had_substream_put() for unreferecing. | |
161 | * Don't call this inside had_spinlock, as it takes by itself | |
162 | */ | |
163 | static struct snd_pcm_substream * | |
164 | had_substream_get(struct snd_intelhad *intelhaddata) | |
165 | { | |
166 | struct snd_pcm_substream *substream; | |
167 | unsigned long flags; | |
168 | ||
169 | spin_lock_irqsave(&intelhaddata->had_spinlock, flags); | |
170 | substream = intelhaddata->stream_info.substream; | |
171 | if (substream) | |
172 | intelhaddata->stream_info.substream_refcount++; | |
173 | spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); | |
174 | return substream; | |
175 | } | |
176 | ||
177 | /* Unref the active PCM substream; | |
178 | * Don't call this inside had_spinlock, as it takes by itself | |
179 | */ | |
180 | static void had_substream_put(struct snd_intelhad *intelhaddata) | |
181 | { | |
182 | unsigned long flags; | |
183 | ||
184 | spin_lock_irqsave(&intelhaddata->had_spinlock, flags); | |
185 | intelhaddata->stream_info.substream_refcount--; | |
186 | spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); | |
187 | } | |
188 | ||
5dab11d8 | 189 | /* Register access functions */ |
da864809 TI |
190 | static inline void |
191 | mid_hdmi_audio_read(struct snd_intelhad *ctx, u32 reg, u32 *val) | |
5dab11d8 | 192 | { |
da864809 | 193 | *val = ioread32(ctx->mmio_start + ctx->had_config_offset + reg); |
5dab11d8 JA |
194 | } |
195 | ||
da864809 TI |
196 | static inline void |
197 | mid_hdmi_audio_write(struct snd_intelhad *ctx, u32 reg, u32 val) | |
5dab11d8 | 198 | { |
da864809 | 199 | iowrite32(val, ctx->mmio_start + ctx->had_config_offset + reg); |
5dab11d8 JA |
200 | } |
201 | ||
372d855f TI |
202 | static int had_read_register(struct snd_intelhad *intelhaddata, |
203 | u32 offset, u32 *data) | |
5dab11d8 | 204 | { |
79f439ea TI |
205 | if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) |
206 | return -ENODEV; | |
5dab11d8 | 207 | |
da864809 TI |
208 | mid_hdmi_audio_read(intelhaddata, offset, data); |
209 | return 0; | |
210 | } | |
211 | ||
212 | static void fixup_dp_config(struct snd_intelhad *intelhaddata, | |
213 | u32 offset, u32 *data) | |
214 | { | |
215 | if (intelhaddata->dp_output) { | |
216 | if (offset == AUD_CONFIG && (*data & AUD_CONFIG_VALID_BIT)) | |
217 | *data |= AUD_CONFIG_DP_MODE | AUD_CONFIG_BLOCK_BIT; | |
218 | } | |
5dab11d8 JA |
219 | } |
220 | ||
372d855f TI |
221 | static int had_write_register(struct snd_intelhad *intelhaddata, |
222 | u32 offset, u32 data) | |
5dab11d8 | 223 | { |
79f439ea TI |
224 | if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) |
225 | return -ENODEV; | |
5dab11d8 | 226 | |
da864809 TI |
227 | fixup_dp_config(intelhaddata, offset, &data); |
228 | mid_hdmi_audio_write(intelhaddata, offset, data); | |
229 | return 0; | |
5dab11d8 JA |
230 | } |
231 | ||
372d855f TI |
232 | static int had_read_modify(struct snd_intelhad *intelhaddata, u32 offset, |
233 | u32 data, u32 mask) | |
5dab11d8 | 234 | { |
da864809 | 235 | u32 val_tmp; |
5dab11d8 | 236 | |
79f439ea TI |
237 | if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) |
238 | return -ENODEV; | |
5dab11d8 | 239 | |
da864809 TI |
240 | mid_hdmi_audio_read(intelhaddata, offset, &val_tmp); |
241 | val_tmp &= ~mask; | |
242 | val_tmp |= (data & mask); | |
243 | ||
244 | fixup_dp_config(intelhaddata, offset, &val_tmp); | |
245 | mid_hdmi_audio_write(intelhaddata, offset, val_tmp); | |
246 | return 0; | |
5dab11d8 | 247 | } |
da864809 TI |
248 | |
249 | /* | |
313d9f28 TI |
250 | * enable / disable audio configuration |
251 | * | |
da864809 TI |
252 | * The had_read_modify() function should not directly be used on VLV2 for |
253 | * updating AUD_CONFIG register. | |
5dab11d8 JA |
254 | * This is because: |
255 | * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2 | |
256 | * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always | |
257 | * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the | |
258 | * register. This field should be 1xy binary for configuration with 6 or | |
259 | * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio) | |
260 | * causes the "channels" field to be updated as 0xy binary resulting in | |
261 | * bad audio. The fix is to always write the AUD_CONFIG[6:4] with | |
262 | * appropriate value when doing read-modify of AUD_CONFIG register. | |
5dab11d8 | 263 | */ |
313d9f28 TI |
264 | static void snd_intelhad_enable_audio(struct snd_pcm_substream *substream, |
265 | struct snd_intelhad *intelhaddata, | |
266 | bool enable) | |
5dab11d8 | 267 | { |
7ceba75f | 268 | union aud_cfg cfg_val = {.regval = 0}; |
313d9f28 | 269 | u8 channels, data, mask; |
5dab11d8 JA |
270 | |
271 | /* | |
272 | * If substream is NULL, there is no active stream. | |
273 | * In this case just set channels to 2 | |
274 | */ | |
313d9f28 | 275 | channels = substream ? substream->runtime->channels : 2; |
7ceba75f | 276 | cfg_val.regx.num_ch = channels - 2; |
5dab11d8 | 277 | |
7ceba75f | 278 | data = cfg_val.regval; |
313d9f28 TI |
279 | if (enable) |
280 | data |= 1; | |
281 | mask = AUD_CONFIG_CH_MASK | 1; | |
5dab11d8 | 282 | |
c75b0476 TI |
283 | dev_dbg(intelhaddata->dev, "%s : data = %x, mask =%x\n", |
284 | __func__, data, mask); | |
5dab11d8 | 285 | |
313d9f28 | 286 | had_read_modify(intelhaddata, AUD_CONFIG, data, mask); |
5dab11d8 JA |
287 | } |
288 | ||
313d9f28 | 289 | /* enable / disable the audio interface */ |
372d855f | 290 | static void snd_intelhad_enable_audio_int(struct snd_intelhad *ctx, bool enable) |
da864809 TI |
291 | { |
292 | u32 status_reg; | |
293 | ||
294 | if (enable) { | |
4151ee84 | 295 | mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS, &status_reg); |
da864809 | 296 | status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN; |
4151ee84 TI |
297 | mid_hdmi_audio_write(ctx, AUD_HDMI_STATUS, status_reg); |
298 | mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS, &status_reg); | |
da864809 TI |
299 | } |
300 | } | |
301 | ||
79dda75a TI |
302 | static void snd_intelhad_reset_audio(struct snd_intelhad *intelhaddata, |
303 | u8 reset) | |
5dab11d8 | 304 | { |
4151ee84 | 305 | had_write_register(intelhaddata, AUD_HDMI_STATUS, reset); |
5dab11d8 JA |
306 | } |
307 | ||
2e52f5e5 | 308 | /* |
5dab11d8 JA |
309 | * initialize audio channel status registers |
310 | * This function is called in the prepare callback | |
311 | */ | |
312 | static int had_prog_status_reg(struct snd_pcm_substream *substream, | |
313 | struct snd_intelhad *intelhaddata) | |
314 | { | |
7ceba75f TI |
315 | union aud_cfg cfg_val = {.regval = 0}; |
316 | union aud_ch_status_0 ch_stat0 = {.regval = 0}; | |
317 | union aud_ch_status_1 ch_stat1 = {.regval = 0}; | |
5dab11d8 JA |
318 | int format; |
319 | ||
7ceba75f | 320 | ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits & |
2e52f5e5 | 321 | IEC958_AES0_NONAUDIO) >> 1; |
7ceba75f | 322 | ch_stat0.regx.clk_acc = (intelhaddata->aes_bits & |
2e52f5e5 | 323 | IEC958_AES3_CON_CLOCK) >> 4; |
7ceba75f | 324 | cfg_val.regx.val_bit = ch_stat0.regx.lpcm_id; |
5dab11d8 JA |
325 | |
326 | switch (substream->runtime->rate) { | |
327 | case AUD_SAMPLE_RATE_32: | |
7ceba75f | 328 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ; |
5dab11d8 JA |
329 | break; |
330 | ||
331 | case AUD_SAMPLE_RATE_44_1: | |
7ceba75f | 332 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ; |
5dab11d8 JA |
333 | break; |
334 | case AUD_SAMPLE_RATE_48: | |
7ceba75f | 335 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ; |
5dab11d8 JA |
336 | break; |
337 | case AUD_SAMPLE_RATE_88_2: | |
7ceba75f | 338 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ; |
5dab11d8 JA |
339 | break; |
340 | case AUD_SAMPLE_RATE_96: | |
7ceba75f | 341 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ; |
5dab11d8 JA |
342 | break; |
343 | case AUD_SAMPLE_RATE_176_4: | |
7ceba75f | 344 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ; |
5dab11d8 JA |
345 | break; |
346 | case AUD_SAMPLE_RATE_192: | |
7ceba75f | 347 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ; |
5dab11d8 JA |
348 | break; |
349 | ||
350 | default: | |
351 | /* control should never come here */ | |
352 | return -EINVAL; | |
5dab11d8 | 353 | } |
2e52f5e5 | 354 | |
79dda75a | 355 | had_write_register(intelhaddata, |
7ceba75f | 356 | AUD_CH_STATUS_0, ch_stat0.regval); |
5dab11d8 JA |
357 | |
358 | format = substream->runtime->format; | |
359 | ||
360 | if (format == SNDRV_PCM_FORMAT_S16_LE) { | |
7ceba75f TI |
361 | ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20; |
362 | ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS; | |
5dab11d8 | 363 | } else if (format == SNDRV_PCM_FORMAT_S24_LE) { |
7ceba75f TI |
364 | ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24; |
365 | ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS; | |
5dab11d8 | 366 | } else { |
7ceba75f TI |
367 | ch_stat1.regx.max_wrd_len = 0; |
368 | ch_stat1.regx.wrd_len = 0; | |
5dab11d8 | 369 | } |
2e52f5e5 | 370 | |
79dda75a | 371 | had_write_register(intelhaddata, |
7ceba75f | 372 | AUD_CH_STATUS_1, ch_stat1.regval); |
5dab11d8 JA |
373 | return 0; |
374 | } | |
375 | ||
76296ef0 | 376 | /* |
5dab11d8 JA |
377 | * function to initialize audio |
378 | * registers and buffer confgiuration registers | |
379 | * This function is called in the prepare callback | |
380 | */ | |
76296ef0 TI |
381 | static int snd_intelhad_audio_ctrl(struct snd_pcm_substream *substream, |
382 | struct snd_intelhad *intelhaddata) | |
5dab11d8 | 383 | { |
7ceba75f TI |
384 | union aud_cfg cfg_val = {.regval = 0}; |
385 | union aud_buf_config buf_cfg = {.regval = 0}; | |
5dab11d8 JA |
386 | u8 channels; |
387 | ||
388 | had_prog_status_reg(substream, intelhaddata); | |
389 | ||
7ceba75f TI |
390 | buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD; |
391 | buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD; | |
392 | buf_cfg.regx.aud_delay = 0; | |
393 | had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval); | |
5dab11d8 JA |
394 | |
395 | channels = substream->runtime->channels; | |
7ceba75f | 396 | cfg_val.regx.num_ch = channels - 2; |
5dab11d8 | 397 | if (channels <= 2) |
7ceba75f | 398 | cfg_val.regx.layout = LAYOUT0; |
5dab11d8 | 399 | else |
7ceba75f | 400 | cfg_val.regx.layout = LAYOUT1; |
5dab11d8 | 401 | |
7ceba75f TI |
402 | cfg_val.regx.val_bit = 1; |
403 | had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval); | |
5dab11d8 JA |
404 | return 0; |
405 | } | |
406 | ||
5dab11d8 JA |
407 | /* |
408 | * Compute derived values in channel_allocations[]. | |
409 | */ | |
410 | static void init_channel_allocations(void) | |
411 | { | |
412 | int i, j; | |
413 | struct cea_channel_speaker_allocation *p; | |
414 | ||
5dab11d8 JA |
415 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { |
416 | p = channel_allocations + i; | |
417 | p->channels = 0; | |
418 | p->spk_mask = 0; | |
419 | for (j = 0; j < ARRAY_SIZE(p->speakers); j++) | |
420 | if (p->speakers[j]) { | |
421 | p->channels++; | |
422 | p->spk_mask |= p->speakers[j]; | |
423 | } | |
424 | } | |
425 | } | |
426 | ||
427 | /* | |
428 | * The transformation takes two steps: | |
429 | * | |
430 | * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask | |
431 | * spk_mask => (channel_allocations[]) => ai->CA | |
432 | * | |
433 | * TODO: it could select the wrong CA from multiple candidates. | |
434 | */ | |
435 | static int snd_intelhad_channel_allocation(struct snd_intelhad *intelhaddata, | |
436 | int channels) | |
437 | { | |
438 | int i; | |
439 | int ca = 0; | |
440 | int spk_mask = 0; | |
441 | ||
442 | /* | |
443 | * CA defaults to 0 for basic stereo audio | |
444 | */ | |
445 | if (channels <= 2) | |
446 | return 0; | |
447 | ||
448 | /* | |
449 | * expand ELD's speaker allocation mask | |
450 | * | |
451 | * ELD tells the speaker mask in a compact(paired) form, | |
452 | * expand ELD's notions to match the ones used by Audio InfoFrame. | |
453 | */ | |
454 | ||
455 | for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { | |
df0435db | 456 | if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) |
5dab11d8 JA |
457 | spk_mask |= eld_speaker_allocation_bits[i]; |
458 | } | |
459 | ||
460 | /* search for the first working match in the CA table */ | |
461 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { | |
462 | if (channels == channel_allocations[i].channels && | |
463 | (spk_mask & channel_allocations[i].spk_mask) == | |
464 | channel_allocations[i].spk_mask) { | |
465 | ca = channel_allocations[i].ca_index; | |
466 | break; | |
467 | } | |
468 | } | |
469 | ||
c75b0476 | 470 | dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels); |
5dab11d8 JA |
471 | |
472 | return ca; | |
473 | } | |
474 | ||
475 | /* from speaker bit mask to ALSA API channel position */ | |
476 | static int spk_to_chmap(int spk) | |
477 | { | |
4a5ddb2c | 478 | const struct channel_map_table *t = map_tables; |
5dab11d8 JA |
479 | |
480 | for (; t->map; t++) { | |
481 | if (t->spk_mask == spk) | |
482 | return t->map; | |
483 | } | |
484 | return 0; | |
485 | } | |
486 | ||
372d855f | 487 | static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata) |
5dab11d8 | 488 | { |
2e52f5e5 | 489 | int i, c; |
5dab11d8 JA |
490 | int spk_mask = 0; |
491 | struct snd_pcm_chmap_elem *chmap; | |
492 | u8 eld_high, eld_high_mask = 0xF0; | |
493 | u8 high_msb; | |
494 | ||
495 | chmap = kzalloc(sizeof(*chmap), GFP_KERNEL); | |
2e52f5e5 | 496 | if (!chmap) { |
5dab11d8 JA |
497 | intelhaddata->chmap->chmap = NULL; |
498 | return; | |
499 | } | |
500 | ||
df0435db TI |
501 | dev_dbg(intelhaddata->dev, "eld speaker = %x\n", |
502 | intelhaddata->eld[DRM_ELD_SPEAKER]); | |
5dab11d8 JA |
503 | |
504 | /* WA: Fix the max channel supported to 8 */ | |
505 | ||
506 | /* | |
507 | * Sink may support more than 8 channels, if eld_high has more than | |
508 | * one bit set. SOC supports max 8 channels. | |
509 | * Refer eld_speaker_allocation_bits, for sink speaker allocation | |
510 | */ | |
511 | ||
512 | /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */ | |
df0435db | 513 | eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask; |
5dab11d8 JA |
514 | if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) { |
515 | /* eld_high & (eld_high-1): if more than 1 bit set */ | |
516 | /* 0x1F: 7 channels */ | |
517 | for (i = 1; i < 4; i++) { | |
518 | high_msb = eld_high & (0x80 >> i); | |
519 | if (high_msb) { | |
df0435db | 520 | intelhaddata->eld[DRM_ELD_SPEAKER] &= |
5dab11d8 JA |
521 | high_msb | 0xF; |
522 | break; | |
523 | } | |
524 | } | |
525 | } | |
526 | ||
527 | for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { | |
df0435db | 528 | if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) |
5dab11d8 JA |
529 | spk_mask |= eld_speaker_allocation_bits[i]; |
530 | } | |
531 | ||
532 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { | |
533 | if (spk_mask == channel_allocations[i].spk_mask) { | |
534 | for (c = 0; c < channel_allocations[i].channels; c++) { | |
535 | chmap->map[c] = spk_to_chmap( | |
536 | channel_allocations[i].speakers[ | |
2e52f5e5 | 537 | (MAX_SPEAKERS - 1) - c]); |
5dab11d8 JA |
538 | } |
539 | chmap->channels = channel_allocations[i].channels; | |
540 | intelhaddata->chmap->chmap = chmap; | |
541 | break; | |
542 | } | |
543 | } | |
544 | if (i >= ARRAY_SIZE(channel_allocations)) { | |
545 | intelhaddata->chmap->chmap = NULL; | |
546 | kfree(chmap); | |
547 | } | |
548 | } | |
549 | ||
550 | /* | |
551 | * ALSA API channel-map control callbacks | |
552 | */ | |
553 | static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol, | |
554 | struct snd_ctl_elem_info *uinfo) | |
555 | { | |
556 | struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); | |
557 | struct snd_intelhad *intelhaddata = info->private_data; | |
558 | ||
559 | if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) | |
560 | return -ENODEV; | |
561 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
562 | uinfo->count = HAD_MAX_CHANNEL; | |
563 | uinfo->value.integer.min = 0; | |
564 | uinfo->value.integer.max = SNDRV_CHMAP_LAST; | |
565 | return 0; | |
566 | } | |
567 | ||
568 | static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol, | |
569 | struct snd_ctl_elem_value *ucontrol) | |
570 | { | |
571 | struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); | |
572 | struct snd_intelhad *intelhaddata = info->private_data; | |
2e52f5e5 | 573 | int i; |
5dab11d8 JA |
574 | const struct snd_pcm_chmap_elem *chmap; |
575 | ||
576 | if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) | |
577 | return -ENODEV; | |
8f8d1d7f TI |
578 | |
579 | mutex_lock(&intelhaddata->mutex); | |
580 | if (!intelhaddata->chmap->chmap) { | |
581 | mutex_unlock(&intelhaddata->mutex); | |
5dab11d8 | 582 | return -ENODATA; |
8f8d1d7f TI |
583 | } |
584 | ||
5dab11d8 | 585 | chmap = intelhaddata->chmap->chmap; |
c75b0476 | 586 | for (i = 0; i < chmap->channels; i++) |
5dab11d8 | 587 | ucontrol->value.integer.value[i] = chmap->map[i]; |
8f8d1d7f | 588 | mutex_unlock(&intelhaddata->mutex); |
5dab11d8 JA |
589 | |
590 | return 0; | |
591 | } | |
592 | ||
593 | static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata, | |
594 | struct snd_pcm *pcm) | |
595 | { | |
2e52f5e5 | 596 | int err; |
5dab11d8 JA |
597 | |
598 | err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, | |
599 | NULL, 0, (unsigned long)intelhaddata, | |
600 | &intelhaddata->chmap); | |
601 | if (err < 0) | |
602 | return err; | |
603 | ||
604 | intelhaddata->chmap->private_data = intelhaddata; | |
e9d65abf TI |
605 | intelhaddata->chmap->kctl->info = had_chmap_ctl_info; |
606 | intelhaddata->chmap->kctl->get = had_chmap_ctl_get; | |
5dab11d8 JA |
607 | intelhaddata->chmap->chmap = NULL; |
608 | return 0; | |
609 | } | |
610 | ||
76296ef0 | 611 | /* |
44684f61 | 612 | * Initialize Data Island Packets registers |
5dab11d8 JA |
613 | * This function is called in the prepare callback |
614 | */ | |
76296ef0 TI |
615 | static void snd_intelhad_prog_dip(struct snd_pcm_substream *substream, |
616 | struct snd_intelhad *intelhaddata) | |
5dab11d8 JA |
617 | { |
618 | int i; | |
7ceba75f TI |
619 | union aud_ctrl_st ctrl_state = {.regval = 0}; |
620 | union aud_info_frame2 frame2 = {.regval = 0}; | |
621 | union aud_info_frame3 frame3 = {.regval = 0}; | |
5dab11d8 | 622 | u8 checksum = 0; |
964ca808 | 623 | u32 info_frame; |
5dab11d8 | 624 | int channels; |
36ed3466 | 625 | int ca; |
5dab11d8 JA |
626 | |
627 | channels = substream->runtime->channels; | |
628 | ||
7ceba75f | 629 | had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); |
5dab11d8 | 630 | |
36ed3466 | 631 | ca = snd_intelhad_channel_allocation(intelhaddata, channels); |
964ca808 PLB |
632 | if (intelhaddata->dp_output) { |
633 | info_frame = DP_INFO_FRAME_WORD1; | |
36ed3466 | 634 | frame2.regval = (substream->runtime->channels - 1) | (ca << 24); |
964ca808 PLB |
635 | } else { |
636 | info_frame = HDMI_INFO_FRAME_WORD1; | |
7ceba75f | 637 | frame2.regx.chnl_cnt = substream->runtime->channels - 1; |
36ed3466 | 638 | frame3.regx.chnl_alloc = ca; |
5dab11d8 | 639 | |
2e52f5e5 | 640 | /* Calculte the byte wide checksum for all valid DIP words */ |
964ca808 | 641 | for (i = 0; i < BYTES_PER_WORD; i++) |
7ceba75f | 642 | checksum += (info_frame >> (i * 8)) & 0xff; |
964ca808 | 643 | for (i = 0; i < BYTES_PER_WORD; i++) |
7ceba75f | 644 | checksum += (frame2.regval >> (i * 8)) & 0xff; |
964ca808 | 645 | for (i = 0; i < BYTES_PER_WORD; i++) |
7ceba75f | 646 | checksum += (frame3.regval >> (i * 8)) & 0xff; |
5dab11d8 | 647 | |
7ceba75f | 648 | frame2.regx.chksum = -(checksum); |
964ca808 | 649 | } |
5dab11d8 | 650 | |
4151ee84 | 651 | had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame); |
7ceba75f TI |
652 | had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval); |
653 | had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval); | |
5dab11d8 JA |
654 | |
655 | /* program remaining DIP words with zero */ | |
656 | for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++) | |
4151ee84 | 657 | had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0); |
5dab11d8 | 658 | |
7ceba75f TI |
659 | ctrl_state.regx.dip_freq = 1; |
660 | ctrl_state.regx.dip_en_sta = 1; | |
661 | had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); | |
5dab11d8 JA |
662 | } |
663 | ||
2e52f5e5 | 664 | /* |
44684f61 | 665 | * Programs buffer address and length registers |
5dab11d8 JA |
666 | * This function programs ring buffer address and length into registers. |
667 | */ | |
313d9f28 TI |
668 | static int snd_intelhad_prog_buffer(struct snd_pcm_substream *substream, |
669 | struct snd_intelhad *intelhaddata, | |
670 | int start, int end) | |
5dab11d8 JA |
671 | { |
672 | u32 ring_buf_addr, ring_buf_size, period_bytes; | |
673 | u8 i, num_periods; | |
5dab11d8 JA |
674 | |
675 | ring_buf_addr = substream->runtime->dma_addr; | |
676 | ring_buf_size = snd_pcm_lib_buffer_bytes(substream); | |
677 | intelhaddata->stream_info.ring_buf_size = ring_buf_size; | |
678 | period_bytes = frames_to_bytes(substream->runtime, | |
679 | substream->runtime->period_size); | |
680 | num_periods = substream->runtime->periods; | |
681 | ||
682 | /* | |
683 | * buffer addr should be 64 byte aligned, period bytes | |
684 | * will be used to calculate addr offset | |
685 | */ | |
686 | period_bytes &= ~0x3F; | |
687 | ||
688 | /* Hardware supports MAX_PERIODS buffers */ | |
689 | if (end >= HAD_MAX_PERIODS) | |
690 | return -EINVAL; | |
691 | ||
692 | for (i = start; i <= end; i++) { | |
693 | /* Program the buf registers with addr and len */ | |
694 | intelhaddata->buf_info[i].buf_addr = ring_buf_addr + | |
695 | (i * period_bytes); | |
696 | if (i < num_periods-1) | |
697 | intelhaddata->buf_info[i].buf_size = period_bytes; | |
698 | else | |
699 | intelhaddata->buf_info[i].buf_size = ring_buf_size - | |
2e52f5e5 | 700 | (i * period_bytes); |
5dab11d8 | 701 | |
79dda75a TI |
702 | had_write_register(intelhaddata, |
703 | AUD_BUF_A_ADDR + (i * HAD_REG_WIDTH), | |
5dab11d8 JA |
704 | intelhaddata->buf_info[i].buf_addr | |
705 | BIT(0) | BIT(1)); | |
79dda75a TI |
706 | had_write_register(intelhaddata, |
707 | AUD_BUF_A_LENGTH + (i * HAD_REG_WIDTH), | |
5dab11d8 JA |
708 | period_bytes); |
709 | intelhaddata->buf_info[i].is_valid = true; | |
710 | } | |
c75b0476 TI |
711 | dev_dbg(intelhaddata->dev, "%s:buf[%d-%d] addr=%#x and size=%d\n", |
712 | __func__, start, end, | |
713 | intelhaddata->buf_info[start].buf_addr, | |
714 | intelhaddata->buf_info[start].buf_size); | |
5dab11d8 JA |
715 | intelhaddata->valid_buf_cnt = num_periods; |
716 | return 0; | |
717 | } | |
718 | ||
372d855f | 719 | static int snd_intelhad_read_len(struct snd_intelhad *intelhaddata) |
5dab11d8 JA |
720 | { |
721 | int i, retval = 0; | |
722 | u32 len[4]; | |
723 | ||
724 | for (i = 0; i < 4 ; i++) { | |
79dda75a TI |
725 | had_read_register(intelhaddata, |
726 | AUD_BUF_A_LENGTH + (i * HAD_REG_WIDTH), | |
727 | &len[i]); | |
5dab11d8 JA |
728 | if (!len[i]) |
729 | retval++; | |
730 | } | |
731 | if (retval != 1) { | |
732 | for (i = 0; i < 4 ; i++) | |
c75b0476 TI |
733 | dev_dbg(intelhaddata->dev, "buf[%d] size=%d\n", |
734 | i, len[i]); | |
5dab11d8 JA |
735 | } |
736 | ||
737 | return retval; | |
738 | } | |
739 | ||
964ca808 PLB |
740 | static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate) |
741 | { | |
742 | u32 maud_val; | |
743 | ||
2e52f5e5 | 744 | /* Select maud according to DP 1.2 spec */ |
964ca808 PLB |
745 | if (link_rate == DP_2_7_GHZ) { |
746 | switch (aud_samp_freq) { | |
747 | case AUD_SAMPLE_RATE_32: | |
748 | maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL; | |
749 | break; | |
750 | ||
751 | case AUD_SAMPLE_RATE_44_1: | |
752 | maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL; | |
753 | break; | |
754 | ||
755 | case AUD_SAMPLE_RATE_48: | |
756 | maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL; | |
757 | break; | |
758 | ||
759 | case AUD_SAMPLE_RATE_88_2: | |
760 | maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL; | |
761 | break; | |
762 | ||
763 | case AUD_SAMPLE_RATE_96: | |
764 | maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL; | |
765 | break; | |
766 | ||
767 | case AUD_SAMPLE_RATE_176_4: | |
768 | maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL; | |
769 | break; | |
770 | ||
771 | case HAD_MAX_RATE: | |
772 | maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL; | |
773 | break; | |
774 | ||
775 | default: | |
776 | maud_val = -EINVAL; | |
777 | break; | |
778 | } | |
779 | } else if (link_rate == DP_1_62_GHZ) { | |
780 | switch (aud_samp_freq) { | |
781 | case AUD_SAMPLE_RATE_32: | |
782 | maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL; | |
783 | break; | |
784 | ||
785 | case AUD_SAMPLE_RATE_44_1: | |
786 | maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL; | |
787 | break; | |
788 | ||
789 | case AUD_SAMPLE_RATE_48: | |
790 | maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL; | |
791 | break; | |
792 | ||
793 | case AUD_SAMPLE_RATE_88_2: | |
794 | maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL; | |
795 | break; | |
796 | ||
797 | case AUD_SAMPLE_RATE_96: | |
798 | maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL; | |
799 | break; | |
800 | ||
801 | case AUD_SAMPLE_RATE_176_4: | |
802 | maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL; | |
803 | break; | |
804 | ||
805 | case HAD_MAX_RATE: | |
806 | maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL; | |
807 | break; | |
808 | ||
809 | default: | |
810 | maud_val = -EINVAL; | |
811 | break; | |
812 | } | |
813 | } else | |
814 | maud_val = -EINVAL; | |
815 | ||
816 | return maud_val; | |
817 | } | |
818 | ||
76296ef0 | 819 | /* |
44684f61 | 820 | * Program HDMI audio CTS value |
5dab11d8 JA |
821 | * |
822 | * @aud_samp_freq: sampling frequency of audio data | |
823 | * @tmds: sampling frequency of the display data | |
824 | * @n_param: N value, depends on aud_samp_freq | |
825 | * @intelhaddata:substream private data | |
826 | * | |
827 | * Program CTS register based on the audio and display sampling frequency | |
828 | */ | |
76296ef0 TI |
829 | static void snd_intelhad_prog_cts(u32 aud_samp_freq, u32 tmds, |
830 | u32 link_rate, u32 n_param, | |
831 | struct snd_intelhad *intelhaddata) | |
5dab11d8 JA |
832 | { |
833 | u32 cts_val; | |
834 | u64 dividend, divisor; | |
835 | ||
964ca808 PLB |
836 | if (intelhaddata->dp_output) { |
837 | /* Substitute cts_val with Maud according to DP 1.2 spec*/ | |
838 | cts_val = had_calculate_maud_value(aud_samp_freq, link_rate); | |
839 | } else { | |
840 | /* Calculate CTS according to HDMI 1.3a spec*/ | |
841 | dividend = (u64)tmds * n_param*1000; | |
842 | divisor = 128 * aud_samp_freq; | |
843 | cts_val = div64_u64(dividend, divisor); | |
844 | } | |
c75b0476 | 845 | dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n", |
964ca808 | 846 | tmds, n_param, cts_val); |
79dda75a | 847 | had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val)); |
5dab11d8 JA |
848 | } |
849 | ||
850 | static int had_calculate_n_value(u32 aud_samp_freq) | |
851 | { | |
2e52f5e5 | 852 | int n_val; |
5dab11d8 JA |
853 | |
854 | /* Select N according to HDMI 1.3a spec*/ | |
855 | switch (aud_samp_freq) { | |
856 | case AUD_SAMPLE_RATE_32: | |
857 | n_val = 4096; | |
2e52f5e5 | 858 | break; |
5dab11d8 JA |
859 | |
860 | case AUD_SAMPLE_RATE_44_1: | |
861 | n_val = 6272; | |
2e52f5e5 | 862 | break; |
5dab11d8 JA |
863 | |
864 | case AUD_SAMPLE_RATE_48: | |
865 | n_val = 6144; | |
2e52f5e5 | 866 | break; |
5dab11d8 JA |
867 | |
868 | case AUD_SAMPLE_RATE_88_2: | |
869 | n_val = 12544; | |
2e52f5e5 | 870 | break; |
5dab11d8 JA |
871 | |
872 | case AUD_SAMPLE_RATE_96: | |
873 | n_val = 12288; | |
2e52f5e5 | 874 | break; |
5dab11d8 JA |
875 | |
876 | case AUD_SAMPLE_RATE_176_4: | |
877 | n_val = 25088; | |
2e52f5e5 | 878 | break; |
5dab11d8 JA |
879 | |
880 | case HAD_MAX_RATE: | |
881 | n_val = 24576; | |
2e52f5e5 | 882 | break; |
5dab11d8 JA |
883 | |
884 | default: | |
885 | n_val = -EINVAL; | |
2e52f5e5 | 886 | break; |
5dab11d8 JA |
887 | } |
888 | return n_val; | |
889 | } | |
890 | ||
76296ef0 | 891 | /* |
44684f61 | 892 | * Program HDMI audio N value |
5dab11d8 JA |
893 | * |
894 | * @aud_samp_freq: sampling frequency of audio data | |
895 | * @n_param: N value, depends on aud_samp_freq | |
896 | * @intelhaddata:substream private data | |
897 | * | |
898 | * This function is called in the prepare callback. | |
899 | * It programs based on the audio and display sampling frequency | |
900 | */ | |
76296ef0 TI |
901 | static int snd_intelhad_prog_n(u32 aud_samp_freq, u32 *n_param, |
902 | struct snd_intelhad *intelhaddata) | |
5dab11d8 | 903 | { |
2e52f5e5 | 904 | int n_val; |
5dab11d8 | 905 | |
964ca808 PLB |
906 | if (intelhaddata->dp_output) { |
907 | /* | |
908 | * According to DP specs, Maud and Naud values hold | |
909 | * a relationship, which is stated as: | |
910 | * Maud/Naud = 512 * fs / f_LS_Clk | |
911 | * where, fs is the sampling frequency of the audio stream | |
912 | * and Naud is 32768 for Async clock. | |
913 | */ | |
914 | ||
915 | n_val = DP_NAUD_VAL; | |
916 | } else | |
917 | n_val = had_calculate_n_value(aud_samp_freq); | |
5dab11d8 JA |
918 | |
919 | if (n_val < 0) | |
920 | return n_val; | |
921 | ||
79dda75a | 922 | had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val)); |
5dab11d8 JA |
923 | *n_param = n_val; |
924 | return 0; | |
925 | } | |
926 | ||
03c34377 TI |
927 | #define MAX_CNT 0xFF |
928 | ||
372d855f | 929 | static void snd_intelhad_handle_underrun(struct snd_intelhad *intelhaddata) |
5dab11d8 | 930 | { |
79f439ea | 931 | u32 hdmi_status = 0, i = 0; |
5dab11d8 JA |
932 | |
933 | /* Handle Underrun interrupt within Audio Unit */ | |
79dda75a | 934 | had_write_register(intelhaddata, AUD_CONFIG, 0); |
5dab11d8 | 935 | /* Reset buffer pointers */ |
4151ee84 TI |
936 | had_write_register(intelhaddata, AUD_HDMI_STATUS, 1); |
937 | had_write_register(intelhaddata, AUD_HDMI_STATUS, 0); | |
2e52f5e5 | 938 | /* |
5dab11d8 JA |
939 | * The interrupt status 'sticky' bits might not be cleared by |
940 | * setting '1' to that bit once... | |
941 | */ | |
942 | do { /* clear bit30, 31 AUD_HDMI_STATUS */ | |
4151ee84 | 943 | had_read_register(intelhaddata, AUD_HDMI_STATUS, |
79dda75a | 944 | &hdmi_status); |
c75b0476 | 945 | dev_dbg(intelhaddata->dev, "HDMI status =0x%x\n", hdmi_status); |
5dab11d8 JA |
946 | if (hdmi_status & AUD_CONFIG_MASK_UNDERRUN) { |
947 | i++; | |
79dda75a | 948 | had_write_register(intelhaddata, |
4151ee84 | 949 | AUD_HDMI_STATUS, hdmi_status); |
5dab11d8 JA |
950 | } else |
951 | break; | |
952 | } while (i < MAX_CNT); | |
953 | if (i >= MAX_CNT) | |
c75b0476 | 954 | dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n"); |
5dab11d8 JA |
955 | } |
956 | ||
2e52f5e5 | 957 | /* |
44684f61 | 958 | * ALSA PCM open callback |
5dab11d8 JA |
959 | */ |
960 | static int snd_intelhad_open(struct snd_pcm_substream *substream) | |
961 | { | |
962 | struct snd_intelhad *intelhaddata; | |
963 | struct snd_pcm_runtime *runtime; | |
5dab11d8 JA |
964 | int retval; |
965 | ||
5dab11d8 | 966 | intelhaddata = snd_pcm_substream_chip(substream); |
5dab11d8 JA |
967 | runtime = substream->runtime; |
968 | ||
182cdf23 | 969 | pm_runtime_get_sync(intelhaddata->dev); |
5dab11d8 | 970 | |
79f439ea | 971 | if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) { |
c75b0476 TI |
972 | dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n", |
973 | __func__); | |
5dab11d8 | 974 | retval = -ENODEV; |
fa5dfe6a | 975 | goto error; |
5dab11d8 JA |
976 | } |
977 | ||
978 | /* set the runtime hw parameter with local snd_pcm_hardware struct */ | |
979 | runtime->hw = snd_intel_hadstream; | |
980 | ||
5dab11d8 JA |
981 | retval = snd_pcm_hw_constraint_integer(runtime, |
982 | SNDRV_PCM_HW_PARAM_PERIODS); | |
983 | if (retval < 0) | |
fa5dfe6a | 984 | goto error; |
5dab11d8 JA |
985 | |
986 | /* Make sure, that the period size is always aligned | |
987 | * 64byte boundary | |
988 | */ | |
989 | retval = snd_pcm_hw_constraint_step(substream->runtime, 0, | |
990 | SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64); | |
73997b05 | 991 | if (retval < 0) |
fa5dfe6a | 992 | goto error; |
5dab11d8 | 993 | |
73997b05 | 994 | /* expose PCM substream */ |
313d9f28 TI |
995 | spin_lock_irq(&intelhaddata->had_spinlock); |
996 | intelhaddata->stream_info.substream = substream; | |
997 | intelhaddata->stream_info.substream_refcount++; | |
998 | spin_unlock_irq(&intelhaddata->had_spinlock); | |
999 | ||
73997b05 TI |
1000 | /* these are cleared in prepare callback, but just to be sure */ |
1001 | intelhaddata->curr_buf = 0; | |
1002 | intelhaddata->underrun_count = 0; | |
1003 | intelhaddata->stream_info.buffer_rendered = 0; | |
1004 | ||
5dab11d8 | 1005 | return retval; |
fa5dfe6a | 1006 | error: |
5dab11d8 | 1007 | pm_runtime_put(intelhaddata->dev); |
5dab11d8 JA |
1008 | return retval; |
1009 | } | |
1010 | ||
2e52f5e5 | 1011 | /* |
44684f61 | 1012 | * ALSA PCM close callback |
5dab11d8 JA |
1013 | */ |
1014 | static int snd_intelhad_close(struct snd_pcm_substream *substream) | |
1015 | { | |
1016 | struct snd_intelhad *intelhaddata; | |
5dab11d8 | 1017 | |
5dab11d8 | 1018 | intelhaddata = snd_pcm_substream_chip(substream); |
5dab11d8 | 1019 | |
73997b05 | 1020 | /* unreference and sync with the pending PCM accesses */ |
313d9f28 TI |
1021 | spin_lock_irq(&intelhaddata->had_spinlock); |
1022 | intelhaddata->stream_info.substream = NULL; | |
1023 | intelhaddata->stream_info.substream_refcount--; | |
1024 | while (intelhaddata->stream_info.substream_refcount > 0) { | |
1025 | spin_unlock_irq(&intelhaddata->had_spinlock); | |
1026 | cpu_relax(); | |
1027 | spin_lock_irq(&intelhaddata->had_spinlock); | |
1028 | } | |
1029 | spin_unlock_irq(&intelhaddata->had_spinlock); | |
5dab11d8 | 1030 | |
5dab11d8 JA |
1031 | pm_runtime_put(intelhaddata->dev); |
1032 | return 0; | |
1033 | } | |
1034 | ||
2e52f5e5 | 1035 | /* |
44684f61 | 1036 | * ALSA PCM hw_params callback |
5dab11d8 JA |
1037 | */ |
1038 | static int snd_intelhad_hw_params(struct snd_pcm_substream *substream, | |
1039 | struct snd_pcm_hw_params *hw_params) | |
1040 | { | |
c75b0476 | 1041 | struct snd_intelhad *intelhaddata; |
5dab11d8 JA |
1042 | unsigned long addr; |
1043 | int pages, buf_size, retval; | |
1044 | ||
c75b0476 | 1045 | intelhaddata = snd_pcm_substream_chip(substream); |
5dab11d8 JA |
1046 | buf_size = params_buffer_bytes(hw_params); |
1047 | retval = snd_pcm_lib_malloc_pages(substream, buf_size); | |
1048 | if (retval < 0) | |
1049 | return retval; | |
c75b0476 TI |
1050 | dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n", |
1051 | __func__, buf_size); | |
5dab11d8 JA |
1052 | /* mark the pages as uncached region */ |
1053 | addr = (unsigned long) substream->runtime->dma_area; | |
1054 | pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE; | |
1055 | retval = set_memory_uc(addr, pages); | |
1056 | if (retval) { | |
c75b0476 TI |
1057 | dev_err(intelhaddata->dev, "set_memory_uc failed.Error:%d\n", |
1058 | retval); | |
5dab11d8 JA |
1059 | return retval; |
1060 | } | |
1061 | memset(substream->runtime->dma_area, 0, buf_size); | |
1062 | ||
1063 | return retval; | |
1064 | } | |
1065 | ||
2e52f5e5 | 1066 | /* |
44684f61 | 1067 | * ALSA PCM hw_free callback |
5dab11d8 JA |
1068 | */ |
1069 | static int snd_intelhad_hw_free(struct snd_pcm_substream *substream) | |
1070 | { | |
1071 | unsigned long addr; | |
1072 | u32 pages; | |
1073 | ||
5dab11d8 JA |
1074 | /* mark back the pages as cached/writeback region before the free */ |
1075 | if (substream->runtime->dma_area != NULL) { | |
1076 | addr = (unsigned long) substream->runtime->dma_area; | |
1077 | pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / | |
1078 | PAGE_SIZE; | |
1079 | set_memory_wb(addr, pages); | |
1080 | return snd_pcm_lib_free_pages(substream); | |
1081 | } | |
1082 | return 0; | |
1083 | } | |
1084 | ||
2e52f5e5 | 1085 | /* |
44684f61 | 1086 | * ALSA PCM trigger callback |
5dab11d8 JA |
1087 | */ |
1088 | static int snd_intelhad_pcm_trigger(struct snd_pcm_substream *substream, | |
1089 | int cmd) | |
1090 | { | |
da864809 | 1091 | int retval = 0; |
5dab11d8 | 1092 | struct snd_intelhad *intelhaddata; |
5dab11d8 | 1093 | |
5dab11d8 | 1094 | intelhaddata = snd_pcm_substream_chip(substream); |
5dab11d8 JA |
1095 | |
1096 | switch (cmd) { | |
1097 | case SNDRV_PCM_TRIGGER_START: | |
182cdf23 TI |
1098 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
1099 | case SNDRV_PCM_TRIGGER_RESUME: | |
5dab11d8 | 1100 | /* Disable local INTRs till register prgmng is done */ |
79f439ea | 1101 | if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) { |
c75b0476 TI |
1102 | dev_dbg(intelhaddata->dev, |
1103 | "_START: HDMI cable plugged-out\n"); | |
5dab11d8 JA |
1104 | retval = -ENODEV; |
1105 | break; | |
1106 | } | |
5dab11d8 | 1107 | |
f69bd104 | 1108 | intelhaddata->stream_info.running = true; |
5dab11d8 JA |
1109 | |
1110 | /* Enable Audio */ | |
da864809 | 1111 | snd_intelhad_enable_audio_int(intelhaddata, true); |
313d9f28 | 1112 | snd_intelhad_enable_audio(substream, intelhaddata, true); |
5dab11d8 JA |
1113 | break; |
1114 | ||
1115 | case SNDRV_PCM_TRIGGER_STOP: | |
182cdf23 TI |
1116 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
1117 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
bcce775c | 1118 | spin_lock(&intelhaddata->had_spinlock); |
5dab11d8 | 1119 | |
c75b0476 | 1120 | /* Stop reporting BUFFER_DONE/UNDERRUN to above layers */ |
5dab11d8 | 1121 | |
f69bd104 | 1122 | intelhaddata->stream_info.running = false; |
bcce775c | 1123 | spin_unlock(&intelhaddata->had_spinlock); |
5dab11d8 | 1124 | /* Disable Audio */ |
da864809 | 1125 | snd_intelhad_enable_audio_int(intelhaddata, false); |
313d9f28 | 1126 | snd_intelhad_enable_audio(substream, intelhaddata, false); |
5dab11d8 | 1127 | /* Reset buffer pointers */ |
79dda75a TI |
1128 | snd_intelhad_reset_audio(intelhaddata, 1); |
1129 | snd_intelhad_reset_audio(intelhaddata, 0); | |
da864809 | 1130 | snd_intelhad_enable_audio_int(intelhaddata, false); |
5dab11d8 JA |
1131 | break; |
1132 | ||
1133 | default: | |
1134 | retval = -EINVAL; | |
1135 | } | |
1136 | return retval; | |
1137 | } | |
1138 | ||
2e52f5e5 | 1139 | /* |
44684f61 | 1140 | * ALSA PCM prepare callback |
5dab11d8 JA |
1141 | */ |
1142 | static int snd_intelhad_pcm_prepare(struct snd_pcm_substream *substream) | |
1143 | { | |
1144 | int retval; | |
1145 | u32 disp_samp_freq, n_param; | |
964ca808 | 1146 | u32 link_rate = 0; |
5dab11d8 JA |
1147 | struct snd_intelhad *intelhaddata; |
1148 | struct snd_pcm_runtime *runtime; | |
5dab11d8 | 1149 | |
5dab11d8 JA |
1150 | intelhaddata = snd_pcm_substream_chip(substream); |
1151 | runtime = substream->runtime; | |
5dab11d8 | 1152 | |
79f439ea | 1153 | if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) { |
c75b0476 TI |
1154 | dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n", |
1155 | __func__); | |
5dab11d8 JA |
1156 | retval = -ENODEV; |
1157 | goto prep_end; | |
1158 | } | |
1159 | ||
c75b0476 | 1160 | dev_dbg(intelhaddata->dev, "period_size=%d\n", |
5dab11d8 | 1161 | (int)frames_to_bytes(runtime, runtime->period_size)); |
c75b0476 TI |
1162 | dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods); |
1163 | dev_dbg(intelhaddata->dev, "buffer_size=%d\n", | |
1164 | (int)snd_pcm_lib_buffer_bytes(substream)); | |
1165 | dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate); | |
1166 | dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels); | |
5dab11d8 | 1167 | |
73997b05 TI |
1168 | intelhaddata->curr_buf = 0; |
1169 | intelhaddata->underrun_count = 0; | |
2e52f5e5 | 1170 | intelhaddata->stream_info.buffer_rendered = 0; |
5dab11d8 JA |
1171 | |
1172 | /* Get N value in KHz */ | |
da864809 | 1173 | disp_samp_freq = intelhaddata->tmds_clock_speed; |
5dab11d8 | 1174 | |
76296ef0 TI |
1175 | retval = snd_intelhad_prog_n(substream->runtime->rate, &n_param, |
1176 | intelhaddata); | |
5dab11d8 | 1177 | if (retval) { |
c75b0476 TI |
1178 | dev_err(intelhaddata->dev, |
1179 | "programming N value failed %#x\n", retval); | |
5dab11d8 JA |
1180 | goto prep_end; |
1181 | } | |
964ca808 PLB |
1182 | |
1183 | if (intelhaddata->dp_output) | |
da864809 | 1184 | link_rate = intelhaddata->link_rate; |
964ca808 | 1185 | |
76296ef0 TI |
1186 | snd_intelhad_prog_cts(substream->runtime->rate, |
1187 | disp_samp_freq, link_rate, | |
1188 | n_param, intelhaddata); | |
5dab11d8 | 1189 | |
76296ef0 | 1190 | snd_intelhad_prog_dip(substream, intelhaddata); |
5dab11d8 | 1191 | |
76296ef0 | 1192 | retval = snd_intelhad_audio_ctrl(substream, intelhaddata); |
5dab11d8 JA |
1193 | |
1194 | /* Prog buffer address */ | |
313d9f28 | 1195 | retval = snd_intelhad_prog_buffer(substream, intelhaddata, |
5dab11d8 JA |
1196 | HAD_BUF_TYPE_A, HAD_BUF_TYPE_D); |
1197 | ||
1198 | /* | |
1199 | * Program channel mapping in following order: | |
1200 | * FL, FR, C, LFE, RL, RR | |
1201 | */ | |
1202 | ||
79dda75a | 1203 | had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER); |
5dab11d8 JA |
1204 | |
1205 | prep_end: | |
1206 | return retval; | |
1207 | } | |
1208 | ||
2e52f5e5 | 1209 | /* |
44684f61 | 1210 | * ALSA PCM pointer callback |
5dab11d8 | 1211 | */ |
44684f61 TI |
1212 | static snd_pcm_uframes_t |
1213 | snd_intelhad_pcm_pointer(struct snd_pcm_substream *substream) | |
5dab11d8 JA |
1214 | { |
1215 | struct snd_intelhad *intelhaddata; | |
1216 | u32 bytes_rendered = 0; | |
1217 | u32 t; | |
1218 | int buf_id; | |
1219 | ||
5dab11d8 JA |
1220 | intelhaddata = snd_pcm_substream_chip(substream); |
1221 | ||
79f439ea TI |
1222 | if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) |
1223 | return SNDRV_PCM_POS_XRUN; | |
1224 | ||
5dab11d8 JA |
1225 | /* Use a hw register to calculate sub-period position reports. |
1226 | * This makes PulseAudio happier. | |
1227 | */ | |
1228 | ||
1229 | buf_id = intelhaddata->curr_buf % 4; | |
79dda75a TI |
1230 | had_read_register(intelhaddata, |
1231 | AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH), &t); | |
232892fb JA |
1232 | |
1233 | if ((t == 0) || (t == ((u32)-1L))) { | |
6ddb3ab6 | 1234 | intelhaddata->underrun_count++; |
c75b0476 TI |
1235 | dev_dbg(intelhaddata->dev, |
1236 | "discovered buffer done for buf %d, count = %d\n", | |
6ddb3ab6 | 1237 | buf_id, intelhaddata->underrun_count); |
232892fb | 1238 | |
6ddb3ab6 | 1239 | if (intelhaddata->underrun_count > (HAD_MIN_PERIODS/2)) { |
c75b0476 TI |
1240 | dev_dbg(intelhaddata->dev, |
1241 | "assume audio_codec_reset, underrun = %d - do xrun\n", | |
6ddb3ab6 | 1242 | intelhaddata->underrun_count); |
232892fb JA |
1243 | return SNDRV_PCM_POS_XRUN; |
1244 | } | |
1245 | } else { | |
1246 | /* Reset Counter */ | |
6ddb3ab6 | 1247 | intelhaddata->underrun_count = 0; |
5dab11d8 | 1248 | } |
232892fb | 1249 | |
5dab11d8 JA |
1250 | t = intelhaddata->buf_info[buf_id].buf_size - t; |
1251 | ||
1252 | if (intelhaddata->stream_info.buffer_rendered) | |
1253 | div_u64_rem(intelhaddata->stream_info.buffer_rendered, | |
1254 | intelhaddata->stream_info.ring_buf_size, | |
1255 | &(bytes_rendered)); | |
1256 | ||
7d9e7986 | 1257 | return bytes_to_frames(substream->runtime, bytes_rendered + t); |
5dab11d8 JA |
1258 | } |
1259 | ||
2e52f5e5 | 1260 | /* |
44684f61 | 1261 | * ALSA PCM mmap callback |
5dab11d8 JA |
1262 | */ |
1263 | static int snd_intelhad_pcm_mmap(struct snd_pcm_substream *substream, | |
1264 | struct vm_area_struct *vma) | |
1265 | { | |
5dab11d8 JA |
1266 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
1267 | return remap_pfn_range(vma, vma->vm_start, | |
1268 | substream->dma_buffer.addr >> PAGE_SHIFT, | |
1269 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
1270 | } | |
1271 | ||
73997b05 TI |
1272 | /* |
1273 | * ALSA PCM ops | |
1274 | */ | |
1275 | static const struct snd_pcm_ops snd_intelhad_playback_ops = { | |
1276 | .open = snd_intelhad_open, | |
1277 | .close = snd_intelhad_close, | |
1278 | .ioctl = snd_pcm_lib_ioctl, | |
1279 | .hw_params = snd_intelhad_hw_params, | |
1280 | .hw_free = snd_intelhad_hw_free, | |
1281 | .prepare = snd_intelhad_pcm_prepare, | |
1282 | .trigger = snd_intelhad_pcm_trigger, | |
1283 | .pointer = snd_intelhad_pcm_pointer, | |
1284 | .mmap = snd_intelhad_pcm_mmap, | |
1285 | }; | |
1286 | ||
8f8d1d7f | 1287 | /* process mode change of the running stream; called in mutex */ |
da864809 | 1288 | static int hdmi_audio_mode_change(struct snd_intelhad *intelhaddata) |
5dab11d8 | 1289 | { |
da864809 | 1290 | struct snd_pcm_substream *substream; |
5dab11d8 JA |
1291 | int retval = 0; |
1292 | u32 disp_samp_freq, n_param; | |
964ca808 | 1293 | u32 link_rate = 0; |
5dab11d8 | 1294 | |
313d9f28 TI |
1295 | substream = had_substream_get(intelhaddata); |
1296 | if (!substream) | |
da864809 | 1297 | return 0; |
5dab11d8 JA |
1298 | |
1299 | /* Disable Audio */ | |
313d9f28 | 1300 | snd_intelhad_enable_audio(substream, intelhaddata, false); |
5dab11d8 JA |
1301 | |
1302 | /* Update CTS value */ | |
da864809 | 1303 | disp_samp_freq = intelhaddata->tmds_clock_speed; |
5dab11d8 | 1304 | |
76296ef0 TI |
1305 | retval = snd_intelhad_prog_n(substream->runtime->rate, &n_param, |
1306 | intelhaddata); | |
5dab11d8 | 1307 | if (retval) { |
c75b0476 TI |
1308 | dev_err(intelhaddata->dev, |
1309 | "programming N value failed %#x\n", retval); | |
5dab11d8 JA |
1310 | goto out; |
1311 | } | |
964ca808 PLB |
1312 | |
1313 | if (intelhaddata->dp_output) | |
da864809 | 1314 | link_rate = intelhaddata->link_rate; |
964ca808 | 1315 | |
76296ef0 TI |
1316 | snd_intelhad_prog_cts(substream->runtime->rate, |
1317 | disp_samp_freq, link_rate, | |
1318 | n_param, intelhaddata); | |
5dab11d8 JA |
1319 | |
1320 | /* Enable Audio */ | |
313d9f28 | 1321 | snd_intelhad_enable_audio(substream, intelhaddata, true); |
5dab11d8 JA |
1322 | |
1323 | out: | |
313d9f28 | 1324 | had_substream_put(intelhaddata); |
5dab11d8 JA |
1325 | return retval; |
1326 | } | |
1327 | ||
372d855f TI |
1328 | static inline int had_chk_intrmiss(struct snd_intelhad *intelhaddata, |
1329 | enum intel_had_aud_buf_type buf_id) | |
1330 | { | |
1331 | int i, intr_count = 0; | |
1332 | enum intel_had_aud_buf_type buff_done; | |
1333 | u32 buf_size, buf_addr; | |
372d855f TI |
1334 | |
1335 | buff_done = buf_id; | |
1336 | ||
1337 | intr_count = snd_intelhad_read_len(intelhaddata); | |
1338 | if (intr_count > 1) { | |
1339 | /* In case of active playback */ | |
c75b0476 TI |
1340 | dev_err(intelhaddata->dev, |
1341 | "Driver detected %d missed buffer done interrupt(s)\n", | |
1342 | (intr_count - 1)); | |
372d855f TI |
1343 | if (intr_count > 3) |
1344 | return intr_count; | |
1345 | ||
1346 | buf_id += (intr_count - 1); | |
1347 | /* Reprogram registers*/ | |
1348 | for (i = buff_done; i < buf_id; i++) { | |
1349 | int j = i % 4; | |
1350 | ||
1351 | buf_size = intelhaddata->buf_info[j].buf_size; | |
1352 | buf_addr = intelhaddata->buf_info[j].buf_addr; | |
1353 | had_write_register(intelhaddata, | |
1354 | AUD_BUF_A_LENGTH + | |
1355 | (j * HAD_REG_WIDTH), buf_size); | |
1356 | had_write_register(intelhaddata, | |
1357 | AUD_BUF_A_ADDR+(j * HAD_REG_WIDTH), | |
1358 | (buf_addr | BIT(0) | BIT(1))); | |
1359 | } | |
1360 | buf_id = buf_id % 4; | |
372d855f | 1361 | intelhaddata->buff_done = buf_id; |
372d855f TI |
1362 | } |
1363 | ||
1364 | return intr_count; | |
1365 | } | |
1366 | ||
bcce775c | 1367 | /* called from irq handler */ |
372d855f TI |
1368 | static int had_process_buffer_done(struct snd_intelhad *intelhaddata) |
1369 | { | |
1370 | u32 len = 1; | |
1371 | enum intel_had_aud_buf_type buf_id; | |
1372 | enum intel_had_aud_buf_type buff_done; | |
1373 | struct pcm_stream_info *stream; | |
313d9f28 | 1374 | struct snd_pcm_substream *substream; |
372d855f | 1375 | u32 buf_size; |
372d855f | 1376 | int intr_count; |
bcce775c | 1377 | unsigned long flags; |
372d855f | 1378 | |
372d855f TI |
1379 | stream = &intelhaddata->stream_info; |
1380 | intr_count = 1; | |
1381 | ||
bcce775c | 1382 | spin_lock_irqsave(&intelhaddata->had_spinlock, flags); |
372d855f | 1383 | if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) { |
bcce775c | 1384 | spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); |
c75b0476 TI |
1385 | dev_dbg(intelhaddata->dev, |
1386 | "%s:Device already disconnected\n", __func__); | |
372d855f TI |
1387 | return 0; |
1388 | } | |
1389 | buf_id = intelhaddata->curr_buf; | |
1390 | intelhaddata->buff_done = buf_id; | |
1391 | buff_done = intelhaddata->buff_done; | |
1392 | buf_size = intelhaddata->buf_info[buf_id].buf_size; | |
372d855f | 1393 | |
372d855f TI |
1394 | /* Every debug statement has an implication |
1395 | * of ~5msec. Thus, avoid having >3 debug statements | |
1396 | * for each buffer_done handling. | |
1397 | */ | |
1398 | ||
1399 | /* Check for any intr_miss in case of active playback */ | |
f69bd104 | 1400 | if (stream->running) { |
372d855f TI |
1401 | intr_count = had_chk_intrmiss(intelhaddata, buf_id); |
1402 | if (!intr_count || (intr_count > 3)) { | |
bcce775c TI |
1403 | spin_unlock_irqrestore(&intelhaddata->had_spinlock, |
1404 | flags); | |
c75b0476 TI |
1405 | dev_err(intelhaddata->dev, |
1406 | "HAD SW state in non-recoverable mode\n"); | |
372d855f TI |
1407 | return 0; |
1408 | } | |
1409 | buf_id += (intr_count - 1); | |
1410 | buf_id = buf_id % 4; | |
372d855f TI |
1411 | } |
1412 | ||
1413 | intelhaddata->buf_info[buf_id].is_valid = true; | |
1414 | if (intelhaddata->valid_buf_cnt-1 == buf_id) { | |
f69bd104 | 1415 | if (stream->running) |
372d855f TI |
1416 | intelhaddata->curr_buf = HAD_BUF_TYPE_A; |
1417 | } else | |
1418 | intelhaddata->curr_buf = buf_id + 1; | |
1419 | ||
bcce775c | 1420 | spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); |
372d855f | 1421 | |
79f439ea | 1422 | if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) { |
c75b0476 | 1423 | dev_dbg(intelhaddata->dev, "HDMI cable plugged-out\n"); |
372d855f TI |
1424 | return 0; |
1425 | } | |
1426 | ||
2e52f5e5 | 1427 | /* Reprogram the registers with addr and length */ |
372d855f TI |
1428 | had_write_register(intelhaddata, |
1429 | AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH), | |
1430 | buf_size); | |
1431 | had_write_register(intelhaddata, | |
1432 | AUD_BUF_A_ADDR + (buf_id * HAD_REG_WIDTH), | |
1433 | intelhaddata->buf_info[buf_id].buf_addr | | |
1434 | BIT(0) | BIT(1)); | |
1435 | ||
1436 | had_read_register(intelhaddata, | |
1437 | AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH), | |
1438 | &len); | |
c75b0476 | 1439 | dev_dbg(intelhaddata->dev, "%s:Enabled buf[%d]\n", __func__, buf_id); |
372d855f TI |
1440 | |
1441 | /* In case of actual data, | |
1442 | * report buffer_done to above ALSA layer | |
1443 | */ | |
313d9f28 TI |
1444 | substream = had_substream_get(intelhaddata); |
1445 | if (substream) { | |
1446 | buf_size = intelhaddata->buf_info[buf_id].buf_size; | |
372d855f TI |
1447 | intelhaddata->stream_info.buffer_rendered += |
1448 | (intr_count * buf_size); | |
313d9f28 TI |
1449 | snd_pcm_period_elapsed(substream); |
1450 | had_substream_put(intelhaddata); | |
372d855f TI |
1451 | } |
1452 | ||
1453 | return 0; | |
1454 | } | |
1455 | ||
bcce775c | 1456 | /* called from irq handler */ |
372d855f TI |
1457 | static int had_process_buffer_underrun(struct snd_intelhad *intelhaddata) |
1458 | { | |
1459 | enum intel_had_aud_buf_type buf_id; | |
1460 | struct pcm_stream_info *stream; | |
313d9f28 | 1461 | struct snd_pcm_substream *substream; |
bcce775c | 1462 | unsigned long flags; |
372d855f TI |
1463 | int drv_status; |
1464 | ||
372d855f TI |
1465 | stream = &intelhaddata->stream_info; |
1466 | ||
bcce775c | 1467 | spin_lock_irqsave(&intelhaddata->had_spinlock, flags); |
372d855f | 1468 | buf_id = intelhaddata->curr_buf; |
372d855f TI |
1469 | intelhaddata->buff_done = buf_id; |
1470 | drv_status = intelhaddata->drv_status; | |
f69bd104 | 1471 | if (stream->running) |
372d855f TI |
1472 | intelhaddata->curr_buf = HAD_BUF_TYPE_A; |
1473 | ||
bcce775c | 1474 | spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); |
372d855f | 1475 | |
f69bd104 TI |
1476 | dev_dbg(intelhaddata->dev, "Enter:%s buf_id=%d, stream_running=%d\n", |
1477 | __func__, buf_id, stream->running); | |
372d855f TI |
1478 | |
1479 | snd_intelhad_handle_underrun(intelhaddata); | |
1480 | ||
1481 | if (drv_status == HAD_DRV_DISCONNECTED) { | |
c75b0476 TI |
1482 | dev_dbg(intelhaddata->dev, |
1483 | "%s:Device already disconnected\n", __func__); | |
372d855f TI |
1484 | return 0; |
1485 | } | |
1486 | ||
f69bd104 TI |
1487 | /* Report UNDERRUN error to above layers */ |
1488 | substream = had_substream_get(intelhaddata); | |
1489 | if (substream) { | |
1490 | snd_pcm_stop_xrun(substream); | |
1491 | had_substream_put(intelhaddata); | |
372d855f TI |
1492 | } |
1493 | ||
1494 | return 0; | |
1495 | } | |
1496 | ||
8f8d1d7f | 1497 | /* process hot plug, called from wq with mutex locked */ |
0e9c67d7 | 1498 | static void had_process_hot_plug(struct snd_intelhad *intelhaddata) |
372d855f TI |
1499 | { |
1500 | enum intel_had_aud_buf_type buf_id; | |
1501 | struct snd_pcm_substream *substream; | |
372d855f | 1502 | |
bcce775c | 1503 | spin_lock_irq(&intelhaddata->had_spinlock); |
372d855f | 1504 | if (intelhaddata->drv_status == HAD_DRV_CONNECTED) { |
c75b0476 | 1505 | dev_dbg(intelhaddata->dev, "Device already connected\n"); |
bcce775c | 1506 | spin_unlock_irq(&intelhaddata->had_spinlock); |
0e9c67d7 | 1507 | return; |
372d855f | 1508 | } |
0e9c67d7 | 1509 | |
372d855f TI |
1510 | buf_id = intelhaddata->curr_buf; |
1511 | intelhaddata->buff_done = buf_id; | |
1512 | intelhaddata->drv_status = HAD_DRV_CONNECTED; | |
c75b0476 TI |
1513 | dev_dbg(intelhaddata->dev, |
1514 | "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n", | |
372d855f | 1515 | __func__, __LINE__); |
bcce775c | 1516 | spin_unlock_irq(&intelhaddata->had_spinlock); |
372d855f | 1517 | |
c75b0476 TI |
1518 | dev_dbg(intelhaddata->dev, "Processing HOT_PLUG, buf_id = %d\n", |
1519 | buf_id); | |
372d855f TI |
1520 | |
1521 | /* Safety check */ | |
313d9f28 | 1522 | substream = had_substream_get(intelhaddata); |
372d855f | 1523 | if (substream) { |
c75b0476 TI |
1524 | dev_dbg(intelhaddata->dev, |
1525 | "Force to stop the active stream by disconnection\n"); | |
372d855f TI |
1526 | /* Set runtime->state to hw_params done */ |
1527 | snd_pcm_stop(substream, SNDRV_PCM_STATE_SETUP); | |
313d9f28 | 1528 | had_substream_put(intelhaddata); |
372d855f TI |
1529 | } |
1530 | ||
1531 | had_build_channel_allocation_map(intelhaddata); | |
372d855f TI |
1532 | } |
1533 | ||
8f8d1d7f | 1534 | /* process hot unplug, called from wq with mutex locked */ |
0e9c67d7 | 1535 | static void had_process_hot_unplug(struct snd_intelhad *intelhaddata) |
372d855f TI |
1536 | { |
1537 | enum intel_had_aud_buf_type buf_id; | |
313d9f28 | 1538 | struct snd_pcm_substream *substream; |
372d855f | 1539 | |
372d855f TI |
1540 | buf_id = intelhaddata->curr_buf; |
1541 | ||
313d9f28 TI |
1542 | substream = had_substream_get(intelhaddata); |
1543 | ||
bcce775c | 1544 | spin_lock_irq(&intelhaddata->had_spinlock); |
372d855f TI |
1545 | |
1546 | if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) { | |
c75b0476 | 1547 | dev_dbg(intelhaddata->dev, "Device already disconnected\n"); |
bcce775c | 1548 | spin_unlock_irq(&intelhaddata->had_spinlock); |
313d9f28 | 1549 | goto out; |
372d855f | 1550 | |
372d855f TI |
1551 | } |
1552 | ||
0e9c67d7 TI |
1553 | /* Disable Audio */ |
1554 | snd_intelhad_enable_audio_int(intelhaddata, false); | |
313d9f28 | 1555 | snd_intelhad_enable_audio(substream, intelhaddata, false); |
0e9c67d7 | 1556 | |
372d855f | 1557 | intelhaddata->drv_status = HAD_DRV_DISCONNECTED; |
c75b0476 TI |
1558 | dev_dbg(intelhaddata->dev, |
1559 | "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n", | |
372d855f | 1560 | __func__, __LINE__); |
313d9f28 | 1561 | spin_unlock_irq(&intelhaddata->had_spinlock); |
372d855f TI |
1562 | |
1563 | /* Report to above ALSA layer */ | |
313d9f28 TI |
1564 | if (substream) |
1565 | snd_pcm_stop(substream, SNDRV_PCM_STATE_SETUP); | |
372d855f | 1566 | |
313d9f28 TI |
1567 | out: |
1568 | if (substream) | |
1569 | had_substream_put(intelhaddata); | |
372d855f TI |
1570 | kfree(intelhaddata->chmap->chmap); |
1571 | intelhaddata->chmap->chmap = NULL; | |
372d855f TI |
1572 | } |
1573 | ||
73997b05 TI |
1574 | /* |
1575 | * ALSA iec958 and ELD controls | |
1576 | */ | |
5dab11d8 | 1577 | |
5dab11d8 JA |
1578 | static int had_iec958_info(struct snd_kcontrol *kcontrol, |
1579 | struct snd_ctl_elem_info *uinfo) | |
1580 | { | |
1581 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1582 | uinfo->count = 1; | |
1583 | return 0; | |
1584 | } | |
1585 | ||
1586 | static int had_iec958_get(struct snd_kcontrol *kcontrol, | |
1587 | struct snd_ctl_elem_value *ucontrol) | |
1588 | { | |
1589 | struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); | |
1590 | ||
8f8d1d7f | 1591 | mutex_lock(&intelhaddata->mutex); |
5dab11d8 JA |
1592 | ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff; |
1593 | ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff; | |
1594 | ucontrol->value.iec958.status[2] = | |
1595 | (intelhaddata->aes_bits >> 16) & 0xff; | |
1596 | ucontrol->value.iec958.status[3] = | |
1597 | (intelhaddata->aes_bits >> 24) & 0xff; | |
8f8d1d7f | 1598 | mutex_unlock(&intelhaddata->mutex); |
5dab11d8 JA |
1599 | return 0; |
1600 | } | |
372d855f | 1601 | |
5dab11d8 JA |
1602 | static int had_iec958_mask_get(struct snd_kcontrol *kcontrol, |
1603 | struct snd_ctl_elem_value *ucontrol) | |
1604 | { | |
1605 | ucontrol->value.iec958.status[0] = 0xff; | |
1606 | ucontrol->value.iec958.status[1] = 0xff; | |
1607 | ucontrol->value.iec958.status[2] = 0xff; | |
1608 | ucontrol->value.iec958.status[3] = 0xff; | |
1609 | return 0; | |
1610 | } | |
372d855f | 1611 | |
5dab11d8 JA |
1612 | static int had_iec958_put(struct snd_kcontrol *kcontrol, |
1613 | struct snd_ctl_elem_value *ucontrol) | |
1614 | { | |
1615 | unsigned int val; | |
1616 | struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); | |
8f8d1d7f | 1617 | int changed = 0; |
5dab11d8 | 1618 | |
5dab11d8 JA |
1619 | val = (ucontrol->value.iec958.status[0] << 0) | |
1620 | (ucontrol->value.iec958.status[1] << 8) | | |
1621 | (ucontrol->value.iec958.status[2] << 16) | | |
1622 | (ucontrol->value.iec958.status[3] << 24); | |
8f8d1d7f | 1623 | mutex_lock(&intelhaddata->mutex); |
5dab11d8 JA |
1624 | if (intelhaddata->aes_bits != val) { |
1625 | intelhaddata->aes_bits = val; | |
8f8d1d7f | 1626 | changed = 1; |
5dab11d8 | 1627 | } |
8f8d1d7f TI |
1628 | mutex_unlock(&intelhaddata->mutex); |
1629 | return changed; | |
5dab11d8 JA |
1630 | } |
1631 | ||
4aedb946 TI |
1632 | static int had_ctl_eld_info(struct snd_kcontrol *kcontrol, |
1633 | struct snd_ctl_elem_info *uinfo) | |
1634 | { | |
1635 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; | |
1636 | uinfo->count = HDMI_MAX_ELD_BYTES; | |
1637 | return 0; | |
1638 | } | |
1639 | ||
1640 | static int had_ctl_eld_get(struct snd_kcontrol *kcontrol, | |
1641 | struct snd_ctl_elem_value *ucontrol) | |
1642 | { | |
1643 | struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); | |
1644 | ||
1645 | mutex_lock(&intelhaddata->mutex); | |
1646 | memcpy(ucontrol->value.bytes.data, intelhaddata->eld, | |
1647 | HDMI_MAX_ELD_BYTES); | |
1648 | mutex_unlock(&intelhaddata->mutex); | |
1649 | return 0; | |
1650 | } | |
5dab11d8 | 1651 | |
73997b05 | 1652 | static const struct snd_kcontrol_new had_controls[] = { |
4aedb946 TI |
1653 | { |
1654 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
1655 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
1656 | .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), | |
1657 | .info = had_iec958_info, /* shared */ | |
1658 | .get = had_iec958_mask_get, | |
1659 | }, | |
1660 | { | |
1661 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
1662 | .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), | |
1663 | .info = had_iec958_info, | |
1664 | .get = had_iec958_get, | |
1665 | .put = had_iec958_put, | |
1666 | }, | |
1667 | { | |
1668 | .access = (SNDRV_CTL_ELEM_ACCESS_READ | | |
1669 | SNDRV_CTL_ELEM_ACCESS_VOLATILE), | |
1670 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
1671 | .name = "ELD", | |
1672 | .info = had_ctl_eld_info, | |
1673 | .get = had_ctl_eld_get, | |
1674 | }, | |
5dab11d8 JA |
1675 | }; |
1676 | ||
73997b05 TI |
1677 | /* |
1678 | * audio interrupt handler | |
1679 | */ | |
da864809 TI |
1680 | static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id) |
1681 | { | |
1682 | struct snd_intelhad *ctx = dev_id; | |
1683 | u32 audio_stat, audio_reg; | |
1684 | ||
4151ee84 | 1685 | audio_reg = AUD_HDMI_STATUS; |
da864809 TI |
1686 | mid_hdmi_audio_read(ctx, audio_reg, &audio_stat); |
1687 | ||
1688 | if (audio_stat & HDMI_AUDIO_UNDERRUN) { | |
1689 | mid_hdmi_audio_write(ctx, audio_reg, HDMI_AUDIO_UNDERRUN); | |
1690 | had_process_buffer_underrun(ctx); | |
1691 | } | |
1692 | ||
1693 | if (audio_stat & HDMI_AUDIO_BUFFER_DONE) { | |
1694 | mid_hdmi_audio_write(ctx, audio_reg, HDMI_AUDIO_BUFFER_DONE); | |
1695 | had_process_buffer_done(ctx); | |
1696 | } | |
1697 | ||
1698 | return IRQ_HANDLED; | |
1699 | } | |
1700 | ||
73997b05 TI |
1701 | /* |
1702 | * monitor plug/unplug notification from i915; just kick off the work | |
1703 | */ | |
da864809 TI |
1704 | static void notify_audio_lpe(struct platform_device *pdev) |
1705 | { | |
1706 | struct snd_intelhad *ctx = platform_get_drvdata(pdev); | |
da864809 | 1707 | |
99b2ab9d TI |
1708 | schedule_work(&ctx->hdmi_audio_wq); |
1709 | } | |
da864809 | 1710 | |
73997b05 | 1711 | /* the work to handle monitor hot plug/unplug */ |
99b2ab9d TI |
1712 | static void had_audio_wq(struct work_struct *work) |
1713 | { | |
1714 | struct snd_intelhad *ctx = | |
1715 | container_of(work, struct snd_intelhad, hdmi_audio_wq); | |
1716 | struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data; | |
da864809 | 1717 | |
182cdf23 | 1718 | pm_runtime_get_sync(ctx->dev); |
8f8d1d7f | 1719 | mutex_lock(&ctx->mutex); |
99b2ab9d TI |
1720 | if (!pdata->hdmi_connected) { |
1721 | dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG\n", | |
1722 | __func__); | |
4aedb946 | 1723 | memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */ |
0e9c67d7 | 1724 | had_process_hot_unplug(ctx); |
da864809 TI |
1725 | } else { |
1726 | struct intel_hdmi_lpe_audio_eld *eld = &pdata->eld; | |
1727 | ||
0e9c67d7 TI |
1728 | dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n", |
1729 | __func__, eld->port_id, pdata->tmds_clock_speed); | |
1730 | ||
da864809 TI |
1731 | switch (eld->pipe_id) { |
1732 | case 0: | |
1733 | ctx->had_config_offset = AUDIO_HDMI_CONFIG_A; | |
1734 | break; | |
1735 | case 1: | |
1736 | ctx->had_config_offset = AUDIO_HDMI_CONFIG_B; | |
1737 | break; | |
1738 | case 2: | |
1739 | ctx->had_config_offset = AUDIO_HDMI_CONFIG_C; | |
1740 | break; | |
1741 | default: | |
99b2ab9d | 1742 | dev_dbg(ctx->dev, "Invalid pipe %d\n", |
da864809 TI |
1743 | eld->pipe_id); |
1744 | break; | |
1745 | } | |
1746 | ||
df0435db | 1747 | memcpy(ctx->eld, eld->eld_data, sizeof(ctx->eld)); |
da864809 | 1748 | |
0e9c67d7 TI |
1749 | ctx->dp_output = pdata->dp_output; |
1750 | ctx->tmds_clock_speed = pdata->tmds_clock_speed; | |
1751 | ctx->link_rate = pdata->link_rate; | |
da864809 | 1752 | |
0e9c67d7 | 1753 | had_process_hot_plug(ctx); |
da864809 | 1754 | |
0e9c67d7 | 1755 | /* Process mode change if stream is active */ |
f69bd104 | 1756 | hdmi_audio_mode_change(ctx); |
da864809 | 1757 | } |
8f8d1d7f | 1758 | mutex_unlock(&ctx->mutex); |
182cdf23 TI |
1759 | pm_runtime_put(ctx->dev); |
1760 | } | |
1761 | ||
1762 | /* | |
1763 | * PM callbacks | |
1764 | */ | |
1765 | ||
1766 | static int hdmi_lpe_audio_runtime_suspend(struct device *dev) | |
1767 | { | |
1768 | struct snd_intelhad *ctx = dev_get_drvdata(dev); | |
1769 | struct snd_pcm_substream *substream; | |
1770 | ||
1771 | substream = had_substream_get(ctx); | |
1772 | if (substream) { | |
1773 | snd_pcm_suspend(substream); | |
1774 | had_substream_put(ctx); | |
1775 | } | |
1776 | ||
1777 | return 0; | |
1778 | } | |
1779 | ||
1780 | static int hdmi_lpe_audio_suspend(struct device *dev) | |
1781 | { | |
1782 | struct snd_intelhad *ctx = dev_get_drvdata(dev); | |
1783 | int err; | |
1784 | ||
1785 | err = hdmi_lpe_audio_runtime_suspend(dev); | |
1786 | if (!err) | |
1787 | snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D3hot); | |
1788 | return err; | |
1789 | } | |
1790 | ||
1791 | static int hdmi_lpe_audio_resume(struct device *dev) | |
1792 | { | |
1793 | struct snd_intelhad *ctx = dev_get_drvdata(dev); | |
1794 | ||
1795 | snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D0); | |
1796 | return 0; | |
da864809 TI |
1797 | } |
1798 | ||
1799 | /* release resources */ | |
1800 | static void hdmi_lpe_audio_free(struct snd_card *card) | |
1801 | { | |
1802 | struct snd_intelhad *ctx = card->private_data; | |
1803 | ||
99b2ab9d TI |
1804 | cancel_work_sync(&ctx->hdmi_audio_wq); |
1805 | ||
da864809 TI |
1806 | if (ctx->mmio_start) |
1807 | iounmap(ctx->mmio_start); | |
1808 | if (ctx->irq >= 0) | |
1809 | free_irq(ctx->irq, ctx); | |
1810 | } | |
1811 | ||
79dda75a | 1812 | /* |
da864809 | 1813 | * hdmi_lpe_audio_probe - start bridge with i915 |
5dab11d8 | 1814 | * |
da864809 | 1815 | * This function is called when the i915 driver creates the |
2e52f5e5 | 1816 | * hdmi-lpe-audio platform device. |
5dab11d8 | 1817 | */ |
da864809 | 1818 | static int hdmi_lpe_audio_probe(struct platform_device *pdev) |
5dab11d8 | 1819 | { |
5dab11d8 | 1820 | struct snd_card *card; |
da864809 TI |
1821 | struct snd_intelhad *ctx; |
1822 | struct snd_pcm *pcm; | |
1823 | struct intel_hdmi_lpe_audio_pdata *pdata; | |
1824 | int irq; | |
1825 | struct resource *res_mmio; | |
4aedb946 | 1826 | int i, ret; |
da864809 | 1827 | |
da864809 TI |
1828 | dev_dbg(&pdev->dev, "dma_mask: %p\n", pdev->dev.dma_mask); |
1829 | ||
1830 | pdata = pdev->dev.platform_data; | |
1831 | if (!pdata) { | |
1832 | dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__); | |
1833 | return -EINVAL; | |
1834 | } | |
5dab11d8 | 1835 | |
da864809 TI |
1836 | /* get resources */ |
1837 | irq = platform_get_irq(pdev, 0); | |
1838 | if (irq < 0) { | |
1839 | dev_err(&pdev->dev, "Could not get irq resource\n"); | |
1840 | return -ENODEV; | |
1841 | } | |
1842 | ||
1843 | res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1844 | if (!res_mmio) { | |
1845 | dev_err(&pdev->dev, "Could not get IO_MEM resources\n"); | |
1846 | return -ENXIO; | |
1847 | } | |
5dab11d8 | 1848 | |
5647aec2 | 1849 | /* create a card instance with ALSA framework */ |
da864809 TI |
1850 | ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id, |
1851 | THIS_MODULE, sizeof(*ctx), &card); | |
1852 | if (ret) | |
1853 | return ret; | |
1854 | ||
1855 | ctx = card->private_data; | |
1856 | spin_lock_init(&ctx->had_spinlock); | |
8f8d1d7f | 1857 | mutex_init(&ctx->mutex); |
da864809 TI |
1858 | ctx->drv_status = HAD_DRV_DISCONNECTED; |
1859 | ctx->dev = &pdev->dev; | |
1860 | ctx->card = card; | |
da864809 TI |
1861 | ctx->aes_bits = SNDRV_PCM_DEFAULT_CON_SPDIF; |
1862 | strcpy(card->driver, INTEL_HAD); | |
1863 | strcpy(card->shortname, INTEL_HAD); | |
1864 | ||
1865 | ctx->irq = -1; | |
1866 | ctx->tmds_clock_speed = DIS_SAMPLE_RATE_148_5; | |
99b2ab9d | 1867 | INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq); |
da864809 TI |
1868 | |
1869 | card->private_free = hdmi_lpe_audio_free; | |
1870 | ||
1871 | /* assume pipe A as default */ | |
1872 | ctx->had_config_offset = AUDIO_HDMI_CONFIG_A; | |
1873 | ||
1874 | platform_set_drvdata(pdev, ctx); | |
1875 | ||
1876 | dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n", | |
1877 | __func__, (unsigned int)res_mmio->start, | |
1878 | (unsigned int)res_mmio->end); | |
1879 | ||
1880 | ctx->mmio_start = ioremap_nocache(res_mmio->start, | |
1881 | (size_t)(resource_size(res_mmio))); | |
1882 | if (!ctx->mmio_start) { | |
1883 | dev_err(&pdev->dev, "Could not get ioremap\n"); | |
1884 | ret = -EACCES; | |
1885 | goto err; | |
1886 | } | |
5dab11d8 | 1887 | |
da864809 TI |
1888 | /* setup interrupt handler */ |
1889 | ret = request_irq(irq, display_pipe_interrupt_handler, 0, | |
1890 | pdev->name, ctx); | |
1891 | if (ret < 0) { | |
1892 | dev_err(&pdev->dev, "request_irq failed\n"); | |
1893 | goto err; | |
1894 | } | |
5dab11d8 | 1895 | |
da864809 TI |
1896 | ctx->irq = irq; |
1897 | ||
1898 | ret = snd_pcm_new(card, INTEL_HAD, PCM_INDEX, MAX_PB_STREAMS, | |
1899 | MAX_CAP_STREAMS, &pcm); | |
1900 | if (ret) | |
5dab11d8 JA |
1901 | goto err; |
1902 | ||
1903 | /* setup private data which can be retrieved when required */ | |
da864809 | 1904 | pcm->private_data = ctx; |
5dab11d8 JA |
1905 | pcm->info_flags = 0; |
1906 | strncpy(pcm->name, card->shortname, strlen(card->shortname)); | |
da864809 | 1907 | /* setup the ops for playabck */ |
5dab11d8 JA |
1908 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, |
1909 | &snd_intelhad_playback_ops); | |
1910 | /* allocate dma pages for ALSA stream operations | |
1911 | * memory allocated is based on size, not max value | |
1912 | * thus using same argument for max & size | |
1913 | */ | |
da864809 | 1914 | snd_pcm_lib_preallocate_pages_for_all(pcm, |
5dab11d8 JA |
1915 | SNDRV_DMA_TYPE_DEV, NULL, |
1916 | HAD_MAX_BUFFER, HAD_MAX_BUFFER); | |
5dab11d8 | 1917 | |
4aedb946 TI |
1918 | /* create controls */ |
1919 | for (i = 0; i < ARRAY_SIZE(had_controls); i++) { | |
1920 | ret = snd_ctl_add(card, snd_ctl_new1(&had_controls[i], ctx)); | |
1921 | if (ret < 0) | |
1922 | goto err; | |
1923 | } | |
5dab11d8 JA |
1924 | |
1925 | init_channel_allocations(); | |
1926 | ||
1927 | /* Register channel map controls */ | |
da864809 TI |
1928 | ret = had_register_chmap_ctls(ctx, pcm); |
1929 | if (ret < 0) | |
5dab11d8 JA |
1930 | goto err; |
1931 | ||
da864809 TI |
1932 | ret = snd_card_register(card); |
1933 | if (ret) | |
36ec0d99 TI |
1934 | goto err; |
1935 | ||
bcce775c | 1936 | spin_lock_irq(&pdata->lpe_audio_slock); |
da864809 | 1937 | pdata->notify_audio_lpe = notify_audio_lpe; |
99b2ab9d | 1938 | pdata->notify_pending = false; |
bcce775c | 1939 | spin_unlock_irq(&pdata->lpe_audio_slock); |
da864809 TI |
1940 | |
1941 | pm_runtime_set_active(&pdev->dev); | |
1942 | pm_runtime_enable(&pdev->dev); | |
1943 | ||
99b2ab9d | 1944 | dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__); |
da864809 | 1945 | schedule_work(&ctx->hdmi_audio_wq); |
5dab11d8 | 1946 | |
79dda75a | 1947 | return 0; |
5647aec2 | 1948 | |
5dab11d8 JA |
1949 | err: |
1950 | snd_card_free(card); | |
da864809 | 1951 | return ret; |
5dab11d8 JA |
1952 | } |
1953 | ||
79dda75a | 1954 | /* |
da864809 | 1955 | * hdmi_lpe_audio_remove - stop bridge with i915 |
5dab11d8 | 1956 | * |
2e52f5e5 | 1957 | * This function is called when the platform device is destroyed. |
5dab11d8 | 1958 | */ |
da864809 | 1959 | static int hdmi_lpe_audio_remove(struct platform_device *pdev) |
5dab11d8 | 1960 | { |
da864809 | 1961 | struct snd_intelhad *ctx = platform_get_drvdata(pdev); |
5dab11d8 | 1962 | |
da864809 TI |
1963 | if (ctx->drv_status != HAD_DRV_DISCONNECTED) |
1964 | snd_intelhad_enable_audio_int(ctx, false); | |
1965 | snd_card_free(ctx->card); | |
5dab11d8 JA |
1966 | return 0; |
1967 | } | |
1968 | ||
182cdf23 TI |
1969 | static const struct dev_pm_ops hdmi_lpe_audio_pm = { |
1970 | SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume) | |
1971 | SET_RUNTIME_PM_OPS(hdmi_lpe_audio_runtime_suspend, NULL, NULL) | |
1972 | }; | |
1973 | ||
da864809 TI |
1974 | static struct platform_driver hdmi_lpe_audio_driver = { |
1975 | .driver = { | |
1976 | .name = "hdmi-lpe-audio", | |
182cdf23 | 1977 | .pm = &hdmi_lpe_audio_pm, |
da864809 TI |
1978 | }, |
1979 | .probe = hdmi_lpe_audio_probe, | |
1980 | .remove = hdmi_lpe_audio_remove, | |
da864809 TI |
1981 | }; |
1982 | ||
1983 | module_platform_driver(hdmi_lpe_audio_driver); | |
1984 | MODULE_ALIAS("platform:hdmi_lpe_audio"); | |
1985 | ||
5dab11d8 JA |
1986 | MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>"); |
1987 | MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>"); | |
1988 | MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>"); | |
1989 | MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>"); | |
1990 | MODULE_DESCRIPTION("Intel HDMI Audio driver"); | |
1991 | MODULE_LICENSE("GPL v2"); | |
1992 | MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}"); |