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ALSA: x86: Set CA bits for DisplayPort too
[linux-block.git] / sound / x86 / intel_hdmi_audio.c
CommitLineData
5dab11d8
JA		 1/*
2 * intel_hdmi_audio.c - Intel HDMI audio driver
3 *
4 * Copyright (C) 2016 Intel Corp
5 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
6 * Ramesh Babu K V <ramesh.babu@intel.com>
7 * Vaibhav Agarwal <vaibhav.agarwal@intel.com>
8 * Jerome Anand <jerome.anand@intel.com>
9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
21 * ALSA driver for Intel HDMI audio
22 */
23
03c34377 24#include <linux/types.h>
5dab11d8
JA		 25#include <linux/platform_device.h>
26#include <linux/io.h>
27#include <linux/slab.h>
28#include <linux/module.h>
da864809 29#include <linux/interrupt.h>
03c34377 30#include <linux/pm_runtime.h>
5dab11d8 31#include <asm/cacheflush.h>
5dab11d8 32#include <sound/core.h>
03c34377
TI		 33#include <sound/asoundef.h>
34#include <sound/pcm.h>
5dab11d8
JA		 35#include <sound/pcm_params.h>
36#include <sound/initval.h>
37#include <sound/control.h>
03c34377 38#include <drm/drm_edid.h>
da864809 39#include <drm/intel_lpe_audio.h>
5dab11d8
JA		 40#include "intel_hdmi_audio.h"
41
5dab11d8
JA		 42/*standard module options for ALSA. This module supports only one card*/
43static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
44static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
5dab11d8
JA		 45
46module_param_named(index, hdmi_card_index, int, 0444);
47MODULE_PARM_DESC(index,
48 "Index value for INTEL Intel HDMI Audio controller.");
49module_param_named(id, hdmi_card_id, charp, 0444);
50MODULE_PARM_DESC(id,
51 "ID string for INTEL Intel HDMI Audio controller.");
52
53/*
54 * ELD SA bits in the CEA Speaker Allocation data block
55 */
4a5ddb2c 56static const int eld_speaker_allocation_bits[] = {
5dab11d8
JA		 57 [0] = FL | FR,
58 [1] = LFE,
59 [2] = FC,
60 [3] = RL | RR,
61 [4] = RC,
62 [5] = FLC | FRC,
63 [6] = RLC | RRC,
64 /* the following are not defined in ELD yet */
65 [7] = 0,
66};
67
68/*
69 * This is an ordered list!
70 *
71 * The preceding ones have better chances to be selected by
72 * hdmi_channel_allocation().
73 */
74static struct cea_channel_speaker_allocation channel_allocations[] = {
75/* channel: 7 6 5 4 3 2 1 0 */
76{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
77 /* 2.1 */
78{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
79 /* Dolby Surround */
80{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
81 /* surround40 */
82{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
83 /* surround41 */
84{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
85 /* surround50 */
86{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
87 /* surround51 */
88{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
89 /* 6.1 */
90{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
91 /* surround71 */
92{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
93
94{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
95{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
96{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
97{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
98{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
99{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
100{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
101{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
102{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
103{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
104{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
105{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
106{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
107{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
108{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
109{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
110{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
111{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
112{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
113{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
114{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
115{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
116{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
117};
118
4a5ddb2c 119static const struct channel_map_table map_tables[] = {
5dab11d8
JA		 120 { SNDRV_CHMAP_FL, 0x00, FL },
121 { SNDRV_CHMAP_FR, 0x01, FR },
122 { SNDRV_CHMAP_RL, 0x04, RL },
123 { SNDRV_CHMAP_RR, 0x05, RR },
124 { SNDRV_CHMAP_LFE, 0x02, LFE },
125 { SNDRV_CHMAP_FC, 0x03, FC },
126 { SNDRV_CHMAP_RLC, 0x06, RLC },
127 { SNDRV_CHMAP_RRC, 0x07, RRC },
128 {} /* terminator */
129};
130
131/* hardware capability structure */
132static const struct snd_pcm_hardware snd_intel_hadstream = {
133 .info = (SNDRV_PCM_INFO_INTERLEAVED |
134 SNDRV_PCM_INFO_DOUBLE |
135 SNDRV_PCM_INFO_MMAP|
136 SNDRV_PCM_INFO_MMAP_VALID |
137 SNDRV_PCM_INFO_BATCH),
138 .formats = (SNDRV_PCM_FMTBIT_S24 |
139 SNDRV_PCM_FMTBIT_U24),
140 .rates = SNDRV_PCM_RATE_32000 |
141 SNDRV_PCM_RATE_44100 |
142 SNDRV_PCM_RATE_48000 |
143 SNDRV_PCM_RATE_88200 |
144 SNDRV_PCM_RATE_96000 |
145 SNDRV_PCM_RATE_176400 |
146 SNDRV_PCM_RATE_192000,
147 .rate_min = HAD_MIN_RATE,
148 .rate_max = HAD_MAX_RATE,
149 .channels_min = HAD_MIN_CHANNEL,
150 .channels_max = HAD_MAX_CHANNEL,
151 .buffer_bytes_max = HAD_MAX_BUFFER,
152 .period_bytes_min = HAD_MIN_PERIOD_BYTES,
153 .period_bytes_max = HAD_MAX_PERIOD_BYTES,
154 .periods_min = HAD_MIN_PERIODS,
155 .periods_max = HAD_MAX_PERIODS,
156 .fifo_size = HAD_FIFO_SIZE,
157};
158
313d9f28
TI		 159/* Get the active PCM substream;
160 * Call had_substream_put() for unreferecing.
161 * Don't call this inside had_spinlock, as it takes by itself
162 */
163static struct snd_pcm_substream *
164had_substream_get(struct snd_intelhad *intelhaddata)
165{
166 struct snd_pcm_substream *substream;
167 unsigned long flags;
168
169 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
170 substream = intelhaddata->stream_info.substream;
171 if (substream)
172 intelhaddata->stream_info.substream_refcount++;
173 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
174 return substream;
175}
176
177/* Unref the active PCM substream;
178 * Don't call this inside had_spinlock, as it takes by itself
179 */
180static void had_substream_put(struct snd_intelhad *intelhaddata)
181{
182 unsigned long flags;
183
184 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
185 intelhaddata->stream_info.substream_refcount--;
186 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
187}
188
5dab11d8 189/* Register access functions */
da864809
TI		 190static inline void
191mid_hdmi_audio_read(struct snd_intelhad *ctx, u32 reg, u32 *val)
5dab11d8 192{
da864809 193 *val = ioread32(ctx->mmio_start + ctx->had_config_offset + reg);
5dab11d8
JA		 194}
195
da864809
TI		 196static inline void
197mid_hdmi_audio_write(struct snd_intelhad *ctx, u32 reg, u32 val)
5dab11d8 198{
da864809 199 iowrite32(val, ctx->mmio_start + ctx->had_config_offset + reg);
5dab11d8
JA		 200}
201
372d855f
TI		 202static int had_read_register(struct snd_intelhad *intelhaddata,
203 u32 offset, u32 *data)
5dab11d8 204{
79f439ea
TI		 205 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
206 return -ENODEV;
5dab11d8 207
da864809
TI		 208 mid_hdmi_audio_read(intelhaddata, offset, data);
209 return 0;
210}
211
212static void fixup_dp_config(struct snd_intelhad *intelhaddata,
213 u32 offset, u32 *data)
214{
215 if (intelhaddata->dp_output) {
216 if (offset == AUD_CONFIG && (*data & AUD_CONFIG_VALID_BIT))
217 *data |= AUD_CONFIG_DP_MODE | AUD_CONFIG_BLOCK_BIT;
218 }
5dab11d8
JA		 219}
220
372d855f
TI		 221static int had_write_register(struct snd_intelhad *intelhaddata,
222 u32 offset, u32 data)
5dab11d8 223{
79f439ea
TI		 224 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
225 return -ENODEV;
5dab11d8 226
da864809
TI		 227 fixup_dp_config(intelhaddata, offset, &data);
228 mid_hdmi_audio_write(intelhaddata, offset, data);
229 return 0;
5dab11d8
JA		 230}
231
372d855f
TI		 232static int had_read_modify(struct snd_intelhad *intelhaddata, u32 offset,
233 u32 data, u32 mask)
5dab11d8 234{
da864809 235 u32 val_tmp;
5dab11d8 236
79f439ea
TI		 237 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
238 return -ENODEV;
5dab11d8 239
da864809
TI		 240 mid_hdmi_audio_read(intelhaddata, offset, &val_tmp);
241 val_tmp &= ~mask;
242 val_tmp |= (data & mask);
243
244 fixup_dp_config(intelhaddata, offset, &val_tmp);
245 mid_hdmi_audio_write(intelhaddata, offset, val_tmp);
246 return 0;
5dab11d8 247}
da864809
TI		 248
249/*
313d9f28
TI		 250 * enable / disable audio configuration
251 *
da864809
TI		 252 * The had_read_modify() function should not directly be used on VLV2 for
253 * updating AUD_CONFIG register.
5dab11d8
JA		 254 * This is because:
255 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
256 * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always
257 * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
258 * register. This field should be 1xy binary for configuration with 6 or
259 * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
260 * causes the "channels" field to be updated as 0xy binary resulting in
261 * bad audio. The fix is to always write the AUD_CONFIG[6:4] with
262 * appropriate value when doing read-modify of AUD_CONFIG register.
5dab11d8 263 */
313d9f28
TI		 264static void snd_intelhad_enable_audio(struct snd_pcm_substream *substream,
265 struct snd_intelhad *intelhaddata,
266 bool enable)
5dab11d8 267{
7ceba75f 268 union aud_cfg cfg_val = {.regval = 0};
313d9f28 269 u8 channels, data, mask;
5dab11d8
JA		 270
271 /*
272 * If substream is NULL, there is no active stream.
273 * In this case just set channels to 2
274 */
313d9f28 275 channels = substream ? substream->runtime->channels : 2;
7ceba75f 276 cfg_val.regx.num_ch = channels - 2;
5dab11d8 277
7ceba75f 278 data = cfg_val.regval;
313d9f28
TI		 279 if (enable)
280 data |= 1;
281 mask = AUD_CONFIG_CH_MASK | 1;
5dab11d8 282
c75b0476
TI		 283 dev_dbg(intelhaddata->dev, "%s : data = %x, mask =%x\n",
284 __func__, data, mask);
5dab11d8 285
313d9f28 286 had_read_modify(intelhaddata, AUD_CONFIG, data, mask);
5dab11d8
JA		 287}
288
313d9f28 289/* enable / disable the audio interface */
372d855f 290static void snd_intelhad_enable_audio_int(struct snd_intelhad *ctx, bool enable)
da864809
TI		 291{
292 u32 status_reg;
293
294 if (enable) {
4151ee84 295 mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS, &status_reg);
da864809 296 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
4151ee84
TI		 297 mid_hdmi_audio_write(ctx, AUD_HDMI_STATUS, status_reg);
298 mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS, &status_reg);
da864809
TI		 299 }
300}
301
79dda75a
TI		 302static void snd_intelhad_reset_audio(struct snd_intelhad *intelhaddata,
303 u8 reset)
5dab11d8 304{
4151ee84 305 had_write_register(intelhaddata, AUD_HDMI_STATUS, reset);
5dab11d8
JA		 306}
307
2e52f5e5 308/*
5dab11d8
JA		 309 * initialize audio channel status registers
310 * This function is called in the prepare callback
311 */
312static int had_prog_status_reg(struct snd_pcm_substream *substream,
313 struct snd_intelhad *intelhaddata)
314{
7ceba75f
TI		 315 union aud_cfg cfg_val = {.regval = 0};
316 union aud_ch_status_0 ch_stat0 = {.regval = 0};
317 union aud_ch_status_1 ch_stat1 = {.regval = 0};
5dab11d8
JA		 318 int format;
319
7ceba75f 320 ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
2e52f5e5 321 IEC958_AES0_NONAUDIO) >> 1;
7ceba75f 322 ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
2e52f5e5 323 IEC958_AES3_CON_CLOCK) >> 4;
7ceba75f 324 cfg_val.regx.val_bit = ch_stat0.regx.lpcm_id;
5dab11d8
JA		 325
326 switch (substream->runtime->rate) {
327 case AUD_SAMPLE_RATE_32:
7ceba75f 328 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
5dab11d8
JA		 329 break;
330
331 case AUD_SAMPLE_RATE_44_1:
7ceba75f 332 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
5dab11d8
JA		 333 break;
334 case AUD_SAMPLE_RATE_48:
7ceba75f 335 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
5dab11d8
JA		 336 break;
337 case AUD_SAMPLE_RATE_88_2:
7ceba75f 338 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
5dab11d8
JA		 339 break;
340 case AUD_SAMPLE_RATE_96:
7ceba75f 341 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
5dab11d8
JA		 342 break;
343 case AUD_SAMPLE_RATE_176_4:
7ceba75f 344 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
5dab11d8
JA		 345 break;
346 case AUD_SAMPLE_RATE_192:
7ceba75f 347 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
5dab11d8
JA		 348 break;
349
350 default:
351 /* control should never come here */
352 return -EINVAL;
5dab11d8 353 }
2e52f5e5 354
79dda75a 355 had_write_register(intelhaddata,
7ceba75f 356 AUD_CH_STATUS_0, ch_stat0.regval);
5dab11d8
JA		 357
358 format = substream->runtime->format;
359
360 if (format == SNDRV_PCM_FORMAT_S16_LE) {
7ceba75f
TI		 361 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
362 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
5dab11d8 363 } else if (format == SNDRV_PCM_FORMAT_S24_LE) {
7ceba75f
TI		 364 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
365 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
5dab11d8 366 } else {
7ceba75f
TI		 367 ch_stat1.regx.max_wrd_len = 0;
368 ch_stat1.regx.wrd_len = 0;
5dab11d8 369 }
2e52f5e5 370
79dda75a 371 had_write_register(intelhaddata,
7ceba75f 372 AUD_CH_STATUS_1, ch_stat1.regval);
5dab11d8
JA		 373 return 0;
374}
375
76296ef0 376/*
5dab11d8
JA		 377 * function to initialize audio
378 * registers and buffer confgiuration registers
379 * This function is called in the prepare callback
380 */
76296ef0
TI		 381static int snd_intelhad_audio_ctrl(struct snd_pcm_substream *substream,
382 struct snd_intelhad *intelhaddata)
5dab11d8 383{
7ceba75f
TI		 384 union aud_cfg cfg_val = {.regval = 0};
385 union aud_buf_config buf_cfg = {.regval = 0};
5dab11d8
JA		 386 u8 channels;
387
388 had_prog_status_reg(substream, intelhaddata);
389
7ceba75f
TI		 390 buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
391 buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
392 buf_cfg.regx.aud_delay = 0;
393 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval);
5dab11d8
JA		 394
395 channels = substream->runtime->channels;
7ceba75f 396 cfg_val.regx.num_ch = channels - 2;
5dab11d8 397 if (channels <= 2)
7ceba75f 398 cfg_val.regx.layout = LAYOUT0;
5dab11d8 399 else
7ceba75f 400 cfg_val.regx.layout = LAYOUT1;
5dab11d8 401
7ceba75f
TI		 402 cfg_val.regx.val_bit = 1;
403 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
5dab11d8
JA		 404 return 0;
405}
406
5dab11d8
JA		 407/*
408 * Compute derived values in channel_allocations[].
409 */
410static void init_channel_allocations(void)
411{
412 int i, j;
413 struct cea_channel_speaker_allocation *p;
414
5dab11d8
JA		 415 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
416 p = channel_allocations + i;
417 p->channels = 0;
418 p->spk_mask = 0;
419 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
420 if (p->speakers[j]) {
421 p->channels++;
422 p->spk_mask |= p->speakers[j];
423 }
424 }
425}
426
427/*
428 * The transformation takes two steps:
429 *
430 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
431 * spk_mask => (channel_allocations[]) => ai->CA
432 *
433 * TODO: it could select the wrong CA from multiple candidates.
434 */
435static int snd_intelhad_channel_allocation(struct snd_intelhad *intelhaddata,
436 int channels)
437{
438 int i;
439 int ca = 0;
440 int spk_mask = 0;
441
442 /*
443 * CA defaults to 0 for basic stereo audio
444 */
445 if (channels <= 2)
446 return 0;
447
448 /*
449 * expand ELD's speaker allocation mask
450 *
451 * ELD tells the speaker mask in a compact(paired) form,
452 * expand ELD's notions to match the ones used by Audio InfoFrame.
453 */
454
455 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
df0435db 456 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
5dab11d8
JA		 457 spk_mask |= eld_speaker_allocation_bits[i];
458 }
459
460 /* search for the first working match in the CA table */
461 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
462 if (channels == channel_allocations[i].channels &&
463 (spk_mask & channel_allocations[i].spk_mask) ==
464 channel_allocations[i].spk_mask) {
465 ca = channel_allocations[i].ca_index;
466 break;
467 }
468 }
469
c75b0476 470 dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
5dab11d8
JA		 471
472 return ca;
473}
474
475/* from speaker bit mask to ALSA API channel position */
476static int spk_to_chmap(int spk)
477{
4a5ddb2c 478 const struct channel_map_table *t = map_tables;
5dab11d8
JA		 479
480 for (; t->map; t++) {
481 if (t->spk_mask == spk)
482 return t->map;
483 }
484 return 0;
485}
486
372d855f 487static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
5dab11d8 488{
2e52f5e5 489 int i, c;
5dab11d8
JA		 490 int spk_mask = 0;
491 struct snd_pcm_chmap_elem *chmap;
492 u8 eld_high, eld_high_mask = 0xF0;
493 u8 high_msb;
494
495 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
2e52f5e5 496 if (!chmap) {
5dab11d8
JA		 497 intelhaddata->chmap->chmap = NULL;
498 return;
499 }
500
df0435db
TI		 501 dev_dbg(intelhaddata->dev, "eld speaker = %x\n",
502 intelhaddata->eld[DRM_ELD_SPEAKER]);
5dab11d8
JA		 503
504 /* WA: Fix the max channel supported to 8 */
505
506 /*
507 * Sink may support more than 8 channels, if eld_high has more than
508 * one bit set. SOC supports max 8 channels.
509 * Refer eld_speaker_allocation_bits, for sink speaker allocation
510 */
511
512 /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
df0435db 513 eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask;
5dab11d8
JA		 514 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
515 /* eld_high & (eld_high-1): if more than 1 bit set */
516 /* 0x1F: 7 channels */
517 for (i = 1; i < 4; i++) {
518 high_msb = eld_high & (0x80 >> i);
519 if (high_msb) {
df0435db 520 intelhaddata->eld[DRM_ELD_SPEAKER] &=
5dab11d8
JA		 521 high_msb | 0xF;
522 break;
523 }
524 }
525 }
526
527 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
df0435db 528 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
5dab11d8
JA		 529 spk_mask |= eld_speaker_allocation_bits[i];
530 }
531
532 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
533 if (spk_mask == channel_allocations[i].spk_mask) {
534 for (c = 0; c < channel_allocations[i].channels; c++) {
535 chmap->map[c] = spk_to_chmap(
536 channel_allocations[i].speakers[
2e52f5e5 537 (MAX_SPEAKERS - 1) - c]);
5dab11d8
JA		 538 }
539 chmap->channels = channel_allocations[i].channels;
540 intelhaddata->chmap->chmap = chmap;
541 break;
542 }
543 }
544 if (i >= ARRAY_SIZE(channel_allocations)) {
545 intelhaddata->chmap->chmap = NULL;
546 kfree(chmap);
547 }
548}
549
550/*
551 * ALSA API channel-map control callbacks
552 */
553static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
554 struct snd_ctl_elem_info *uinfo)
555{
556 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
557 struct snd_intelhad *intelhaddata = info->private_data;
558
559 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
560 return -ENODEV;
561 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
562 uinfo->count = HAD_MAX_CHANNEL;
563 uinfo->value.integer.min = 0;
564 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
565 return 0;
566}
567
568static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
569 struct snd_ctl_elem_value *ucontrol)
570{
571 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
572 struct snd_intelhad *intelhaddata = info->private_data;
2e52f5e5 573 int i;
5dab11d8
JA		 574 const struct snd_pcm_chmap_elem *chmap;
575
576 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
577 return -ENODEV;
8f8d1d7f
TI		 578
579 mutex_lock(&intelhaddata->mutex);
580 if (!intelhaddata->chmap->chmap) {
581 mutex_unlock(&intelhaddata->mutex);
5dab11d8 582 return -ENODATA;
8f8d1d7f
TI		 583 }
584
5dab11d8 585 chmap = intelhaddata->chmap->chmap;
c75b0476 586 for (i = 0; i < chmap->channels; i++)
5dab11d8 587 ucontrol->value.integer.value[i] = chmap->map[i];
8f8d1d7f 588 mutex_unlock(&intelhaddata->mutex);
5dab11d8
JA		 589
590 return 0;
591}
592
593static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
594 struct snd_pcm *pcm)
595{
2e52f5e5 596 int err;
5dab11d8
JA		 597
598 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
599 NULL, 0, (unsigned long)intelhaddata,
600 &intelhaddata->chmap);
601 if (err < 0)
602 return err;
603
604 intelhaddata->chmap->private_data = intelhaddata;
e9d65abf
TI		 605 intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
606 intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
5dab11d8
JA		 607 intelhaddata->chmap->chmap = NULL;
608 return 0;
609}
610
76296ef0
TI		 611/*
612 * snd_intelhad_prog_dip - to initialize Data Island Packets registers
5dab11d8
JA		 613 *
614 * @substream:substream for which the prepare function is called
615 * @intelhaddata:substream private data
616 *
617 * This function is called in the prepare callback
618 */
76296ef0
TI		 619static void snd_intelhad_prog_dip(struct snd_pcm_substream *substream,
620 struct snd_intelhad *intelhaddata)
5dab11d8
JA		 621{
622 int i;
7ceba75f
TI		 623 union aud_ctrl_st ctrl_state = {.regval = 0};
624 union aud_info_frame2 frame2 = {.regval = 0};
625 union aud_info_frame3 frame3 = {.regval = 0};
5dab11d8 626 u8 checksum = 0;
964ca808 627 u32 info_frame;
5dab11d8 628 int channels;
36ed3466 629 int ca;
5dab11d8
JA		 630
631 channels = substream->runtime->channels;
632
7ceba75f 633 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
5dab11d8 634
36ed3466 635 ca = snd_intelhad_channel_allocation(intelhaddata, channels);
964ca808
PLB		 636 if (intelhaddata->dp_output) {
637 info_frame = DP_INFO_FRAME_WORD1;
36ed3466 638 frame2.regval = (substream->runtime->channels - 1) | (ca << 24);
964ca808
PLB		 639 } else {
640 info_frame = HDMI_INFO_FRAME_WORD1;
7ceba75f 641 frame2.regx.chnl_cnt = substream->runtime->channels - 1;
36ed3466 642 frame3.regx.chnl_alloc = ca;
5dab11d8 643
2e52f5e5 644 /* Calculte the byte wide checksum for all valid DIP words */
964ca808 645 for (i = 0; i < BYTES_PER_WORD; i++)
7ceba75f 646 checksum += (info_frame >> (i * 8)) & 0xff;
964ca808 647 for (i = 0; i < BYTES_PER_WORD; i++)
7ceba75f 648 checksum += (frame2.regval >> (i * 8)) & 0xff;
964ca808 649 for (i = 0; i < BYTES_PER_WORD; i++)
7ceba75f 650 checksum += (frame3.regval >> (i * 8)) & 0xff;
5dab11d8 651
7ceba75f 652 frame2.regx.chksum = -(checksum);
964ca808 653 }
5dab11d8 654
4151ee84 655 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
7ceba75f
TI		 656 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval);
657 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval);
5dab11d8
JA		 658
659 /* program remaining DIP words with zero */
660 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
4151ee84 661 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
5dab11d8 662
7ceba75f
TI		 663 ctrl_state.regx.dip_freq = 1;
664 ctrl_state.regx.dip_en_sta = 1;
665 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
5dab11d8
JA		 666}
667
2e52f5e5
TI		 668/*
669 * snd_intelhad_prog_buffer - programs buffer address and length registers
313d9f28
TI		 670 * @substream: substream for which the prepare function is called
671 * @intelhaddata: substream private data
5dab11d8
JA		 672 *
673 * This function programs ring buffer address and length into registers.
674 */
313d9f28
TI		 675static int snd_intelhad_prog_buffer(struct snd_pcm_substream *substream,
676 struct snd_intelhad *intelhaddata,
677 int start, int end)
5dab11d8
JA		 678{
679 u32 ring_buf_addr, ring_buf_size, period_bytes;
680 u8 i, num_periods;
5dab11d8
JA		 681
682 ring_buf_addr = substream->runtime->dma_addr;
683 ring_buf_size = snd_pcm_lib_buffer_bytes(substream);
684 intelhaddata->stream_info.ring_buf_size = ring_buf_size;
685 period_bytes = frames_to_bytes(substream->runtime,
686 substream->runtime->period_size);
687 num_periods = substream->runtime->periods;
688
689 /*
690 * buffer addr should be 64 byte aligned, period bytes
691 * will be used to calculate addr offset
692 */
693 period_bytes &= ~0x3F;
694
695 /* Hardware supports MAX_PERIODS buffers */
696 if (end >= HAD_MAX_PERIODS)
697 return -EINVAL;
698
699 for (i = start; i <= end; i++) {
700 /* Program the buf registers with addr and len */
701 intelhaddata->buf_info[i].buf_addr = ring_buf_addr +
702 (i * period_bytes);
703 if (i < num_periods-1)
704 intelhaddata->buf_info[i].buf_size = period_bytes;
705 else
706 intelhaddata->buf_info[i].buf_size = ring_buf_size -
2e52f5e5 707 (i * period_bytes);
5dab11d8 708
79dda75a
TI		 709 had_write_register(intelhaddata,
710 AUD_BUF_A_ADDR + (i * HAD_REG_WIDTH),
5dab11d8
JA		 711 intelhaddata->buf_info[i].buf_addr |
712 BIT(0) | BIT(1));
79dda75a
TI		 713 had_write_register(intelhaddata,
714 AUD_BUF_A_LENGTH + (i * HAD_REG_WIDTH),
5dab11d8
JA		 715 period_bytes);
716 intelhaddata->buf_info[i].is_valid = true;
717 }
c75b0476
TI		 718 dev_dbg(intelhaddata->dev, "%s:buf[%d-%d] addr=%#x and size=%d\n",
719 __func__, start, end,
720 intelhaddata->buf_info[start].buf_addr,
721 intelhaddata->buf_info[start].buf_size);
5dab11d8
JA		 722 intelhaddata->valid_buf_cnt = num_periods;
723 return 0;
724}
725
372d855f 726static int snd_intelhad_read_len(struct snd_intelhad *intelhaddata)
5dab11d8
JA		 727{
728 int i, retval = 0;
729 u32 len[4];
730
731 for (i = 0; i < 4 ; i++) {
79dda75a
TI		 732 had_read_register(intelhaddata,
733 AUD_BUF_A_LENGTH + (i * HAD_REG_WIDTH),
734 &len[i]);
5dab11d8
JA		 735 if (!len[i])
736 retval++;
737 }
738 if (retval != 1) {
739 for (i = 0; i < 4 ; i++)
c75b0476
TI		 740 dev_dbg(intelhaddata->dev, "buf[%d] size=%d\n",
741 i, len[i]);
5dab11d8
JA		 742 }
743
744 return retval;
745}
746
964ca808
PLB		 747static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
748{
749 u32 maud_val;
750
2e52f5e5 751 /* Select maud according to DP 1.2 spec */
964ca808
PLB		 752 if (link_rate == DP_2_7_GHZ) {
753 switch (aud_samp_freq) {
754 case AUD_SAMPLE_RATE_32:
755 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
756 break;
757
758 case AUD_SAMPLE_RATE_44_1:
759 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
760 break;
761
762 case AUD_SAMPLE_RATE_48:
763 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
764 break;
765
766 case AUD_SAMPLE_RATE_88_2:
767 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
768 break;
769
770 case AUD_SAMPLE_RATE_96:
771 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
772 break;
773
774 case AUD_SAMPLE_RATE_176_4:
775 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
776 break;
777
778 case HAD_MAX_RATE:
779 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
780 break;
781
782 default:
783 maud_val = -EINVAL;
784 break;
785 }
786 } else if (link_rate == DP_1_62_GHZ) {
787 switch (aud_samp_freq) {
788 case AUD_SAMPLE_RATE_32:
789 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
790 break;
791
792 case AUD_SAMPLE_RATE_44_1:
793 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
794 break;
795
796 case AUD_SAMPLE_RATE_48:
797 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
798 break;
799
800 case AUD_SAMPLE_RATE_88_2:
801 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
802 break;
803
804 case AUD_SAMPLE_RATE_96:
805 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
806 break;
807
808 case AUD_SAMPLE_RATE_176_4:
809 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
810 break;
811
812 case HAD_MAX_RATE:
813 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
814 break;
815
816 default:
817 maud_val = -EINVAL;
818 break;
819 }
820 } else
821 maud_val = -EINVAL;
822
823 return maud_val;
824}
825
76296ef0
TI		 826/*
827 * snd_intelhad_prog_cts - Program HDMI audio CTS value
5dab11d8
JA		 828 *
829 * @aud_samp_freq: sampling frequency of audio data
830 * @tmds: sampling frequency of the display data
831 * @n_param: N value, depends on aud_samp_freq
832 * @intelhaddata:substream private data
833 *
834 * Program CTS register based on the audio and display sampling frequency
835 */
76296ef0
TI		 836static void snd_intelhad_prog_cts(u32 aud_samp_freq, u32 tmds,
837 u32 link_rate, u32 n_param,
838 struct snd_intelhad *intelhaddata)
5dab11d8
JA		 839{
840 u32 cts_val;
841 u64 dividend, divisor;
842
964ca808
PLB		 843 if (intelhaddata->dp_output) {
844 /* Substitute cts_val with Maud according to DP 1.2 spec*/
845 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
846 } else {
847 /* Calculate CTS according to HDMI 1.3a spec*/
848 dividend = (u64)tmds * n_param*1000;
849 divisor = 128 * aud_samp_freq;
850 cts_val = div64_u64(dividend, divisor);
851 }
c75b0476 852 dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
964ca808 853 tmds, n_param, cts_val);
79dda75a 854 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
5dab11d8
JA		 855}
856
857static int had_calculate_n_value(u32 aud_samp_freq)
858{
2e52f5e5 859 int n_val;
5dab11d8
JA		 860
861 /* Select N according to HDMI 1.3a spec*/
862 switch (aud_samp_freq) {
863 case AUD_SAMPLE_RATE_32:
864 n_val = 4096;
2e52f5e5 865 break;
5dab11d8
JA		 866
867 case AUD_SAMPLE_RATE_44_1:
868 n_val = 6272;
2e52f5e5 869 break;
5dab11d8
JA		 870
871 case AUD_SAMPLE_RATE_48:
872 n_val = 6144;
2e52f5e5 873 break;
5dab11d8
JA		 874
875 case AUD_SAMPLE_RATE_88_2:
876 n_val = 12544;
2e52f5e5 877 break;
5dab11d8
JA		 878
879 case AUD_SAMPLE_RATE_96:
880 n_val = 12288;
2e52f5e5 881 break;
5dab11d8
JA		 882
883 case AUD_SAMPLE_RATE_176_4:
884 n_val = 25088;
2e52f5e5 885 break;
5dab11d8
JA		 886
887 case HAD_MAX_RATE:
888 n_val = 24576;
2e52f5e5 889 break;
5dab11d8
JA		 890
891 default:
892 n_val = -EINVAL;
2e52f5e5 893 break;
5dab11d8
JA		 894 }
895 return n_val;
896}
897
76296ef0
TI		 898/*
899 * snd_intelhad_prog_n - Program HDMI audio N value
5dab11d8
JA		 900 *
901 * @aud_samp_freq: sampling frequency of audio data
902 * @n_param: N value, depends on aud_samp_freq
903 * @intelhaddata:substream private data
904 *
905 * This function is called in the prepare callback.
906 * It programs based on the audio and display sampling frequency
907 */
76296ef0
TI		 908static int snd_intelhad_prog_n(u32 aud_samp_freq, u32 *n_param,
909 struct snd_intelhad *intelhaddata)
5dab11d8 910{
2e52f5e5 911 int n_val;
5dab11d8 912
964ca808
PLB		 913 if (intelhaddata->dp_output) {
914 /*
915 * According to DP specs, Maud and Naud values hold
916 * a relationship, which is stated as:
917 * Maud/Naud = 512 * fs / f_LS_Clk
918 * where, fs is the sampling frequency of the audio stream
919 * and Naud is 32768 for Async clock.
920 */
921
922 n_val = DP_NAUD_VAL;
923 } else
924 n_val = had_calculate_n_value(aud_samp_freq);
5dab11d8
JA		 925
926 if (n_val < 0)
927 return n_val;
928
79dda75a 929 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
5dab11d8
JA		 930 *n_param = n_val;
931 return 0;
932}
933
03c34377
TI		 934#define MAX_CNT 0xFF
935
372d855f 936static void snd_intelhad_handle_underrun(struct snd_intelhad *intelhaddata)
5dab11d8 937{
79f439ea 938 u32 hdmi_status = 0, i = 0;
5dab11d8
JA		 939
940 /* Handle Underrun interrupt within Audio Unit */
79dda75a 941 had_write_register(intelhaddata, AUD_CONFIG, 0);
5dab11d8 942 /* Reset buffer pointers */
4151ee84
TI		 943 had_write_register(intelhaddata, AUD_HDMI_STATUS, 1);
944 had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
2e52f5e5 945 /*
5dab11d8
JA		 946 * The interrupt status 'sticky' bits might not be cleared by
947 * setting '1' to that bit once...
948 */
949 do { /* clear bit30, 31 AUD_HDMI_STATUS */
4151ee84 950 had_read_register(intelhaddata, AUD_HDMI_STATUS,
79dda75a 951 &hdmi_status);
c75b0476 952 dev_dbg(intelhaddata->dev, "HDMI status =0x%x\n", hdmi_status);
5dab11d8
JA		 953 if (hdmi_status & AUD_CONFIG_MASK_UNDERRUN) {
954 i++;
79dda75a 955 had_write_register(intelhaddata,
4151ee84 956 AUD_HDMI_STATUS, hdmi_status);
5dab11d8
JA		 957 } else
958 break;
959 } while (i < MAX_CNT);
960 if (i >= MAX_CNT)
c75b0476 961 dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
5dab11d8
JA		 962}
963
2e52f5e5 964/*
5dab11d8
JA		 965 * snd_intelhad_open - stream initializations are done here
966 * @substream:substream for which the stream function is called
967 *
968 * This function is called whenever a PCM stream is opened
969 */
970static int snd_intelhad_open(struct snd_pcm_substream *substream)
971{
972 struct snd_intelhad *intelhaddata;
973 struct snd_pcm_runtime *runtime;
5dab11d8
JA		 974 int retval;
975
5dab11d8 976 intelhaddata = snd_pcm_substream_chip(substream);
5dab11d8 977 runtime = substream->runtime;
6ddb3ab6 978 intelhaddata->underrun_count = 0;
5dab11d8 979
182cdf23 980 pm_runtime_get_sync(intelhaddata->dev);
5dab11d8 981
79f439ea 982 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
c75b0476
TI		 983 dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
984 __func__);
5dab11d8 985 retval = -ENODEV;
fa5dfe6a 986 goto error;
5dab11d8
JA		 987 }
988
989 /* set the runtime hw parameter with local snd_pcm_hardware struct */
990 runtime->hw = snd_intel_hadstream;
991
5dab11d8
JA		 992 retval = snd_pcm_hw_constraint_integer(runtime,
993 SNDRV_PCM_HW_PARAM_PERIODS);
994 if (retval < 0)
fa5dfe6a 995 goto error;
5dab11d8
JA		 996
997 /* Make sure, that the period size is always aligned
998 * 64byte boundary
999 */
1000 retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
1001 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
1002 if (retval < 0) {
c75b0476
TI		 1003 dev_dbg(intelhaddata->dev, "%s:step_size=64 failed,err=%d\n",
1004 __func__, retval);
fa5dfe6a 1005 goto error;
5dab11d8
JA		 1006 }
1007
313d9f28
TI		 1008 spin_lock_irq(&intelhaddata->had_spinlock);
1009 intelhaddata->stream_info.substream = substream;
1010 intelhaddata->stream_info.substream_refcount++;
1011 spin_unlock_irq(&intelhaddata->had_spinlock);
1012
5dab11d8 1013 return retval;
fa5dfe6a 1014 error:
5dab11d8 1015 pm_runtime_put(intelhaddata->dev);
5dab11d8
JA		 1016 return retval;
1017}
1018
2e52f5e5
TI		 1019/*
1020 * snd_intelhad_close - to free parameteres when stream is stopped
5dab11d8
JA		 1021 * @substream: substream for which the function is called
1022 *
1023 * This function is called by ALSA framework when stream is stopped
1024 */
1025static int snd_intelhad_close(struct snd_pcm_substream *substream)
1026{
1027 struct snd_intelhad *intelhaddata;
5dab11d8 1028
5dab11d8 1029 intelhaddata = snd_pcm_substream_chip(substream);
5dab11d8
JA		 1030
1031 intelhaddata->stream_info.buffer_rendered = 0;
313d9f28
TI		 1032 spin_lock_irq(&intelhaddata->had_spinlock);
1033 intelhaddata->stream_info.substream = NULL;
1034 intelhaddata->stream_info.substream_refcount--;
1035 while (intelhaddata->stream_info.substream_refcount > 0) {
1036 spin_unlock_irq(&intelhaddata->had_spinlock);
1037 cpu_relax();
1038 spin_lock_irq(&intelhaddata->had_spinlock);
1039 }
1040 spin_unlock_irq(&intelhaddata->had_spinlock);
5dab11d8
JA		 1041
1042 /* Check if following drv_status modification is required - VA */
1043 if (intelhaddata->drv_status != HAD_DRV_DISCONNECTED) {
1044 intelhaddata->drv_status = HAD_DRV_CONNECTED;
c75b0476
TI		 1045 dev_dbg(intelhaddata->dev,
1046 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
5dab11d8
JA		 1047 __func__, __LINE__);
1048 }
5dab11d8
JA		 1049 pm_runtime_put(intelhaddata->dev);
1050 return 0;
1051}
1052
2e52f5e5
TI		 1053/*
1054 * snd_intelhad_hw_params - to setup the hardware parameters
1055 * like allocating the buffers
1056 * @substream: substream for which the function is called
5dab11d8
JA		 1057 * @hw_params: hardware parameters
1058 *
1059 * This function is called by ALSA framework when hardware params are set
1060 */
1061static int snd_intelhad_hw_params(struct snd_pcm_substream *substream,
1062 struct snd_pcm_hw_params *hw_params)
1063{
c75b0476 1064 struct snd_intelhad *intelhaddata;
5dab11d8
JA		 1065 unsigned long addr;
1066 int pages, buf_size, retval;
1067
5dab11d8
JA		 1068 if (!hw_params)
1069 return -EINVAL;
1070
c75b0476 1071 intelhaddata = snd_pcm_substream_chip(substream);
5dab11d8
JA		 1072 buf_size = params_buffer_bytes(hw_params);
1073 retval = snd_pcm_lib_malloc_pages(substream, buf_size);
1074 if (retval < 0)
1075 return retval;
c75b0476
TI		 1076 dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
1077 __func__, buf_size);
5dab11d8
JA		 1078 /* mark the pages as uncached region */
1079 addr = (unsigned long) substream->runtime->dma_area;
1080 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE;
1081 retval = set_memory_uc(addr, pages);
1082 if (retval) {
c75b0476
TI		 1083 dev_err(intelhaddata->dev, "set_memory_uc failed.Error:%d\n",
1084 retval);
5dab11d8
JA		 1085 return retval;
1086 }
1087 memset(substream->runtime->dma_area, 0, buf_size);
1088
1089 return retval;
1090}
1091
2e52f5e5
TI		 1092/*
1093 * snd_intelhad_hw_free - to release the resources allocated during
1094 * hardware params setup
5dab11d8
JA		 1095 * @substream: substream for which the function is called
1096 *
1097 * This function is called by ALSA framework before close callback.
5dab11d8
JA		 1098 */
1099static int snd_intelhad_hw_free(struct snd_pcm_substream *substream)
1100{
1101 unsigned long addr;
1102 u32 pages;
1103
5dab11d8
JA		 1104 /* mark back the pages as cached/writeback region before the free */
1105 if (substream->runtime->dma_area != NULL) {
1106 addr = (unsigned long) substream->runtime->dma_area;
1107 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) /
1108 PAGE_SIZE;
1109 set_memory_wb(addr, pages);
1110 return snd_pcm_lib_free_pages(substream);
1111 }
1112 return 0;
1113}
1114
2e52f5e5 1115/*
5dab11d8 1116 * snd_intelhad_pcm_trigger - stream activities are handled here
2e52f5e5
TI		 1117 * @substream: substream for which the stream function is called
1118 * @cmd: the stream commamd thats requested from upper layer
1119 *
5dab11d8
JA		 1120 * This function is called whenever an a stream activity is invoked
1121 */
1122static int snd_intelhad_pcm_trigger(struct snd_pcm_substream *substream,
1123 int cmd)
1124{
da864809 1125 int retval = 0;
5dab11d8 1126 struct snd_intelhad *intelhaddata;
5dab11d8 1127
5dab11d8 1128 intelhaddata = snd_pcm_substream_chip(substream);
5dab11d8
JA		 1129
1130 switch (cmd) {
1131 case SNDRV_PCM_TRIGGER_START:
182cdf23
TI		 1132 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1133 case SNDRV_PCM_TRIGGER_RESUME:
5dab11d8 1134 /* Disable local INTRs till register prgmng is done */
79f439ea 1135 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
c75b0476
TI		 1136 dev_dbg(intelhaddata->dev,
1137 "_START: HDMI cable plugged-out\n");
5dab11d8
JA		 1138 retval = -ENODEV;
1139 break;
1140 }
5dab11d8 1141
f69bd104 1142 intelhaddata->stream_info.running = true;
5dab11d8
JA		 1143
1144 /* Enable Audio */
da864809 1145 snd_intelhad_enable_audio_int(intelhaddata, true);
313d9f28 1146 snd_intelhad_enable_audio(substream, intelhaddata, true);
5dab11d8
JA		 1147 break;
1148
1149 case SNDRV_PCM_TRIGGER_STOP:
182cdf23
TI		 1150 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1151 case SNDRV_PCM_TRIGGER_SUSPEND:
bcce775c 1152 spin_lock(&intelhaddata->had_spinlock);
5dab11d8
JA		 1153 intelhaddata->curr_buf = 0;
1154
c75b0476 1155 /* Stop reporting BUFFER_DONE/UNDERRUN to above layers */
5dab11d8 1156
f69bd104 1157 intelhaddata->stream_info.running = false;
bcce775c 1158 spin_unlock(&intelhaddata->had_spinlock);
5dab11d8 1159 /* Disable Audio */
da864809 1160 snd_intelhad_enable_audio_int(intelhaddata, false);
313d9f28 1161 snd_intelhad_enable_audio(substream, intelhaddata, false);
5dab11d8 1162 /* Reset buffer pointers */
79dda75a
TI		 1163 snd_intelhad_reset_audio(intelhaddata, 1);
1164 snd_intelhad_reset_audio(intelhaddata, 0);
da864809 1165 snd_intelhad_enable_audio_int(intelhaddata, false);
5dab11d8
JA		 1166 break;
1167
1168 default:
1169 retval = -EINVAL;
1170 }
1171 return retval;
1172}
1173
2e52f5e5
TI		 1174/*
1175 * snd_intelhad_pcm_prepare - internal preparation before starting a stream
1176 * @substream: substream for which the function is called
5dab11d8
JA		 1177 *
1178 * This function is called when a stream is started for internal preparation.
1179 */
1180static int snd_intelhad_pcm_prepare(struct snd_pcm_substream *substream)
1181{
1182 int retval;
1183 u32 disp_samp_freq, n_param;
964ca808 1184 u32 link_rate = 0;
5dab11d8
JA		 1185 struct snd_intelhad *intelhaddata;
1186 struct snd_pcm_runtime *runtime;
5dab11d8 1187
5dab11d8
JA		 1188 intelhaddata = snd_pcm_substream_chip(substream);
1189 runtime = substream->runtime;
5dab11d8 1190
79f439ea 1191 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
c75b0476
TI		 1192 dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
1193 __func__);
5dab11d8
JA		 1194 retval = -ENODEV;
1195 goto prep_end;
1196 }
1197
c75b0476 1198 dev_dbg(intelhaddata->dev, "period_size=%d\n",
5dab11d8 1199 (int)frames_to_bytes(runtime, runtime->period_size));
c75b0476
TI		 1200 dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
1201 dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
1202 (int)snd_pcm_lib_buffer_bytes(substream));
1203 dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
1204 dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
5dab11d8 1205
2e52f5e5 1206 intelhaddata->stream_info.buffer_rendered = 0;
5dab11d8
JA		 1207
1208 /* Get N value in KHz */
da864809 1209 disp_samp_freq = intelhaddata->tmds_clock_speed;
5dab11d8 1210
76296ef0
TI		 1211 retval = snd_intelhad_prog_n(substream->runtime->rate, &n_param,
1212 intelhaddata);
5dab11d8 1213 if (retval) {
c75b0476
TI		 1214 dev_err(intelhaddata->dev,
1215 "programming N value failed %#x\n", retval);
5dab11d8
JA		 1216 goto prep_end;
1217 }
964ca808
PLB		 1218
1219 if (intelhaddata->dp_output)
da864809 1220 link_rate = intelhaddata->link_rate;
964ca808 1221
76296ef0
TI		 1222 snd_intelhad_prog_cts(substream->runtime->rate,
1223 disp_samp_freq, link_rate,
1224 n_param, intelhaddata);
5dab11d8 1225
76296ef0 1226 snd_intelhad_prog_dip(substream, intelhaddata);
5dab11d8 1227
76296ef0 1228 retval = snd_intelhad_audio_ctrl(substream, intelhaddata);
5dab11d8
JA		 1229
1230 /* Prog buffer address */
313d9f28 1231 retval = snd_intelhad_prog_buffer(substream, intelhaddata,
5dab11d8
JA		 1232 HAD_BUF_TYPE_A, HAD_BUF_TYPE_D);
1233
1234 /*
1235 * Program channel mapping in following order:
1236 * FL, FR, C, LFE, RL, RR
1237 */
1238
79dda75a 1239 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
5dab11d8
JA		 1240
1241prep_end:
1242 return retval;
1243}
1244
2e52f5e5 1245/*
5dab11d8 1246 * snd_intelhad_pcm_pointer- to send the current buffer pointerprocessed by hw
2e52f5e5 1247 * @substream: substream for which the function is called
5dab11d8
JA		 1248 *
1249 * This function is called by ALSA framework to get the current hw buffer ptr
1250 * when a period is elapsed
1251 */
1252static snd_pcm_uframes_t snd_intelhad_pcm_pointer(
1253 struct snd_pcm_substream *substream)
1254{
1255 struct snd_intelhad *intelhaddata;
1256 u32 bytes_rendered = 0;
1257 u32 t;
1258 int buf_id;
1259
5dab11d8
JA		 1260 intelhaddata = snd_pcm_substream_chip(substream);
1261
79f439ea
TI		 1262 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED)
1263 return SNDRV_PCM_POS_XRUN;
1264
5dab11d8
JA		 1265 /* Use a hw register to calculate sub-period position reports.
1266 * This makes PulseAudio happier.
1267 */
1268
1269 buf_id = intelhaddata->curr_buf % 4;
79dda75a
TI		 1270 had_read_register(intelhaddata,
1271 AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH), &t);
232892fb
JA		 1272
1273 if ((t == 0) || (t == ((u32)-1L))) {
6ddb3ab6 1274 intelhaddata->underrun_count++;
c75b0476
TI		 1275 dev_dbg(intelhaddata->dev,
1276 "discovered buffer done for buf %d, count = %d\n",
6ddb3ab6 1277 buf_id, intelhaddata->underrun_count);
232892fb 1278
6ddb3ab6 1279 if (intelhaddata->underrun_count > (HAD_MIN_PERIODS/2)) {
c75b0476
TI		 1280 dev_dbg(intelhaddata->dev,
1281 "assume audio_codec_reset, underrun = %d - do xrun\n",
6ddb3ab6
TI		 1282 intelhaddata->underrun_count);
1283 intelhaddata->underrun_count = 0;
232892fb
JA		 1284 return SNDRV_PCM_POS_XRUN;
1285 }
1286 } else {
1287 /* Reset Counter */
6ddb3ab6 1288 intelhaddata->underrun_count = 0;
5dab11d8 1289 }
232892fb 1290
5dab11d8
JA		 1291 t = intelhaddata->buf_info[buf_id].buf_size - t;
1292
1293 if (intelhaddata->stream_info.buffer_rendered)
1294 div_u64_rem(intelhaddata->stream_info.buffer_rendered,
1295 intelhaddata->stream_info.ring_buf_size,
1296 &(bytes_rendered));
1297
7d9e7986 1298 return bytes_to_frames(substream->runtime, bytes_rendered + t);
5dab11d8
JA		 1299}
1300
2e52f5e5 1301/*
5dab11d8 1302 * snd_intelhad_pcm_mmap- mmaps a kernel buffer to user space for copying data
2e52f5e5
TI		 1303 * @substream: substream for which the function is called
1304 * @vma: struct instance of memory VMM memory area
5dab11d8
JA		 1305 *
1306 * This function is called by OS when a user space component
1307 * tries to get mmap memory from driver
1308 */
1309static int snd_intelhad_pcm_mmap(struct snd_pcm_substream *substream,
1310 struct vm_area_struct *vma)
1311{
5dab11d8
JA		 1312 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1313 return remap_pfn_range(vma, vma->vm_start,
1314 substream->dma_buffer.addr >> PAGE_SHIFT,
1315 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1316}
1317
8f8d1d7f 1318/* process mode change of the running stream; called in mutex */
da864809 1319static int hdmi_audio_mode_change(struct snd_intelhad *intelhaddata)
5dab11d8 1320{
da864809 1321 struct snd_pcm_substream *substream;
5dab11d8
JA		 1322 int retval = 0;
1323 u32 disp_samp_freq, n_param;
964ca808 1324 u32 link_rate = 0;
5dab11d8 1325
313d9f28
TI		 1326 substream = had_substream_get(intelhaddata);
1327 if (!substream)
da864809 1328 return 0;
5dab11d8
JA		 1329
1330 /* Disable Audio */
313d9f28 1331 snd_intelhad_enable_audio(substream, intelhaddata, false);
5dab11d8
JA		 1332
1333 /* Update CTS value */
da864809 1334 disp_samp_freq = intelhaddata->tmds_clock_speed;
5dab11d8 1335
76296ef0
TI		 1336 retval = snd_intelhad_prog_n(substream->runtime->rate, &n_param,
1337 intelhaddata);
5dab11d8 1338 if (retval) {
c75b0476
TI		 1339 dev_err(intelhaddata->dev,
1340 "programming N value failed %#x\n", retval);
5dab11d8
JA		 1341 goto out;
1342 }
964ca808
PLB		 1343
1344 if (intelhaddata->dp_output)
da864809 1345 link_rate = intelhaddata->link_rate;
964ca808 1346
76296ef0
TI		 1347 snd_intelhad_prog_cts(substream->runtime->rate,
1348 disp_samp_freq, link_rate,
1349 n_param, intelhaddata);
5dab11d8
JA		 1350
1351 /* Enable Audio */
313d9f28 1352 snd_intelhad_enable_audio(substream, intelhaddata, true);
5dab11d8
JA		 1353
1354out:
313d9f28 1355 had_substream_put(intelhaddata);
5dab11d8
JA		 1356 return retval;
1357}
1358
372d855f
TI		 1359static inline int had_chk_intrmiss(struct snd_intelhad *intelhaddata,
1360 enum intel_had_aud_buf_type buf_id)
1361{
1362 int i, intr_count = 0;
1363 enum intel_had_aud_buf_type buff_done;
1364 u32 buf_size, buf_addr;
372d855f
TI		 1365
1366 buff_done = buf_id;
1367
1368 intr_count = snd_intelhad_read_len(intelhaddata);
1369 if (intr_count > 1) {
1370 /* In case of active playback */
c75b0476
TI		 1371 dev_err(intelhaddata->dev,
1372 "Driver detected %d missed buffer done interrupt(s)\n",
1373 (intr_count - 1));
372d855f
TI		 1374 if (intr_count > 3)
1375 return intr_count;
1376
1377 buf_id += (intr_count - 1);
1378 /* Reprogram registers*/
1379 for (i = buff_done; i < buf_id; i++) {
1380 int j = i % 4;
1381
1382 buf_size = intelhaddata->buf_info[j].buf_size;
1383 buf_addr = intelhaddata->buf_info[j].buf_addr;
1384 had_write_register(intelhaddata,
1385 AUD_BUF_A_LENGTH +
1386 (j * HAD_REG_WIDTH), buf_size);
1387 had_write_register(intelhaddata,
1388 AUD_BUF_A_ADDR+(j * HAD_REG_WIDTH),
1389 (buf_addr | BIT(0) | BIT(1)));
1390 }
1391 buf_id = buf_id % 4;
372d855f 1392 intelhaddata->buff_done = buf_id;
372d855f
TI		 1393 }
1394
1395 return intr_count;
1396}
1397
bcce775c 1398/* called from irq handler */
372d855f
TI		 1399static int had_process_buffer_done(struct snd_intelhad *intelhaddata)
1400{
1401 u32 len = 1;
1402 enum intel_had_aud_buf_type buf_id;
1403 enum intel_had_aud_buf_type buff_done;
1404 struct pcm_stream_info *stream;
313d9f28 1405 struct snd_pcm_substream *substream;
372d855f 1406 u32 buf_size;
372d855f 1407 int intr_count;
bcce775c 1408 unsigned long flags;
372d855f 1409
372d855f
TI		 1410 stream = &intelhaddata->stream_info;
1411 intr_count = 1;
1412
bcce775c 1413 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
372d855f 1414 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
bcce775c 1415 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
c75b0476
TI		 1416 dev_dbg(intelhaddata->dev,
1417 "%s:Device already disconnected\n", __func__);
372d855f
TI		 1418 return 0;
1419 }
1420 buf_id = intelhaddata->curr_buf;
1421 intelhaddata->buff_done = buf_id;
1422 buff_done = intelhaddata->buff_done;
1423 buf_size = intelhaddata->buf_info[buf_id].buf_size;
372d855f 1424
372d855f
TI		 1425 /* Every debug statement has an implication
1426 * of ~5msec. Thus, avoid having >3 debug statements
1427 * for each buffer_done handling.
1428 */
1429
1430 /* Check for any intr_miss in case of active playback */
f69bd104 1431 if (stream->running) {
372d855f
TI		 1432 intr_count = had_chk_intrmiss(intelhaddata, buf_id);
1433 if (!intr_count || (intr_count > 3)) {
bcce775c
TI		 1434 spin_unlock_irqrestore(&intelhaddata->had_spinlock,
1435 flags);
c75b0476
TI		 1436 dev_err(intelhaddata->dev,
1437 "HAD SW state in non-recoverable mode\n");
372d855f
TI		 1438 return 0;
1439 }
1440 buf_id += (intr_count - 1);
1441 buf_id = buf_id % 4;
372d855f
TI		 1442 }
1443
1444 intelhaddata->buf_info[buf_id].is_valid = true;
1445 if (intelhaddata->valid_buf_cnt-1 == buf_id) {
f69bd104 1446 if (stream->running)
372d855f
TI		 1447 intelhaddata->curr_buf = HAD_BUF_TYPE_A;
1448 } else
1449 intelhaddata->curr_buf = buf_id + 1;
1450
bcce775c 1451 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
372d855f 1452
79f439ea 1453 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
c75b0476 1454 dev_dbg(intelhaddata->dev, "HDMI cable plugged-out\n");
372d855f
TI		 1455 return 0;
1456 }
1457
2e52f5e5 1458 /* Reprogram the registers with addr and length */
372d855f
TI		 1459 had_write_register(intelhaddata,
1460 AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH),
1461 buf_size);
1462 had_write_register(intelhaddata,
1463 AUD_BUF_A_ADDR + (buf_id * HAD_REG_WIDTH),
1464 intelhaddata->buf_info[buf_id].buf_addr |
1465 BIT(0) | BIT(1));
1466
1467 had_read_register(intelhaddata,
1468 AUD_BUF_A_LENGTH + (buf_id * HAD_REG_WIDTH),
1469 &len);
c75b0476 1470 dev_dbg(intelhaddata->dev, "%s:Enabled buf[%d]\n", __func__, buf_id);
372d855f
TI		 1471
1472 /* In case of actual data,
1473 * report buffer_done to above ALSA layer
1474 */
313d9f28
TI		 1475 substream = had_substream_get(intelhaddata);
1476 if (substream) {
1477 buf_size = intelhaddata->buf_info[buf_id].buf_size;
372d855f
TI		 1478 intelhaddata->stream_info.buffer_rendered +=
1479 (intr_count * buf_size);
313d9f28
TI		 1480 snd_pcm_period_elapsed(substream);
1481 had_substream_put(intelhaddata);
372d855f
TI		 1482 }
1483
1484 return 0;
1485}
1486
bcce775c 1487/* called from irq handler */
372d855f
TI		 1488static int had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
1489{
1490 enum intel_had_aud_buf_type buf_id;
1491 struct pcm_stream_info *stream;
313d9f28 1492 struct snd_pcm_substream *substream;
bcce775c 1493 unsigned long flags;
372d855f
TI		 1494 int drv_status;
1495
372d855f
TI		 1496 stream = &intelhaddata->stream_info;
1497
bcce775c 1498 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
372d855f 1499 buf_id = intelhaddata->curr_buf;
372d855f
TI		 1500 intelhaddata->buff_done = buf_id;
1501 drv_status = intelhaddata->drv_status;
f69bd104 1502 if (stream->running)
372d855f
TI		 1503 intelhaddata->curr_buf = HAD_BUF_TYPE_A;
1504
bcce775c 1505 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
372d855f 1506
f69bd104
TI		 1507 dev_dbg(intelhaddata->dev, "Enter:%s buf_id=%d, stream_running=%d\n",
1508 __func__, buf_id, stream->running);
372d855f
TI		 1509
1510 snd_intelhad_handle_underrun(intelhaddata);
1511
1512 if (drv_status == HAD_DRV_DISCONNECTED) {
c75b0476
TI		 1513 dev_dbg(intelhaddata->dev,
1514 "%s:Device already disconnected\n", __func__);
372d855f
TI		 1515 return 0;
1516 }
1517
f69bd104
TI		 1518 /* Report UNDERRUN error to above layers */
1519 substream = had_substream_get(intelhaddata);
1520 if (substream) {
1521 snd_pcm_stop_xrun(substream);
1522 had_substream_put(intelhaddata);
372d855f
TI		 1523 }
1524
1525 return 0;
1526}
1527
8f8d1d7f 1528/* process hot plug, called from wq with mutex locked */
0e9c67d7 1529static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
372d855f
TI		 1530{
1531 enum intel_had_aud_buf_type buf_id;
1532 struct snd_pcm_substream *substream;
372d855f 1533
bcce775c 1534 spin_lock_irq(&intelhaddata->had_spinlock);
372d855f 1535 if (intelhaddata->drv_status == HAD_DRV_CONNECTED) {
c75b0476 1536 dev_dbg(intelhaddata->dev, "Device already connected\n");
bcce775c 1537 spin_unlock_irq(&intelhaddata->had_spinlock);
0e9c67d7 1538 return;
372d855f 1539 }
0e9c67d7 1540
372d855f
TI		 1541 buf_id = intelhaddata->curr_buf;
1542 intelhaddata->buff_done = buf_id;
1543 intelhaddata->drv_status = HAD_DRV_CONNECTED;
c75b0476
TI		 1544 dev_dbg(intelhaddata->dev,
1545 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
372d855f 1546 __func__, __LINE__);
bcce775c 1547 spin_unlock_irq(&intelhaddata->had_spinlock);
372d855f 1548
c75b0476
TI		 1549 dev_dbg(intelhaddata->dev, "Processing HOT_PLUG, buf_id = %d\n",
1550 buf_id);
372d855f
TI		 1551
1552 /* Safety check */
313d9f28 1553 substream = had_substream_get(intelhaddata);
372d855f 1554 if (substream) {
c75b0476
TI		 1555 dev_dbg(intelhaddata->dev,
1556 "Force to stop the active stream by disconnection\n");
372d855f
TI		 1557 /* Set runtime->state to hw_params done */
1558 snd_pcm_stop(substream, SNDRV_PCM_STATE_SETUP);
313d9f28 1559 had_substream_put(intelhaddata);
372d855f
TI		 1560 }
1561
1562 had_build_channel_allocation_map(intelhaddata);
372d855f
TI		 1563}
1564
8f8d1d7f 1565/* process hot unplug, called from wq with mutex locked */
0e9c67d7 1566static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
372d855f
TI		 1567{
1568 enum intel_had_aud_buf_type buf_id;
313d9f28 1569 struct snd_pcm_substream *substream;
372d855f 1570
372d855f
TI		 1571 buf_id = intelhaddata->curr_buf;
1572
313d9f28
TI		 1573 substream = had_substream_get(intelhaddata);
1574
bcce775c 1575 spin_lock_irq(&intelhaddata->had_spinlock);
372d855f
TI		 1576
1577 if (intelhaddata->drv_status == HAD_DRV_DISCONNECTED) {
c75b0476 1578 dev_dbg(intelhaddata->dev, "Device already disconnected\n");
bcce775c 1579 spin_unlock_irq(&intelhaddata->had_spinlock);
313d9f28 1580 goto out;
372d855f 1581
372d855f
TI		 1582 }
1583
0e9c67d7
TI		 1584 /* Disable Audio */
1585 snd_intelhad_enable_audio_int(intelhaddata, false);
313d9f28 1586 snd_intelhad_enable_audio(substream, intelhaddata, false);
0e9c67d7 1587
372d855f 1588 intelhaddata->drv_status = HAD_DRV_DISCONNECTED;
c75b0476
TI		 1589 dev_dbg(intelhaddata->dev,
1590 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
372d855f 1591 __func__, __LINE__);
313d9f28 1592 spin_unlock_irq(&intelhaddata->had_spinlock);
372d855f
TI		 1593
1594 /* Report to above ALSA layer */
313d9f28
TI		 1595 if (substream)
1596 snd_pcm_stop(substream, SNDRV_PCM_STATE_SETUP);
372d855f 1597
313d9f28
TI		 1598 out:
1599 if (substream)
1600 had_substream_put(intelhaddata);
372d855f
TI		 1601 kfree(intelhaddata->chmap->chmap);
1602 intelhaddata->chmap->chmap = NULL;
372d855f
TI		 1603}
1604
1605/* PCM operations structure and the calls back for the same */
1606static struct snd_pcm_ops snd_intelhad_playback_ops = {
5dab11d8
JA		 1607 .open = snd_intelhad_open,
1608 .close = snd_intelhad_close,
1609 .ioctl = snd_pcm_lib_ioctl,
1610 .hw_params = snd_intelhad_hw_params,
1611 .hw_free = snd_intelhad_hw_free,
1612 .prepare = snd_intelhad_pcm_prepare,
1613 .trigger = snd_intelhad_pcm_trigger,
1614 .pointer = snd_intelhad_pcm_pointer,
1615 .mmap = snd_intelhad_pcm_mmap,
1616};
1617
5dab11d8
JA		 1618static int had_iec958_info(struct snd_kcontrol *kcontrol,
1619 struct snd_ctl_elem_info *uinfo)
1620{
1621 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1622 uinfo->count = 1;
1623 return 0;
1624}
1625
1626static int had_iec958_get(struct snd_kcontrol *kcontrol,
1627 struct snd_ctl_elem_value *ucontrol)
1628{
1629 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1630
8f8d1d7f 1631 mutex_lock(&intelhaddata->mutex);
5dab11d8
JA		 1632 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
1633 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
1634 ucontrol->value.iec958.status[2] =
1635 (intelhaddata->aes_bits >> 16) & 0xff;
1636 ucontrol->value.iec958.status[3] =
1637 (intelhaddata->aes_bits >> 24) & 0xff;
8f8d1d7f 1638 mutex_unlock(&intelhaddata->mutex);
5dab11d8
JA		 1639 return 0;
1640}
372d855f 1641
5dab11d8
JA		 1642static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
1643 struct snd_ctl_elem_value *ucontrol)
1644{
1645 ucontrol->value.iec958.status[0] = 0xff;
1646 ucontrol->value.iec958.status[1] = 0xff;
1647 ucontrol->value.iec958.status[2] = 0xff;
1648 ucontrol->value.iec958.status[3] = 0xff;
1649 return 0;
1650}
372d855f 1651
5dab11d8
JA		 1652static int had_iec958_put(struct snd_kcontrol *kcontrol,
1653 struct snd_ctl_elem_value *ucontrol)
1654{
1655 unsigned int val;
1656 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
8f8d1d7f 1657 int changed = 0;
5dab11d8 1658
5dab11d8
JA		 1659 val = (ucontrol->value.iec958.status[0] << 0) |
1660 (ucontrol->value.iec958.status[1] << 8) |
1661 (ucontrol->value.iec958.status[2] << 16) |
1662 (ucontrol->value.iec958.status[3] << 24);
8f8d1d7f 1663 mutex_lock(&intelhaddata->mutex);
5dab11d8
JA		 1664 if (intelhaddata->aes_bits != val) {
1665 intelhaddata->aes_bits = val;
8f8d1d7f 1666 changed = 1;
5dab11d8 1667 }
8f8d1d7f
TI		 1668 mutex_unlock(&intelhaddata->mutex);
1669 return changed;
5dab11d8
JA		 1670}
1671
4aedb946
TI		 1672static int had_ctl_eld_info(struct snd_kcontrol *kcontrol,
1673 struct snd_ctl_elem_info *uinfo)
1674{
1675 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1676 uinfo->count = HDMI_MAX_ELD_BYTES;
1677 return 0;
1678}
1679
1680static int had_ctl_eld_get(struct snd_kcontrol *kcontrol,
1681 struct snd_ctl_elem_value *ucontrol)
1682{
1683 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1684
1685 mutex_lock(&intelhaddata->mutex);
1686 memcpy(ucontrol->value.bytes.data, intelhaddata->eld,
1687 HDMI_MAX_ELD_BYTES);
1688 mutex_unlock(&intelhaddata->mutex);
1689 return 0;
1690}
5dab11d8 1691
4aedb946
TI		 1692static struct snd_kcontrol_new had_controls[] = {
1693 {
1694 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1695 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1696 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
1697 .info = had_iec958_info, /* shared */
1698 .get = had_iec958_mask_get,
1699 },
1700 {
1701 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1702 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1703 .info = had_iec958_info,
1704 .get = had_iec958_get,
1705 .put = had_iec958_put,
1706 },
1707 {
1708 .access = (SNDRV_CTL_ELEM_ACCESS_READ |
1709 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
1710 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1711 .name = "ELD",
1712 .info = had_ctl_eld_info,
1713 .get = had_ctl_eld_get,
1714 },
5dab11d8
JA		 1715};
1716
4aedb946 1717
da864809
TI		 1718static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1719{
1720 struct snd_intelhad *ctx = dev_id;
1721 u32 audio_stat, audio_reg;
1722
4151ee84 1723 audio_reg = AUD_HDMI_STATUS;
da864809
TI		 1724 mid_hdmi_audio_read(ctx, audio_reg, &audio_stat);
1725
1726 if (audio_stat & HDMI_AUDIO_UNDERRUN) {
1727 mid_hdmi_audio_write(ctx, audio_reg, HDMI_AUDIO_UNDERRUN);
1728 had_process_buffer_underrun(ctx);
1729 }
1730
1731 if (audio_stat & HDMI_AUDIO_BUFFER_DONE) {
1732 mid_hdmi_audio_write(ctx, audio_reg, HDMI_AUDIO_BUFFER_DONE);
1733 had_process_buffer_done(ctx);
1734 }
1735
1736 return IRQ_HANDLED;
1737}
1738
1739static void notify_audio_lpe(struct platform_device *pdev)
1740{
1741 struct snd_intelhad *ctx = platform_get_drvdata(pdev);
da864809 1742
99b2ab9d
TI		 1743 schedule_work(&ctx->hdmi_audio_wq);
1744}
da864809 1745
99b2ab9d
TI		 1746static void had_audio_wq(struct work_struct *work)
1747{
1748 struct snd_intelhad *ctx =
1749 container_of(work, struct snd_intelhad, hdmi_audio_wq);
1750 struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
da864809 1751
182cdf23 1752 pm_runtime_get_sync(ctx->dev);
8f8d1d7f 1753 mutex_lock(&ctx->mutex);
99b2ab9d
TI		 1754 if (!pdata->hdmi_connected) {
1755 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG\n",
1756 __func__);
4aedb946 1757 memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */
0e9c67d7 1758 had_process_hot_unplug(ctx);
da864809
TI		 1759 } else {
1760 struct intel_hdmi_lpe_audio_eld *eld = &pdata->eld;
1761
0e9c67d7
TI		 1762 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
1763 __func__, eld->port_id, pdata->tmds_clock_speed);
1764
da864809
TI		 1765 switch (eld->pipe_id) {
1766 case 0:
1767 ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1768 break;
1769 case 1:
1770 ctx->had_config_offset = AUDIO_HDMI_CONFIG_B;
1771 break;
1772 case 2:
1773 ctx->had_config_offset = AUDIO_HDMI_CONFIG_C;
1774 break;
1775 default:
99b2ab9d 1776 dev_dbg(ctx->dev, "Invalid pipe %d\n",
da864809
TI		 1777 eld->pipe_id);
1778 break;
1779 }
1780
df0435db 1781 memcpy(ctx->eld, eld->eld_data, sizeof(ctx->eld));
da864809 1782
0e9c67d7
TI		 1783 ctx->dp_output = pdata->dp_output;
1784 ctx->tmds_clock_speed = pdata->tmds_clock_speed;
1785 ctx->link_rate = pdata->link_rate;
da864809 1786
0e9c67d7 1787 had_process_hot_plug(ctx);
da864809 1788
0e9c67d7 1789 /* Process mode change if stream is active */
f69bd104 1790 hdmi_audio_mode_change(ctx);
da864809 1791 }
8f8d1d7f 1792 mutex_unlock(&ctx->mutex);
182cdf23
TI		 1793 pm_runtime_put(ctx->dev);
1794}
1795
1796/*
1797 * PM callbacks
1798 */
1799
1800static int hdmi_lpe_audio_runtime_suspend(struct device *dev)
1801{
1802 struct snd_intelhad *ctx = dev_get_drvdata(dev);
1803 struct snd_pcm_substream *substream;
1804
1805 substream = had_substream_get(ctx);
1806 if (substream) {
1807 snd_pcm_suspend(substream);
1808 had_substream_put(ctx);
1809 }
1810
1811 return 0;
1812}
1813
1814static int hdmi_lpe_audio_suspend(struct device *dev)
1815{
1816 struct snd_intelhad *ctx = dev_get_drvdata(dev);
1817 int err;
1818
1819 err = hdmi_lpe_audio_runtime_suspend(dev);
1820 if (!err)
1821 snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D3hot);
1822 return err;
1823}
1824
1825static int hdmi_lpe_audio_resume(struct device *dev)
1826{
1827 struct snd_intelhad *ctx = dev_get_drvdata(dev);
1828
1829 snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D0);
1830 return 0;
da864809
TI		 1831}
1832
1833/* release resources */
1834static void hdmi_lpe_audio_free(struct snd_card *card)
1835{
1836 struct snd_intelhad *ctx = card->private_data;
1837
99b2ab9d
TI		 1838 cancel_work_sync(&ctx->hdmi_audio_wq);
1839
da864809
TI		 1840 if (ctx->mmio_start)
1841 iounmap(ctx->mmio_start);
1842 if (ctx->irq >= 0)
1843 free_irq(ctx->irq, ctx);
1844}
1845
79dda75a 1846/*
da864809 1847 * hdmi_lpe_audio_probe - start bridge with i915
5dab11d8 1848 *
da864809 1849 * This function is called when the i915 driver creates the
2e52f5e5 1850 * hdmi-lpe-audio platform device.
5dab11d8 1851 */
da864809 1852static int hdmi_lpe_audio_probe(struct platform_device *pdev)
5dab11d8 1853{
5dab11d8 1854 struct snd_card *card;
da864809
TI		 1855 struct snd_intelhad *ctx;
1856 struct snd_pcm *pcm;
1857 struct intel_hdmi_lpe_audio_pdata *pdata;
1858 int irq;
1859 struct resource *res_mmio;
4aedb946 1860 int i, ret;
da864809 1861
da864809
TI		 1862 dev_dbg(&pdev->dev, "dma_mask: %p\n", pdev->dev.dma_mask);
1863
1864 pdata = pdev->dev.platform_data;
1865 if (!pdata) {
1866 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
1867 return -EINVAL;
1868 }
5dab11d8 1869
da864809
TI		 1870 /* get resources */
1871 irq = platform_get_irq(pdev, 0);
1872 if (irq < 0) {
1873 dev_err(&pdev->dev, "Could not get irq resource\n");
1874 return -ENODEV;
1875 }
1876
1877 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1878 if (!res_mmio) {
1879 dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
1880 return -ENXIO;
1881 }
5dab11d8 1882
5647aec2 1883 /* create a card instance with ALSA framework */
da864809
TI		 1884 ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
1885 THIS_MODULE, sizeof(*ctx), &card);
1886 if (ret)
1887 return ret;
1888
1889 ctx = card->private_data;
1890 spin_lock_init(&ctx->had_spinlock);
8f8d1d7f 1891 mutex_init(&ctx->mutex);
da864809
TI		 1892 ctx->drv_status = HAD_DRV_DISCONNECTED;
1893 ctx->dev = &pdev->dev;
1894 ctx->card = card;
da864809
TI		 1895 ctx->aes_bits = SNDRV_PCM_DEFAULT_CON_SPDIF;
1896 strcpy(card->driver, INTEL_HAD);
1897 strcpy(card->shortname, INTEL_HAD);
1898
1899 ctx->irq = -1;
1900 ctx->tmds_clock_speed = DIS_SAMPLE_RATE_148_5;
99b2ab9d 1901 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
da864809
TI		 1902
1903 card->private_free = hdmi_lpe_audio_free;
1904
1905 /* assume pipe A as default */
1906 ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1907
1908 platform_set_drvdata(pdev, ctx);
1909
1910 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
1911 __func__, (unsigned int)res_mmio->start,
1912 (unsigned int)res_mmio->end);
1913
1914 ctx->mmio_start = ioremap_nocache(res_mmio->start,
1915 (size_t)(resource_size(res_mmio)));
1916 if (!ctx->mmio_start) {
1917 dev_err(&pdev->dev, "Could not get ioremap\n");
1918 ret = -EACCES;
1919 goto err;
1920 }
5dab11d8 1921
da864809
TI		 1922 /* setup interrupt handler */
1923 ret = request_irq(irq, display_pipe_interrupt_handler, 0,
1924 pdev->name, ctx);
1925 if (ret < 0) {
1926 dev_err(&pdev->dev, "request_irq failed\n");
1927 goto err;
1928 }
5dab11d8 1929
da864809
TI		 1930 ctx->irq = irq;
1931
1932 ret = snd_pcm_new(card, INTEL_HAD, PCM_INDEX, MAX_PB_STREAMS,
1933 MAX_CAP_STREAMS, &pcm);
1934 if (ret)
5dab11d8
JA		 1935 goto err;
1936
1937 /* setup private data which can be retrieved when required */
da864809 1938 pcm->private_data = ctx;
5dab11d8
JA		 1939 pcm->info_flags = 0;
1940 strncpy(pcm->name, card->shortname, strlen(card->shortname));
da864809 1941 /* setup the ops for playabck */
5dab11d8
JA		 1942 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1943 &snd_intelhad_playback_ops);
1944 /* allocate dma pages for ALSA stream operations
1945 * memory allocated is based on size, not max value
1946 * thus using same argument for max & size
1947 */
da864809 1948 snd_pcm_lib_preallocate_pages_for_all(pcm,
5dab11d8
JA		 1949 SNDRV_DMA_TYPE_DEV, NULL,
1950 HAD_MAX_BUFFER, HAD_MAX_BUFFER);
5dab11d8 1951
4aedb946
TI		 1952 /* create controls */
1953 for (i = 0; i < ARRAY_SIZE(had_controls); i++) {
1954 ret = snd_ctl_add(card, snd_ctl_new1(&had_controls[i], ctx));
1955 if (ret < 0)
1956 goto err;
1957 }
5dab11d8
JA		 1958
1959 init_channel_allocations();
1960
1961 /* Register channel map controls */
da864809
TI		 1962 ret = had_register_chmap_ctls(ctx, pcm);
1963 if (ret < 0)
5dab11d8
JA		 1964 goto err;
1965
da864809
TI		 1966 ret = snd_card_register(card);
1967 if (ret)
36ec0d99
TI		 1968 goto err;
1969
bcce775c 1970 spin_lock_irq(&pdata->lpe_audio_slock);
da864809 1971 pdata->notify_audio_lpe = notify_audio_lpe;
99b2ab9d 1972 pdata->notify_pending = false;
bcce775c 1973 spin_unlock_irq(&pdata->lpe_audio_slock);
da864809
TI		 1974
1975 pm_runtime_set_active(&pdev->dev);
1976 pm_runtime_enable(&pdev->dev);
1977
99b2ab9d 1978 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
da864809 1979 schedule_work(&ctx->hdmi_audio_wq);
5dab11d8 1980
79dda75a 1981 return 0;
5647aec2 1982
5dab11d8
JA		 1983err:
1984 snd_card_free(card);
da864809 1985 return ret;
5dab11d8
JA		 1986}
1987
79dda75a 1988/*
da864809 1989 * hdmi_lpe_audio_remove - stop bridge with i915
5dab11d8 1990 *
2e52f5e5 1991 * This function is called when the platform device is destroyed.
5dab11d8 1992 */
da864809 1993static int hdmi_lpe_audio_remove(struct platform_device *pdev)
5dab11d8 1994{
da864809 1995 struct snd_intelhad *ctx = platform_get_drvdata(pdev);
5dab11d8 1996
da864809
TI		 1997 if (ctx->drv_status != HAD_DRV_DISCONNECTED)
1998 snd_intelhad_enable_audio_int(ctx, false);
1999 snd_card_free(ctx->card);
5dab11d8
JA		 2000 return 0;
2001}
2002
182cdf23
TI		 2003static const struct dev_pm_ops hdmi_lpe_audio_pm = {
2004 SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume)
2005 SET_RUNTIME_PM_OPS(hdmi_lpe_audio_runtime_suspend, NULL, NULL)
2006};
2007
da864809
TI		 2008static struct platform_driver hdmi_lpe_audio_driver = {
2009 .driver = {
2010 .name = "hdmi-lpe-audio",
182cdf23 2011 .pm = &hdmi_lpe_audio_pm,
da864809
TI		 2012 },
2013 .probe = hdmi_lpe_audio_probe,
2014 .remove = hdmi_lpe_audio_remove,
da864809
TI		 2015};
2016
2017module_platform_driver(hdmi_lpe_audio_driver);
2018MODULE_ALIAS("platform:hdmi_lpe_audio");
2019
5dab11d8
JA		 2020MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
2021MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
2022MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
2023MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
2024MODULE_DESCRIPTION("Intel HDMI Audio driver");
2025MODULE_LICENSE("GPL v2");
2026MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");
Linux 6.x block layer and io_uring tree(s)