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ALSA: x86: Fix memory leak in had_build_channel_allocation_map()
[linux-block.git] / sound / x86 / intel_hdmi_audio.c
CommitLineData
5dab11d8
JA		 1/*
2 * intel_hdmi_audio.c - Intel HDMI audio driver
3 *
4 * Copyright (C) 2016 Intel Corp
5 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
6 * Ramesh Babu K V <ramesh.babu@intel.com>
7 * Vaibhav Agarwal <vaibhav.agarwal@intel.com>
8 * Jerome Anand <jerome.anand@intel.com>
9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
21 * ALSA driver for Intel HDMI audio
22 */
23
03c34377 24#include <linux/types.h>
5dab11d8
JA		 25#include <linux/platform_device.h>
26#include <linux/io.h>
27#include <linux/slab.h>
28#include <linux/module.h>
da864809 29#include <linux/interrupt.h>
03c34377 30#include <linux/pm_runtime.h>
412bbe7d 31#include <linux/dma-mapping.h>
e2acecf2 32#include <linux/delay.h>
5dab11d8 33#include <asm/cacheflush.h>
5dab11d8 34#include <sound/core.h>
03c34377
TI		 35#include <sound/asoundef.h>
36#include <sound/pcm.h>
5dab11d8
JA		 37#include <sound/pcm_params.h>
38#include <sound/initval.h>
39#include <sound/control.h>
b9bacf27 40#include <sound/jack.h>
03c34377 41#include <drm/drm_edid.h>
da864809 42#include <drm/intel_lpe_audio.h>
5dab11d8
JA		 43#include "intel_hdmi_audio.h"
44
5dab11d8
JA		 45/*standard module options for ALSA. This module supports only one card*/
46static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
47static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
5dab11d8
JA		 48
49module_param_named(index, hdmi_card_index, int, 0444);
50MODULE_PARM_DESC(index,
51 "Index value for INTEL Intel HDMI Audio controller.");
52module_param_named(id, hdmi_card_id, charp, 0444);
53MODULE_PARM_DESC(id,
54 "ID string for INTEL Intel HDMI Audio controller.");
55
56/*
57 * ELD SA bits in the CEA Speaker Allocation data block
58 */
4a5ddb2c 59static const int eld_speaker_allocation_bits[] = {
5dab11d8
JA		 60 [0] = FL | FR,
61 [1] = LFE,
62 [2] = FC,
63 [3] = RL | RR,
64 [4] = RC,
65 [5] = FLC | FRC,
66 [6] = RLC | RRC,
67 /* the following are not defined in ELD yet */
68 [7] = 0,
69};
70
71/*
72 * This is an ordered list!
73 *
74 * The preceding ones have better chances to be selected by
75 * hdmi_channel_allocation().
76 */
77static struct cea_channel_speaker_allocation channel_allocations[] = {
78/* channel: 7 6 5 4 3 2 1 0 */
79{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
80 /* 2.1 */
81{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
82 /* Dolby Surround */
83{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
84 /* surround40 */
85{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
86 /* surround41 */
87{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
88 /* surround50 */
89{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
90 /* surround51 */
91{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
92 /* 6.1 */
93{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
94 /* surround71 */
95{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
96
97{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
98{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
99{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
100{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
101{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
102{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
103{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
104{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
105{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
106{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
107{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
108{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
109{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
110{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
111{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
112{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
113{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
114{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
115{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
116{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
117{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
118{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
119{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
120};
121
4a5ddb2c 122static const struct channel_map_table map_tables[] = {
5dab11d8
JA		 123 { SNDRV_CHMAP_FL, 0x00, FL },
124 { SNDRV_CHMAP_FR, 0x01, FR },
125 { SNDRV_CHMAP_RL, 0x04, RL },
126 { SNDRV_CHMAP_RR, 0x05, RR },
127 { SNDRV_CHMAP_LFE, 0x02, LFE },
128 { SNDRV_CHMAP_FC, 0x03, FC },
129 { SNDRV_CHMAP_RLC, 0x06, RLC },
130 { SNDRV_CHMAP_RRC, 0x07, RRC },
131 {} /* terminator */
132};
133
134/* hardware capability structure */
b556290f 135static const struct snd_pcm_hardware had_pcm_hardware = {
5dab11d8 136 .info = (SNDRV_PCM_INFO_INTERLEAVED |
a9ebdd0e 137 SNDRV_PCM_INFO_MMAP |
e8de9859
TI		 138 SNDRV_PCM_INFO_MMAP_VALID |
139 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
3fe2cf7e
TI		 140 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
141 SNDRV_PCM_FMTBIT_S24_LE |
85bd8748 142 SNDRV_PCM_FMTBIT_S32_LE),
5dab11d8
JA		 143 .rates = SNDRV_PCM_RATE_32000 |
144 SNDRV_PCM_RATE_44100 |
145 SNDRV_PCM_RATE_48000 |
146 SNDRV_PCM_RATE_88200 |
147 SNDRV_PCM_RATE_96000 |
148 SNDRV_PCM_RATE_176400 |
149 SNDRV_PCM_RATE_192000,
150 .rate_min = HAD_MIN_RATE,
151 .rate_max = HAD_MAX_RATE,
152 .channels_min = HAD_MIN_CHANNEL,
153 .channels_max = HAD_MAX_CHANNEL,
154 .buffer_bytes_max = HAD_MAX_BUFFER,
155 .period_bytes_min = HAD_MIN_PERIOD_BYTES,
156 .period_bytes_max = HAD_MAX_PERIOD_BYTES,
157 .periods_min = HAD_MIN_PERIODS,
158 .periods_max = HAD_MAX_PERIODS,
159 .fifo_size = HAD_FIFO_SIZE,
160};
161
313d9f28
TI		 162/* Get the active PCM substream;
163 * Call had_substream_put() for unreferecing.
164 * Don't call this inside had_spinlock, as it takes by itself
165 */
166static struct snd_pcm_substream *
167had_substream_get(struct snd_intelhad *intelhaddata)
168{
169 struct snd_pcm_substream *substream;
170 unsigned long flags;
171
172 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
173 substream = intelhaddata->stream_info.substream;
174 if (substream)
175 intelhaddata->stream_info.substream_refcount++;
176 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
177 return substream;
178}
179
180/* Unref the active PCM substream;
181 * Don't call this inside had_spinlock, as it takes by itself
182 */
183static void had_substream_put(struct snd_intelhad *intelhaddata)
184{
185 unsigned long flags;
186
187 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
188 intelhaddata->stream_info.substream_refcount--;
189 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
190}
191
5dab11d8 192/* Register access functions */
83af57dd 193static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val)
5dab11d8 194{
da864809 195 *val = ioread32(ctx->mmio_start + ctx->had_config_offset + reg);
5dab11d8
JA		 196}
197
83af57dd 198static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val)
5dab11d8 199{
da864809 200 iowrite32(val, ctx->mmio_start + ctx->had_config_offset + reg);
5dab11d8
JA		 201}
202
da864809 203/*
313d9f28
TI		 204 * enable / disable audio configuration
205 *
83af57dd 206 * The normal read/modify should not directly be used on VLV2 for
da864809 207 * updating AUD_CONFIG register.
5dab11d8
JA		 208 * This is because:
209 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
210 * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always
211 * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
212 * register. This field should be 1xy binary for configuration with 6 or
213 * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
214 * causes the "channels" field to be updated as 0xy binary resulting in
215 * bad audio. The fix is to always write the AUD_CONFIG[6:4] with
216 * appropriate value when doing read-modify of AUD_CONFIG register.
5dab11d8 217 */
40ce4b5d 218static void had_enable_audio(struct snd_intelhad *intelhaddata,
b556290f 219 bool enable)
5dab11d8 220{
40ce4b5d
TI		 221 /* update the cached value */
222 intelhaddata->aud_config.regx.aud_en = enable;
223 had_write_register(intelhaddata, AUD_CONFIG,
224 intelhaddata->aud_config.regval);
5dab11d8
JA		 225}
226
075a1d46
TI		 227/* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */
228static void had_ack_irqs(struct snd_intelhad *ctx)
da864809
TI		 229{
230 u32 status_reg;
231
075a1d46
TI		 232 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
233 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
234 had_write_register(ctx, AUD_HDMI_STATUS, status_reg);
235 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
da864809
TI		 236}
237
f4566aa1
TI		 238/* Reset buffer pointers */
239static void had_reset_audio(struct snd_intelhad *intelhaddata)
5dab11d8 240{
77531bee
TI		 241 had_write_register(intelhaddata, AUD_HDMI_STATUS,
242 AUD_HDMI_STATUSG_MASK_FUNCRST);
f4566aa1 243 had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
5dab11d8
JA		 244}
245
2e52f5e5 246/*
5dab11d8
JA		 247 * initialize audio channel status registers
248 * This function is called in the prepare callback
249 */
250static int had_prog_status_reg(struct snd_pcm_substream *substream,
251 struct snd_intelhad *intelhaddata)
252{
7ceba75f
TI		 253 union aud_cfg cfg_val = {.regval = 0};
254 union aud_ch_status_0 ch_stat0 = {.regval = 0};
255 union aud_ch_status_1 ch_stat1 = {.regval = 0};
5dab11d8 256
7ceba75f 257 ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
2e52f5e5 258 IEC958_AES0_NONAUDIO) >> 1;
7ceba75f 259 ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
2e52f5e5 260 IEC958_AES3_CON_CLOCK) >> 4;
7ceba75f 261 cfg_val.regx.val_bit = ch_stat0.regx.lpcm_id;
5dab11d8
JA		 262
263 switch (substream->runtime->rate) {
264 case AUD_SAMPLE_RATE_32:
7ceba75f 265 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
5dab11d8
JA		 266 break;
267
268 case AUD_SAMPLE_RATE_44_1:
7ceba75f 269 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
5dab11d8
JA		 270 break;
271 case AUD_SAMPLE_RATE_48:
7ceba75f 272 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
5dab11d8
JA		 273 break;
274 case AUD_SAMPLE_RATE_88_2:
7ceba75f 275 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
5dab11d8
JA		 276 break;
277 case AUD_SAMPLE_RATE_96:
7ceba75f 278 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
5dab11d8
JA		 279 break;
280 case AUD_SAMPLE_RATE_176_4:
7ceba75f 281 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
5dab11d8
JA		 282 break;
283 case AUD_SAMPLE_RATE_192:
7ceba75f 284 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
5dab11d8
JA		 285 break;
286
287 default:
288 /* control should never come here */
289 return -EINVAL;
5dab11d8 290 }
2e52f5e5 291
79dda75a 292 had_write_register(intelhaddata,
7ceba75f 293 AUD_CH_STATUS_0, ch_stat0.regval);
5dab11d8 294
85bd8748 295 switch (substream->runtime->format) {
85bd8748 296 case SNDRV_PCM_FORMAT_S16_LE:
7ceba75f
TI		 297 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
298 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
85bd8748 299 break;
85bd8748
TI		 300 case SNDRV_PCM_FORMAT_S24_LE:
301 case SNDRV_PCM_FORMAT_S32_LE:
7ceba75f
TI		 302 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
303 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
85bd8748
TI		 304 break;
305 default:
306 return -EINVAL;
5dab11d8 307 }
2e52f5e5 308
79dda75a 309 had_write_register(intelhaddata,
7ceba75f 310 AUD_CH_STATUS_1, ch_stat1.regval);
5dab11d8
JA		 311 return 0;
312}
313
76296ef0 314/*
5dab11d8
JA		 315 * function to initialize audio
316 * registers and buffer confgiuration registers
317 * This function is called in the prepare callback
318 */
b556290f
TI		 319static int had_init_audio_ctrl(struct snd_pcm_substream *substream,
320 struct snd_intelhad *intelhaddata)
5dab11d8 321{
7ceba75f
TI		 322 union aud_cfg cfg_val = {.regval = 0};
323 union aud_buf_config buf_cfg = {.regval = 0};
5dab11d8
JA		 324 u8 channels;
325
326 had_prog_status_reg(substream, intelhaddata);
327
7ceba75f
TI		 328 buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
329 buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
330 buf_cfg.regx.aud_delay = 0;
331 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval);
5dab11d8
JA		 332
333 channels = substream->runtime->channels;
7ceba75f 334 cfg_val.regx.num_ch = channels - 2;
5dab11d8 335 if (channels <= 2)
7ceba75f 336 cfg_val.regx.layout = LAYOUT0;
5dab11d8 337 else
7ceba75f 338 cfg_val.regx.layout = LAYOUT1;
5dab11d8 339
3fe2cf7e
TI		 340 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
341 cfg_val.regx.packet_mode = 1;
342
85bd8748
TI		 343 if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE)
344 cfg_val.regx.left_align = 1;
345
7ceba75f 346 cfg_val.regx.val_bit = 1;
83af57dd
TI		 347
348 /* fix up the DP bits */
349 if (intelhaddata->dp_output) {
350 cfg_val.regx.dp_modei = 1;
351 cfg_val.regx.set = 1;
352 }
353
7ceba75f 354 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
40ce4b5d 355 intelhaddata->aud_config = cfg_val;
5dab11d8
JA		 356 return 0;
357}
358
5dab11d8
JA		 359/*
360 * Compute derived values in channel_allocations[].
361 */
362static void init_channel_allocations(void)
363{
364 int i, j;
365 struct cea_channel_speaker_allocation *p;
366
5dab11d8
JA		 367 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
368 p = channel_allocations + i;
369 p->channels = 0;
370 p->spk_mask = 0;
371 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
372 if (p->speakers[j]) {
373 p->channels++;
374 p->spk_mask |= p->speakers[j];
375 }
376 }
377}
378
379/*
380 * The transformation takes two steps:
381 *
382 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
383 * spk_mask => (channel_allocations[]) => ai->CA
384 *
385 * TODO: it could select the wrong CA from multiple candidates.
386 */
b556290f
TI		 387static int had_channel_allocation(struct snd_intelhad *intelhaddata,
388 int channels)
5dab11d8
JA		 389{
390 int i;
391 int ca = 0;
392 int spk_mask = 0;
393
394 /*
395 * CA defaults to 0 for basic stereo audio
396 */
397 if (channels <= 2)
398 return 0;
399
400 /*
401 * expand ELD's speaker allocation mask
402 *
403 * ELD tells the speaker mask in a compact(paired) form,
404 * expand ELD's notions to match the ones used by Audio InfoFrame.
405 */
406
407 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
df0435db 408 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
5dab11d8
JA		 409 spk_mask |= eld_speaker_allocation_bits[i];
410 }
411
412 /* search for the first working match in the CA table */
413 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
414 if (channels == channel_allocations[i].channels &&
415 (spk_mask & channel_allocations[i].spk_mask) ==
416 channel_allocations[i].spk_mask) {
417 ca = channel_allocations[i].ca_index;
418 break;
419 }
420 }
421
c75b0476 422 dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
5dab11d8
JA		 423
424 return ca;
425}
426
427/* from speaker bit mask to ALSA API channel position */
428static int spk_to_chmap(int spk)
429{
4a5ddb2c 430 const struct channel_map_table *t = map_tables;
5dab11d8
JA		 431
432 for (; t->map; t++) {
433 if (t->spk_mask == spk)
434 return t->map;
435 }
436 return 0;
437}
438
372d855f 439static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
5dab11d8 440{
2e52f5e5 441 int i, c;
5dab11d8
JA		 442 int spk_mask = 0;
443 struct snd_pcm_chmap_elem *chmap;
444 u8 eld_high, eld_high_mask = 0xF0;
445 u8 high_msb;
446
18353192
TI		 447 kfree(intelhaddata->chmap->chmap);
448 intelhaddata->chmap->chmap = NULL;
449
5dab11d8 450 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
18353192 451 if (!chmap)
5dab11d8 452 return;
5dab11d8 453
df0435db
TI		 454 dev_dbg(intelhaddata->dev, "eld speaker = %x\n",
455 intelhaddata->eld[DRM_ELD_SPEAKER]);
5dab11d8
JA		 456
457 /* WA: Fix the max channel supported to 8 */
458
459 /*
460 * Sink may support more than 8 channels, if eld_high has more than
461 * one bit set. SOC supports max 8 channels.
462 * Refer eld_speaker_allocation_bits, for sink speaker allocation
463 */
464
465 /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
df0435db 466 eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask;
5dab11d8
JA		 467 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
468 /* eld_high & (eld_high-1): if more than 1 bit set */
469 /* 0x1F: 7 channels */
470 for (i = 1; i < 4; i++) {
471 high_msb = eld_high & (0x80 >> i);
472 if (high_msb) {
df0435db 473 intelhaddata->eld[DRM_ELD_SPEAKER] &=
5dab11d8
JA		 474 high_msb | 0xF;
475 break;
476 }
477 }
478 }
479
480 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
df0435db 481 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
5dab11d8
JA		 482 spk_mask |= eld_speaker_allocation_bits[i];
483 }
484
485 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
486 if (spk_mask == channel_allocations[i].spk_mask) {
487 for (c = 0; c < channel_allocations[i].channels; c++) {
488 chmap->map[c] = spk_to_chmap(
489 channel_allocations[i].speakers[
2e52f5e5 490 (MAX_SPEAKERS - 1) - c]);
5dab11d8
JA		 491 }
492 chmap->channels = channel_allocations[i].channels;
493 intelhaddata->chmap->chmap = chmap;
494 break;
495 }
496 }
18353192 497 if (i >= ARRAY_SIZE(channel_allocations))
5dab11d8 498 kfree(chmap);
5dab11d8
JA		 499}
500
501/*
502 * ALSA API channel-map control callbacks
503 */
504static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
505 struct snd_ctl_elem_info *uinfo)
506{
507 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
508 struct snd_intelhad *intelhaddata = info->private_data;
509
91b0cb0c 510 if (!intelhaddata->connected)
5dab11d8
JA		 511 return -ENODEV;
512 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
513 uinfo->count = HAD_MAX_CHANNEL;
514 uinfo->value.integer.min = 0;
515 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
516 return 0;
517}
518
519static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
520 struct snd_ctl_elem_value *ucontrol)
521{
522 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
523 struct snd_intelhad *intelhaddata = info->private_data;
2e52f5e5 524 int i;
5dab11d8
JA		 525 const struct snd_pcm_chmap_elem *chmap;
526
91b0cb0c 527 if (!intelhaddata->connected)
5dab11d8 528 return -ENODEV;
8f8d1d7f
TI		 529
530 mutex_lock(&intelhaddata->mutex);
531 if (!intelhaddata->chmap->chmap) {
532 mutex_unlock(&intelhaddata->mutex);
5dab11d8 533 return -ENODATA;
8f8d1d7f
TI		 534 }
535
5dab11d8 536 chmap = intelhaddata->chmap->chmap;
c75b0476 537 for (i = 0; i < chmap->channels; i++)
5dab11d8 538 ucontrol->value.integer.value[i] = chmap->map[i];
8f8d1d7f 539 mutex_unlock(&intelhaddata->mutex);
5dab11d8
JA		 540
541 return 0;
542}
543
544static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
545 struct snd_pcm *pcm)
546{
2e52f5e5 547 int err;
5dab11d8
JA		 548
549 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
550 NULL, 0, (unsigned long)intelhaddata,
551 &intelhaddata->chmap);
552 if (err < 0)
553 return err;
554
555 intelhaddata->chmap->private_data = intelhaddata;
e9d65abf
TI		 556 intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
557 intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
5dab11d8
JA		 558 intelhaddata->chmap->chmap = NULL;
559 return 0;
560}
561
76296ef0 562/*
44684f61 563 * Initialize Data Island Packets registers
5dab11d8
JA		 564 * This function is called in the prepare callback
565 */
b556290f
TI		 566static void had_prog_dip(struct snd_pcm_substream *substream,
567 struct snd_intelhad *intelhaddata)
5dab11d8
JA		 568{
569 int i;
7ceba75f
TI		 570 union aud_ctrl_st ctrl_state = {.regval = 0};
571 union aud_info_frame2 frame2 = {.regval = 0};
572 union aud_info_frame3 frame3 = {.regval = 0};
5dab11d8 573 u8 checksum = 0;
964ca808 574 u32 info_frame;
5dab11d8 575 int channels;
36ed3466 576 int ca;
5dab11d8
JA		 577
578 channels = substream->runtime->channels;
579
7ceba75f 580 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
5dab11d8 581
b556290f 582 ca = had_channel_allocation(intelhaddata, channels);
964ca808
PLB		 583 if (intelhaddata->dp_output) {
584 info_frame = DP_INFO_FRAME_WORD1;
36ed3466 585 frame2.regval = (substream->runtime->channels - 1) | (ca << 24);
964ca808
PLB		 586 } else {
587 info_frame = HDMI_INFO_FRAME_WORD1;
7ceba75f 588 frame2.regx.chnl_cnt = substream->runtime->channels - 1;
36ed3466 589 frame3.regx.chnl_alloc = ca;
5dab11d8 590
2e52f5e5 591 /* Calculte the byte wide checksum for all valid DIP words */
964ca808 592 for (i = 0; i < BYTES_PER_WORD; i++)
7ceba75f 593 checksum += (info_frame >> (i * 8)) & 0xff;
964ca808 594 for (i = 0; i < BYTES_PER_WORD; i++)
7ceba75f 595 checksum += (frame2.regval >> (i * 8)) & 0xff;
964ca808 596 for (i = 0; i < BYTES_PER_WORD; i++)
7ceba75f 597 checksum += (frame3.regval >> (i * 8)) & 0xff;
5dab11d8 598
7ceba75f 599 frame2.regx.chksum = -(checksum);
964ca808 600 }
5dab11d8 601
4151ee84 602 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
7ceba75f
TI		 603 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval);
604 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval);
5dab11d8
JA		 605
606 /* program remaining DIP words with zero */
607 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
4151ee84 608 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
5dab11d8 609
7ceba75f
TI		 610 ctrl_state.regx.dip_freq = 1;
611 ctrl_state.regx.dip_en_sta = 1;
612 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
5dab11d8
JA		 613}
614
964ca808
PLB		 615static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
616{
617 u32 maud_val;
618
2e52f5e5 619 /* Select maud according to DP 1.2 spec */
964ca808
PLB		 620 if (link_rate == DP_2_7_GHZ) {
621 switch (aud_samp_freq) {
622 case AUD_SAMPLE_RATE_32:
623 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
624 break;
625
626 case AUD_SAMPLE_RATE_44_1:
627 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
628 break;
629
630 case AUD_SAMPLE_RATE_48:
631 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
632 break;
633
634 case AUD_SAMPLE_RATE_88_2:
635 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
636 break;
637
638 case AUD_SAMPLE_RATE_96:
639 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
640 break;
641
642 case AUD_SAMPLE_RATE_176_4:
643 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
644 break;
645
646 case HAD_MAX_RATE:
647 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
648 break;
649
650 default:
651 maud_val = -EINVAL;
652 break;
653 }
654 } else if (link_rate == DP_1_62_GHZ) {
655 switch (aud_samp_freq) {
656 case AUD_SAMPLE_RATE_32:
657 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
658 break;
659
660 case AUD_SAMPLE_RATE_44_1:
661 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
662 break;
663
664 case AUD_SAMPLE_RATE_48:
665 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
666 break;
667
668 case AUD_SAMPLE_RATE_88_2:
669 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
670 break;
671
672 case AUD_SAMPLE_RATE_96:
673 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
674 break;
675
676 case AUD_SAMPLE_RATE_176_4:
677 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
678 break;
679
680 case HAD_MAX_RATE:
681 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
682 break;
683
684 default:
685 maud_val = -EINVAL;
686 break;
687 }
688 } else
689 maud_val = -EINVAL;
690
691 return maud_val;
692}
693
76296ef0 694/*
44684f61 695 * Program HDMI audio CTS value
5dab11d8
JA		 696 *
697 * @aud_samp_freq: sampling frequency of audio data
698 * @tmds: sampling frequency of the display data
b556290f 699 * @link_rate: DP link rate
5dab11d8 700 * @n_param: N value, depends on aud_samp_freq
b556290f 701 * @intelhaddata: substream private data
5dab11d8
JA		 702 *
703 * Program CTS register based on the audio and display sampling frequency
704 */
b556290f
TI		 705static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate,
706 u32 n_param, struct snd_intelhad *intelhaddata)
5dab11d8
JA		 707{
708 u32 cts_val;
709 u64 dividend, divisor;
710
964ca808
PLB		 711 if (intelhaddata->dp_output) {
712 /* Substitute cts_val with Maud according to DP 1.2 spec*/
713 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
714 } else {
715 /* Calculate CTS according to HDMI 1.3a spec*/
716 dividend = (u64)tmds * n_param*1000;
717 divisor = 128 * aud_samp_freq;
718 cts_val = div64_u64(dividend, divisor);
719 }
c75b0476 720 dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
964ca808 721 tmds, n_param, cts_val);
79dda75a 722 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
5dab11d8
JA		 723}
724
725static int had_calculate_n_value(u32 aud_samp_freq)
726{
2e52f5e5 727 int n_val;
5dab11d8
JA		 728
729 /* Select N according to HDMI 1.3a spec*/
730 switch (aud_samp_freq) {
731 case AUD_SAMPLE_RATE_32:
732 n_val = 4096;
2e52f5e5 733 break;
5dab11d8
JA		 734
735 case AUD_SAMPLE_RATE_44_1:
736 n_val = 6272;
2e52f5e5 737 break;
5dab11d8
JA		 738
739 case AUD_SAMPLE_RATE_48:
740 n_val = 6144;
2e52f5e5 741 break;
5dab11d8
JA		 742
743 case AUD_SAMPLE_RATE_88_2:
744 n_val = 12544;
2e52f5e5 745 break;
5dab11d8
JA		 746
747 case AUD_SAMPLE_RATE_96:
748 n_val = 12288;
2e52f5e5 749 break;
5dab11d8
JA		 750
751 case AUD_SAMPLE_RATE_176_4:
752 n_val = 25088;
2e52f5e5 753 break;
5dab11d8
JA		 754
755 case HAD_MAX_RATE:
756 n_val = 24576;
2e52f5e5 757 break;
5dab11d8
JA		 758
759 default:
760 n_val = -EINVAL;
2e52f5e5 761 break;
5dab11d8
JA		 762 }
763 return n_val;
764}
765
76296ef0 766/*
44684f61 767 * Program HDMI audio N value
5dab11d8
JA		 768 *
769 * @aud_samp_freq: sampling frequency of audio data
770 * @n_param: N value, depends on aud_samp_freq
b556290f 771 * @intelhaddata: substream private data
5dab11d8
JA		 772 *
773 * This function is called in the prepare callback.
774 * It programs based on the audio and display sampling frequency
775 */
b556290f
TI		 776static int had_prog_n(u32 aud_samp_freq, u32 *n_param,
777 struct snd_intelhad *intelhaddata)
5dab11d8 778{
2e52f5e5 779 int n_val;
5dab11d8 780
964ca808
PLB		 781 if (intelhaddata->dp_output) {
782 /*
783 * According to DP specs, Maud and Naud values hold
784 * a relationship, which is stated as:
785 * Maud/Naud = 512 * fs / f_LS_Clk
786 * where, fs is the sampling frequency of the audio stream
787 * and Naud is 32768 for Async clock.
788 */
789
790 n_val = DP_NAUD_VAL;
791 } else
792 n_val = had_calculate_n_value(aud_samp_freq);
5dab11d8
JA		 793
794 if (n_val < 0)
795 return n_val;
796
79dda75a 797 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
5dab11d8
JA		 798 *n_param = n_val;
799 return 0;
800}
801
e1b239f3
TI		 802/*
803 * PCM ring buffer handling
804 *
805 * The hardware provides a ring buffer with the fixed 4 buffer descriptors
806 * (BDs). The driver maps these 4 BDs onto the PCM ring buffer. The mapping
807 * moves at each period elapsed. The below illustrates how it works:
808 *
809 * At time=0
810 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
811 * BD | 0 | 1 | 2 | 3 |
812 *
813 * At time=1 (period elapsed)
814 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
815 * BD | 1 | 2 | 3 | 0 |
816 *
817 * At time=2 (second period elapsed)
818 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
819 * BD | 2 | 3 | 0 | 1 |
820 *
821 * The bd_head field points to the index of the BD to be read. It's also the
822 * position to be filled at next. The pcm_head and the pcm_filled fields
823 * point to the indices of the current position and of the next position to
824 * be filled, respectively. For PCM buffer there are both _head and _filled
825 * because they may be difference when nperiods > 4. For example, in the
826 * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5:
827 *
828 * pcm_head (=1) --v v-- pcm_filled (=5)
829 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
830 * BD | 1 | 2 | 3 | 0 |
831 * bd_head (=1) --^ ^-- next to fill (= bd_head)
832 *
833 * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that
834 * the hardware skips those BDs in the loop.
8d48c016
TI		 835 *
836 * An exceptional setup is the case with nperiods=1. Since we have to update
837 * BDs after finishing one BD processing, we'd need at least two BDs, where
838 * both BDs point to the same content, the same address, the same size of the
839 * whole PCM buffer.
e1b239f3
TI		 840 */
841
842#define AUD_BUF_ADDR(x) (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH)
843#define AUD_BUF_LEN(x) (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH)
844
845/* Set up a buffer descriptor at the "filled" position */
846static void had_prog_bd(struct snd_pcm_substream *substream,
847 struct snd_intelhad *intelhaddata)
848{
849 int idx = intelhaddata->bd_head;
850 int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes;
851 u32 addr = substream->runtime->dma_addr + ofs;
852
e8de9859
TI		 853 addr |= AUD_BUF_VALID;
854 if (!substream->runtime->no_period_wakeup)
855 addr |= AUD_BUF_INTR_EN;
e1b239f3
TI		 856 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr);
857 had_write_register(intelhaddata, AUD_BUF_LEN(idx),
858 intelhaddata->period_bytes);
859
860 /* advance the indices to the next */
861 intelhaddata->bd_head++;
862 intelhaddata->bd_head %= intelhaddata->num_bds;
863 intelhaddata->pcmbuf_filled++;
864 intelhaddata->pcmbuf_filled %= substream->runtime->periods;
865}
866
867/* invalidate a buffer descriptor with the given index */
868static void had_invalidate_bd(struct snd_intelhad *intelhaddata,
869 int idx)
870{
871 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0);
872 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0);
873}
874
875/* Initial programming of ring buffer */
876static void had_init_ringbuf(struct snd_pcm_substream *substream,
877 struct snd_intelhad *intelhaddata)
878{
879 struct snd_pcm_runtime *runtime = substream->runtime;
880 int i, num_periods;
881
882 num_periods = runtime->periods;
883 intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS);
8d48c016
TI		 884 /* set the minimum 2 BDs for num_periods=1 */
885 intelhaddata->num_bds = max(intelhaddata->num_bds, 2U);
e1b239f3
TI		 886 intelhaddata->period_bytes =
887 frames_to_bytes(runtime, runtime->period_size);
888 WARN_ON(intelhaddata->period_bytes & 0x3f);
889
890 intelhaddata->bd_head = 0;
891 intelhaddata->pcmbuf_head = 0;
892 intelhaddata->pcmbuf_filled = 0;
893
894 for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) {
8d48c016 895 if (i < intelhaddata->num_bds)
e1b239f3
TI		 896 had_prog_bd(substream, intelhaddata);
897 else /* invalidate the rest */
898 had_invalidate_bd(intelhaddata, i);
899 }
900
901 intelhaddata->bd_head = 0; /* reset at head again before starting */
902}
903
904/* process a bd, advance to the next */
905static void had_advance_ringbuf(struct snd_pcm_substream *substream,
906 struct snd_intelhad *intelhaddata)
907{
908 int num_periods = substream->runtime->periods;
909
910 /* reprogram the next buffer */
911 had_prog_bd(substream, intelhaddata);
912
913 /* proceed to next */
914 intelhaddata->pcmbuf_head++;
915 intelhaddata->pcmbuf_head %= num_periods;
916}
917
918/* process the current BD(s);
919 * returns the current PCM buffer byte position, or -EPIPE for underrun.
920 */
921static int had_process_ringbuf(struct snd_pcm_substream *substream,
922 struct snd_intelhad *intelhaddata)
923{
924 int len, processed;
925 unsigned long flags;
926
927 processed = 0;
928 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
929 for (;;) {
930 /* get the remaining bytes on the buffer */
931 had_read_register(intelhaddata,
932 AUD_BUF_LEN(intelhaddata->bd_head),
933 &len);
934 if (len < 0 || len > intelhaddata->period_bytes) {
935 dev_dbg(intelhaddata->dev, "Invalid buf length %d\n",
936 len);
937 len = -EPIPE;
938 goto out;
939 }
940
941 if (len > 0) /* OK, this is the current buffer */
942 break;
943
944 /* len=0 => already empty, check the next buffer */
945 if (++processed >= intelhaddata->num_bds) {
946 len = -EPIPE; /* all empty? - report underrun */
947 goto out;
948 }
949 had_advance_ringbuf(substream, intelhaddata);
950 }
951
952 len = intelhaddata->period_bytes - len;
953 len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head;
954 out:
955 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
956 return len;
957}
958
959/* called from irq handler */
960static void had_process_buffer_done(struct snd_intelhad *intelhaddata)
961{
962 struct snd_pcm_substream *substream;
963
964 if (!intelhaddata->connected)
965 return; /* disconnected? - bail out */
966
967 substream = had_substream_get(intelhaddata);
968 if (!substream)
969 return; /* no stream? - bail out */
970
971 /* process or stop the stream */
972 if (had_process_ringbuf(substream, intelhaddata) < 0)
973 snd_pcm_stop_xrun(substream);
974 else
975 snd_pcm_period_elapsed(substream);
976
977 had_substream_put(intelhaddata);
978}
979
e1b239f3
TI		 980/*
981 * The interrupt status 'sticky' bits might not be cleared by
982 * setting '1' to that bit once...
983 */
984static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata)
985{
986 int i;
987 u32 val;
988
e2acecf2 989 for (i = 0; i < 100; i++) {
e1b239f3
TI		 990 /* clear bit30, 31 AUD_HDMI_STATUS */
991 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val);
77531bee 992 if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN))
e1b239f3 993 return;
e2acecf2
TI		 994 udelay(100);
995 cond_resched();
e1b239f3
TI		 996 had_write_register(intelhaddata, AUD_HDMI_STATUS, val);
997 }
998 dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
999}
1000
e2acecf2
TI		 1001/* Perform some reset procedure but only when need_reset is set;
1002 * this is called from prepare or hw_free callbacks once after trigger STOP
1003 * or underrun has been processed in order to settle down the h/w state.
1004 */
1005static void had_do_reset(struct snd_intelhad *intelhaddata)
5dab11d8 1006{
e2acecf2
TI		 1007 if (!intelhaddata->need_reset)
1008 return;
5dab11d8 1009
5dab11d8 1010 /* Reset buffer pointers */
f4566aa1 1011 had_reset_audio(intelhaddata);
e1b239f3 1012 wait_clear_underrun_bit(intelhaddata);
e2acecf2
TI		 1013 intelhaddata->need_reset = false;
1014}
e1b239f3 1015
e2acecf2
TI		 1016/* called from irq handler */
1017static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
1018{
1019 struct snd_pcm_substream *substream;
e1b239f3
TI		 1020
1021 /* Report UNDERRUN error to above layers */
1022 substream = had_substream_get(intelhaddata);
1023 if (substream) {
1024 snd_pcm_stop_xrun(substream);
1025 had_substream_put(intelhaddata);
1026 }
e2acecf2 1027 intelhaddata->need_reset = true;
5dab11d8
JA		 1028}
1029
2e52f5e5 1030/*
44684f61 1031 * ALSA PCM open callback
5dab11d8 1032 */
b556290f 1033static int had_pcm_open(struct snd_pcm_substream *substream)
5dab11d8
JA		 1034{
1035 struct snd_intelhad *intelhaddata;
1036 struct snd_pcm_runtime *runtime;
5dab11d8
JA		 1037 int retval;
1038
5dab11d8 1039 intelhaddata = snd_pcm_substream_chip(substream);
5dab11d8
JA		 1040 runtime = substream->runtime;
1041
182cdf23 1042 pm_runtime_get_sync(intelhaddata->dev);
5dab11d8 1043
91b0cb0c 1044 if (!intelhaddata->connected) {
c75b0476
TI		 1045 dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
1046 __func__);
5dab11d8 1047 retval = -ENODEV;
fa5dfe6a 1048 goto error;
5dab11d8
JA		 1049 }
1050
1051 /* set the runtime hw parameter with local snd_pcm_hardware struct */
b556290f 1052 runtime->hw = had_pcm_hardware;
5dab11d8 1053
5dab11d8
JA		 1054 retval = snd_pcm_hw_constraint_integer(runtime,
1055 SNDRV_PCM_HW_PARAM_PERIODS);
1056 if (retval < 0)
fa5dfe6a 1057 goto error;
5dab11d8
JA		 1058
1059 /* Make sure, that the period size is always aligned
1060 * 64byte boundary
1061 */
1062 retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
1063 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
73997b05 1064 if (retval < 0)
fa5dfe6a 1065 goto error;
5dab11d8 1066
85bd8748
TI		 1067 retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1068 if (retval < 0)
1069 goto error;
1070
73997b05 1071 /* expose PCM substream */
313d9f28
TI		 1072 spin_lock_irq(&intelhaddata->had_spinlock);
1073 intelhaddata->stream_info.substream = substream;
1074 intelhaddata->stream_info.substream_refcount++;
1075 spin_unlock_irq(&intelhaddata->had_spinlock);
1076
5dab11d8 1077 return retval;
fa5dfe6a 1078 error:
5dab11d8 1079 pm_runtime_put(intelhaddata->dev);
5dab11d8
JA		 1080 return retval;
1081}
1082
2e52f5e5 1083/*
44684f61 1084 * ALSA PCM close callback
5dab11d8 1085 */
b556290f 1086static int had_pcm_close(struct snd_pcm_substream *substream)
5dab11d8
JA		 1087{
1088 struct snd_intelhad *intelhaddata;
5dab11d8 1089
5dab11d8 1090 intelhaddata = snd_pcm_substream_chip(substream);
5dab11d8 1091
73997b05 1092 /* unreference and sync with the pending PCM accesses */
313d9f28
TI		 1093 spin_lock_irq(&intelhaddata->had_spinlock);
1094 intelhaddata->stream_info.substream = NULL;
1095 intelhaddata->stream_info.substream_refcount--;
1096 while (intelhaddata->stream_info.substream_refcount > 0) {
1097 spin_unlock_irq(&intelhaddata->had_spinlock);
1098 cpu_relax();
1099 spin_lock_irq(&intelhaddata->had_spinlock);
1100 }
1101 spin_unlock_irq(&intelhaddata->had_spinlock);
5dab11d8 1102
5dab11d8
JA		 1103 pm_runtime_put(intelhaddata->dev);
1104 return 0;
1105}
1106
2e52f5e5 1107/*
44684f61 1108 * ALSA PCM hw_params callback
5dab11d8 1109 */
b556290f
TI		 1110static int had_pcm_hw_params(struct snd_pcm_substream *substream,
1111 struct snd_pcm_hw_params *hw_params)
5dab11d8 1112{
c75b0476 1113 struct snd_intelhad *intelhaddata;
5dab11d8
JA		 1114 unsigned long addr;
1115 int pages, buf_size, retval;
1116
c75b0476 1117 intelhaddata = snd_pcm_substream_chip(substream);
5dab11d8
JA		 1118 buf_size = params_buffer_bytes(hw_params);
1119 retval = snd_pcm_lib_malloc_pages(substream, buf_size);
1120 if (retval < 0)
1121 return retval;
c75b0476
TI		 1122 dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
1123 __func__, buf_size);
5dab11d8
JA		 1124 /* mark the pages as uncached region */
1125 addr = (unsigned long) substream->runtime->dma_area;
1126 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE;
1127 retval = set_memory_uc(addr, pages);
1128 if (retval) {
c75b0476
TI		 1129 dev_err(intelhaddata->dev, "set_memory_uc failed.Error:%d\n",
1130 retval);
5dab11d8
JA		 1131 return retval;
1132 }
1133 memset(substream->runtime->dma_area, 0, buf_size);
1134
1135 return retval;
1136}
1137
2e52f5e5 1138/*
44684f61 1139 * ALSA PCM hw_free callback
5dab11d8 1140 */
b556290f 1141static int had_pcm_hw_free(struct snd_pcm_substream *substream)
5dab11d8 1142{
e2acecf2 1143 struct snd_intelhad *intelhaddata;
5dab11d8
JA		 1144 unsigned long addr;
1145 u32 pages;
1146
e2acecf2
TI		 1147 intelhaddata = snd_pcm_substream_chip(substream);
1148 had_do_reset(intelhaddata);
1149
5dab11d8
JA		 1150 /* mark back the pages as cached/writeback region before the free */
1151 if (substream->runtime->dma_area != NULL) {
1152 addr = (unsigned long) substream->runtime->dma_area;
1153 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) /
1154 PAGE_SIZE;
1155 set_memory_wb(addr, pages);
1156 return snd_pcm_lib_free_pages(substream);
1157 }
1158 return 0;
1159}
1160
2e52f5e5 1161/*
44684f61 1162 * ALSA PCM trigger callback
5dab11d8 1163 */
b556290f 1164static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
5dab11d8 1165{
da864809 1166 int retval = 0;
5dab11d8 1167 struct snd_intelhad *intelhaddata;
5dab11d8 1168
5dab11d8 1169 intelhaddata = snd_pcm_substream_chip(substream);
5dab11d8 1170
df42cb49 1171 spin_lock(&intelhaddata->had_spinlock);
5dab11d8
JA		 1172 switch (cmd) {
1173 case SNDRV_PCM_TRIGGER_START:
182cdf23
TI		 1174 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1175 case SNDRV_PCM_TRIGGER_RESUME:
5dab11d8 1176 /* Disable local INTRs till register prgmng is done */
91b0cb0c 1177 if (!intelhaddata->connected) {
c75b0476
TI		 1178 dev_dbg(intelhaddata->dev,
1179 "_START: HDMI cable plugged-out\n");
5dab11d8
JA		 1180 retval = -ENODEV;
1181 break;
1182 }
5dab11d8 1183
5dab11d8 1184 /* Enable Audio */
075a1d46 1185 had_ack_irqs(intelhaddata); /* FIXME: do we need this? */
40ce4b5d 1186 had_enable_audio(intelhaddata, true);
5dab11d8
JA		 1187 break;
1188
1189 case SNDRV_PCM_TRIGGER_STOP:
182cdf23 1190 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
5dab11d8 1191 /* Disable Audio */
40ce4b5d 1192 had_enable_audio(intelhaddata, false);
e2acecf2 1193 intelhaddata->need_reset = true;
5dab11d8
JA		 1194 break;
1195
1196 default:
1197 retval = -EINVAL;
1198 }
df42cb49 1199 spin_unlock(&intelhaddata->had_spinlock);
5dab11d8
JA		 1200 return retval;
1201}
1202
2e52f5e5 1203/*
44684f61 1204 * ALSA PCM prepare callback
5dab11d8 1205 */
b556290f 1206static int had_pcm_prepare(struct snd_pcm_substream *substream)
5dab11d8
JA		 1207{
1208 int retval;
1209 u32 disp_samp_freq, n_param;
964ca808 1210 u32 link_rate = 0;
5dab11d8
JA		 1211 struct snd_intelhad *intelhaddata;
1212 struct snd_pcm_runtime *runtime;
5dab11d8 1213
5dab11d8
JA		 1214 intelhaddata = snd_pcm_substream_chip(substream);
1215 runtime = substream->runtime;
5dab11d8 1216
91b0cb0c 1217 if (!intelhaddata->connected) {
c75b0476
TI		 1218 dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n",
1219 __func__);
5dab11d8
JA		 1220 retval = -ENODEV;
1221 goto prep_end;
1222 }
1223
c75b0476 1224 dev_dbg(intelhaddata->dev, "period_size=%d\n",
5dab11d8 1225 (int)frames_to_bytes(runtime, runtime->period_size));
c75b0476
TI		 1226 dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
1227 dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
1228 (int)snd_pcm_lib_buffer_bytes(substream));
1229 dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
1230 dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
5dab11d8 1231
e2acecf2
TI		 1232 had_do_reset(intelhaddata);
1233
5dab11d8 1234 /* Get N value in KHz */
da864809 1235 disp_samp_freq = intelhaddata->tmds_clock_speed;
5dab11d8 1236
b556290f 1237 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
5dab11d8 1238 if (retval) {
c75b0476
TI		 1239 dev_err(intelhaddata->dev,
1240 "programming N value failed %#x\n", retval);
5dab11d8
JA		 1241 goto prep_end;
1242 }
964ca808
PLB		 1243
1244 if (intelhaddata->dp_output)
da864809 1245 link_rate = intelhaddata->link_rate;
964ca808 1246
b556290f
TI		 1247 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1248 n_param, intelhaddata);
5dab11d8 1249
b556290f 1250 had_prog_dip(substream, intelhaddata);
5dab11d8 1251
b556290f 1252 retval = had_init_audio_ctrl(substream, intelhaddata);
5dab11d8
JA		 1253
1254 /* Prog buffer address */
e1b239f3 1255 had_init_ringbuf(substream, intelhaddata);
5dab11d8
JA		 1256
1257 /*
1258 * Program channel mapping in following order:
1259 * FL, FR, C, LFE, RL, RR
1260 */
1261
79dda75a 1262 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
5dab11d8
JA		 1263
1264prep_end:
1265 return retval;
1266}
1267
2e52f5e5 1268/*
44684f61 1269 * ALSA PCM pointer callback
5dab11d8 1270 */
b556290f 1271static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream)
5dab11d8
JA		 1272{
1273 struct snd_intelhad *intelhaddata;
e1b239f3 1274 int len;
5dab11d8 1275
5dab11d8
JA		 1276 intelhaddata = snd_pcm_substream_chip(substream);
1277
91b0cb0c 1278 if (!intelhaddata->connected)
79f439ea
TI		 1279 return SNDRV_PCM_POS_XRUN;
1280
e1b239f3
TI		 1281 len = had_process_ringbuf(substream, intelhaddata);
1282 if (len < 0)
1283 return SNDRV_PCM_POS_XRUN;
8d48c016
TI		 1284 len = bytes_to_frames(substream->runtime, len);
1285 /* wrapping may happen when periods=1 */
1286 len %= substream->runtime->buffer_size;
1287 return len;
5dab11d8
JA		 1288}
1289
2e52f5e5 1290/*
44684f61 1291 * ALSA PCM mmap callback
5dab11d8 1292 */
b556290f
TI		 1293static int had_pcm_mmap(struct snd_pcm_substream *substream,
1294 struct vm_area_struct *vma)
5dab11d8 1295{
5dab11d8
JA		 1296 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1297 return remap_pfn_range(vma, vma->vm_start,
1298 substream->dma_buffer.addr >> PAGE_SHIFT,
1299 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1300}
1301
73997b05
TI		 1302/*
1303 * ALSA PCM ops
1304 */
b556290f
TI		 1305static const struct snd_pcm_ops had_pcm_ops = {
1306 .open = had_pcm_open,
1307 .close = had_pcm_close,
73997b05 1308 .ioctl = snd_pcm_lib_ioctl,
b556290f
TI		 1309 .hw_params = had_pcm_hw_params,
1310 .hw_free = had_pcm_hw_free,
1311 .prepare = had_pcm_prepare,
1312 .trigger = had_pcm_trigger,
1313 .pointer = had_pcm_pointer,
1314 .mmap = had_pcm_mmap,
73997b05
TI		 1315};
1316
8f8d1d7f 1317/* process mode change of the running stream; called in mutex */
b556290f 1318static int had_process_mode_change(struct snd_intelhad *intelhaddata)
5dab11d8 1319{
da864809 1320 struct snd_pcm_substream *substream;
5dab11d8
JA		 1321 int retval = 0;
1322 u32 disp_samp_freq, n_param;
964ca808 1323 u32 link_rate = 0;
5dab11d8 1324
313d9f28
TI		 1325 substream = had_substream_get(intelhaddata);
1326 if (!substream)
da864809 1327 return 0;
5dab11d8
JA		 1328
1329 /* Disable Audio */
40ce4b5d 1330 had_enable_audio(intelhaddata, false);
5dab11d8
JA		 1331
1332 /* Update CTS value */
da864809 1333 disp_samp_freq = intelhaddata->tmds_clock_speed;
5dab11d8 1334
b556290f 1335 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
5dab11d8 1336 if (retval) {
c75b0476
TI		 1337 dev_err(intelhaddata->dev,
1338 "programming N value failed %#x\n", retval);
5dab11d8
JA		 1339 goto out;
1340 }
964ca808
PLB		 1341
1342 if (intelhaddata->dp_output)
da864809 1343 link_rate = intelhaddata->link_rate;
964ca808 1344
b556290f
TI		 1345 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1346 n_param, intelhaddata);
5dab11d8
JA		 1347
1348 /* Enable Audio */
40ce4b5d 1349 had_enable_audio(intelhaddata, true);
5dab11d8
JA		 1350
1351out:
313d9f28 1352 had_substream_put(intelhaddata);
5dab11d8
JA		 1353 return retval;
1354}
1355
8f8d1d7f 1356/* process hot plug, called from wq with mutex locked */
0e9c67d7 1357static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
372d855f 1358{
372d855f 1359 struct snd_pcm_substream *substream;
372d855f 1360
bcce775c 1361 spin_lock_irq(&intelhaddata->had_spinlock);
91b0cb0c 1362 if (intelhaddata->connected) {
c75b0476 1363 dev_dbg(intelhaddata->dev, "Device already connected\n");
bcce775c 1364 spin_unlock_irq(&intelhaddata->had_spinlock);
0e9c67d7 1365 return;
372d855f 1366 }
0e9c67d7 1367
91b0cb0c 1368 intelhaddata->connected = true;
c75b0476
TI		 1369 dev_dbg(intelhaddata->dev,
1370 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
372d855f 1371 __func__, __LINE__);
bcce775c 1372 spin_unlock_irq(&intelhaddata->had_spinlock);
372d855f 1373
372d855f 1374 /* Safety check */
313d9f28 1375 substream = had_substream_get(intelhaddata);
372d855f 1376 if (substream) {
c75b0476
TI		 1377 dev_dbg(intelhaddata->dev,
1378 "Force to stop the active stream by disconnection\n");
372d855f 1379 /* Set runtime->state to hw_params done */
5def9019 1380 snd_pcm_stop_xrun(substream);
313d9f28 1381 had_substream_put(intelhaddata);
372d855f
TI		 1382 }
1383
1384 had_build_channel_allocation_map(intelhaddata);
b9bacf27
TI		 1385
1386 snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT);
372d855f
TI		 1387}
1388
8f8d1d7f 1389/* process hot unplug, called from wq with mutex locked */
0e9c67d7 1390static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
372d855f 1391{
313d9f28 1392 struct snd_pcm_substream *substream;
372d855f 1393
313d9f28
TI		 1394 substream = had_substream_get(intelhaddata);
1395
bcce775c 1396 spin_lock_irq(&intelhaddata->had_spinlock);
372d855f 1397
91b0cb0c 1398 if (!intelhaddata->connected) {
c75b0476 1399 dev_dbg(intelhaddata->dev, "Device already disconnected\n");
bcce775c 1400 spin_unlock_irq(&intelhaddata->had_spinlock);
313d9f28 1401 goto out;
372d855f 1402
372d855f
TI		 1403 }
1404
0e9c67d7 1405 /* Disable Audio */
40ce4b5d 1406 had_enable_audio(intelhaddata, false);
0e9c67d7 1407
91b0cb0c 1408 intelhaddata->connected = false;
c75b0476
TI		 1409 dev_dbg(intelhaddata->dev,
1410 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
372d855f 1411 __func__, __LINE__);
313d9f28 1412 spin_unlock_irq(&intelhaddata->had_spinlock);
372d855f
TI		 1413
1414 /* Report to above ALSA layer */
313d9f28 1415 if (substream)
5def9019 1416 snd_pcm_stop_xrun(substream);
372d855f 1417
313d9f28 1418 out:
b9bacf27 1419 snd_jack_report(intelhaddata->jack, 0);
313d9f28
TI		 1420 if (substream)
1421 had_substream_put(intelhaddata);
372d855f
TI		 1422 kfree(intelhaddata->chmap->chmap);
1423 intelhaddata->chmap->chmap = NULL;
372d855f
TI		 1424}
1425
73997b05
TI		 1426/*
1427 * ALSA iec958 and ELD controls
1428 */
5dab11d8 1429
5dab11d8
JA		 1430static int had_iec958_info(struct snd_kcontrol *kcontrol,
1431 struct snd_ctl_elem_info *uinfo)
1432{
1433 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1434 uinfo->count = 1;
1435 return 0;
1436}
1437
1438static int had_iec958_get(struct snd_kcontrol *kcontrol,
1439 struct snd_ctl_elem_value *ucontrol)
1440{
1441 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1442
8f8d1d7f 1443 mutex_lock(&intelhaddata->mutex);
5dab11d8
JA		 1444 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
1445 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
1446 ucontrol->value.iec958.status[2] =
1447 (intelhaddata->aes_bits >> 16) & 0xff;
1448 ucontrol->value.iec958.status[3] =
1449 (intelhaddata->aes_bits >> 24) & 0xff;
8f8d1d7f 1450 mutex_unlock(&intelhaddata->mutex);
5dab11d8
JA		 1451 return 0;
1452}
372d855f 1453
5dab11d8
JA		 1454static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
1455 struct snd_ctl_elem_value *ucontrol)
1456{
1457 ucontrol->value.iec958.status[0] = 0xff;
1458 ucontrol->value.iec958.status[1] = 0xff;
1459 ucontrol->value.iec958.status[2] = 0xff;
1460 ucontrol->value.iec958.status[3] = 0xff;
1461 return 0;
1462}
372d855f 1463
5dab11d8
JA		 1464static int had_iec958_put(struct snd_kcontrol *kcontrol,
1465 struct snd_ctl_elem_value *ucontrol)
1466{
1467 unsigned int val;
1468 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
8f8d1d7f 1469 int changed = 0;
5dab11d8 1470
5dab11d8
JA		 1471 val = (ucontrol->value.iec958.status[0] << 0) |
1472 (ucontrol->value.iec958.status[1] << 8) |
1473 (ucontrol->value.iec958.status[2] << 16) |
1474 (ucontrol->value.iec958.status[3] << 24);
8f8d1d7f 1475 mutex_lock(&intelhaddata->mutex);
5dab11d8
JA		 1476 if (intelhaddata->aes_bits != val) {
1477 intelhaddata->aes_bits = val;
8f8d1d7f 1478 changed = 1;
5dab11d8 1479 }
8f8d1d7f
TI		 1480 mutex_unlock(&intelhaddata->mutex);
1481 return changed;
5dab11d8
JA		 1482}
1483
4aedb946
TI		 1484static int had_ctl_eld_info(struct snd_kcontrol *kcontrol,
1485 struct snd_ctl_elem_info *uinfo)
1486{
1487 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1488 uinfo->count = HDMI_MAX_ELD_BYTES;
1489 return 0;
1490}
1491
1492static int had_ctl_eld_get(struct snd_kcontrol *kcontrol,
1493 struct snd_ctl_elem_value *ucontrol)
1494{
1495 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1496
1497 mutex_lock(&intelhaddata->mutex);
1498 memcpy(ucontrol->value.bytes.data, intelhaddata->eld,
1499 HDMI_MAX_ELD_BYTES);
1500 mutex_unlock(&intelhaddata->mutex);
1501 return 0;
1502}
5dab11d8 1503
73997b05 1504static const struct snd_kcontrol_new had_controls[] = {
4aedb946
TI		 1505 {
1506 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1507 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1508 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
1509 .info = had_iec958_info, /* shared */
1510 .get = had_iec958_mask_get,
1511 },
1512 {
1513 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1514 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1515 .info = had_iec958_info,
1516 .get = had_iec958_get,
1517 .put = had_iec958_put,
1518 },
1519 {
1520 .access = (SNDRV_CTL_ELEM_ACCESS_READ |
1521 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
1522 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1523 .name = "ELD",
1524 .info = had_ctl_eld_info,
1525 .get = had_ctl_eld_get,
1526 },
5dab11d8
JA		 1527};
1528
73997b05
TI		 1529/*
1530 * audio interrupt handler
1531 */
da864809
TI		 1532static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1533{
1534 struct snd_intelhad *ctx = dev_id;
1535 u32 audio_stat, audio_reg;
1536
4151ee84 1537 audio_reg = AUD_HDMI_STATUS;
83af57dd 1538 had_read_register(ctx, audio_reg, &audio_stat);
da864809
TI		 1539
1540 if (audio_stat & HDMI_AUDIO_UNDERRUN) {
83af57dd 1541 had_write_register(ctx, audio_reg, HDMI_AUDIO_UNDERRUN);
da864809
TI		 1542 had_process_buffer_underrun(ctx);
1543 }
1544
1545 if (audio_stat & HDMI_AUDIO_BUFFER_DONE) {
83af57dd 1546 had_write_register(ctx, audio_reg, HDMI_AUDIO_BUFFER_DONE);
da864809
TI		 1547 had_process_buffer_done(ctx);
1548 }
1549
1550 return IRQ_HANDLED;
1551}
1552
73997b05
TI		 1553/*
1554 * monitor plug/unplug notification from i915; just kick off the work
1555 */
da864809
TI		 1556static void notify_audio_lpe(struct platform_device *pdev)
1557{
1558 struct snd_intelhad *ctx = platform_get_drvdata(pdev);
da864809 1559
99b2ab9d
TI		 1560 schedule_work(&ctx->hdmi_audio_wq);
1561}
da864809 1562
73997b05 1563/* the work to handle monitor hot plug/unplug */
99b2ab9d
TI		 1564static void had_audio_wq(struct work_struct *work)
1565{
1566 struct snd_intelhad *ctx =
1567 container_of(work, struct snd_intelhad, hdmi_audio_wq);
1568 struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
da864809 1569
182cdf23 1570 pm_runtime_get_sync(ctx->dev);
8f8d1d7f 1571 mutex_lock(&ctx->mutex);
99b2ab9d
TI		 1572 if (!pdata->hdmi_connected) {
1573 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG\n",
1574 __func__);
4aedb946 1575 memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */
0e9c67d7 1576 had_process_hot_unplug(ctx);
da864809
TI		 1577 } else {
1578 struct intel_hdmi_lpe_audio_eld *eld = &pdata->eld;
1579
0e9c67d7
TI		 1580 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
1581 __func__, eld->port_id, pdata->tmds_clock_speed);
1582
da864809
TI		 1583 switch (eld->pipe_id) {
1584 case 0:
1585 ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1586 break;
1587 case 1:
1588 ctx->had_config_offset = AUDIO_HDMI_CONFIG_B;
1589 break;
1590 case 2:
1591 ctx->had_config_offset = AUDIO_HDMI_CONFIG_C;
1592 break;
1593 default:
99b2ab9d 1594 dev_dbg(ctx->dev, "Invalid pipe %d\n",
da864809
TI		 1595 eld->pipe_id);
1596 break;
1597 }
1598
df0435db 1599 memcpy(ctx->eld, eld->eld_data, sizeof(ctx->eld));
da864809 1600
0e9c67d7
TI		 1601 ctx->dp_output = pdata->dp_output;
1602 ctx->tmds_clock_speed = pdata->tmds_clock_speed;
1603 ctx->link_rate = pdata->link_rate;
da864809 1604
0e9c67d7 1605 had_process_hot_plug(ctx);
da864809 1606
0e9c67d7 1607 /* Process mode change if stream is active */
b556290f 1608 had_process_mode_change(ctx);
da864809 1609 }
8f8d1d7f 1610 mutex_unlock(&ctx->mutex);
182cdf23
TI		 1611 pm_runtime_put(ctx->dev);
1612}
1613
b9bacf27
TI		 1614/*
1615 * Jack interface
1616 */
1617static int had_create_jack(struct snd_intelhad *ctx)
1618{
1619 int err;
1620
1621 err = snd_jack_new(ctx->card, "HDMI/DP", SND_JACK_AVOUT, &ctx->jack,
1622 true, false);
1623 if (err < 0)
1624 return err;
1625 ctx->jack->private_data = ctx;
1626 return 0;
1627}
1628
182cdf23
TI		 1629/*
1630 * PM callbacks
1631 */
1632
1633static int hdmi_lpe_audio_runtime_suspend(struct device *dev)
1634{
1635 struct snd_intelhad *ctx = dev_get_drvdata(dev);
1636 struct snd_pcm_substream *substream;
1637
1638 substream = had_substream_get(ctx);
1639 if (substream) {
1640 snd_pcm_suspend(substream);
1641 had_substream_put(ctx);
1642 }
1643
1644 return 0;
1645}
1646
1df98924 1647static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev)
182cdf23
TI		 1648{
1649 struct snd_intelhad *ctx = dev_get_drvdata(dev);
1650 int err;
1651
1652 err = hdmi_lpe_audio_runtime_suspend(dev);
1653 if (!err)
1654 snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D3hot);
1655 return err;
1656}
1657
1df98924 1658static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev)
182cdf23
TI		 1659{
1660 struct snd_intelhad *ctx = dev_get_drvdata(dev);
1661
1662 snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D0);
1663 return 0;
da864809
TI		 1664}
1665
1666/* release resources */
1667static void hdmi_lpe_audio_free(struct snd_card *card)
1668{
1669 struct snd_intelhad *ctx = card->private_data;
1670
99b2ab9d
TI		 1671 cancel_work_sync(&ctx->hdmi_audio_wq);
1672
da864809
TI		 1673 if (ctx->mmio_start)
1674 iounmap(ctx->mmio_start);
1675 if (ctx->irq >= 0)
1676 free_irq(ctx->irq, ctx);
1677}
1678
79dda75a 1679/*
da864809 1680 * hdmi_lpe_audio_probe - start bridge with i915
5dab11d8 1681 *
da864809 1682 * This function is called when the i915 driver creates the
2e52f5e5 1683 * hdmi-lpe-audio platform device.
5dab11d8 1684 */
da864809 1685static int hdmi_lpe_audio_probe(struct platform_device *pdev)
5dab11d8 1686{
5dab11d8 1687 struct snd_card *card;
da864809
TI		 1688 struct snd_intelhad *ctx;
1689 struct snd_pcm *pcm;
1690 struct intel_hdmi_lpe_audio_pdata *pdata;
1691 int irq;
1692 struct resource *res_mmio;
4aedb946 1693 int i, ret;
da864809 1694
da864809
TI		 1695 pdata = pdev->dev.platform_data;
1696 if (!pdata) {
1697 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
1698 return -EINVAL;
1699 }
5dab11d8 1700
da864809
TI		 1701 /* get resources */
1702 irq = platform_get_irq(pdev, 0);
1703 if (irq < 0) {
1704 dev_err(&pdev->dev, "Could not get irq resource\n");
1705 return -ENODEV;
1706 }
1707
1708 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1709 if (!res_mmio) {
1710 dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
1711 return -ENXIO;
1712 }
5dab11d8 1713
5647aec2 1714 /* create a card instance with ALSA framework */
da864809
TI		 1715 ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
1716 THIS_MODULE, sizeof(*ctx), &card);
1717 if (ret)
1718 return ret;
1719
1720 ctx = card->private_data;
1721 spin_lock_init(&ctx->had_spinlock);
8f8d1d7f 1722 mutex_init(&ctx->mutex);
91b0cb0c 1723 ctx->connected = false;
da864809
TI		 1724 ctx->dev = &pdev->dev;
1725 ctx->card = card;
da864809
TI		 1726 ctx->aes_bits = SNDRV_PCM_DEFAULT_CON_SPDIF;
1727 strcpy(card->driver, INTEL_HAD);
873ab035
TI		 1728 strcpy(card->shortname, "Intel HDMI/DP LPE Audio");
1729 strcpy(card->longname, "Intel HDMI/DP LPE Audio");
da864809
TI		 1730
1731 ctx->irq = -1;
1732 ctx->tmds_clock_speed = DIS_SAMPLE_RATE_148_5;
99b2ab9d 1733 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
da864809
TI		 1734
1735 card->private_free = hdmi_lpe_audio_free;
1736
1737 /* assume pipe A as default */
1738 ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1739
1740 platform_set_drvdata(pdev, ctx);
1741
1742 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
1743 __func__, (unsigned int)res_mmio->start,
1744 (unsigned int)res_mmio->end);
1745
1746 ctx->mmio_start = ioremap_nocache(res_mmio->start,
1747 (size_t)(resource_size(res_mmio)));
1748 if (!ctx->mmio_start) {
1749 dev_err(&pdev->dev, "Could not get ioremap\n");
1750 ret = -EACCES;
1751 goto err;
1752 }
5dab11d8 1753
da864809
TI		 1754 /* setup interrupt handler */
1755 ret = request_irq(irq, display_pipe_interrupt_handler, 0,
1756 pdev->name, ctx);
1757 if (ret < 0) {
1758 dev_err(&pdev->dev, "request_irq failed\n");
1759 goto err;
1760 }
5dab11d8 1761
da864809
TI		 1762 ctx->irq = irq;
1763
1764 ret = snd_pcm_new(card, INTEL_HAD, PCM_INDEX, MAX_PB_STREAMS,
1765 MAX_CAP_STREAMS, &pcm);
1766 if (ret)
5dab11d8
JA		 1767 goto err;
1768
1769 /* setup private data which can be retrieved when required */
da864809 1770 pcm->private_data = ctx;
5dab11d8
JA		 1771 pcm->info_flags = 0;
1772 strncpy(pcm->name, card->shortname, strlen(card->shortname));
da864809 1773 /* setup the ops for playabck */
b556290f 1774 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops);
412bbe7d
TI		 1775
1776 /* only 32bit addressable */
1777 dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1778 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1779
e1b239f3
TI		 1780 /* allocate dma pages;
1781 * try to allocate 600k buffer as default which is large enough
5dab11d8 1782 */
da864809 1783 snd_pcm_lib_preallocate_pages_for_all(pcm,
5dab11d8 1784 SNDRV_DMA_TYPE_DEV, NULL,
e1b239f3 1785 HAD_DEFAULT_BUFFER, HAD_MAX_BUFFER);
5dab11d8 1786
4aedb946
TI		 1787 /* create controls */
1788 for (i = 0; i < ARRAY_SIZE(had_controls); i++) {
1789 ret = snd_ctl_add(card, snd_ctl_new1(&had_controls[i], ctx));
1790 if (ret < 0)
1791 goto err;
1792 }
5dab11d8
JA		 1793
1794 init_channel_allocations();
1795
1796 /* Register channel map controls */
da864809
TI		 1797 ret = had_register_chmap_ctls(ctx, pcm);
1798 if (ret < 0)
5dab11d8
JA		 1799 goto err;
1800
b9bacf27
TI		 1801 ret = had_create_jack(ctx);
1802 if (ret < 0)
1803 goto err;
1804
da864809
TI		 1805 ret = snd_card_register(card);
1806 if (ret)
36ec0d99
TI		 1807 goto err;
1808
bcce775c 1809 spin_lock_irq(&pdata->lpe_audio_slock);
da864809 1810 pdata->notify_audio_lpe = notify_audio_lpe;
99b2ab9d 1811 pdata->notify_pending = false;
bcce775c 1812 spin_unlock_irq(&pdata->lpe_audio_slock);
da864809
TI		 1813
1814 pm_runtime_set_active(&pdev->dev);
1815 pm_runtime_enable(&pdev->dev);
1816
99b2ab9d 1817 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
da864809 1818 schedule_work(&ctx->hdmi_audio_wq);
5dab11d8 1819
79dda75a 1820 return 0;
5647aec2 1821
5dab11d8
JA		 1822err:
1823 snd_card_free(card);
da864809 1824 return ret;
5dab11d8
JA		 1825}
1826
79dda75a 1827/*
da864809 1828 * hdmi_lpe_audio_remove - stop bridge with i915
5dab11d8 1829 *
2e52f5e5 1830 * This function is called when the platform device is destroyed.
5dab11d8 1831 */
da864809 1832static int hdmi_lpe_audio_remove(struct platform_device *pdev)
5dab11d8 1833{
da864809 1834 struct snd_intelhad *ctx = platform_get_drvdata(pdev);
5dab11d8 1835
da864809 1836 snd_card_free(ctx->card);
5dab11d8
JA		 1837 return 0;
1838}
1839
182cdf23
TI		 1840static const struct dev_pm_ops hdmi_lpe_audio_pm = {
1841 SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume)
1842 SET_RUNTIME_PM_OPS(hdmi_lpe_audio_runtime_suspend, NULL, NULL)
1843};
1844
da864809
TI		 1845static struct platform_driver hdmi_lpe_audio_driver = {
1846 .driver = {
1847 .name = "hdmi-lpe-audio",
182cdf23 1848 .pm = &hdmi_lpe_audio_pm,
da864809
TI		 1849 },
1850 .probe = hdmi_lpe_audio_probe,
1851 .remove = hdmi_lpe_audio_remove,
da864809
TI		 1852};
1853
1854module_platform_driver(hdmi_lpe_audio_driver);
1855MODULE_ALIAS("platform:hdmi_lpe_audio");
1856
5dab11d8
JA		 1857MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
1858MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
1859MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
1860MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
1861MODULE_DESCRIPTION("Intel HDMI Audio driver");
1862MODULE_LICENSE("GPL v2");
1863MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");
Linux 6.x block layer and io_uring tree(s)