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8e8e69d6 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
5dab11d8 JA |
2 | /* |
3 | * intel_hdmi_audio.c - Intel HDMI audio driver | |
4 | * | |
5 | * Copyright (C) 2016 Intel Corp | |
6 | * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com> | |
7 | * Ramesh Babu K V <ramesh.babu@intel.com> | |
8 | * Vaibhav Agarwal <vaibhav.agarwal@intel.com> | |
9 | * Jerome Anand <jerome.anand@intel.com> | |
10 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
11 | * | |
5dab11d8 JA |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
13 | * ALSA driver for Intel HDMI audio | |
14 | */ | |
15 | ||
03c34377 | 16 | #include <linux/types.h> |
5dab11d8 JA |
17 | #include <linux/platform_device.h> |
18 | #include <linux/io.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/module.h> | |
da864809 | 21 | #include <linux/interrupt.h> |
03c34377 | 22 | #include <linux/pm_runtime.h> |
412bbe7d | 23 | #include <linux/dma-mapping.h> |
e2acecf2 | 24 | #include <linux/delay.h> |
5dab11d8 | 25 | #include <sound/core.h> |
03c34377 TI |
26 | #include <sound/asoundef.h> |
27 | #include <sound/pcm.h> | |
5dab11d8 JA |
28 | #include <sound/pcm_params.h> |
29 | #include <sound/initval.h> | |
30 | #include <sound/control.h> | |
b9bacf27 | 31 | #include <sound/jack.h> |
03c34377 | 32 | #include <drm/drm_edid.h> |
da864809 | 33 | #include <drm/intel_lpe_audio.h> |
5dab11d8 JA |
34 | #include "intel_hdmi_audio.h" |
35 | ||
e87c65ae PLB |
36 | #define INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS 5000 |
37 | ||
8a2d6ae1 VS |
38 | #define for_each_pipe(card_ctx, pipe) \ |
39 | for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++) | |
b4eb0d52 VS |
40 | #define for_each_port(card_ctx, port) \ |
41 | for ((port) = 0; (port) < (card_ctx)->num_ports; (port)++) | |
42 | ||
5dab11d8 JA |
43 | /*standard module options for ALSA. This module supports only one card*/ |
44 | static int hdmi_card_index = SNDRV_DEFAULT_IDX1; | |
45 | static char *hdmi_card_id = SNDRV_DEFAULT_STR1; | |
7229b12f | 46 | static bool single_port; |
5dab11d8 JA |
47 | |
48 | module_param_named(index, hdmi_card_index, int, 0444); | |
49 | MODULE_PARM_DESC(index, | |
50 | "Index value for INTEL Intel HDMI Audio controller."); | |
51 | module_param_named(id, hdmi_card_id, charp, 0444); | |
52 | MODULE_PARM_DESC(id, | |
53 | "ID string for INTEL Intel HDMI Audio controller."); | |
7229b12f TI |
54 | module_param(single_port, bool, 0444); |
55 | MODULE_PARM_DESC(single_port, | |
56 | "Single-port mode (for compatibility)"); | |
5dab11d8 JA |
57 | |
58 | /* | |
59 | * ELD SA bits in the CEA Speaker Allocation data block | |
60 | */ | |
4a5ddb2c | 61 | static const int eld_speaker_allocation_bits[] = { |
5dab11d8 JA |
62 | [0] = FL | FR, |
63 | [1] = LFE, | |
64 | [2] = FC, | |
65 | [3] = RL | RR, | |
66 | [4] = RC, | |
67 | [5] = FLC | FRC, | |
68 | [6] = RLC | RRC, | |
69 | /* the following are not defined in ELD yet */ | |
70 | [7] = 0, | |
71 | }; | |
72 | ||
73 | /* | |
74 | * This is an ordered list! | |
75 | * | |
76 | * The preceding ones have better chances to be selected by | |
77 | * hdmi_channel_allocation(). | |
78 | */ | |
79 | static struct cea_channel_speaker_allocation channel_allocations[] = { | |
80 | /* channel: 7 6 5 4 3 2 1 0 */ | |
81 | { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, | |
82 | /* 2.1 */ | |
83 | { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, | |
84 | /* Dolby Surround */ | |
85 | { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, | |
86 | /* surround40 */ | |
87 | { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, | |
88 | /* surround41 */ | |
89 | { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, | |
90 | /* surround50 */ | |
91 | { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, | |
92 | /* surround51 */ | |
93 | { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, | |
94 | /* 6.1 */ | |
95 | { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, | |
96 | /* surround71 */ | |
97 | { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, | |
98 | ||
99 | { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, | |
100 | { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, | |
101 | { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, | |
102 | { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, | |
103 | { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, | |
104 | { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, | |
105 | { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, | |
106 | { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, | |
107 | { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, | |
108 | { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, | |
109 | { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, | |
110 | { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, | |
111 | { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, | |
112 | { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, | |
113 | { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, | |
114 | { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, | |
115 | { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, | |
116 | { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, | |
117 | { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, | |
118 | { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, | |
119 | { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, | |
120 | { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, | |
121 | { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, | |
122 | }; | |
123 | ||
4a5ddb2c | 124 | static const struct channel_map_table map_tables[] = { |
5dab11d8 JA |
125 | { SNDRV_CHMAP_FL, 0x00, FL }, |
126 | { SNDRV_CHMAP_FR, 0x01, FR }, | |
127 | { SNDRV_CHMAP_RL, 0x04, RL }, | |
128 | { SNDRV_CHMAP_RR, 0x05, RR }, | |
129 | { SNDRV_CHMAP_LFE, 0x02, LFE }, | |
130 | { SNDRV_CHMAP_FC, 0x03, FC }, | |
131 | { SNDRV_CHMAP_RLC, 0x06, RLC }, | |
132 | { SNDRV_CHMAP_RRC, 0x07, RRC }, | |
133 | {} /* terminator */ | |
134 | }; | |
135 | ||
136 | /* hardware capability structure */ | |
b556290f | 137 | static const struct snd_pcm_hardware had_pcm_hardware = { |
5dab11d8 | 138 | .info = (SNDRV_PCM_INFO_INTERLEAVED | |
a9ebdd0e | 139 | SNDRV_PCM_INFO_MMAP | |
e8de9859 TI |
140 | SNDRV_PCM_INFO_MMAP_VALID | |
141 | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), | |
3fe2cf7e TI |
142 | .formats = (SNDRV_PCM_FMTBIT_S16_LE | |
143 | SNDRV_PCM_FMTBIT_S24_LE | | |
85bd8748 | 144 | SNDRV_PCM_FMTBIT_S32_LE), |
5dab11d8 JA |
145 | .rates = SNDRV_PCM_RATE_32000 | |
146 | SNDRV_PCM_RATE_44100 | | |
147 | SNDRV_PCM_RATE_48000 | | |
148 | SNDRV_PCM_RATE_88200 | | |
149 | SNDRV_PCM_RATE_96000 | | |
150 | SNDRV_PCM_RATE_176400 | | |
151 | SNDRV_PCM_RATE_192000, | |
152 | .rate_min = HAD_MIN_RATE, | |
153 | .rate_max = HAD_MAX_RATE, | |
154 | .channels_min = HAD_MIN_CHANNEL, | |
155 | .channels_max = HAD_MAX_CHANNEL, | |
156 | .buffer_bytes_max = HAD_MAX_BUFFER, | |
157 | .period_bytes_min = HAD_MIN_PERIOD_BYTES, | |
158 | .period_bytes_max = HAD_MAX_PERIOD_BYTES, | |
159 | .periods_min = HAD_MIN_PERIODS, | |
160 | .periods_max = HAD_MAX_PERIODS, | |
161 | .fifo_size = HAD_FIFO_SIZE, | |
162 | }; | |
163 | ||
313d9f28 TI |
164 | /* Get the active PCM substream; |
165 | * Call had_substream_put() for unreferecing. | |
166 | * Don't call this inside had_spinlock, as it takes by itself | |
167 | */ | |
168 | static struct snd_pcm_substream * | |
169 | had_substream_get(struct snd_intelhad *intelhaddata) | |
170 | { | |
171 | struct snd_pcm_substream *substream; | |
172 | unsigned long flags; | |
173 | ||
174 | spin_lock_irqsave(&intelhaddata->had_spinlock, flags); | |
175 | substream = intelhaddata->stream_info.substream; | |
176 | if (substream) | |
177 | intelhaddata->stream_info.substream_refcount++; | |
178 | spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); | |
179 | return substream; | |
180 | } | |
181 | ||
182 | /* Unref the active PCM substream; | |
183 | * Don't call this inside had_spinlock, as it takes by itself | |
184 | */ | |
185 | static void had_substream_put(struct snd_intelhad *intelhaddata) | |
186 | { | |
187 | unsigned long flags; | |
188 | ||
189 | spin_lock_irqsave(&intelhaddata->had_spinlock, flags); | |
190 | intelhaddata->stream_info.substream_refcount--; | |
191 | spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); | |
192 | } | |
193 | ||
8a2d6ae1 VS |
194 | static u32 had_config_offset(int pipe) |
195 | { | |
196 | switch (pipe) { | |
197 | default: | |
198 | case 0: | |
199 | return AUDIO_HDMI_CONFIG_A; | |
200 | case 1: | |
201 | return AUDIO_HDMI_CONFIG_B; | |
202 | case 2: | |
203 | return AUDIO_HDMI_CONFIG_C; | |
204 | } | |
205 | } | |
206 | ||
5dab11d8 | 207 | /* Register access functions */ |
8a2d6ae1 VS |
208 | static u32 had_read_register_raw(struct snd_intelhad_card *card_ctx, |
209 | int pipe, u32 reg) | |
28ed125b | 210 | { |
8a2d6ae1 | 211 | return ioread32(card_ctx->mmio_start + had_config_offset(pipe) + reg); |
28ed125b TI |
212 | } |
213 | ||
8a2d6ae1 VS |
214 | static void had_write_register_raw(struct snd_intelhad_card *card_ctx, |
215 | int pipe, u32 reg, u32 val) | |
28ed125b | 216 | { |
8a2d6ae1 | 217 | iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg); |
28ed125b TI |
218 | } |
219 | ||
83af57dd | 220 | static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val) |
5dab11d8 | 221 | { |
28ed125b TI |
222 | if (!ctx->connected) |
223 | *val = 0; | |
224 | else | |
8a2d6ae1 | 225 | *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg); |
5dab11d8 JA |
226 | } |
227 | ||
83af57dd | 228 | static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val) |
5dab11d8 | 229 | { |
28ed125b | 230 | if (ctx->connected) |
8a2d6ae1 | 231 | had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val); |
5dab11d8 JA |
232 | } |
233 | ||
da864809 | 234 | /* |
313d9f28 TI |
235 | * enable / disable audio configuration |
236 | * | |
83af57dd | 237 | * The normal read/modify should not directly be used on VLV2 for |
da864809 | 238 | * updating AUD_CONFIG register. |
5dab11d8 JA |
239 | * This is because: |
240 | * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2 | |
1d7a0395 | 241 | * HDMI IP. As a result a read-modify of AUD_CONFIG register will always |
5dab11d8 JA |
242 | * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the |
243 | * register. This field should be 1xy binary for configuration with 6 or | |
244 | * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio) | |
245 | * causes the "channels" field to be updated as 0xy binary resulting in | |
246 | * bad audio. The fix is to always write the AUD_CONFIG[6:4] with | |
247 | * appropriate value when doing read-modify of AUD_CONFIG register. | |
5dab11d8 | 248 | */ |
40ce4b5d | 249 | static void had_enable_audio(struct snd_intelhad *intelhaddata, |
b556290f | 250 | bool enable) |
5dab11d8 | 251 | { |
40ce4b5d TI |
252 | /* update the cached value */ |
253 | intelhaddata->aud_config.regx.aud_en = enable; | |
254 | had_write_register(intelhaddata, AUD_CONFIG, | |
255 | intelhaddata->aud_config.regval); | |
5dab11d8 JA |
256 | } |
257 | ||
075a1d46 TI |
258 | /* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */ |
259 | static void had_ack_irqs(struct snd_intelhad *ctx) | |
da864809 TI |
260 | { |
261 | u32 status_reg; | |
262 | ||
28ed125b TI |
263 | if (!ctx->connected) |
264 | return; | |
075a1d46 TI |
265 | had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); |
266 | status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN; | |
267 | had_write_register(ctx, AUD_HDMI_STATUS, status_reg); | |
268 | had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); | |
da864809 TI |
269 | } |
270 | ||
f4566aa1 TI |
271 | /* Reset buffer pointers */ |
272 | static void had_reset_audio(struct snd_intelhad *intelhaddata) | |
5dab11d8 | 273 | { |
77531bee TI |
274 | had_write_register(intelhaddata, AUD_HDMI_STATUS, |
275 | AUD_HDMI_STATUSG_MASK_FUNCRST); | |
f4566aa1 | 276 | had_write_register(intelhaddata, AUD_HDMI_STATUS, 0); |
5dab11d8 JA |
277 | } |
278 | ||
2e52f5e5 | 279 | /* |
5dab11d8 JA |
280 | * initialize audio channel status registers |
281 | * This function is called in the prepare callback | |
282 | */ | |
283 | static int had_prog_status_reg(struct snd_pcm_substream *substream, | |
284 | struct snd_intelhad *intelhaddata) | |
285 | { | |
7ceba75f TI |
286 | union aud_ch_status_0 ch_stat0 = {.regval = 0}; |
287 | union aud_ch_status_1 ch_stat1 = {.regval = 0}; | |
5dab11d8 | 288 | |
7ceba75f | 289 | ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits & |
2e52f5e5 | 290 | IEC958_AES0_NONAUDIO) >> 1; |
7ceba75f | 291 | ch_stat0.regx.clk_acc = (intelhaddata->aes_bits & |
2e52f5e5 | 292 | IEC958_AES3_CON_CLOCK) >> 4; |
5dab11d8 JA |
293 | |
294 | switch (substream->runtime->rate) { | |
295 | case AUD_SAMPLE_RATE_32: | |
7ceba75f | 296 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ; |
5dab11d8 JA |
297 | break; |
298 | ||
299 | case AUD_SAMPLE_RATE_44_1: | |
7ceba75f | 300 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ; |
5dab11d8 JA |
301 | break; |
302 | case AUD_SAMPLE_RATE_48: | |
7ceba75f | 303 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ; |
5dab11d8 JA |
304 | break; |
305 | case AUD_SAMPLE_RATE_88_2: | |
7ceba75f | 306 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ; |
5dab11d8 JA |
307 | break; |
308 | case AUD_SAMPLE_RATE_96: | |
7ceba75f | 309 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ; |
5dab11d8 JA |
310 | break; |
311 | case AUD_SAMPLE_RATE_176_4: | |
7ceba75f | 312 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ; |
5dab11d8 JA |
313 | break; |
314 | case AUD_SAMPLE_RATE_192: | |
7ceba75f | 315 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ; |
5dab11d8 JA |
316 | break; |
317 | ||
318 | default: | |
319 | /* control should never come here */ | |
320 | return -EINVAL; | |
5dab11d8 | 321 | } |
2e52f5e5 | 322 | |
79dda75a | 323 | had_write_register(intelhaddata, |
7ceba75f | 324 | AUD_CH_STATUS_0, ch_stat0.regval); |
5dab11d8 | 325 | |
85bd8748 | 326 | switch (substream->runtime->format) { |
85bd8748 | 327 | case SNDRV_PCM_FORMAT_S16_LE: |
7ceba75f TI |
328 | ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20; |
329 | ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS; | |
85bd8748 | 330 | break; |
85bd8748 TI |
331 | case SNDRV_PCM_FORMAT_S24_LE: |
332 | case SNDRV_PCM_FORMAT_S32_LE: | |
7ceba75f TI |
333 | ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24; |
334 | ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS; | |
85bd8748 TI |
335 | break; |
336 | default: | |
337 | return -EINVAL; | |
5dab11d8 | 338 | } |
2e52f5e5 | 339 | |
79dda75a | 340 | had_write_register(intelhaddata, |
7ceba75f | 341 | AUD_CH_STATUS_1, ch_stat1.regval); |
5dab11d8 JA |
342 | return 0; |
343 | } | |
344 | ||
76296ef0 | 345 | /* |
5dab11d8 | 346 | * function to initialize audio |
1d7a0395 | 347 | * registers and buffer configuration registers |
5dab11d8 JA |
348 | * This function is called in the prepare callback |
349 | */ | |
b556290f TI |
350 | static int had_init_audio_ctrl(struct snd_pcm_substream *substream, |
351 | struct snd_intelhad *intelhaddata) | |
5dab11d8 | 352 | { |
7ceba75f TI |
353 | union aud_cfg cfg_val = {.regval = 0}; |
354 | union aud_buf_config buf_cfg = {.regval = 0}; | |
5dab11d8 JA |
355 | u8 channels; |
356 | ||
357 | had_prog_status_reg(substream, intelhaddata); | |
358 | ||
7ceba75f TI |
359 | buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD; |
360 | buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD; | |
361 | buf_cfg.regx.aud_delay = 0; | |
362 | had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval); | |
5dab11d8 JA |
363 | |
364 | channels = substream->runtime->channels; | |
7ceba75f | 365 | cfg_val.regx.num_ch = channels - 2; |
5dab11d8 | 366 | if (channels <= 2) |
7ceba75f | 367 | cfg_val.regx.layout = LAYOUT0; |
5dab11d8 | 368 | else |
7ceba75f | 369 | cfg_val.regx.layout = LAYOUT1; |
5dab11d8 | 370 | |
3fe2cf7e TI |
371 | if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) |
372 | cfg_val.regx.packet_mode = 1; | |
373 | ||
85bd8748 TI |
374 | if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE) |
375 | cfg_val.regx.left_align = 1; | |
376 | ||
7ceba75f | 377 | cfg_val.regx.val_bit = 1; |
83af57dd TI |
378 | |
379 | /* fix up the DP bits */ | |
380 | if (intelhaddata->dp_output) { | |
381 | cfg_val.regx.dp_modei = 1; | |
382 | cfg_val.regx.set = 1; | |
383 | } | |
384 | ||
7ceba75f | 385 | had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval); |
40ce4b5d | 386 | intelhaddata->aud_config = cfg_val; |
5dab11d8 JA |
387 | return 0; |
388 | } | |
389 | ||
5dab11d8 JA |
390 | /* |
391 | * Compute derived values in channel_allocations[]. | |
392 | */ | |
393 | static void init_channel_allocations(void) | |
394 | { | |
395 | int i, j; | |
396 | struct cea_channel_speaker_allocation *p; | |
397 | ||
5dab11d8 JA |
398 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { |
399 | p = channel_allocations + i; | |
400 | p->channels = 0; | |
401 | p->spk_mask = 0; | |
402 | for (j = 0; j < ARRAY_SIZE(p->speakers); j++) | |
403 | if (p->speakers[j]) { | |
404 | p->channels++; | |
405 | p->spk_mask |= p->speakers[j]; | |
406 | } | |
407 | } | |
408 | } | |
409 | ||
410 | /* | |
411 | * The transformation takes two steps: | |
412 | * | |
413 | * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask | |
414 | * spk_mask => (channel_allocations[]) => ai->CA | |
415 | * | |
416 | * TODO: it could select the wrong CA from multiple candidates. | |
417 | */ | |
b556290f TI |
418 | static int had_channel_allocation(struct snd_intelhad *intelhaddata, |
419 | int channels) | |
5dab11d8 JA |
420 | { |
421 | int i; | |
422 | int ca = 0; | |
423 | int spk_mask = 0; | |
424 | ||
425 | /* | |
426 | * CA defaults to 0 for basic stereo audio | |
427 | */ | |
428 | if (channels <= 2) | |
429 | return 0; | |
430 | ||
431 | /* | |
432 | * expand ELD's speaker allocation mask | |
433 | * | |
434 | * ELD tells the speaker mask in a compact(paired) form, | |
435 | * expand ELD's notions to match the ones used by Audio InfoFrame. | |
436 | */ | |
437 | ||
438 | for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { | |
df0435db | 439 | if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) |
5dab11d8 JA |
440 | spk_mask |= eld_speaker_allocation_bits[i]; |
441 | } | |
442 | ||
443 | /* search for the first working match in the CA table */ | |
444 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { | |
445 | if (channels == channel_allocations[i].channels && | |
446 | (spk_mask & channel_allocations[i].spk_mask) == | |
447 | channel_allocations[i].spk_mask) { | |
448 | ca = channel_allocations[i].ca_index; | |
449 | break; | |
450 | } | |
451 | } | |
452 | ||
c75b0476 | 453 | dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels); |
5dab11d8 JA |
454 | |
455 | return ca; | |
456 | } | |
457 | ||
458 | /* from speaker bit mask to ALSA API channel position */ | |
459 | static int spk_to_chmap(int spk) | |
460 | { | |
4a5ddb2c | 461 | const struct channel_map_table *t = map_tables; |
5dab11d8 JA |
462 | |
463 | for (; t->map; t++) { | |
464 | if (t->spk_mask == spk) | |
465 | return t->map; | |
466 | } | |
467 | return 0; | |
468 | } | |
469 | ||
372d855f | 470 | static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata) |
5dab11d8 | 471 | { |
2e52f5e5 | 472 | int i, c; |
5dab11d8 JA |
473 | int spk_mask = 0; |
474 | struct snd_pcm_chmap_elem *chmap; | |
475 | u8 eld_high, eld_high_mask = 0xF0; | |
476 | u8 high_msb; | |
477 | ||
18353192 TI |
478 | kfree(intelhaddata->chmap->chmap); |
479 | intelhaddata->chmap->chmap = NULL; | |
480 | ||
5dab11d8 | 481 | chmap = kzalloc(sizeof(*chmap), GFP_KERNEL); |
18353192 | 482 | if (!chmap) |
5dab11d8 | 483 | return; |
5dab11d8 | 484 | |
df0435db TI |
485 | dev_dbg(intelhaddata->dev, "eld speaker = %x\n", |
486 | intelhaddata->eld[DRM_ELD_SPEAKER]); | |
5dab11d8 JA |
487 | |
488 | /* WA: Fix the max channel supported to 8 */ | |
489 | ||
490 | /* | |
491 | * Sink may support more than 8 channels, if eld_high has more than | |
492 | * one bit set. SOC supports max 8 channels. | |
493 | * Refer eld_speaker_allocation_bits, for sink speaker allocation | |
494 | */ | |
495 | ||
496 | /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */ | |
df0435db | 497 | eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask; |
5dab11d8 JA |
498 | if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) { |
499 | /* eld_high & (eld_high-1): if more than 1 bit set */ | |
500 | /* 0x1F: 7 channels */ | |
501 | for (i = 1; i < 4; i++) { | |
502 | high_msb = eld_high & (0x80 >> i); | |
503 | if (high_msb) { | |
df0435db | 504 | intelhaddata->eld[DRM_ELD_SPEAKER] &= |
5dab11d8 JA |
505 | high_msb | 0xF; |
506 | break; | |
507 | } | |
508 | } | |
509 | } | |
510 | ||
511 | for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { | |
df0435db | 512 | if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) |
5dab11d8 JA |
513 | spk_mask |= eld_speaker_allocation_bits[i]; |
514 | } | |
515 | ||
516 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { | |
517 | if (spk_mask == channel_allocations[i].spk_mask) { | |
518 | for (c = 0; c < channel_allocations[i].channels; c++) { | |
519 | chmap->map[c] = spk_to_chmap( | |
520 | channel_allocations[i].speakers[ | |
2e52f5e5 | 521 | (MAX_SPEAKERS - 1) - c]); |
5dab11d8 JA |
522 | } |
523 | chmap->channels = channel_allocations[i].channels; | |
524 | intelhaddata->chmap->chmap = chmap; | |
525 | break; | |
526 | } | |
527 | } | |
18353192 | 528 | if (i >= ARRAY_SIZE(channel_allocations)) |
5dab11d8 | 529 | kfree(chmap); |
5dab11d8 JA |
530 | } |
531 | ||
532 | /* | |
533 | * ALSA API channel-map control callbacks | |
534 | */ | |
535 | static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol, | |
536 | struct snd_ctl_elem_info *uinfo) | |
537 | { | |
5dab11d8 JA |
538 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; |
539 | uinfo->count = HAD_MAX_CHANNEL; | |
540 | uinfo->value.integer.min = 0; | |
541 | uinfo->value.integer.max = SNDRV_CHMAP_LAST; | |
542 | return 0; | |
543 | } | |
544 | ||
545 | static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol, | |
546 | struct snd_ctl_elem_value *ucontrol) | |
547 | { | |
548 | struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); | |
549 | struct snd_intelhad *intelhaddata = info->private_data; | |
2e52f5e5 | 550 | int i; |
5dab11d8 JA |
551 | const struct snd_pcm_chmap_elem *chmap; |
552 | ||
a72ccfba TI |
553 | memset(ucontrol->value.integer.value, 0, |
554 | sizeof(long) * HAD_MAX_CHANNEL); | |
8f8d1d7f TI |
555 | mutex_lock(&intelhaddata->mutex); |
556 | if (!intelhaddata->chmap->chmap) { | |
557 | mutex_unlock(&intelhaddata->mutex); | |
a72ccfba | 558 | return 0; |
8f8d1d7f TI |
559 | } |
560 | ||
5dab11d8 | 561 | chmap = intelhaddata->chmap->chmap; |
c75b0476 | 562 | for (i = 0; i < chmap->channels; i++) |
5dab11d8 | 563 | ucontrol->value.integer.value[i] = chmap->map[i]; |
8f8d1d7f | 564 | mutex_unlock(&intelhaddata->mutex); |
5dab11d8 JA |
565 | |
566 | return 0; | |
567 | } | |
568 | ||
569 | static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata, | |
570 | struct snd_pcm *pcm) | |
571 | { | |
2e52f5e5 | 572 | int err; |
5dab11d8 JA |
573 | |
574 | err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, | |
575 | NULL, 0, (unsigned long)intelhaddata, | |
576 | &intelhaddata->chmap); | |
577 | if (err < 0) | |
578 | return err; | |
579 | ||
580 | intelhaddata->chmap->private_data = intelhaddata; | |
e9d65abf TI |
581 | intelhaddata->chmap->kctl->info = had_chmap_ctl_info; |
582 | intelhaddata->chmap->kctl->get = had_chmap_ctl_get; | |
5dab11d8 JA |
583 | intelhaddata->chmap->chmap = NULL; |
584 | return 0; | |
585 | } | |
586 | ||
76296ef0 | 587 | /* |
44684f61 | 588 | * Initialize Data Island Packets registers |
5dab11d8 JA |
589 | * This function is called in the prepare callback |
590 | */ | |
b556290f TI |
591 | static void had_prog_dip(struct snd_pcm_substream *substream, |
592 | struct snd_intelhad *intelhaddata) | |
5dab11d8 JA |
593 | { |
594 | int i; | |
7ceba75f TI |
595 | union aud_ctrl_st ctrl_state = {.regval = 0}; |
596 | union aud_info_frame2 frame2 = {.regval = 0}; | |
597 | union aud_info_frame3 frame3 = {.regval = 0}; | |
5dab11d8 | 598 | u8 checksum = 0; |
964ca808 | 599 | u32 info_frame; |
5dab11d8 | 600 | int channels; |
36ed3466 | 601 | int ca; |
5dab11d8 JA |
602 | |
603 | channels = substream->runtime->channels; | |
604 | ||
7ceba75f | 605 | had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); |
5dab11d8 | 606 | |
b556290f | 607 | ca = had_channel_allocation(intelhaddata, channels); |
964ca808 PLB |
608 | if (intelhaddata->dp_output) { |
609 | info_frame = DP_INFO_FRAME_WORD1; | |
36ed3466 | 610 | frame2.regval = (substream->runtime->channels - 1) | (ca << 24); |
964ca808 PLB |
611 | } else { |
612 | info_frame = HDMI_INFO_FRAME_WORD1; | |
7ceba75f | 613 | frame2.regx.chnl_cnt = substream->runtime->channels - 1; |
36ed3466 | 614 | frame3.regx.chnl_alloc = ca; |
5dab11d8 | 615 | |
2e52f5e5 | 616 | /* Calculte the byte wide checksum for all valid DIP words */ |
964ca808 | 617 | for (i = 0; i < BYTES_PER_WORD; i++) |
7ceba75f | 618 | checksum += (info_frame >> (i * 8)) & 0xff; |
964ca808 | 619 | for (i = 0; i < BYTES_PER_WORD; i++) |
7ceba75f | 620 | checksum += (frame2.regval >> (i * 8)) & 0xff; |
964ca808 | 621 | for (i = 0; i < BYTES_PER_WORD; i++) |
7ceba75f | 622 | checksum += (frame3.regval >> (i * 8)) & 0xff; |
5dab11d8 | 623 | |
7ceba75f | 624 | frame2.regx.chksum = -(checksum); |
964ca808 | 625 | } |
5dab11d8 | 626 | |
4151ee84 | 627 | had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame); |
7ceba75f TI |
628 | had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval); |
629 | had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval); | |
5dab11d8 JA |
630 | |
631 | /* program remaining DIP words with zero */ | |
632 | for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++) | |
4151ee84 | 633 | had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0); |
5dab11d8 | 634 | |
7ceba75f TI |
635 | ctrl_state.regx.dip_freq = 1; |
636 | ctrl_state.regx.dip_en_sta = 1; | |
637 | had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); | |
5dab11d8 JA |
638 | } |
639 | ||
964ca808 PLB |
640 | static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate) |
641 | { | |
642 | u32 maud_val; | |
643 | ||
2e52f5e5 | 644 | /* Select maud according to DP 1.2 spec */ |
964ca808 PLB |
645 | if (link_rate == DP_2_7_GHZ) { |
646 | switch (aud_samp_freq) { | |
647 | case AUD_SAMPLE_RATE_32: | |
648 | maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL; | |
649 | break; | |
650 | ||
651 | case AUD_SAMPLE_RATE_44_1: | |
652 | maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL; | |
653 | break; | |
654 | ||
655 | case AUD_SAMPLE_RATE_48: | |
656 | maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL; | |
657 | break; | |
658 | ||
659 | case AUD_SAMPLE_RATE_88_2: | |
660 | maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL; | |
661 | break; | |
662 | ||
663 | case AUD_SAMPLE_RATE_96: | |
664 | maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL; | |
665 | break; | |
666 | ||
667 | case AUD_SAMPLE_RATE_176_4: | |
668 | maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL; | |
669 | break; | |
670 | ||
671 | case HAD_MAX_RATE: | |
672 | maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL; | |
673 | break; | |
674 | ||
675 | default: | |
676 | maud_val = -EINVAL; | |
677 | break; | |
678 | } | |
679 | } else if (link_rate == DP_1_62_GHZ) { | |
680 | switch (aud_samp_freq) { | |
681 | case AUD_SAMPLE_RATE_32: | |
682 | maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL; | |
683 | break; | |
684 | ||
685 | case AUD_SAMPLE_RATE_44_1: | |
686 | maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL; | |
687 | break; | |
688 | ||
689 | case AUD_SAMPLE_RATE_48: | |
690 | maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL; | |
691 | break; | |
692 | ||
693 | case AUD_SAMPLE_RATE_88_2: | |
694 | maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL; | |
695 | break; | |
696 | ||
697 | case AUD_SAMPLE_RATE_96: | |
698 | maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL; | |
699 | break; | |
700 | ||
701 | case AUD_SAMPLE_RATE_176_4: | |
702 | maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL; | |
703 | break; | |
704 | ||
705 | case HAD_MAX_RATE: | |
706 | maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL; | |
707 | break; | |
708 | ||
709 | default: | |
710 | maud_val = -EINVAL; | |
711 | break; | |
712 | } | |
713 | } else | |
714 | maud_val = -EINVAL; | |
715 | ||
716 | return maud_val; | |
717 | } | |
718 | ||
76296ef0 | 719 | /* |
44684f61 | 720 | * Program HDMI audio CTS value |
5dab11d8 JA |
721 | * |
722 | * @aud_samp_freq: sampling frequency of audio data | |
723 | * @tmds: sampling frequency of the display data | |
b556290f | 724 | * @link_rate: DP link rate |
5dab11d8 | 725 | * @n_param: N value, depends on aud_samp_freq |
b556290f | 726 | * @intelhaddata: substream private data |
5dab11d8 JA |
727 | * |
728 | * Program CTS register based on the audio and display sampling frequency | |
729 | */ | |
b556290f TI |
730 | static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate, |
731 | u32 n_param, struct snd_intelhad *intelhaddata) | |
5dab11d8 JA |
732 | { |
733 | u32 cts_val; | |
734 | u64 dividend, divisor; | |
735 | ||
964ca808 PLB |
736 | if (intelhaddata->dp_output) { |
737 | /* Substitute cts_val with Maud according to DP 1.2 spec*/ | |
738 | cts_val = had_calculate_maud_value(aud_samp_freq, link_rate); | |
739 | } else { | |
740 | /* Calculate CTS according to HDMI 1.3a spec*/ | |
741 | dividend = (u64)tmds * n_param*1000; | |
742 | divisor = 128 * aud_samp_freq; | |
743 | cts_val = div64_u64(dividend, divisor); | |
744 | } | |
c75b0476 | 745 | dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n", |
964ca808 | 746 | tmds, n_param, cts_val); |
79dda75a | 747 | had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val)); |
5dab11d8 JA |
748 | } |
749 | ||
750 | static int had_calculate_n_value(u32 aud_samp_freq) | |
751 | { | |
2e52f5e5 | 752 | int n_val; |
5dab11d8 JA |
753 | |
754 | /* Select N according to HDMI 1.3a spec*/ | |
755 | switch (aud_samp_freq) { | |
756 | case AUD_SAMPLE_RATE_32: | |
757 | n_val = 4096; | |
2e52f5e5 | 758 | break; |
5dab11d8 JA |
759 | |
760 | case AUD_SAMPLE_RATE_44_1: | |
761 | n_val = 6272; | |
2e52f5e5 | 762 | break; |
5dab11d8 JA |
763 | |
764 | case AUD_SAMPLE_RATE_48: | |
765 | n_val = 6144; | |
2e52f5e5 | 766 | break; |
5dab11d8 JA |
767 | |
768 | case AUD_SAMPLE_RATE_88_2: | |
769 | n_val = 12544; | |
2e52f5e5 | 770 | break; |
5dab11d8 JA |
771 | |
772 | case AUD_SAMPLE_RATE_96: | |
773 | n_val = 12288; | |
2e52f5e5 | 774 | break; |
5dab11d8 JA |
775 | |
776 | case AUD_SAMPLE_RATE_176_4: | |
777 | n_val = 25088; | |
2e52f5e5 | 778 | break; |
5dab11d8 JA |
779 | |
780 | case HAD_MAX_RATE: | |
781 | n_val = 24576; | |
2e52f5e5 | 782 | break; |
5dab11d8 JA |
783 | |
784 | default: | |
785 | n_val = -EINVAL; | |
2e52f5e5 | 786 | break; |
5dab11d8 JA |
787 | } |
788 | return n_val; | |
789 | } | |
790 | ||
76296ef0 | 791 | /* |
44684f61 | 792 | * Program HDMI audio N value |
5dab11d8 JA |
793 | * |
794 | * @aud_samp_freq: sampling frequency of audio data | |
795 | * @n_param: N value, depends on aud_samp_freq | |
b556290f | 796 | * @intelhaddata: substream private data |
5dab11d8 JA |
797 | * |
798 | * This function is called in the prepare callback. | |
799 | * It programs based on the audio and display sampling frequency | |
800 | */ | |
b556290f TI |
801 | static int had_prog_n(u32 aud_samp_freq, u32 *n_param, |
802 | struct snd_intelhad *intelhaddata) | |
5dab11d8 | 803 | { |
2e52f5e5 | 804 | int n_val; |
5dab11d8 | 805 | |
964ca808 PLB |
806 | if (intelhaddata->dp_output) { |
807 | /* | |
808 | * According to DP specs, Maud and Naud values hold | |
809 | * a relationship, which is stated as: | |
810 | * Maud/Naud = 512 * fs / f_LS_Clk | |
811 | * where, fs is the sampling frequency of the audio stream | |
812 | * and Naud is 32768 for Async clock. | |
813 | */ | |
814 | ||
815 | n_val = DP_NAUD_VAL; | |
816 | } else | |
817 | n_val = had_calculate_n_value(aud_samp_freq); | |
5dab11d8 JA |
818 | |
819 | if (n_val < 0) | |
820 | return n_val; | |
821 | ||
79dda75a | 822 | had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val)); |
5dab11d8 JA |
823 | *n_param = n_val; |
824 | return 0; | |
825 | } | |
826 | ||
e1b239f3 TI |
827 | /* |
828 | * PCM ring buffer handling | |
829 | * | |
830 | * The hardware provides a ring buffer with the fixed 4 buffer descriptors | |
831 | * (BDs). The driver maps these 4 BDs onto the PCM ring buffer. The mapping | |
832 | * moves at each period elapsed. The below illustrates how it works: | |
833 | * | |
834 | * At time=0 | |
835 | * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| | |
836 | * BD | 0 | 1 | 2 | 3 | | |
837 | * | |
838 | * At time=1 (period elapsed) | |
839 | * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| | |
840 | * BD | 1 | 2 | 3 | 0 | | |
841 | * | |
842 | * At time=2 (second period elapsed) | |
843 | * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| | |
844 | * BD | 2 | 3 | 0 | 1 | | |
845 | * | |
846 | * The bd_head field points to the index of the BD to be read. It's also the | |
847 | * position to be filled at next. The pcm_head and the pcm_filled fields | |
848 | * point to the indices of the current position and of the next position to | |
849 | * be filled, respectively. For PCM buffer there are both _head and _filled | |
850 | * because they may be difference when nperiods > 4. For example, in the | |
851 | * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5: | |
852 | * | |
853 | * pcm_head (=1) --v v-- pcm_filled (=5) | |
854 | * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| | |
855 | * BD | 1 | 2 | 3 | 0 | | |
856 | * bd_head (=1) --^ ^-- next to fill (= bd_head) | |
857 | * | |
858 | * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that | |
859 | * the hardware skips those BDs in the loop. | |
8d48c016 TI |
860 | * |
861 | * An exceptional setup is the case with nperiods=1. Since we have to update | |
862 | * BDs after finishing one BD processing, we'd need at least two BDs, where | |
863 | * both BDs point to the same content, the same address, the same size of the | |
864 | * whole PCM buffer. | |
e1b239f3 TI |
865 | */ |
866 | ||
867 | #define AUD_BUF_ADDR(x) (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH) | |
868 | #define AUD_BUF_LEN(x) (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH) | |
869 | ||
870 | /* Set up a buffer descriptor at the "filled" position */ | |
871 | static void had_prog_bd(struct snd_pcm_substream *substream, | |
872 | struct snd_intelhad *intelhaddata) | |
873 | { | |
874 | int idx = intelhaddata->bd_head; | |
875 | int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes; | |
876 | u32 addr = substream->runtime->dma_addr + ofs; | |
877 | ||
e8de9859 TI |
878 | addr |= AUD_BUF_VALID; |
879 | if (!substream->runtime->no_period_wakeup) | |
880 | addr |= AUD_BUF_INTR_EN; | |
e1b239f3 TI |
881 | had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr); |
882 | had_write_register(intelhaddata, AUD_BUF_LEN(idx), | |
883 | intelhaddata->period_bytes); | |
884 | ||
885 | /* advance the indices to the next */ | |
886 | intelhaddata->bd_head++; | |
887 | intelhaddata->bd_head %= intelhaddata->num_bds; | |
888 | intelhaddata->pcmbuf_filled++; | |
889 | intelhaddata->pcmbuf_filled %= substream->runtime->periods; | |
890 | } | |
891 | ||
892 | /* invalidate a buffer descriptor with the given index */ | |
893 | static void had_invalidate_bd(struct snd_intelhad *intelhaddata, | |
894 | int idx) | |
895 | { | |
896 | had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0); | |
897 | had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0); | |
898 | } | |
899 | ||
900 | /* Initial programming of ring buffer */ | |
901 | static void had_init_ringbuf(struct snd_pcm_substream *substream, | |
902 | struct snd_intelhad *intelhaddata) | |
903 | { | |
904 | struct snd_pcm_runtime *runtime = substream->runtime; | |
905 | int i, num_periods; | |
906 | ||
907 | num_periods = runtime->periods; | |
908 | intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS); | |
8d48c016 TI |
909 | /* set the minimum 2 BDs for num_periods=1 */ |
910 | intelhaddata->num_bds = max(intelhaddata->num_bds, 2U); | |
e1b239f3 TI |
911 | intelhaddata->period_bytes = |
912 | frames_to_bytes(runtime, runtime->period_size); | |
913 | WARN_ON(intelhaddata->period_bytes & 0x3f); | |
914 | ||
915 | intelhaddata->bd_head = 0; | |
916 | intelhaddata->pcmbuf_head = 0; | |
917 | intelhaddata->pcmbuf_filled = 0; | |
918 | ||
919 | for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) { | |
8d48c016 | 920 | if (i < intelhaddata->num_bds) |
e1b239f3 TI |
921 | had_prog_bd(substream, intelhaddata); |
922 | else /* invalidate the rest */ | |
923 | had_invalidate_bd(intelhaddata, i); | |
924 | } | |
925 | ||
926 | intelhaddata->bd_head = 0; /* reset at head again before starting */ | |
927 | } | |
928 | ||
929 | /* process a bd, advance to the next */ | |
930 | static void had_advance_ringbuf(struct snd_pcm_substream *substream, | |
931 | struct snd_intelhad *intelhaddata) | |
932 | { | |
933 | int num_periods = substream->runtime->periods; | |
934 | ||
935 | /* reprogram the next buffer */ | |
936 | had_prog_bd(substream, intelhaddata); | |
937 | ||
938 | /* proceed to next */ | |
939 | intelhaddata->pcmbuf_head++; | |
940 | intelhaddata->pcmbuf_head %= num_periods; | |
941 | } | |
942 | ||
943 | /* process the current BD(s); | |
944 | * returns the current PCM buffer byte position, or -EPIPE for underrun. | |
945 | */ | |
946 | static int had_process_ringbuf(struct snd_pcm_substream *substream, | |
947 | struct snd_intelhad *intelhaddata) | |
948 | { | |
949 | int len, processed; | |
950 | unsigned long flags; | |
951 | ||
952 | processed = 0; | |
953 | spin_lock_irqsave(&intelhaddata->had_spinlock, flags); | |
954 | for (;;) { | |
955 | /* get the remaining bytes on the buffer */ | |
956 | had_read_register(intelhaddata, | |
957 | AUD_BUF_LEN(intelhaddata->bd_head), | |
958 | &len); | |
959 | if (len < 0 || len > intelhaddata->period_bytes) { | |
960 | dev_dbg(intelhaddata->dev, "Invalid buf length %d\n", | |
961 | len); | |
962 | len = -EPIPE; | |
963 | goto out; | |
964 | } | |
965 | ||
966 | if (len > 0) /* OK, this is the current buffer */ | |
967 | break; | |
968 | ||
969 | /* len=0 => already empty, check the next buffer */ | |
970 | if (++processed >= intelhaddata->num_bds) { | |
971 | len = -EPIPE; /* all empty? - report underrun */ | |
972 | goto out; | |
973 | } | |
974 | had_advance_ringbuf(substream, intelhaddata); | |
975 | } | |
976 | ||
977 | len = intelhaddata->period_bytes - len; | |
978 | len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head; | |
979 | out: | |
980 | spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); | |
981 | return len; | |
982 | } | |
983 | ||
984 | /* called from irq handler */ | |
985 | static void had_process_buffer_done(struct snd_intelhad *intelhaddata) | |
986 | { | |
987 | struct snd_pcm_substream *substream; | |
988 | ||
e1b239f3 TI |
989 | substream = had_substream_get(intelhaddata); |
990 | if (!substream) | |
991 | return; /* no stream? - bail out */ | |
992 | ||
be9a2e93 TI |
993 | if (!intelhaddata->connected) { |
994 | snd_pcm_stop_xrun(substream); | |
995 | goto out; /* disconnected? - bail out */ | |
996 | } | |
997 | ||
e1b239f3 TI |
998 | /* process or stop the stream */ |
999 | if (had_process_ringbuf(substream, intelhaddata) < 0) | |
1000 | snd_pcm_stop_xrun(substream); | |
1001 | else | |
1002 | snd_pcm_period_elapsed(substream); | |
1003 | ||
be9a2e93 | 1004 | out: |
e1b239f3 TI |
1005 | had_substream_put(intelhaddata); |
1006 | } | |
1007 | ||
e1b239f3 TI |
1008 | /* |
1009 | * The interrupt status 'sticky' bits might not be cleared by | |
1010 | * setting '1' to that bit once... | |
1011 | */ | |
1012 | static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata) | |
1013 | { | |
1014 | int i; | |
1015 | u32 val; | |
1016 | ||
e2acecf2 | 1017 | for (i = 0; i < 100; i++) { |
e1b239f3 TI |
1018 | /* clear bit30, 31 AUD_HDMI_STATUS */ |
1019 | had_read_register(intelhaddata, AUD_HDMI_STATUS, &val); | |
77531bee | 1020 | if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN)) |
e1b239f3 | 1021 | return; |
e2acecf2 TI |
1022 | udelay(100); |
1023 | cond_resched(); | |
e1b239f3 TI |
1024 | had_write_register(intelhaddata, AUD_HDMI_STATUS, val); |
1025 | } | |
1026 | dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n"); | |
1027 | } | |
1028 | ||
82a60352 | 1029 | /* Perform some reset procedure after stopping the stream; |
e2acecf2 TI |
1030 | * this is called from prepare or hw_free callbacks once after trigger STOP |
1031 | * or underrun has been processed in order to settle down the h/w state. | |
1032 | */ | |
82a60352 | 1033 | static int had_pcm_sync_stop(struct snd_pcm_substream *substream) |
5dab11d8 | 1034 | { |
82a60352 TI |
1035 | struct snd_intelhad *intelhaddata = snd_pcm_substream_chip(substream); |
1036 | ||
1037 | if (!intelhaddata->connected) | |
1038 | return 0; | |
5dab11d8 | 1039 | |
5dab11d8 | 1040 | /* Reset buffer pointers */ |
f4566aa1 | 1041 | had_reset_audio(intelhaddata); |
e1b239f3 | 1042 | wait_clear_underrun_bit(intelhaddata); |
82a60352 | 1043 | return 0; |
e2acecf2 | 1044 | } |
e1b239f3 | 1045 | |
e2acecf2 TI |
1046 | /* called from irq handler */ |
1047 | static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata) | |
1048 | { | |
1049 | struct snd_pcm_substream *substream; | |
e1b239f3 TI |
1050 | |
1051 | /* Report UNDERRUN error to above layers */ | |
1052 | substream = had_substream_get(intelhaddata); | |
1053 | if (substream) { | |
1054 | snd_pcm_stop_xrun(substream); | |
1055 | had_substream_put(intelhaddata); | |
1056 | } | |
5dab11d8 JA |
1057 | } |
1058 | ||
2e52f5e5 | 1059 | /* |
44684f61 | 1060 | * ALSA PCM open callback |
5dab11d8 | 1061 | */ |
b556290f | 1062 | static int had_pcm_open(struct snd_pcm_substream *substream) |
5dab11d8 JA |
1063 | { |
1064 | struct snd_intelhad *intelhaddata; | |
1065 | struct snd_pcm_runtime *runtime; | |
5dab11d8 JA |
1066 | int retval; |
1067 | ||
5dab11d8 | 1068 | intelhaddata = snd_pcm_substream_chip(substream); |
5dab11d8 JA |
1069 | runtime = substream->runtime; |
1070 | ||
bb30b453 PLB |
1071 | retval = pm_runtime_resume_and_get(intelhaddata->dev); |
1072 | if (retval < 0) | |
1073 | return retval; | |
5dab11d8 | 1074 | |
5dab11d8 | 1075 | /* set the runtime hw parameter with local snd_pcm_hardware struct */ |
b556290f | 1076 | runtime->hw = had_pcm_hardware; |
5dab11d8 | 1077 | |
5dab11d8 JA |
1078 | retval = snd_pcm_hw_constraint_integer(runtime, |
1079 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1080 | if (retval < 0) | |
fa5dfe6a | 1081 | goto error; |
5dab11d8 JA |
1082 | |
1083 | /* Make sure, that the period size is always aligned | |
1084 | * 64byte boundary | |
1085 | */ | |
1086 | retval = snd_pcm_hw_constraint_step(substream->runtime, 0, | |
1087 | SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64); | |
73997b05 | 1088 | if (retval < 0) |
fa5dfe6a | 1089 | goto error; |
5dab11d8 | 1090 | |
85bd8748 TI |
1091 | retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); |
1092 | if (retval < 0) | |
1093 | goto error; | |
1094 | ||
73997b05 | 1095 | /* expose PCM substream */ |
313d9f28 TI |
1096 | spin_lock_irq(&intelhaddata->had_spinlock); |
1097 | intelhaddata->stream_info.substream = substream; | |
1098 | intelhaddata->stream_info.substream_refcount++; | |
1099 | spin_unlock_irq(&intelhaddata->had_spinlock); | |
1100 | ||
5dab11d8 | 1101 | return retval; |
fa5dfe6a | 1102 | error: |
3002b9fb TI |
1103 | pm_runtime_mark_last_busy(intelhaddata->dev); |
1104 | pm_runtime_put_autosuspend(intelhaddata->dev); | |
5dab11d8 JA |
1105 | return retval; |
1106 | } | |
1107 | ||
2e52f5e5 | 1108 | /* |
44684f61 | 1109 | * ALSA PCM close callback |
5dab11d8 | 1110 | */ |
b556290f | 1111 | static int had_pcm_close(struct snd_pcm_substream *substream) |
5dab11d8 JA |
1112 | { |
1113 | struct snd_intelhad *intelhaddata; | |
5dab11d8 | 1114 | |
5dab11d8 | 1115 | intelhaddata = snd_pcm_substream_chip(substream); |
5dab11d8 | 1116 | |
73997b05 | 1117 | /* unreference and sync with the pending PCM accesses */ |
313d9f28 TI |
1118 | spin_lock_irq(&intelhaddata->had_spinlock); |
1119 | intelhaddata->stream_info.substream = NULL; | |
1120 | intelhaddata->stream_info.substream_refcount--; | |
1121 | while (intelhaddata->stream_info.substream_refcount > 0) { | |
1122 | spin_unlock_irq(&intelhaddata->had_spinlock); | |
1123 | cpu_relax(); | |
1124 | spin_lock_irq(&intelhaddata->had_spinlock); | |
1125 | } | |
1126 | spin_unlock_irq(&intelhaddata->had_spinlock); | |
5dab11d8 | 1127 | |
3002b9fb TI |
1128 | pm_runtime_mark_last_busy(intelhaddata->dev); |
1129 | pm_runtime_put_autosuspend(intelhaddata->dev); | |
5dab11d8 JA |
1130 | return 0; |
1131 | } | |
1132 | ||
2e52f5e5 | 1133 | /* |
44684f61 | 1134 | * ALSA PCM hw_params callback |
5dab11d8 | 1135 | */ |
b556290f TI |
1136 | static int had_pcm_hw_params(struct snd_pcm_substream *substream, |
1137 | struct snd_pcm_hw_params *hw_params) | |
5dab11d8 | 1138 | { |
c75b0476 | 1139 | struct snd_intelhad *intelhaddata; |
cc6c6912 | 1140 | int buf_size; |
5dab11d8 | 1141 | |
c75b0476 | 1142 | intelhaddata = snd_pcm_substream_chip(substream); |
5dab11d8 | 1143 | buf_size = params_buffer_bytes(hw_params); |
c75b0476 TI |
1144 | dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n", |
1145 | __func__, buf_size); | |
cc6c6912 | 1146 | return 0; |
5dab11d8 JA |
1147 | } |
1148 | ||
2e52f5e5 | 1149 | /* |
44684f61 | 1150 | * ALSA PCM trigger callback |
5dab11d8 | 1151 | */ |
b556290f | 1152 | static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
5dab11d8 | 1153 | { |
da864809 | 1154 | int retval = 0; |
5dab11d8 | 1155 | struct snd_intelhad *intelhaddata; |
5dab11d8 | 1156 | |
5dab11d8 | 1157 | intelhaddata = snd_pcm_substream_chip(substream); |
5dab11d8 | 1158 | |
df42cb49 | 1159 | spin_lock(&intelhaddata->had_spinlock); |
5dab11d8 JA |
1160 | switch (cmd) { |
1161 | case SNDRV_PCM_TRIGGER_START: | |
182cdf23 TI |
1162 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
1163 | case SNDRV_PCM_TRIGGER_RESUME: | |
5dab11d8 | 1164 | /* Enable Audio */ |
075a1d46 | 1165 | had_ack_irqs(intelhaddata); /* FIXME: do we need this? */ |
40ce4b5d | 1166 | had_enable_audio(intelhaddata, true); |
5dab11d8 JA |
1167 | break; |
1168 | ||
1169 | case SNDRV_PCM_TRIGGER_STOP: | |
182cdf23 | 1170 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
5dab11d8 | 1171 | /* Disable Audio */ |
40ce4b5d | 1172 | had_enable_audio(intelhaddata, false); |
5dab11d8 JA |
1173 | break; |
1174 | ||
1175 | default: | |
1176 | retval = -EINVAL; | |
1177 | } | |
df42cb49 | 1178 | spin_unlock(&intelhaddata->had_spinlock); |
5dab11d8 JA |
1179 | return retval; |
1180 | } | |
1181 | ||
2e52f5e5 | 1182 | /* |
44684f61 | 1183 | * ALSA PCM prepare callback |
5dab11d8 | 1184 | */ |
b556290f | 1185 | static int had_pcm_prepare(struct snd_pcm_substream *substream) |
5dab11d8 JA |
1186 | { |
1187 | int retval; | |
1188 | u32 disp_samp_freq, n_param; | |
964ca808 | 1189 | u32 link_rate = 0; |
5dab11d8 JA |
1190 | struct snd_intelhad *intelhaddata; |
1191 | struct snd_pcm_runtime *runtime; | |
5dab11d8 | 1192 | |
5dab11d8 JA |
1193 | intelhaddata = snd_pcm_substream_chip(substream); |
1194 | runtime = substream->runtime; | |
5dab11d8 | 1195 | |
c75b0476 | 1196 | dev_dbg(intelhaddata->dev, "period_size=%d\n", |
5dab11d8 | 1197 | (int)frames_to_bytes(runtime, runtime->period_size)); |
c75b0476 TI |
1198 | dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods); |
1199 | dev_dbg(intelhaddata->dev, "buffer_size=%d\n", | |
1200 | (int)snd_pcm_lib_buffer_bytes(substream)); | |
1201 | dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate); | |
1202 | dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels); | |
5dab11d8 | 1203 | |
5dab11d8 | 1204 | /* Get N value in KHz */ |
da864809 | 1205 | disp_samp_freq = intelhaddata->tmds_clock_speed; |
5dab11d8 | 1206 | |
b556290f | 1207 | retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); |
5dab11d8 | 1208 | if (retval) { |
c75b0476 TI |
1209 | dev_err(intelhaddata->dev, |
1210 | "programming N value failed %#x\n", retval); | |
5dab11d8 JA |
1211 | goto prep_end; |
1212 | } | |
964ca808 PLB |
1213 | |
1214 | if (intelhaddata->dp_output) | |
da864809 | 1215 | link_rate = intelhaddata->link_rate; |
964ca808 | 1216 | |
b556290f TI |
1217 | had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, |
1218 | n_param, intelhaddata); | |
5dab11d8 | 1219 | |
b556290f | 1220 | had_prog_dip(substream, intelhaddata); |
5dab11d8 | 1221 | |
b556290f | 1222 | retval = had_init_audio_ctrl(substream, intelhaddata); |
5dab11d8 JA |
1223 | |
1224 | /* Prog buffer address */ | |
e1b239f3 | 1225 | had_init_ringbuf(substream, intelhaddata); |
5dab11d8 JA |
1226 | |
1227 | /* | |
1228 | * Program channel mapping in following order: | |
1229 | * FL, FR, C, LFE, RL, RR | |
1230 | */ | |
1231 | ||
79dda75a | 1232 | had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER); |
5dab11d8 JA |
1233 | |
1234 | prep_end: | |
1235 | return retval; | |
1236 | } | |
1237 | ||
2e52f5e5 | 1238 | /* |
44684f61 | 1239 | * ALSA PCM pointer callback |
5dab11d8 | 1240 | */ |
b556290f | 1241 | static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream) |
5dab11d8 JA |
1242 | { |
1243 | struct snd_intelhad *intelhaddata; | |
e1b239f3 | 1244 | int len; |
5dab11d8 | 1245 | |
5dab11d8 JA |
1246 | intelhaddata = snd_pcm_substream_chip(substream); |
1247 | ||
91b0cb0c | 1248 | if (!intelhaddata->connected) |
79f439ea TI |
1249 | return SNDRV_PCM_POS_XRUN; |
1250 | ||
e1b239f3 TI |
1251 | len = had_process_ringbuf(substream, intelhaddata); |
1252 | if (len < 0) | |
1253 | return SNDRV_PCM_POS_XRUN; | |
8d48c016 TI |
1254 | len = bytes_to_frames(substream->runtime, len); |
1255 | /* wrapping may happen when periods=1 */ | |
1256 | len %= substream->runtime->buffer_size; | |
1257 | return len; | |
5dab11d8 JA |
1258 | } |
1259 | ||
73997b05 TI |
1260 | /* |
1261 | * ALSA PCM ops | |
1262 | */ | |
b556290f TI |
1263 | static const struct snd_pcm_ops had_pcm_ops = { |
1264 | .open = had_pcm_open, | |
1265 | .close = had_pcm_close, | |
b556290f | 1266 | .hw_params = had_pcm_hw_params, |
b556290f TI |
1267 | .prepare = had_pcm_prepare, |
1268 | .trigger = had_pcm_trigger, | |
82a60352 | 1269 | .sync_stop = had_pcm_sync_stop, |
b556290f | 1270 | .pointer = had_pcm_pointer, |
73997b05 TI |
1271 | }; |
1272 | ||
8f8d1d7f | 1273 | /* process mode change of the running stream; called in mutex */ |
b556290f | 1274 | static int had_process_mode_change(struct snd_intelhad *intelhaddata) |
5dab11d8 | 1275 | { |
da864809 | 1276 | struct snd_pcm_substream *substream; |
5dab11d8 JA |
1277 | int retval = 0; |
1278 | u32 disp_samp_freq, n_param; | |
964ca808 | 1279 | u32 link_rate = 0; |
5dab11d8 | 1280 | |
313d9f28 TI |
1281 | substream = had_substream_get(intelhaddata); |
1282 | if (!substream) | |
da864809 | 1283 | return 0; |
5dab11d8 JA |
1284 | |
1285 | /* Disable Audio */ | |
40ce4b5d | 1286 | had_enable_audio(intelhaddata, false); |
5dab11d8 JA |
1287 | |
1288 | /* Update CTS value */ | |
da864809 | 1289 | disp_samp_freq = intelhaddata->tmds_clock_speed; |
5dab11d8 | 1290 | |
b556290f | 1291 | retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); |
5dab11d8 | 1292 | if (retval) { |
c75b0476 TI |
1293 | dev_err(intelhaddata->dev, |
1294 | "programming N value failed %#x\n", retval); | |
5dab11d8 JA |
1295 | goto out; |
1296 | } | |
964ca808 PLB |
1297 | |
1298 | if (intelhaddata->dp_output) | |
da864809 | 1299 | link_rate = intelhaddata->link_rate; |
964ca808 | 1300 | |
b556290f TI |
1301 | had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, |
1302 | n_param, intelhaddata); | |
5dab11d8 JA |
1303 | |
1304 | /* Enable Audio */ | |
40ce4b5d | 1305 | had_enable_audio(intelhaddata, true); |
5dab11d8 JA |
1306 | |
1307 | out: | |
313d9f28 | 1308 | had_substream_put(intelhaddata); |
5dab11d8 JA |
1309 | return retval; |
1310 | } | |
1311 | ||
8f8d1d7f | 1312 | /* process hot plug, called from wq with mutex locked */ |
0e9c67d7 | 1313 | static void had_process_hot_plug(struct snd_intelhad *intelhaddata) |
372d855f | 1314 | { |
372d855f | 1315 | struct snd_pcm_substream *substream; |
372d855f | 1316 | |
bcce775c | 1317 | spin_lock_irq(&intelhaddata->had_spinlock); |
91b0cb0c | 1318 | if (intelhaddata->connected) { |
c75b0476 | 1319 | dev_dbg(intelhaddata->dev, "Device already connected\n"); |
bcce775c | 1320 | spin_unlock_irq(&intelhaddata->had_spinlock); |
0e9c67d7 | 1321 | return; |
372d855f | 1322 | } |
0e9c67d7 | 1323 | |
8a2d6ae1 VS |
1324 | /* Disable Audio */ |
1325 | had_enable_audio(intelhaddata, false); | |
1326 | ||
91b0cb0c | 1327 | intelhaddata->connected = true; |
c75b0476 TI |
1328 | dev_dbg(intelhaddata->dev, |
1329 | "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n", | |
372d855f | 1330 | __func__, __LINE__); |
bcce775c | 1331 | spin_unlock_irq(&intelhaddata->had_spinlock); |
372d855f | 1332 | |
2d42c033 TI |
1333 | had_build_channel_allocation_map(intelhaddata); |
1334 | ||
1335 | /* Report to above ALSA layer */ | |
313d9f28 | 1336 | substream = had_substream_get(intelhaddata); |
372d855f | 1337 | if (substream) { |
5def9019 | 1338 | snd_pcm_stop_xrun(substream); |
313d9f28 | 1339 | had_substream_put(intelhaddata); |
372d855f TI |
1340 | } |
1341 | ||
b9bacf27 | 1342 | snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT); |
372d855f TI |
1343 | } |
1344 | ||
8f8d1d7f | 1345 | /* process hot unplug, called from wq with mutex locked */ |
0e9c67d7 | 1346 | static void had_process_hot_unplug(struct snd_intelhad *intelhaddata) |
372d855f | 1347 | { |
313d9f28 | 1348 | struct snd_pcm_substream *substream; |
372d855f | 1349 | |
bcce775c | 1350 | spin_lock_irq(&intelhaddata->had_spinlock); |
91b0cb0c | 1351 | if (!intelhaddata->connected) { |
c75b0476 | 1352 | dev_dbg(intelhaddata->dev, "Device already disconnected\n"); |
bcce775c | 1353 | spin_unlock_irq(&intelhaddata->had_spinlock); |
2d42c033 | 1354 | return; |
372d855f | 1355 | |
372d855f TI |
1356 | } |
1357 | ||
0e9c67d7 | 1358 | /* Disable Audio */ |
40ce4b5d | 1359 | had_enable_audio(intelhaddata, false); |
0e9c67d7 | 1360 | |
91b0cb0c | 1361 | intelhaddata->connected = false; |
c75b0476 TI |
1362 | dev_dbg(intelhaddata->dev, |
1363 | "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n", | |
372d855f | 1364 | __func__, __LINE__); |
313d9f28 | 1365 | spin_unlock_irq(&intelhaddata->had_spinlock); |
372d855f | 1366 | |
2d42c033 TI |
1367 | kfree(intelhaddata->chmap->chmap); |
1368 | intelhaddata->chmap->chmap = NULL; | |
1369 | ||
372d855f | 1370 | /* Report to above ALSA layer */ |
2d42c033 TI |
1371 | substream = had_substream_get(intelhaddata); |
1372 | if (substream) { | |
5def9019 | 1373 | snd_pcm_stop_xrun(substream); |
2d42c033 TI |
1374 | had_substream_put(intelhaddata); |
1375 | } | |
372d855f | 1376 | |
b9bacf27 | 1377 | snd_jack_report(intelhaddata->jack, 0); |
372d855f TI |
1378 | } |
1379 | ||
73997b05 TI |
1380 | /* |
1381 | * ALSA iec958 and ELD controls | |
1382 | */ | |
5dab11d8 | 1383 | |
5dab11d8 JA |
1384 | static int had_iec958_info(struct snd_kcontrol *kcontrol, |
1385 | struct snd_ctl_elem_info *uinfo) | |
1386 | { | |
1387 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1388 | uinfo->count = 1; | |
1389 | return 0; | |
1390 | } | |
1391 | ||
1392 | static int had_iec958_get(struct snd_kcontrol *kcontrol, | |
1393 | struct snd_ctl_elem_value *ucontrol) | |
1394 | { | |
1395 | struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); | |
1396 | ||
8f8d1d7f | 1397 | mutex_lock(&intelhaddata->mutex); |
5dab11d8 JA |
1398 | ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff; |
1399 | ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff; | |
1400 | ucontrol->value.iec958.status[2] = | |
1401 | (intelhaddata->aes_bits >> 16) & 0xff; | |
1402 | ucontrol->value.iec958.status[3] = | |
1403 | (intelhaddata->aes_bits >> 24) & 0xff; | |
8f8d1d7f | 1404 | mutex_unlock(&intelhaddata->mutex); |
5dab11d8 JA |
1405 | return 0; |
1406 | } | |
372d855f | 1407 | |
5dab11d8 JA |
1408 | static int had_iec958_mask_get(struct snd_kcontrol *kcontrol, |
1409 | struct snd_ctl_elem_value *ucontrol) | |
1410 | { | |
1411 | ucontrol->value.iec958.status[0] = 0xff; | |
1412 | ucontrol->value.iec958.status[1] = 0xff; | |
1413 | ucontrol->value.iec958.status[2] = 0xff; | |
1414 | ucontrol->value.iec958.status[3] = 0xff; | |
1415 | return 0; | |
1416 | } | |
372d855f | 1417 | |
5dab11d8 JA |
1418 | static int had_iec958_put(struct snd_kcontrol *kcontrol, |
1419 | struct snd_ctl_elem_value *ucontrol) | |
1420 | { | |
1421 | unsigned int val; | |
1422 | struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); | |
8f8d1d7f | 1423 | int changed = 0; |
5dab11d8 | 1424 | |
5dab11d8 JA |
1425 | val = (ucontrol->value.iec958.status[0] << 0) | |
1426 | (ucontrol->value.iec958.status[1] << 8) | | |
1427 | (ucontrol->value.iec958.status[2] << 16) | | |
1428 | (ucontrol->value.iec958.status[3] << 24); | |
8f8d1d7f | 1429 | mutex_lock(&intelhaddata->mutex); |
5dab11d8 JA |
1430 | if (intelhaddata->aes_bits != val) { |
1431 | intelhaddata->aes_bits = val; | |
8f8d1d7f | 1432 | changed = 1; |
5dab11d8 | 1433 | } |
8f8d1d7f TI |
1434 | mutex_unlock(&intelhaddata->mutex); |
1435 | return changed; | |
5dab11d8 JA |
1436 | } |
1437 | ||
4aedb946 TI |
1438 | static int had_ctl_eld_info(struct snd_kcontrol *kcontrol, |
1439 | struct snd_ctl_elem_info *uinfo) | |
1440 | { | |
1441 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; | |
1442 | uinfo->count = HDMI_MAX_ELD_BYTES; | |
1443 | return 0; | |
1444 | } | |
1445 | ||
1446 | static int had_ctl_eld_get(struct snd_kcontrol *kcontrol, | |
1447 | struct snd_ctl_elem_value *ucontrol) | |
1448 | { | |
1449 | struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); | |
1450 | ||
1451 | mutex_lock(&intelhaddata->mutex); | |
1452 | memcpy(ucontrol->value.bytes.data, intelhaddata->eld, | |
1453 | HDMI_MAX_ELD_BYTES); | |
1454 | mutex_unlock(&intelhaddata->mutex); | |
1455 | return 0; | |
1456 | } | |
5dab11d8 | 1457 | |
73997b05 | 1458 | static const struct snd_kcontrol_new had_controls[] = { |
4aedb946 TI |
1459 | { |
1460 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
1461 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
1462 | .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), | |
1463 | .info = had_iec958_info, /* shared */ | |
1464 | .get = had_iec958_mask_get, | |
1465 | }, | |
1466 | { | |
1467 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
1468 | .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), | |
1469 | .info = had_iec958_info, | |
1470 | .get = had_iec958_get, | |
1471 | .put = had_iec958_put, | |
1472 | }, | |
1473 | { | |
1474 | .access = (SNDRV_CTL_ELEM_ACCESS_READ | | |
1475 | SNDRV_CTL_ELEM_ACCESS_VOLATILE), | |
1476 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
1477 | .name = "ELD", | |
1478 | .info = had_ctl_eld_info, | |
1479 | .get = had_ctl_eld_get, | |
1480 | }, | |
5dab11d8 JA |
1481 | }; |
1482 | ||
73997b05 TI |
1483 | /* |
1484 | * audio interrupt handler | |
1485 | */ | |
da864809 TI |
1486 | static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id) |
1487 | { | |
b4eb0d52 | 1488 | struct snd_intelhad_card *card_ctx = dev_id; |
8a2d6ae1 VS |
1489 | u32 audio_stat[3] = {}; |
1490 | int pipe, port; | |
1491 | ||
1492 | for_each_pipe(card_ctx, pipe) { | |
1493 | /* use raw register access to ack IRQs even while disconnected */ | |
1494 | audio_stat[pipe] = had_read_register_raw(card_ctx, pipe, | |
1495 | AUD_HDMI_STATUS) & | |
1496 | (HDMI_AUDIO_UNDERRUN | HDMI_AUDIO_BUFFER_DONE); | |
1497 | ||
1498 | if (audio_stat[pipe]) | |
1499 | had_write_register_raw(card_ctx, pipe, | |
1500 | AUD_HDMI_STATUS, audio_stat[pipe]); | |
1501 | } | |
da864809 | 1502 | |
b4eb0d52 VS |
1503 | for_each_port(card_ctx, port) { |
1504 | struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; | |
8a2d6ae1 | 1505 | int pipe = ctx->pipe; |
da864809 | 1506 | |
8a2d6ae1 VS |
1507 | if (pipe < 0) |
1508 | continue; | |
da864809 | 1509 | |
8a2d6ae1 | 1510 | if (audio_stat[pipe] & HDMI_AUDIO_BUFFER_DONE) |
b4eb0d52 | 1511 | had_process_buffer_done(ctx); |
8a2d6ae1 VS |
1512 | if (audio_stat[pipe] & HDMI_AUDIO_UNDERRUN) |
1513 | had_process_buffer_underrun(ctx); | |
da864809 TI |
1514 | } |
1515 | ||
1516 | return IRQ_HANDLED; | |
1517 | } | |
1518 | ||
73997b05 TI |
1519 | /* |
1520 | * monitor plug/unplug notification from i915; just kick off the work | |
1521 | */ | |
8a2d6ae1 | 1522 | static void notify_audio_lpe(struct platform_device *pdev, int port) |
da864809 | 1523 | { |
b4eb0d52 | 1524 | struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev); |
7229b12f TI |
1525 | struct snd_intelhad *ctx; |
1526 | ||
1527 | ctx = &card_ctx->pcm_ctx[single_port ? 0 : port]; | |
1528 | if (single_port) | |
1529 | ctx->port = port; | |
da864809 | 1530 | |
99b2ab9d TI |
1531 | schedule_work(&ctx->hdmi_audio_wq); |
1532 | } | |
da864809 | 1533 | |
73997b05 | 1534 | /* the work to handle monitor hot plug/unplug */ |
99b2ab9d TI |
1535 | static void had_audio_wq(struct work_struct *work) |
1536 | { | |
1537 | struct snd_intelhad *ctx = | |
1538 | container_of(work, struct snd_intelhad, hdmi_audio_wq); | |
1539 | struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data; | |
8a2d6ae1 | 1540 | struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port[ctx->port]; |
bb30b453 PLB |
1541 | int ret; |
1542 | ||
1543 | ret = pm_runtime_resume_and_get(ctx->dev); | |
1544 | if (ret < 0) | |
1545 | return; | |
da864809 | 1546 | |
8f8d1d7f | 1547 | mutex_lock(&ctx->mutex); |
a8562e4d | 1548 | if (ppdata->pipe < 0) { |
8a2d6ae1 VS |
1549 | dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG : port = %d\n", |
1550 | __func__, ctx->port); | |
1551 | ||
4aedb946 | 1552 | memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */ |
8a2d6ae1 VS |
1553 | |
1554 | ctx->dp_output = false; | |
1555 | ctx->tmds_clock_speed = 0; | |
1556 | ctx->link_rate = 0; | |
1557 | ||
1558 | /* Shut down the stream */ | |
0e9c67d7 | 1559 | had_process_hot_unplug(ctx); |
da864809 | 1560 | |
8a2d6ae1 | 1561 | ctx->pipe = -1; |
da864809 | 1562 | } else { |
0e9c67d7 | 1563 | dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n", |
8a2d6ae1 | 1564 | __func__, ctx->port, ppdata->ls_clock); |
da864809 | 1565 | |
a8562e4d | 1566 | memcpy(ctx->eld, ppdata->eld, sizeof(ctx->eld)); |
da864809 | 1567 | |
a8562e4d | 1568 | ctx->dp_output = ppdata->dp_output; |
c98ec5ba VS |
1569 | if (ctx->dp_output) { |
1570 | ctx->tmds_clock_speed = 0; | |
a8562e4d | 1571 | ctx->link_rate = ppdata->ls_clock; |
c98ec5ba | 1572 | } else { |
a8562e4d | 1573 | ctx->tmds_clock_speed = ppdata->ls_clock; |
c98ec5ba VS |
1574 | ctx->link_rate = 0; |
1575 | } | |
da864809 | 1576 | |
8a2d6ae1 VS |
1577 | /* |
1578 | * Shut down the stream before we change | |
1579 | * the pipe assignment for this pcm device | |
1580 | */ | |
0e9c67d7 | 1581 | had_process_hot_plug(ctx); |
da864809 | 1582 | |
8a2d6ae1 VS |
1583 | ctx->pipe = ppdata->pipe; |
1584 | ||
1585 | /* Restart the stream if necessary */ | |
b556290f | 1586 | had_process_mode_change(ctx); |
da864809 | 1587 | } |
8a2d6ae1 | 1588 | |
8f8d1d7f | 1589 | mutex_unlock(&ctx->mutex); |
3002b9fb TI |
1590 | pm_runtime_mark_last_busy(ctx->dev); |
1591 | pm_runtime_put_autosuspend(ctx->dev); | |
182cdf23 TI |
1592 | } |
1593 | ||
b9bacf27 TI |
1594 | /* |
1595 | * Jack interface | |
1596 | */ | |
bb4ac5a0 VS |
1597 | static int had_create_jack(struct snd_intelhad *ctx, |
1598 | struct snd_pcm *pcm) | |
b9bacf27 | 1599 | { |
bb4ac5a0 | 1600 | char hdmi_str[32]; |
b9bacf27 TI |
1601 | int err; |
1602 | ||
bb4ac5a0 VS |
1603 | snprintf(hdmi_str, sizeof(hdmi_str), |
1604 | "HDMI/DP,pcm=%d", pcm->device); | |
1605 | ||
b4eb0d52 VS |
1606 | err = snd_jack_new(ctx->card_ctx->card, hdmi_str, |
1607 | SND_JACK_AVOUT, &ctx->jack, | |
b9bacf27 TI |
1608 | true, false); |
1609 | if (err < 0) | |
1610 | return err; | |
1611 | ctx->jack->private_data = ctx; | |
1612 | return 0; | |
1613 | } | |
1614 | ||
182cdf23 TI |
1615 | /* |
1616 | * PM callbacks | |
1617 | */ | |
1618 | ||
0019457e | 1619 | static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev) |
182cdf23 | 1620 | { |
b4eb0d52 | 1621 | struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); |
182cdf23 | 1622 | |
0019457e | 1623 | snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D3hot); |
182cdf23 | 1624 | |
3002b9fb TI |
1625 | return 0; |
1626 | } | |
1627 | ||
1df98924 | 1628 | static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev) |
182cdf23 | 1629 | { |
b4eb0d52 | 1630 | struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); |
182cdf23 | 1631 | |
0019457e VS |
1632 | pm_runtime_mark_last_busy(dev); |
1633 | ||
b4eb0d52 | 1634 | snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D0); |
0019457e | 1635 | |
182cdf23 | 1636 | return 0; |
da864809 TI |
1637 | } |
1638 | ||
1639 | /* release resources */ | |
1640 | static void hdmi_lpe_audio_free(struct snd_card *card) | |
1641 | { | |
b4eb0d52 VS |
1642 | struct snd_intelhad_card *card_ctx = card->private_data; |
1643 | struct intel_hdmi_lpe_audio_pdata *pdata = card_ctx->dev->platform_data; | |
1644 | int port; | |
da864809 | 1645 | |
8d5c3030 VS |
1646 | spin_lock_irq(&pdata->lpe_audio_slock); |
1647 | pdata->notify_audio_lpe = NULL; | |
1648 | spin_unlock_irq(&pdata->lpe_audio_slock); | |
da864809 | 1649 | |
b4eb0d52 VS |
1650 | for_each_port(card_ctx, port) { |
1651 | struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; | |
99b2ab9d | 1652 | |
b4eb0d52 VS |
1653 | cancel_work_sync(&ctx->hdmi_audio_wq); |
1654 | } | |
da864809 TI |
1655 | } |
1656 | ||
79dda75a | 1657 | /* |
da864809 | 1658 | * hdmi_lpe_audio_probe - start bridge with i915 |
5dab11d8 | 1659 | * |
da864809 | 1660 | * This function is called when the i915 driver creates the |
2e52f5e5 | 1661 | * hdmi-lpe-audio platform device. |
5dab11d8 | 1662 | */ |
5e154dfb | 1663 | static int __hdmi_lpe_audio_probe(struct platform_device *pdev) |
5dab11d8 | 1664 | { |
5dab11d8 | 1665 | struct snd_card *card; |
b4eb0d52 | 1666 | struct snd_intelhad_card *card_ctx; |
c77a6edb | 1667 | struct snd_intelhad *ctx; |
da864809 TI |
1668 | struct snd_pcm *pcm; |
1669 | struct intel_hdmi_lpe_audio_pdata *pdata; | |
1670 | int irq; | |
1671 | struct resource *res_mmio; | |
b4eb0d52 | 1672 | int port, ret; |
da864809 | 1673 | |
da864809 TI |
1674 | pdata = pdev->dev.platform_data; |
1675 | if (!pdata) { | |
1676 | dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__); | |
1677 | return -EINVAL; | |
1678 | } | |
5dab11d8 | 1679 | |
da864809 TI |
1680 | /* get resources */ |
1681 | irq = platform_get_irq(pdev, 0); | |
0a671dc5 | 1682 | if (irq < 0) |
1967158f | 1683 | return irq; |
da864809 TI |
1684 | |
1685 | res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1686 | if (!res_mmio) { | |
1687 | dev_err(&pdev->dev, "Could not get IO_MEM resources\n"); | |
1688 | return -ENXIO; | |
1689 | } | |
5dab11d8 | 1690 | |
5647aec2 | 1691 | /* create a card instance with ALSA framework */ |
854577ac TI |
1692 | ret = snd_devm_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id, |
1693 | THIS_MODULE, sizeof(*card_ctx), &card); | |
da864809 TI |
1694 | if (ret) |
1695 | return ret; | |
1696 | ||
b4eb0d52 VS |
1697 | card_ctx = card->private_data; |
1698 | card_ctx->dev = &pdev->dev; | |
1699 | card_ctx->card = card; | |
da864809 | 1700 | strcpy(card->driver, INTEL_HAD); |
873ab035 TI |
1701 | strcpy(card->shortname, "Intel HDMI/DP LPE Audio"); |
1702 | strcpy(card->longname, "Intel HDMI/DP LPE Audio"); | |
da864809 | 1703 | |
b4eb0d52 | 1704 | card_ctx->irq = -1; |
da864809 TI |
1705 | |
1706 | card->private_free = hdmi_lpe_audio_free; | |
1707 | ||
b4eb0d52 | 1708 | platform_set_drvdata(pdev, card_ctx); |
da864809 | 1709 | |
c77a6edb TI |
1710 | card_ctx->num_pipes = pdata->num_pipes; |
1711 | card_ctx->num_ports = single_port ? 1 : pdata->num_ports; | |
1712 | ||
1713 | for_each_port(card_ctx, port) { | |
1714 | ctx = &card_ctx->pcm_ctx[port]; | |
1715 | ctx->card_ctx = card_ctx; | |
1716 | ctx->dev = card_ctx->dev; | |
1717 | ctx->port = single_port ? -1 : port; | |
1718 | ctx->pipe = -1; | |
1719 | ||
1720 | spin_lock_init(&ctx->had_spinlock); | |
1721 | mutex_init(&ctx->mutex); | |
1722 | INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq); | |
1723 | } | |
1724 | ||
da864809 TI |
1725 | dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n", |
1726 | __func__, (unsigned int)res_mmio->start, | |
1727 | (unsigned int)res_mmio->end); | |
1728 | ||
854577ac TI |
1729 | card_ctx->mmio_start = |
1730 | devm_ioremap(&pdev->dev, res_mmio->start, | |
1731 | (size_t)(resource_size(res_mmio))); | |
b4eb0d52 | 1732 | if (!card_ctx->mmio_start) { |
da864809 | 1733 | dev_err(&pdev->dev, "Could not get ioremap\n"); |
854577ac | 1734 | return -EACCES; |
da864809 | 1735 | } |
5dab11d8 | 1736 | |
da864809 | 1737 | /* setup interrupt handler */ |
854577ac TI |
1738 | ret = devm_request_irq(&pdev->dev, irq, display_pipe_interrupt_handler, |
1739 | 0, pdev->name, card_ctx); | |
da864809 TI |
1740 | if (ret < 0) { |
1741 | dev_err(&pdev->dev, "request_irq failed\n"); | |
854577ac | 1742 | return ret; |
da864809 | 1743 | } |
5dab11d8 | 1744 | |
b4eb0d52 | 1745 | card_ctx->irq = irq; |
412bbe7d TI |
1746 | |
1747 | /* only 32bit addressable */ | |
1b1f98dd JJ |
1748 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
1749 | if (ret) | |
1750 | return ret; | |
412bbe7d | 1751 | |
b4eb0d52 | 1752 | init_channel_allocations(); |
5dab11d8 | 1753 | |
8a2d6ae1 | 1754 | card_ctx->num_pipes = pdata->num_pipes; |
7229b12f | 1755 | card_ctx->num_ports = single_port ? 1 : pdata->num_ports; |
bb4ac5a0 | 1756 | |
b4eb0d52 | 1757 | for_each_port(card_ctx, port) { |
b4eb0d52 VS |
1758 | int i; |
1759 | ||
c77a6edb | 1760 | ctx = &card_ctx->pcm_ctx[port]; |
8a2d6ae1 | 1761 | ret = snd_pcm_new(card, INTEL_HAD, port, MAX_PB_STREAMS, |
b4eb0d52 VS |
1762 | MAX_CAP_STREAMS, &pcm); |
1763 | if (ret) | |
854577ac | 1764 | return ret; |
5dab11d8 | 1765 | |
b4eb0d52 VS |
1766 | /* setup private data which can be retrieved when required */ |
1767 | pcm->private_data = ctx; | |
1768 | pcm->info_flags = 0; | |
75b1a8f9 | 1769 | strscpy(pcm->name, card->shortname, strlen(card->shortname)); |
1d7a0395 | 1770 | /* setup the ops for playback */ |
b4eb0d52 | 1771 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops); |
5dab11d8 | 1772 | |
b4eb0d52 VS |
1773 | /* allocate dma pages; |
1774 | * try to allocate 600k buffer as default which is large enough | |
1775 | */ | |
58a95dfa | 1776 | snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_WC, |
cc6c6912 TI |
1777 | card->dev, HAD_DEFAULT_BUFFER, |
1778 | HAD_MAX_BUFFER); | |
b4eb0d52 VS |
1779 | |
1780 | /* create controls */ | |
1781 | for (i = 0; i < ARRAY_SIZE(had_controls); i++) { | |
1782 | struct snd_kcontrol *kctl; | |
1783 | ||
1784 | kctl = snd_ctl_new1(&had_controls[i], ctx); | |
854577ac TI |
1785 | if (!kctl) |
1786 | return -ENOMEM; | |
5dab11d8 | 1787 | |
b4eb0d52 VS |
1788 | kctl->id.device = pcm->device; |
1789 | ||
1790 | ret = snd_ctl_add(card, kctl); | |
1791 | if (ret < 0) | |
854577ac | 1792 | return ret; |
bb4ac5a0 VS |
1793 | } |
1794 | ||
b4eb0d52 VS |
1795 | /* Register channel map controls */ |
1796 | ret = had_register_chmap_ctls(ctx, pcm); | |
1797 | if (ret < 0) | |
854577ac | 1798 | return ret; |
bb4ac5a0 | 1799 | |
b4eb0d52 | 1800 | ret = had_create_jack(ctx, pcm); |
4aedb946 | 1801 | if (ret < 0) |
854577ac | 1802 | return ret; |
4aedb946 | 1803 | } |
b9bacf27 | 1804 | |
da864809 TI |
1805 | ret = snd_card_register(card); |
1806 | if (ret) | |
854577ac | 1807 | return ret; |
36ec0d99 | 1808 | |
bcce775c | 1809 | spin_lock_irq(&pdata->lpe_audio_slock); |
da864809 | 1810 | pdata->notify_audio_lpe = notify_audio_lpe; |
bcce775c | 1811 | spin_unlock_irq(&pdata->lpe_audio_slock); |
da864809 | 1812 | |
e87c65ae | 1813 | pm_runtime_set_autosuspend_delay(&pdev->dev, INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS); |
3002b9fb | 1814 | pm_runtime_use_autosuspend(&pdev->dev); |
e87c65ae | 1815 | pm_runtime_enable(&pdev->dev); |
3002b9fb | 1816 | pm_runtime_mark_last_busy(&pdev->dev); |
e87c65ae | 1817 | pm_runtime_idle(&pdev->dev); |
da864809 | 1818 | |
99b2ab9d | 1819 | dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__); |
b4eb0d52 VS |
1820 | for_each_port(card_ctx, port) { |
1821 | struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; | |
1822 | ||
1823 | schedule_work(&ctx->hdmi_audio_wq); | |
1824 | } | |
5dab11d8 | 1825 | |
79dda75a | 1826 | return 0; |
5dab11d8 JA |
1827 | } |
1828 | ||
5e154dfb TI |
1829 | static int hdmi_lpe_audio_probe(struct platform_device *pdev) |
1830 | { | |
1831 | return snd_card_free_on_error(&pdev->dev, __hdmi_lpe_audio_probe(pdev)); | |
1832 | } | |
1833 | ||
182cdf23 TI |
1834 | static const struct dev_pm_ops hdmi_lpe_audio_pm = { |
1835 | SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume) | |
182cdf23 TI |
1836 | }; |
1837 | ||
da864809 TI |
1838 | static struct platform_driver hdmi_lpe_audio_driver = { |
1839 | .driver = { | |
1840 | .name = "hdmi-lpe-audio", | |
182cdf23 | 1841 | .pm = &hdmi_lpe_audio_pm, |
da864809 TI |
1842 | }, |
1843 | .probe = hdmi_lpe_audio_probe, | |
da864809 TI |
1844 | }; |
1845 | ||
1846 | module_platform_driver(hdmi_lpe_audio_driver); | |
1847 | MODULE_ALIAS("platform:hdmi_lpe_audio"); | |
1848 | ||
5dab11d8 JA |
1849 | MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>"); |
1850 | MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>"); | |
1851 | MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>"); | |
1852 | MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>"); | |
1853 | MODULE_DESCRIPTION("Intel HDMI Audio driver"); | |
1854 | MODULE_LICENSE("GPL v2"); |