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[linux-2.6-block.git] / sound / sparc / cs4231.c
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09c434b8 1// SPDX-License-Identifier: GPL-2.0-only
1da177e4
LT		 2/*
3 * Driver for CS4231 sound chips found on Sparcs.
ae251031 4 * Copyright (C) 2002, 2008 David S. Miller <davem@davemloft.net>
1da177e4
LT		 5 *
6 * Based entirely upon drivers/sbus/audio/cs4231.c which is:
9e9abb4f 7 * Copyright (C) 1996, 1997, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
1da177e4 8 * and also sound/isa/cs423x/cs4231_lib.c which is:
c1017a4c 9 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
1da177e4
LT		 10 */
11
1da177e4
LT		 12#include <linux/module.h>
13#include <linux/kernel.h>
1da177e4
LT		 14#include <linux/delay.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/moduleparam.h>
9e9abb4f
KH		 18#include <linux/irq.h>
19#include <linux/io.h>
ae251031
DM		 20#include <linux/of.h>
21#include <linux/of_device.h>
1da177e4 22
1da177e4
LT		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/info.h>
26#include <sound/control.h>
27#include <sound/timer.h>
28#include <sound/initval.h>
29#include <sound/pcm_params.h>
30
1da177e4
LT		 31#ifdef CONFIG_SBUS
32#define SBUS_SUPPORT
1da177e4
LT		 33#endif
34
35#if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
36#define EBUS_SUPPORT
1da177e4 37#include <linux/pci.h>
aae7fb87 38#include <asm/ebus_dma.h>
1da177e4
LT		 39#endif
40
41static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
42static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
9e9abb4f 43/* Enable this card */
a67ff6a5 44static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
1da177e4
LT		 45
46module_param_array(index, int, NULL, 0444);
47MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
48module_param_array(id, charp, NULL, 0444);
49MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
50module_param_array(enable, bool, NULL, 0444);
51MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
52MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
53MODULE_DESCRIPTION("Sun CS4231");
54MODULE_LICENSE("GPL");
55MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
56
5a820fa7 57#ifdef SBUS_SUPPORT
be9b7e8c 58struct sbus_dma_info {
9e9abb4f
KH		 59 spinlock_t lock; /* DMA access lock */
60 int dir;
61 void __iomem *regs;
be9b7e8c 62};
5a820fa7
GC		 63#endif
64
4f3f2f6f 65struct snd_cs4231;
be9b7e8c 66struct cs4231_dma_control {
9e9abb4f
KH		 67 void (*prepare)(struct cs4231_dma_control *dma_cont,
68 int dir);
69 void (*enable)(struct cs4231_dma_control *dma_cont, int on);
70 int (*request)(struct cs4231_dma_control *dma_cont,
71 dma_addr_t bus_addr, size_t len);
72 unsigned int (*address)(struct cs4231_dma_control *dma_cont);
1da177e4 73#ifdef EBUS_SUPPORT
b128254f 74 struct ebus_dma_info ebus_info;
1da177e4 75#endif
5a820fa7 76#ifdef SBUS_SUPPORT
b128254f 77 struct sbus_dma_info sbus_info;
5a820fa7 78#endif
be9b7e8c 79};
b128254f
GC		 80
81struct snd_cs4231 {
9e9abb4f 82 spinlock_t lock; /* registers access lock */
b128254f
GC		 83 void __iomem *port;
84
be9b7e8c
TI		 85 struct cs4231_dma_control p_dma;
86 struct cs4231_dma_control c_dma;
5a820fa7 87
1da177e4
LT		 88 u32 flags;
89#define CS4231_FLAG_EBUS 0x00000001
90#define CS4231_FLAG_PLAYBACK 0x00000002
91#define CS4231_FLAG_CAPTURE 0x00000004
92
be9b7e8c
TI		 93 struct snd_card *card;
94 struct snd_pcm *pcm;
95 struct snd_pcm_substream *playback_substream;
1da177e4 96 unsigned int p_periods_sent;
be9b7e8c 97 struct snd_pcm_substream *capture_substream;
1da177e4 98 unsigned int c_periods_sent;
be9b7e8c 99 struct snd_timer *timer;
1da177e4
LT		 100
101 unsigned short mode;
102#define CS4231_MODE_NONE 0x0000
103#define CS4231_MODE_PLAY 0x0001
104#define CS4231_MODE_RECORD 0x0002
105#define CS4231_MODE_TIMER 0x0004
9e9abb4f
KH		 106#define CS4231_MODE_OPEN (CS4231_MODE_PLAY | CS4231_MODE_RECORD | \
107 CS4231_MODE_TIMER)
1da177e4
LT		 108
109 unsigned char image[32]; /* registers image */
110 int mce_bit;
111 int calibrate_mute;
9e9abb4f
KH		 112 struct mutex mce_mutex; /* mutex for mce register */
113 struct mutex open_mutex; /* mutex for ALSA open/close */
1da177e4 114
2dc11581 115 struct platform_device *op;
1da177e4
LT		 116 unsigned int irq[2];
117 unsigned int regs_size;
118 struct snd_cs4231 *next;
b128254f 119};
1da177e4 120
1da177e4
LT		 121/* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
122 * now.... -DaveM
123 */
124
125/* IO ports */
7e52f3da 126#include <sound/cs4231-regs.h>
1da177e4
LT		 127
128/* XXX offsets are different than PC ISA chips... */
7e52f3da 129#define CS4231U(chip, x) ((chip)->port + ((c_d_c_CS4231##x) << 2))
1da177e4
LT		 130
131/* SBUS DMA register defines. */
132
133#define APCCSR 0x10UL /* APC DMA CSR */
134#define APCCVA 0x20UL /* APC Capture DMA Address */
135#define APCCC 0x24UL /* APC Capture Count */
136#define APCCNVA 0x28UL /* APC Capture DMA Next Address */
137#define APCCNC 0x2cUL /* APC Capture Next Count */
138#define APCPVA 0x30UL /* APC Play DMA Address */
139#define APCPC 0x34UL /* APC Play Count */
140#define APCPNVA 0x38UL /* APC Play DMA Next Address */
141#define APCPNC 0x3cUL /* APC Play Next Count */
142
5a820fa7
GC		 143/* Defines for SBUS DMA-routines */
144
145#define APCVA 0x0UL /* APC DMA Address */
146#define APCC 0x4UL /* APC Count */
147#define APCNVA 0x8UL /* APC DMA Next Address */
148#define APCNC 0xcUL /* APC Next Count */
149#define APC_PLAY 0x30UL /* Play registers start at 0x30 */
150#define APC_RECORD 0x20UL /* Record registers start at 0x20 */
151
1da177e4
LT		 152/* APCCSR bits */
153
154#define APC_INT_PENDING 0x800000 /* Interrupt Pending */
155#define APC_PLAY_INT 0x400000 /* Playback interrupt */
156#define APC_CAPT_INT 0x200000 /* Capture interrupt */
157#define APC_GENL_INT 0x100000 /* General interrupt */
158#define APC_XINT_ENA 0x80000 /* General ext int. enable */
159#define APC_XINT_PLAY 0x40000 /* Playback ext intr */
160#define APC_XINT_CAPT 0x20000 /* Capture ext intr */
161#define APC_XINT_GENL 0x10000 /* Error ext intr */
162#define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
163#define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
164#define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
165#define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
166#define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
167#define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
168#define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
169#define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
170#define APC_PPAUSE 0x80 /* Pause the play DMA */
171#define APC_CPAUSE 0x40 /* Pause the capture DMA */
172#define APC_CDC_RESET 0x20 /* CODEC RESET */
173#define APC_PDMA_READY 0x08 /* Play DMA Go */
174#define APC_CDMA_READY 0x04 /* Capture DMA Go */
175#define APC_CHIP_RESET 0x01 /* Reset the chip */
176
177/* EBUS DMA register offsets */
178
179#define EBDMA_CSR 0x00UL /* Control/Status */
180#define EBDMA_ADDR 0x04UL /* DMA Address */
181#define EBDMA_COUNT 0x08UL /* DMA Count */
182
183/*
184 * Some variables
185 */
186
187static unsigned char freq_bits[14] = {
188 /* 5510 */ 0x00 | CS4231_XTAL2,
189 /* 6620 */ 0x0E | CS4231_XTAL2,
190 /* 8000 */ 0x00 | CS4231_XTAL1,
191 /* 9600 */ 0x0E | CS4231_XTAL1,
192 /* 11025 */ 0x02 | CS4231_XTAL2,
193 /* 16000 */ 0x02 | CS4231_XTAL1,
194 /* 18900 */ 0x04 | CS4231_XTAL2,
195 /* 22050 */ 0x06 | CS4231_XTAL2,
196 /* 27042 */ 0x04 | CS4231_XTAL1,
197 /* 32000 */ 0x06 | CS4231_XTAL1,
198 /* 33075 */ 0x0C | CS4231_XTAL2,
199 /* 37800 */ 0x08 | CS4231_XTAL2,
200 /* 44100 */ 0x0A | CS4231_XTAL2,
201 /* 48000 */ 0x0C | CS4231_XTAL1
202};
203
4e4b7eaa 204static const unsigned int rates[14] = {
1da177e4
LT		 205 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
206 27042, 32000, 33075, 37800, 44100, 48000
207};
208
4e4b7eaa 209static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
c6c2d57b 210 .count = ARRAY_SIZE(rates),
1da177e4
LT		 211 .list = rates,
212};
213
be9b7e8c 214static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
1da177e4
LT		 215{
216 return snd_pcm_hw_constraint_list(runtime, 0,
217 SNDRV_PCM_HW_PARAM_RATE,
218 &hw_constraints_rates);
219}
220
221static unsigned char snd_cs4231_original_image[32] =
222{
223 0x00, /* 00/00 - lic */
224 0x00, /* 01/01 - ric */
225 0x9f, /* 02/02 - la1ic */
226 0x9f, /* 03/03 - ra1ic */
227 0x9f, /* 04/04 - la2ic */
228 0x9f, /* 05/05 - ra2ic */
229 0xbf, /* 06/06 - loc */
230 0xbf, /* 07/07 - roc */
231 0x20, /* 08/08 - pdfr */
232 CS4231_AUTOCALIB, /* 09/09 - ic */
233 0x00, /* 0a/10 - pc */
234 0x00, /* 0b/11 - ti */
235 CS4231_MODE2, /* 0c/12 - mi */
236 0x00, /* 0d/13 - lbc */
237 0x00, /* 0e/14 - pbru */
238 0x00, /* 0f/15 - pbrl */
239 0x80, /* 10/16 - afei */
240 0x01, /* 11/17 - afeii */
241 0x9f, /* 12/18 - llic */
242 0x9f, /* 13/19 - rlic */
243 0x00, /* 14/20 - tlb */
244 0x00, /* 15/21 - thb */
245 0x00, /* 16/22 - la3mic/reserved */
246 0x00, /* 17/23 - ra3mic/reserved */
247 0x00, /* 18/24 - afs */
248 0x00, /* 19/25 - lamoc/version */
249 0x00, /* 1a/26 - mioc */
250 0x00, /* 1b/27 - ramoc/reserved */
251 0x20, /* 1c/28 - cdfr */
252 0x00, /* 1d/29 - res4 */
253 0x00, /* 1e/30 - cbru */
254 0x00, /* 1f/31 - cbrl */
255};
256
be9b7e8c 257static u8 __cs4231_readb(struct snd_cs4231 *cp, void __iomem *reg_addr)
1da177e4 258{
c6c2d57b 259 if (cp->flags & CS4231_FLAG_EBUS)
1da177e4 260 return readb(reg_addr);
c6c2d57b 261 else
1da177e4 262 return sbus_readb(reg_addr);
1da177e4
LT		 263}
264
9e9abb4f
KH		 265static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val,
266 void __iomem *reg_addr)
1da177e4 267{
c6c2d57b 268 if (cp->flags & CS4231_FLAG_EBUS)
1da177e4 269 return writeb(val, reg_addr);
c6c2d57b 270 else
1da177e4 271 return sbus_writeb(val, reg_addr);
1da177e4
LT		 272}
273
274/*
275 * Basic I/O functions
276 */
277
c6c2d57b 278static void snd_cs4231_ready(struct snd_cs4231 *chip)
1da177e4
LT		 279{
280 int timeout;
1da177e4 281
7e52f3da
KH		 282 for (timeout = 250; timeout > 0; timeout--) {
283 int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
284 if ((val & CS4231_INIT) == 0)
285 break;
286 udelay(100);
287 }
1da177e4
LT		 288}
289
9e9abb4f
KH		 290static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg,
291 unsigned char value)
1da177e4 292{
c6c2d57b 293 snd_cs4231_ready(chip);
a131430c 294#ifdef CONFIG_SND_DEBUG
7e52f3da 295 if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
c6c2d57b
KH		 296 snd_printdd("out: auto calibration time out - reg = 0x%x, "
297 "value = 0x%x\n",
298 reg, value);
a131430c 299#endif
7e52f3da 300 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
c6c2d57b 301 wmb();
7e52f3da 302 __cs4231_writeb(chip, value, CS4231U(chip, REG));
1da177e4
LT		 303 mb();
304}
305
c6c2d57b
KH		 306static inline void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
307 unsigned char mask, unsigned char value)
1da177e4 308{
c6c2d57b 309 unsigned char tmp = (chip->image[reg] & mask) | value;
1da177e4 310
c6c2d57b
KH		 311 chip->image[reg] = tmp;
312 if (!chip->calibrate_mute)
313 snd_cs4231_dout(chip, reg, tmp);
314}
315
316static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg,
317 unsigned char value)
318{
319 snd_cs4231_dout(chip, reg, value);
1da177e4
LT		 320 chip->image[reg] = value;
321 mb();
1da177e4
LT		 322}
323
be9b7e8c 324static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
1da177e4 325{
c6c2d57b 326 snd_cs4231_ready(chip);
1da177e4 327#ifdef CONFIG_SND_DEBUG
7e52f3da 328 if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
c6c2d57b
KH		 329 snd_printdd("in: auto calibration time out - reg = 0x%x\n",
330 reg);
1da177e4 331#endif
7e52f3da 332 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
1da177e4 333 mb();
7e52f3da 334 return __cs4231_readb(chip, CS4231U(chip, REG));
1da177e4
LT		 335}
336
1da177e4
LT		 337/*
338 * CS4231 detection / MCE routines
339 */
340
be9b7e8c 341static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
1da177e4
LT		 342{
343 int timeout;
344
9e9abb4f 345 /* looks like this sequence is proper for CS4231A chip (GUS MAX) */
1da177e4 346 for (timeout = 5; timeout > 0; timeout--)
7e52f3da 347 __cs4231_readb(chip, CS4231U(chip, REGSEL));
a131430c 348
1da177e4 349 /* end of cleanup sequence */
7e52f3da
KH		 350 for (timeout = 500; timeout > 0; timeout--) {
351 int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
352 if ((val & CS4231_INIT) == 0)
353 break;
c6c2d57b 354 msleep(1);
7e52f3da 355 }
1da177e4
LT		 356}
357
be9b7e8c 358static void snd_cs4231_mce_up(struct snd_cs4231 *chip)
1da177e4
LT		 359{
360 unsigned long flags;
361 int timeout;
362
363 spin_lock_irqsave(&chip->lock, flags);
c6c2d57b 364 snd_cs4231_ready(chip);
1da177e4 365#ifdef CONFIG_SND_DEBUG
7e52f3da 366 if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
a131430c 367 snd_printdd("mce_up - auto calibration time out (0)\n");
1da177e4
LT		 368#endif
369 chip->mce_bit |= CS4231_MCE;
7e52f3da 370 timeout = __cs4231_readb(chip, CS4231U(chip, REGSEL));
1da177e4 371 if (timeout == 0x80)
9e9abb4f
KH		 372 snd_printdd("mce_up [%p]: serious init problem - "
373 "codec still busy\n",
374 chip->port);
1da177e4 375 if (!(timeout & CS4231_MCE))
7e52f3da
KH		 376 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f),
377 CS4231U(chip, REGSEL));
1da177e4
LT		 378 spin_unlock_irqrestore(&chip->lock, flags);
379}
380
be9b7e8c 381static void snd_cs4231_mce_down(struct snd_cs4231 *chip)
1da177e4 382{
9823adf6
KH		 383 unsigned long flags, timeout;
384 int reg;
1da177e4 385
1da177e4 386 snd_cs4231_busy_wait(chip);
9823adf6 387 spin_lock_irqsave(&chip->lock, flags);
1da177e4 388#ifdef CONFIG_SND_DEBUG
7e52f3da
KH		 389 if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
390 snd_printdd("mce_down [%p] - auto calibration time out (0)\n",
391 CS4231U(chip, REGSEL));
1da177e4
LT		 392#endif
393 chip->mce_bit &= ~CS4231_MCE;
9823adf6
KH		 394 reg = __cs4231_readb(chip, CS4231U(chip, REGSEL));
395 __cs4231_writeb(chip, chip->mce_bit | (reg & 0x1f),
7e52f3da 396 CS4231U(chip, REGSEL));
9823adf6
KH		 397 if (reg == 0x80)
398 snd_printdd("mce_down [%p]: serious init problem "
399 "- codec still busy\n", chip->port);
400 if ((reg & CS4231_MCE) == 0) {
1da177e4
LT		 401 spin_unlock_irqrestore(&chip->lock, flags);
402 return;
403 }
1da177e4 404
56f91585 405 /*
9823adf6 406 * Wait for auto-calibration (AC) process to finish, i.e. ACI to go low.
56f91585 407 */
9823adf6
KH		 408 timeout = jiffies + msecs_to_jiffies(250);
409 do {
1da177e4 410 spin_unlock_irqrestore(&chip->lock, flags);
b875d650 411 msleep(1);
1da177e4 412 spin_lock_irqsave(&chip->lock, flags);
9823adf6
KH		 413 reg = snd_cs4231_in(chip, CS4231_TEST_INIT);
414 reg &= CS4231_CALIB_IN_PROGRESS;
415 } while (reg && time_before(jiffies, timeout));
1da177e4 416 spin_unlock_irqrestore(&chip->lock, flags);
9823adf6
KH		 417
418 if (reg)
419 snd_printk(KERN_ERR
420 "mce_down - auto calibration time out (2)\n");
1da177e4
LT		 421}
422
be9b7e8c
TI		 423static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont,
424 struct snd_pcm_substream *substream,
425 unsigned int *periods_sent)
1da177e4 426{
be9b7e8c 427 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 428
429 while (1) {
a131430c
CZ		 430 unsigned int period_size = snd_pcm_lib_period_bytes(substream);
431 unsigned int offset = period_size * (*periods_sent);
1da177e4 432
5a19b178
TI		 433 if (WARN_ON(period_size >= (1 << 24)))
434 return;
1da177e4 435
9e9abb4f
KH		 436 if (dma_cont->request(dma_cont,
437 runtime->dma_addr + offset, period_size))
1da177e4 438 return;
1da177e4
LT		 439 (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
440 }
441}
a131430c 442
be9b7e8c
TI		 443static void cs4231_dma_trigger(struct snd_pcm_substream *substream,
444 unsigned int what, int on)
1da177e4 445{
be9b7e8c
TI		 446 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
447 struct cs4231_dma_control *dma_cont;
a131430c 448
5a820fa7 449 if (what & CS4231_PLAYBACK_ENABLE) {
b128254f 450 dma_cont = &chip->p_dma;
a131430c 451 if (on) {
b128254f
GC		 452 dma_cont->prepare(dma_cont, 0);
453 dma_cont->enable(dma_cont, 1);
454 snd_cs4231_advance_dma(dma_cont,
5a820fa7
GC		 455 chip->playback_substream,
456 &chip->p_periods_sent);
a131430c 457 } else {
b128254f 458 dma_cont->enable(dma_cont, 0);
a131430c 459 }
5a820fa7
GC		 460 }
461 if (what & CS4231_RECORD_ENABLE) {
b128254f 462 dma_cont = &chip->c_dma;
a131430c 463 if (on) {
b128254f
GC		 464 dma_cont->prepare(dma_cont, 1);
465 dma_cont->enable(dma_cont, 1);
466 snd_cs4231_advance_dma(dma_cont,
5a820fa7
GC		 467 chip->capture_substream,
468 &chip->c_periods_sent);
a131430c 469 } else {
b128254f 470 dma_cont->enable(dma_cont, 0);
a131430c 471 }
a131430c 472 }
1da177e4
LT		 473}
474
be9b7e8c 475static int snd_cs4231_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 476{
be9b7e8c 477 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 478 int result = 0;
479
480 switch (cmd) {
481 case SNDRV_PCM_TRIGGER_START:
482 case SNDRV_PCM_TRIGGER_STOP:
483 {
484 unsigned int what = 0;
be9b7e8c 485 struct snd_pcm_substream *s;
1da177e4
LT		 486 unsigned long flags;
487
ef991b95 488 snd_pcm_group_for_each_entry(s, substream) {
1da177e4
LT		 489 if (s == chip->playback_substream) {
490 what |= CS4231_PLAYBACK_ENABLE;
491 snd_pcm_trigger_done(s, substream);
492 } else if (s == chip->capture_substream) {
493 what |= CS4231_RECORD_ENABLE;
494 snd_pcm_trigger_done(s, substream);
495 }
496 }
497
1da177e4
LT		 498 spin_lock_irqsave(&chip->lock, flags);
499 if (cmd == SNDRV_PCM_TRIGGER_START) {
a131430c 500 cs4231_dma_trigger(substream, what, 1);
1da177e4 501 chip->image[CS4231_IFACE_CTRL] |= what;
1da177e4 502 } else {
a131430c 503 cs4231_dma_trigger(substream, what, 0);
1da177e4
LT		 504 chip->image[CS4231_IFACE_CTRL] &= ~what;
505 }
506 snd_cs4231_out(chip, CS4231_IFACE_CTRL,
507 chip->image[CS4231_IFACE_CTRL]);
508 spin_unlock_irqrestore(&chip->lock, flags);
509 break;
510 }
511 default:
512 result = -EINVAL;
513 break;
514 }
a131430c 515
1da177e4
LT		 516 return result;
517}
518
519/*
520 * CODEC I/O
521 */
522
523static unsigned char snd_cs4231_get_rate(unsigned int rate)
524{
525 int i;
526
527 for (i = 0; i < 14; i++)
528 if (rate == rates[i])
529 return freq_bits[i];
9e9abb4f 530
1da177e4
LT		 531 return freq_bits[13];
532}
533
9e9abb4f
KH		 534static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, int format,
535 int channels)
1da177e4
LT		 536{
537 unsigned char rformat;
538
539 rformat = CS4231_LINEAR_8;
540 switch (format) {
9e9abb4f
KH		 541 case SNDRV_PCM_FORMAT_MU_LAW:
542 rformat = CS4231_ULAW_8;
543 break;
544 case SNDRV_PCM_FORMAT_A_LAW:
545 rformat = CS4231_ALAW_8;
546 break;
547 case SNDRV_PCM_FORMAT_S16_LE:
548 rformat = CS4231_LINEAR_16;
549 break;
550 case SNDRV_PCM_FORMAT_S16_BE:
551 rformat = CS4231_LINEAR_16_BIG;
552 break;
553 case SNDRV_PCM_FORMAT_IMA_ADPCM:
554 rformat = CS4231_ADPCM_16;
555 break;
1da177e4
LT		 556 }
557 if (channels > 1)
558 rformat |= CS4231_STEREO;
1da177e4
LT		 559 return rformat;
560}
561
be9b7e8c 562static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
1da177e4
LT		 563{
564 unsigned long flags;
565
566 mute = mute ? 1 : 0;
567 spin_lock_irqsave(&chip->lock, flags);
568 if (chip->calibrate_mute == mute) {
569 spin_unlock_irqrestore(&chip->lock, flags);
570 return;
571 }
572 if (!mute) {
573 snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
574 chip->image[CS4231_LEFT_INPUT]);
575 snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
576 chip->image[CS4231_RIGHT_INPUT]);
577 snd_cs4231_dout(chip, CS4231_LOOPBACK,
578 chip->image[CS4231_LOOPBACK]);
579 }
580 snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
581 mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
582 snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
583 mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
584 snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
585 mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
586 snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
587 mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
588 snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
589 mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
590 snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
591 mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
592 snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
593 mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
594 snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
595 mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
596 snd_cs4231_dout(chip, CS4231_MONO_CTRL,
597 mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
598 chip->calibrate_mute = mute;
599 spin_unlock_irqrestore(&chip->lock, flags);
600}
601
9e9abb4f
KH		 602static void snd_cs4231_playback_format(struct snd_cs4231 *chip,
603 struct snd_pcm_hw_params *params,
1da177e4
LT		 604 unsigned char pdfr)
605{
606 unsigned long flags;
607
12aa7579 608 mutex_lock(&chip->mce_mutex);
1da177e4
LT		 609 snd_cs4231_calibrate_mute(chip, 1);
610
611 snd_cs4231_mce_up(chip);
612
613 spin_lock_irqsave(&chip->lock, flags);
614 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
615 (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
616 (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
617 pdfr);
618 spin_unlock_irqrestore(&chip->lock, flags);
619
620 snd_cs4231_mce_down(chip);
621
622 snd_cs4231_calibrate_mute(chip, 0);
12aa7579 623 mutex_unlock(&chip->mce_mutex);
1da177e4
LT		 624}
625
9e9abb4f
KH		 626static void snd_cs4231_capture_format(struct snd_cs4231 *chip,
627 struct snd_pcm_hw_params *params,
628 unsigned char cdfr)
1da177e4
LT		 629{
630 unsigned long flags;
631
12aa7579 632 mutex_lock(&chip->mce_mutex);
1da177e4
LT		 633 snd_cs4231_calibrate_mute(chip, 1);
634
635 snd_cs4231_mce_up(chip);
636
637 spin_lock_irqsave(&chip->lock, flags);
638 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
639 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
640 ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
641 (cdfr & 0x0f));
642 spin_unlock_irqrestore(&chip->lock, flags);
643 snd_cs4231_mce_down(chip);
644 snd_cs4231_mce_up(chip);
645 spin_lock_irqsave(&chip->lock, flags);
646 }
647 snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
648 spin_unlock_irqrestore(&chip->lock, flags);
649
650 snd_cs4231_mce_down(chip);
651
652 snd_cs4231_calibrate_mute(chip, 0);
12aa7579 653 mutex_unlock(&chip->mce_mutex);
1da177e4
LT		 654}
655
656/*
657 * Timer interface
658 */
659
be9b7e8c 660static unsigned long snd_cs4231_timer_resolution(struct snd_timer *timer)
1da177e4 661{
be9b7e8c 662 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 663
664 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
665}
666
be9b7e8c 667static int snd_cs4231_timer_start(struct snd_timer *timer)
1da177e4
LT		 668{
669 unsigned long flags;
670 unsigned int ticks;
be9b7e8c 671 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 672
673 spin_lock_irqsave(&chip->lock, flags);
674 ticks = timer->sticks;
675 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
676 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
677 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
678 snd_cs4231_out(chip, CS4231_TIMER_HIGH,
679 chip->image[CS4231_TIMER_HIGH] =
680 (unsigned char) (ticks >> 8));
681 snd_cs4231_out(chip, CS4231_TIMER_LOW,
682 chip->image[CS4231_TIMER_LOW] =
683 (unsigned char) ticks);
684 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
9e9abb4f
KH		 685 chip->image[CS4231_ALT_FEATURE_1] |
686 CS4231_TIMER_ENABLE);
1da177e4
LT		 687 }
688 spin_unlock_irqrestore(&chip->lock, flags);
689
690 return 0;
691}
692
be9b7e8c 693static int snd_cs4231_timer_stop(struct snd_timer *timer)
1da177e4
LT		 694{
695 unsigned long flags;
be9b7e8c 696 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 697
698 spin_lock_irqsave(&chip->lock, flags);
9e9abb4f 699 chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
1da177e4 700 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
9e9abb4f 701 chip->image[CS4231_ALT_FEATURE_1]);
1da177e4
LT		 702 spin_unlock_irqrestore(&chip->lock, flags);
703
704 return 0;
705}
706
32e02a7b 707static void snd_cs4231_init(struct snd_cs4231 *chip)
1da177e4
LT		 708{
709 unsigned long flags;
710
711 snd_cs4231_mce_down(chip);
712
713#ifdef SNDRV_DEBUG_MCE
a131430c 714 snd_printdd("init: (1)\n");
1da177e4
LT		 715#endif
716 snd_cs4231_mce_up(chip);
717 spin_lock_irqsave(&chip->lock, flags);
9e9abb4f
KH		 718 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
719 CS4231_PLAYBACK_PIO |
720 CS4231_RECORD_ENABLE |
721 CS4231_RECORD_PIO |
1da177e4
LT		 722 CS4231_CALIB_MODE);
723 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
724 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
725 spin_unlock_irqrestore(&chip->lock, flags);
726 snd_cs4231_mce_down(chip);
727
728#ifdef SNDRV_DEBUG_MCE
a131430c 729 snd_printdd("init: (2)\n");
1da177e4
LT		 730#endif
731
732 snd_cs4231_mce_up(chip);
733 spin_lock_irqsave(&chip->lock, flags);
9e9abb4f
KH		 734 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
735 chip->image[CS4231_ALT_FEATURE_1]);
1da177e4
LT		 736 spin_unlock_irqrestore(&chip->lock, flags);
737 snd_cs4231_mce_down(chip);
738
739#ifdef SNDRV_DEBUG_MCE
9e9abb4f
KH		 740 snd_printdd("init: (3) - afei = 0x%x\n",
741 chip->image[CS4231_ALT_FEATURE_1]);
1da177e4
LT		 742#endif
743
744 spin_lock_irqsave(&chip->lock, flags);
9e9abb4f
KH		 745 snd_cs4231_out(chip, CS4231_ALT_FEATURE_2,
746 chip->image[CS4231_ALT_FEATURE_2]);
1da177e4
LT		 747 spin_unlock_irqrestore(&chip->lock, flags);
748
749 snd_cs4231_mce_up(chip);
750 spin_lock_irqsave(&chip->lock, flags);
9e9abb4f
KH		 751 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
752 chip->image[CS4231_PLAYBK_FORMAT]);
1da177e4
LT		 753 spin_unlock_irqrestore(&chip->lock, flags);
754 snd_cs4231_mce_down(chip);
755
756#ifdef SNDRV_DEBUG_MCE
a131430c 757 snd_printdd("init: (4)\n");
1da177e4
LT		 758#endif
759
760 snd_cs4231_mce_up(chip);
761 spin_lock_irqsave(&chip->lock, flags);
762 snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
763 spin_unlock_irqrestore(&chip->lock, flags);
764 snd_cs4231_mce_down(chip);
765
766#ifdef SNDRV_DEBUG_MCE
a131430c 767 snd_printdd("init: (5)\n");
1da177e4
LT		 768#endif
769}
770
be9b7e8c 771static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
1da177e4
LT		 772{
773 unsigned long flags;
774
12aa7579 775 mutex_lock(&chip->open_mutex);
1da177e4 776 if ((chip->mode & mode)) {
12aa7579 777 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 778 return -EAGAIN;
779 }
780 if (chip->mode & CS4231_MODE_OPEN) {
781 chip->mode |= mode;
12aa7579 782 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 783 return 0;
784 }
785 /* ok. now enable and ack CODEC IRQ */
786 spin_lock_irqsave(&chip->lock, flags);
787 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
788 CS4231_RECORD_IRQ |
789 CS4231_TIMER_IRQ);
790 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
7e52f3da
KH		 791 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
792 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
1da177e4
LT		 793
794 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
795 CS4231_RECORD_IRQ |
796 CS4231_TIMER_IRQ);
797 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
a131430c 798
1da177e4
LT		 799 spin_unlock_irqrestore(&chip->lock, flags);
800
801 chip->mode = mode;
12aa7579 802 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 803 return 0;
804}
805
be9b7e8c 806static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
1da177e4
LT		 807{
808 unsigned long flags;
809
12aa7579 810 mutex_lock(&chip->open_mutex);
1da177e4
LT		 811 chip->mode &= ~mode;
812 if (chip->mode & CS4231_MODE_OPEN) {
12aa7579 813 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 814 return;
815 }
816 snd_cs4231_calibrate_mute(chip, 1);
817
818 /* disable IRQ */
819 spin_lock_irqsave(&chip->lock, flags);
820 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
7e52f3da
KH		 821 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
822 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
1da177e4
LT		 823
824 /* now disable record & playback */
825
826 if (chip->image[CS4231_IFACE_CTRL] &
827 (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
828 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
829 spin_unlock_irqrestore(&chip->lock, flags);
830 snd_cs4231_mce_up(chip);
831 spin_lock_irqsave(&chip->lock, flags);
832 chip->image[CS4231_IFACE_CTRL] &=
833 ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
834 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
9e9abb4f
KH		 835 snd_cs4231_out(chip, CS4231_IFACE_CTRL,
836 chip->image[CS4231_IFACE_CTRL]);
1da177e4
LT		 837 spin_unlock_irqrestore(&chip->lock, flags);
838 snd_cs4231_mce_down(chip);
839 spin_lock_irqsave(&chip->lock, flags);
840 }
841
842 /* clear IRQ again */
843 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
7e52f3da
KH		 844 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
845 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
1da177e4
LT		 846 spin_unlock_irqrestore(&chip->lock, flags);
847
848 snd_cs4231_calibrate_mute(chip, 0);
849
850 chip->mode = 0;
12aa7579 851 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 852}
853
854/*
855 * timer open/close
856 */
857
be9b7e8c 858static int snd_cs4231_timer_open(struct snd_timer *timer)
1da177e4 859{
be9b7e8c 860 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 861 snd_cs4231_open(chip, CS4231_MODE_TIMER);
862 return 0;
863}
864
9e9abb4f 865static int snd_cs4231_timer_close(struct snd_timer *timer)
1da177e4 866{
be9b7e8c 867 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 868 snd_cs4231_close(chip, CS4231_MODE_TIMER);
869 return 0;
870}
871
9e9abb4f 872static struct snd_timer_hardware snd_cs4231_timer_table = {
1da177e4
LT		 873 .flags = SNDRV_TIMER_HW_AUTO,
874 .resolution = 9945,
875 .ticks = 65535,
876 .open = snd_cs4231_timer_open,
877 .close = snd_cs4231_timer_close,
878 .c_resolution = snd_cs4231_timer_resolution,
879 .start = snd_cs4231_timer_start,
880 .stop = snd_cs4231_timer_stop,
881};
882
883/*
884 * ok.. exported functions..
885 */
886
be9b7e8c
TI		 887static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
888 struct snd_pcm_hw_params *hw_params)
1da177e4 889{
be9b7e8c 890 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 891 unsigned char new_pdfr;
892 int err;
893
9e9abb4f
KH		 894 err = snd_pcm_lib_malloc_pages(substream,
895 params_buffer_bytes(hw_params));
896 if (err < 0)
1da177e4
LT		 897 return err;
898 new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
899 params_channels(hw_params)) |
900 snd_cs4231_get_rate(params_rate(hw_params));
901 snd_cs4231_playback_format(chip, hw_params, new_pdfr);
902
903 return 0;
904}
905
be9b7e8c 906static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 907{
be9b7e8c
TI		 908 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
909 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 910 unsigned long flags;
a522409e 911 int ret = 0;
1da177e4
LT		 912
913 spin_lock_irqsave(&chip->lock, flags);
a131430c 914
1da177e4
LT		 915 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
916 CS4231_PLAYBACK_PIO);
a131430c 917
a522409e
WY		 918 if (WARN_ON(runtime->period_size > 0xffff + 1)) {
919 ret = -EINVAL;
920 goto out;
921 }
a131430c 922
a131430c 923 chip->p_periods_sent = 0;
a522409e
WY		 924
925out:
1da177e4
LT		 926 spin_unlock_irqrestore(&chip->lock, flags);
927
a522409e 928 return ret;
1da177e4
LT		 929}
930
be9b7e8c
TI		 931static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
932 struct snd_pcm_hw_params *hw_params)
1da177e4 933{
be9b7e8c 934 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 935 unsigned char new_cdfr;
936 int err;
937
9e9abb4f
KH		 938 err = snd_pcm_lib_malloc_pages(substream,
939 params_buffer_bytes(hw_params));
940 if (err < 0)
1da177e4
LT		 941 return err;
942 new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
943 params_channels(hw_params)) |
944 snd_cs4231_get_rate(params_rate(hw_params));
945 snd_cs4231_capture_format(chip, hw_params, new_cdfr);
946
947 return 0;
948}
949
be9b7e8c 950static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 951{
be9b7e8c 952 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 953 unsigned long flags;
954
955 spin_lock_irqsave(&chip->lock, flags);
956 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
957 CS4231_RECORD_PIO);
958
a131430c 959
5a820fa7 960 chip->c_periods_sent = 0;
1da177e4
LT		 961 spin_unlock_irqrestore(&chip->lock, flags);
962
963 return 0;
964}
965
be9b7e8c 966static void snd_cs4231_overrange(struct snd_cs4231 *chip)
1da177e4
LT		 967{
968 unsigned long flags;
969 unsigned char res;
970
971 spin_lock_irqsave(&chip->lock, flags);
972 res = snd_cs4231_in(chip, CS4231_TEST_INIT);
973 spin_unlock_irqrestore(&chip->lock, flags);
974
9e9abb4f
KH		 975 /* detect overrange only above 0dB; may be user selectable? */
976 if (res & (0x08 | 0x02))
1da177e4
LT		 977 chip->capture_substream->runtime->overrange++;
978}
979
be9b7e8c 980static void snd_cs4231_play_callback(struct snd_cs4231 *chip)
1da177e4 981{
1da177e4
LT		 982 if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
983 snd_pcm_period_elapsed(chip->playback_substream);
b128254f 984 snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream,
1da177e4
LT		 985 &chip->p_periods_sent);
986 }
987}
988
be9b7e8c 989static void snd_cs4231_capture_callback(struct snd_cs4231 *chip)
1da177e4 990{
1da177e4
LT		 991 if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
992 snd_pcm_period_elapsed(chip->capture_substream);
b128254f 993 snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream,
1da177e4
LT		 994 &chip->c_periods_sent);
995 }
996}
1da177e4 997
9e9abb4f
KH		 998static snd_pcm_uframes_t snd_cs4231_playback_pointer(
999 struct snd_pcm_substream *substream)
1da177e4 1000{
be9b7e8c
TI		 1001 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1002 struct cs4231_dma_control *dma_cont = &chip->p_dma;
5a820fa7 1003 size_t ptr;
9e9abb4f 1004
1da177e4
LT		 1005 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
1006 return 0;
b128254f
GC		 1007 ptr = dma_cont->address(dma_cont);
1008 if (ptr != 0)
1009 ptr -= substream->runtime->dma_addr;
9e9abb4f 1010
1da177e4
LT		 1011 return bytes_to_frames(substream->runtime, ptr);
1012}
1013
9e9abb4f
KH		 1014static snd_pcm_uframes_t snd_cs4231_capture_pointer(
1015 struct snd_pcm_substream *substream)
1da177e4 1016{
be9b7e8c
TI		 1017 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1018 struct cs4231_dma_control *dma_cont = &chip->c_dma;
5a820fa7 1019 size_t ptr;
9e9abb4f 1020
1da177e4
LT		 1021 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
1022 return 0;
b128254f
GC		 1023 ptr = dma_cont->address(dma_cont);
1024 if (ptr != 0)
1025 ptr -= substream->runtime->dma_addr;
9e9abb4f 1026
1da177e4
LT		 1027 return bytes_to_frames(substream->runtime, ptr);
1028}
1029
32e02a7b 1030static int snd_cs4231_probe(struct snd_cs4231 *chip)
1da177e4
LT		 1031{
1032 unsigned long flags;
9e9abb4f
KH		 1033 int i;
1034 int id = 0;
1035 int vers = 0;
1da177e4
LT		 1036 unsigned char *ptr;
1037
1da177e4
LT		 1038 for (i = 0; i < 50; i++) {
1039 mb();
7e52f3da 1040 if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
9e9abb4f 1041 msleep(2);
1da177e4
LT		 1042 else {
1043 spin_lock_irqsave(&chip->lock, flags);
1044 snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
1045 id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
1046 vers = snd_cs4231_in(chip, CS4231_VERSION);
1047 spin_unlock_irqrestore(&chip->lock, flags);
1048 if (id == 0x0a)
1049 break; /* this is valid value */
1050 }
1051 }
1052 snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id);
1053 if (id != 0x0a)
1054 return -ENODEV; /* no valid device found */
1055
1056 spin_lock_irqsave(&chip->lock, flags);
1057
7e52f3da
KH		 1058 /* clear any pendings IRQ */
1059 __cs4231_readb(chip, CS4231U(chip, STATUS));
1060 __cs4231_writeb(chip, 0, CS4231U(chip, STATUS));
1da177e4
LT		 1061 mb();
1062
1063 spin_unlock_irqrestore(&chip->lock, flags);
1064
1065 chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
1066 chip->image[CS4231_IFACE_CTRL] =
1067 chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
1068 chip->image[CS4231_ALT_FEATURE_1] = 0x80;
1069 chip->image[CS4231_ALT_FEATURE_2] = 0x01;
1070 if (vers & 0x20)
1071 chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
1072
1073 ptr = (unsigned char *) &chip->image;
1074
1075 snd_cs4231_mce_down(chip);
1076
1077 spin_lock_irqsave(&chip->lock, flags);
1078
1079 for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
1080 snd_cs4231_out(chip, i, *ptr++);
1081
1082 spin_unlock_irqrestore(&chip->lock, flags);
1083
1084 snd_cs4231_mce_up(chip);
1085
1086 snd_cs4231_mce_down(chip);
1087
1088 mdelay(2);
1089
1090 return 0; /* all things are ok.. */
1091}
1092
688ed206 1093static const struct snd_pcm_hardware snd_cs4231_playback = {
9e9abb4f
KH		 1094 .info = SNDRV_PCM_INFO_MMAP |
1095 SNDRV_PCM_INFO_INTERLEAVED |
1096 SNDRV_PCM_INFO_MMAP_VALID |
1097 SNDRV_PCM_INFO_SYNC_START,
1098 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1099 SNDRV_PCM_FMTBIT_A_LAW |
1100 SNDRV_PCM_FMTBIT_IMA_ADPCM |
1101 SNDRV_PCM_FMTBIT_U8 |
1102 SNDRV_PCM_FMTBIT_S16_LE |
1103 SNDRV_PCM_FMTBIT_S16_BE,
1104 .rates = SNDRV_PCM_RATE_KNOT |
1105 SNDRV_PCM_RATE_8000_48000,
1da177e4
LT		 1106 .rate_min = 5510,
1107 .rate_max = 48000,
1108 .channels_min = 1,
1109 .channels_max = 2,
9e9abb4f 1110 .buffer_bytes_max = 32 * 1024,
f9af1d9d 1111 .period_bytes_min = 64,
9e9abb4f 1112 .period_bytes_max = 32 * 1024,
1da177e4
LT		 1113 .periods_min = 1,
1114 .periods_max = 1024,
1115};
1116
688ed206 1117static const struct snd_pcm_hardware snd_cs4231_capture = {
9e9abb4f
KH		 1118 .info = SNDRV_PCM_INFO_MMAP |
1119 SNDRV_PCM_INFO_INTERLEAVED |
1120 SNDRV_PCM_INFO_MMAP_VALID |
1121 SNDRV_PCM_INFO_SYNC_START,
1122 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1123 SNDRV_PCM_FMTBIT_A_LAW |
1124 SNDRV_PCM_FMTBIT_IMA_ADPCM |
1125 SNDRV_PCM_FMTBIT_U8 |
1126 SNDRV_PCM_FMTBIT_S16_LE |
1127 SNDRV_PCM_FMTBIT_S16_BE,
1128 .rates = SNDRV_PCM_RATE_KNOT |
1129 SNDRV_PCM_RATE_8000_48000,
1da177e4
LT		 1130 .rate_min = 5510,
1131 .rate_max = 48000,
1132 .channels_min = 1,
1133 .channels_max = 2,
9e9abb4f 1134 .buffer_bytes_max = 32 * 1024,
f9af1d9d 1135 .period_bytes_min = 64,
9e9abb4f 1136 .period_bytes_max = 32 * 1024,
1da177e4
LT		 1137 .periods_min = 1,
1138 .periods_max = 1024,
1139};
1140
be9b7e8c 1141static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
1da177e4 1142{
be9b7e8c
TI		 1143 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1144 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1145 int err;
1146
1147 runtime->hw = snd_cs4231_playback;
1148
9e9abb4f 1149 err = snd_cs4231_open(chip, CS4231_MODE_PLAY);
9a20332a 1150 if (err < 0)
1da177e4 1151 return err;
1da177e4
LT		 1152 chip->playback_substream = substream;
1153 chip->p_periods_sent = 0;
1154 snd_pcm_set_sync(substream);
1155 snd_cs4231_xrate(runtime);
1156
1157 return 0;
1158}
1159
be9b7e8c 1160static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
1da177e4 1161{
be9b7e8c
TI		 1162 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1163 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1164 int err;
1165
1166 runtime->hw = snd_cs4231_capture;
1167
9e9abb4f 1168 err = snd_cs4231_open(chip, CS4231_MODE_RECORD);
9a20332a 1169 if (err < 0)
1da177e4 1170 return err;
1da177e4
LT		 1171 chip->capture_substream = substream;
1172 chip->c_periods_sent = 0;
1173 snd_pcm_set_sync(substream);
1174 snd_cs4231_xrate(runtime);
1175
1176 return 0;
1177}
1178
be9b7e8c 1179static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
1da177e4 1180{
be9b7e8c 1181 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4 1182
1da177e4 1183 snd_cs4231_close(chip, CS4231_MODE_PLAY);
b128254f 1184 chip->playback_substream = NULL;
1da177e4
LT		 1185
1186 return 0;
1187}
1188
be9b7e8c 1189static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
1da177e4 1190{
be9b7e8c 1191 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4 1192
1da177e4 1193 snd_cs4231_close(chip, CS4231_MODE_RECORD);
b128254f 1194 chip->capture_substream = NULL;
1da177e4
LT		 1195
1196 return 0;
1197}
1198
1199/* XXX We can do some power-management, in particular on EBUS using
1200 * XXX the audio AUXIO register...
1201 */
1202
544d6272 1203static const struct snd_pcm_ops snd_cs4231_playback_ops = {
1da177e4
LT		 1204 .open = snd_cs4231_playback_open,
1205 .close = snd_cs4231_playback_close,
1206 .ioctl = snd_pcm_lib_ioctl,
1207 .hw_params = snd_cs4231_playback_hw_params,
c6c2d57b 1208 .hw_free = snd_pcm_lib_free_pages,
1da177e4
LT		 1209 .prepare = snd_cs4231_playback_prepare,
1210 .trigger = snd_cs4231_trigger,
1211 .pointer = snd_cs4231_playback_pointer,
1212};
1213
544d6272 1214static const struct snd_pcm_ops snd_cs4231_capture_ops = {
1da177e4
LT		 1215 .open = snd_cs4231_capture_open,
1216 .close = snd_cs4231_capture_close,
1217 .ioctl = snd_pcm_lib_ioctl,
1218 .hw_params = snd_cs4231_capture_hw_params,
c6c2d57b 1219 .hw_free = snd_pcm_lib_free_pages,
1da177e4
LT		 1220 .prepare = snd_cs4231_capture_prepare,
1221 .trigger = snd_cs4231_trigger,
1222 .pointer = snd_cs4231_capture_pointer,
1223};
1224
32e02a7b 1225static int snd_cs4231_pcm(struct snd_card *card)
1da177e4 1226{
c6c2d57b 1227 struct snd_cs4231 *chip = card->private_data;
be9b7e8c 1228 struct snd_pcm *pcm;
1da177e4
LT		 1229 int err;
1230
c6c2d57b
KH		 1231 err = snd_pcm_new(card, "CS4231", 0, 1, 1, &pcm);
1232 if (err < 0)
1da177e4
LT		 1233 return err;
1234
9e9abb4f
KH		 1235 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1236 &snd_cs4231_playback_ops);
1237 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1238 &snd_cs4231_capture_ops);
1239
1da177e4
LT		 1240 /* global setup */
1241 pcm->private_data = chip;
1da177e4
LT		 1242 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1243 strcpy(pcm->name, "CS4231");
1244
afc88ad6
DM		 1245 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1246 &chip->op->dev,
1247 64 * 1024, 128 * 1024);
1da177e4
LT		 1248
1249 chip->pcm = pcm;
1250
1251 return 0;
1252}
1253
32e02a7b 1254static int snd_cs4231_timer(struct snd_card *card)
1da177e4 1255{
c6c2d57b 1256 struct snd_cs4231 *chip = card->private_data;
be9b7e8c
TI		 1257 struct snd_timer *timer;
1258 struct snd_timer_id tid;
1da177e4
LT		 1259 int err;
1260
1261 /* Timer initialization */
1262 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1263 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
c6c2d57b 1264 tid.card = card->number;
1da177e4
LT		 1265 tid.device = 0;
1266 tid.subdevice = 0;
c6c2d57b
KH		 1267 err = snd_timer_new(card, "CS4231", &tid, &timer);
1268 if (err < 0)
1da177e4
LT		 1269 return err;
1270 strcpy(timer->name, "CS4231");
1271 timer->private_data = chip;
1da177e4
LT		 1272 timer->hw = snd_cs4231_timer_table;
1273 chip->timer = timer;
1274
1275 return 0;
1276}
9e9abb4f 1277
1da177e4
LT		 1278/*
1279 * MIXER part
1280 */
1281
be9b7e8c
TI		 1282static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol,
1283 struct snd_ctl_elem_info *uinfo)
1da177e4 1284{
5fe0b0e3 1285 static const char * const texts[4] = {
1da177e4
LT		 1286 "Line", "CD", "Mic", "Mix"
1287 };
1da177e4 1288
5fe0b0e3 1289 return snd_ctl_enum_info(uinfo, 2, 4, texts);
1da177e4
LT		 1290}
1291
be9b7e8c
TI		 1292static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol,
1293 struct snd_ctl_elem_value *ucontrol)
1da177e4 1294{
be9b7e8c 1295 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4 1296 unsigned long flags;
9e9abb4f 1297
1da177e4
LT		 1298 spin_lock_irqsave(&chip->lock, flags);
1299 ucontrol->value.enumerated.item[0] =
1300 (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
1301 ucontrol->value.enumerated.item[1] =
1302 (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
1303 spin_unlock_irqrestore(&chip->lock, flags);
1304
1305 return 0;
1306}
1307
be9b7e8c
TI		 1308static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol,
1309 struct snd_ctl_elem_value *ucontrol)
1da177e4 1310{
be9b7e8c 1311 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1312 unsigned long flags;
1313 unsigned short left, right;
1314 int change;
9e9abb4f 1315
1da177e4
LT		 1316 if (ucontrol->value.enumerated.item[0] > 3 ||
1317 ucontrol->value.enumerated.item[1] > 3)
1318 return -EINVAL;
1319 left = ucontrol->value.enumerated.item[0] << 6;
1320 right = ucontrol->value.enumerated.item[1] << 6;
1321
1322 spin_lock_irqsave(&chip->lock, flags);
1323
1324 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
1325 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
1326 change = left != chip->image[CS4231_LEFT_INPUT] ||
9e9abb4f 1327 right != chip->image[CS4231_RIGHT_INPUT];
1da177e4
LT		 1328 snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
1329 snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
1330
1331 spin_unlock_irqrestore(&chip->lock, flags);
1332
1333 return change;
1334}
1335
be9b7e8c
TI		 1336static int snd_cs4231_info_single(struct snd_kcontrol *kcontrol,
1337 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1338{
1339 int mask = (kcontrol->private_value >> 16) & 0xff;
1340
1341 uinfo->type = (mask == 1) ?
1342 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1343 uinfo->count = 1;
1344 uinfo->value.integer.min = 0;
1345 uinfo->value.integer.max = mask;
1346
1347 return 0;
1348}
1349
be9b7e8c
TI		 1350static int snd_cs4231_get_single(struct snd_kcontrol *kcontrol,
1351 struct snd_ctl_elem_value *ucontrol)
1da177e4 1352{
be9b7e8c 1353 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1354 unsigned long flags;
1355 int reg = kcontrol->private_value & 0xff;
1356 int shift = (kcontrol->private_value >> 8) & 0xff;
1357 int mask = (kcontrol->private_value >> 16) & 0xff;
1358 int invert = (kcontrol->private_value >> 24) & 0xff;
9e9abb4f 1359
1da177e4
LT		 1360 spin_lock_irqsave(&chip->lock, flags);
1361
1362 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
1363
1364 spin_unlock_irqrestore(&chip->lock, flags);
1365
1366 if (invert)
1367 ucontrol->value.integer.value[0] =
1368 (mask - ucontrol->value.integer.value[0]);
1369
1370 return 0;
1371}
1372
be9b7e8c
TI		 1373static int snd_cs4231_put_single(struct snd_kcontrol *kcontrol,
1374 struct snd_ctl_elem_value *ucontrol)
1da177e4 1375{
be9b7e8c 1376 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1377 unsigned long flags;
1378 int reg = kcontrol->private_value & 0xff;
1379 int shift = (kcontrol->private_value >> 8) & 0xff;
1380 int mask = (kcontrol->private_value >> 16) & 0xff;
1381 int invert = (kcontrol->private_value >> 24) & 0xff;
1382 int change;
1383 unsigned short val;
9e9abb4f 1384
1da177e4
LT		 1385 val = (ucontrol->value.integer.value[0] & mask);
1386 if (invert)
1387 val = mask - val;
1388 val <<= shift;
1389
1390 spin_lock_irqsave(&chip->lock, flags);
1391
1392 val = (chip->image[reg] & ~(mask << shift)) | val;
1393 change = val != chip->image[reg];
1394 snd_cs4231_out(chip, reg, val);
1395
1396 spin_unlock_irqrestore(&chip->lock, flags);
1397
1398 return change;
1399}
1400
be9b7e8c
TI		 1401static int snd_cs4231_info_double(struct snd_kcontrol *kcontrol,
1402 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1403{
1404 int mask = (kcontrol->private_value >> 24) & 0xff;
1405
1406 uinfo->type = mask == 1 ?
1407 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1408 uinfo->count = 2;
1409 uinfo->value.integer.min = 0;
1410 uinfo->value.integer.max = mask;
1411
1412 return 0;
1413}
1414
be9b7e8c
TI		 1415static int snd_cs4231_get_double(struct snd_kcontrol *kcontrol,
1416 struct snd_ctl_elem_value *ucontrol)
1da177e4 1417{
be9b7e8c 1418 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1419 unsigned long flags;
1420 int left_reg = kcontrol->private_value & 0xff;
1421 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1422 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1423 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1424 int mask = (kcontrol->private_value >> 24) & 0xff;
1425 int invert = (kcontrol->private_value >> 22) & 1;
9e9abb4f 1426
1da177e4
LT		 1427 spin_lock_irqsave(&chip->lock, flags);
1428
9e9abb4f
KH		 1429 ucontrol->value.integer.value[0] =
1430 (chip->image[left_reg] >> shift_left) & mask;
1431 ucontrol->value.integer.value[1] =
1432 (chip->image[right_reg] >> shift_right) & mask;
1da177e4
LT		 1433
1434 spin_unlock_irqrestore(&chip->lock, flags);
1435
1436 if (invert) {
1437 ucontrol->value.integer.value[0] =
1438 (mask - ucontrol->value.integer.value[0]);
1439 ucontrol->value.integer.value[1] =
1440 (mask - ucontrol->value.integer.value[1]);
1441 }
1442
1443 return 0;
1444}
1445
be9b7e8c
TI		 1446static int snd_cs4231_put_double(struct snd_kcontrol *kcontrol,
1447 struct snd_ctl_elem_value *ucontrol)
1da177e4 1448{
be9b7e8c 1449 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1450 unsigned long flags;
1451 int left_reg = kcontrol->private_value & 0xff;
1452 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1453 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1454 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1455 int mask = (kcontrol->private_value >> 24) & 0xff;
1456 int invert = (kcontrol->private_value >> 22) & 1;
1457 int change;
1458 unsigned short val1, val2;
9e9abb4f 1459
1da177e4
LT		 1460 val1 = ucontrol->value.integer.value[0] & mask;
1461 val2 = ucontrol->value.integer.value[1] & mask;
1462 if (invert) {
1463 val1 = mask - val1;
1464 val2 = mask - val2;
1465 }
1466 val1 <<= shift_left;
1467 val2 <<= shift_right;
1468
1469 spin_lock_irqsave(&chip->lock, flags);
1470
1471 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
1472 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
9e9abb4f
KH		 1473 change = val1 != chip->image[left_reg];
1474 change |= val2 != chip->image[right_reg];
1da177e4
LT		 1475 snd_cs4231_out(chip, left_reg, val1);
1476 snd_cs4231_out(chip, right_reg, val2);
1477
1478 spin_unlock_irqrestore(&chip->lock, flags);
1479
1480 return change;
1481}
1482
1483#define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
9e9abb4f
KH		 1484{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
1485 .info = snd_cs4231_info_single, \
1486 .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
1487 .private_value = (reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24) }
1488
1489#define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, \
1490 shift_right, mask, invert) \
1491{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
1492 .info = snd_cs4231_info_double, \
1493 .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
1494 .private_value = (left_reg) | ((right_reg) << 8) | ((shift_left) << 16) | \
1495 ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22) }
1da177e4 1496
32e02a7b 1497static struct snd_kcontrol_new snd_cs4231_controls[] = {
9e9abb4f
KH		 1498CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT,
1499 CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
1500CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT,
1501 CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
1502CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN,
1503 CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
1504CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN,
1505 CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
1506CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT,
1507 CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
1508CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT,
1509 CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
1510CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT,
1511 CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
1512CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT,
1513 CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
1da177e4
LT		 1514CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
1515CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
1516CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
1517CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
9e9abb4f
KH		 1518CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0,
1519 15, 0),
1da177e4
LT		 1520{
1521 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1522 .name = "Capture Source",
1523 .info = snd_cs4231_info_mux,
1524 .get = snd_cs4231_get_mux,
1525 .put = snd_cs4231_put_mux,
1526},
9e9abb4f
KH		 1527CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5,
1528 1, 0),
1da177e4
LT		 1529CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
1530CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
1531/* SPARC specific uses of XCTL{0,1} general purpose outputs. */
1532CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
1533CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
1534};
9e9abb4f 1535
32e02a7b 1536static int snd_cs4231_mixer(struct snd_card *card)
1da177e4 1537{
c6c2d57b 1538 struct snd_cs4231 *chip = card->private_data;
1da177e4
LT		 1539 int err, idx;
1540
5e246b85
TI		 1541 if (snd_BUG_ON(!chip || !chip->pcm))
1542 return -EINVAL;
1da177e4 1543
1da177e4
LT		 1544 strcpy(card->mixername, chip->pcm->name);
1545
1546 for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
c6c2d57b
KH		 1547 err = snd_ctl_add(card,
1548 snd_ctl_new1(&snd_cs4231_controls[idx], chip));
1549 if (err < 0)
1da177e4
LT		 1550 return err;
1551 }
1552 return 0;
1553}
1554
1555static int dev;
1556
a2fefc35
TI		 1557static int cs4231_attach_begin(struct platform_device *op,
1558 struct snd_card **rcard)
1da177e4 1559{
be9b7e8c 1560 struct snd_card *card;
c6c2d57b 1561 struct snd_cs4231 *chip;
bd7dd77c 1562 int err;
1da177e4
LT		 1563
1564 *rcard = NULL;
1565
1566 if (dev >= SNDRV_CARDS)
1567 return -ENODEV;
1568
1569 if (!enable[dev]) {
1570 dev++;
1571 return -ENOENT;
1572 }
1573
a2fefc35
TI		 1574 err = snd_card_new(&op->dev, index[dev], id[dev], THIS_MODULE,
1575 sizeof(struct snd_cs4231), &card);
bd7dd77c
TI		 1576 if (err < 0)
1577 return err;
1da177e4
LT		 1578
1579 strcpy(card->driver, "CS4231");
1580 strcpy(card->shortname, "Sun CS4231");
1581
c6c2d57b
KH		 1582 chip = card->private_data;
1583 chip->card = card;
1584
1da177e4
LT		 1585 *rcard = card;
1586 return 0;
1587}
1588
32e02a7b 1589static int cs4231_attach_finish(struct snd_card *card)
1da177e4 1590{
c6c2d57b 1591 struct snd_cs4231 *chip = card->private_data;
1da177e4
LT		 1592 int err;
1593
c6c2d57b
KH		 1594 err = snd_cs4231_pcm(card);
1595 if (err < 0)
1da177e4
LT		 1596 goto out_err;
1597
c6c2d57b
KH		 1598 err = snd_cs4231_mixer(card);
1599 if (err < 0)
1da177e4
LT		 1600 goto out_err;
1601
c6c2d57b
KH		 1602 err = snd_cs4231_timer(card);
1603 if (err < 0)
1da177e4
LT		 1604 goto out_err;
1605
c6c2d57b
KH		 1606 err = snd_card_register(card);
1607 if (err < 0)
1da177e4
LT		 1608 goto out_err;
1609
afc88ad6 1610 dev_set_drvdata(&chip->op->dev, chip);
1da177e4
LT		 1611
1612 dev++;
1613 return 0;
1614
1615out_err:
1616 snd_card_free(card);
1617 return err;
1618}
1619
1620#ifdef SBUS_SUPPORT
b128254f 1621
7d12e780 1622static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id)
b128254f
GC		 1623{
1624 unsigned long flags;
1625 unsigned char status;
1626 u32 csr;
be9b7e8c 1627 struct snd_cs4231 *chip = dev_id;
b128254f
GC		 1628
1629 /*This is IRQ is not raised by the cs4231*/
7e52f3da 1630 if (!(__cs4231_readb(chip, CS4231U(chip, STATUS)) & CS4231_GLOBALIRQ))
b128254f
GC		 1631 return IRQ_NONE;
1632
1633 /* ACK the APC interrupt. */
1634 csr = sbus_readl(chip->port + APCCSR);
1635
1636 sbus_writel(csr, chip->port + APCCSR);
1637
9e9abb4f
KH		 1638 if ((csr & APC_PDMA_READY) &&
1639 (csr & APC_PLAY_INT) &&
b128254f
GC		 1640 (csr & APC_XINT_PNVA) &&
1641 !(csr & APC_XINT_EMPT))
1642 snd_cs4231_play_callback(chip);
1643
9e9abb4f
KH		 1644 if ((csr & APC_CDMA_READY) &&
1645 (csr & APC_CAPT_INT) &&
b128254f
GC		 1646 (csr & APC_XINT_CNVA) &&
1647 !(csr & APC_XINT_EMPT))
1648 snd_cs4231_capture_callback(chip);
9e9abb4f 1649
b128254f
GC		 1650 status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
1651
1652 if (status & CS4231_TIMER_IRQ) {
1653 if (chip->timer)
1654 snd_timer_interrupt(chip->timer, chip->timer->sticks);
9e9abb4f 1655 }
b128254f
GC		 1656
1657 if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY))
1658 snd_cs4231_overrange(chip);
1659
1660 /* ACK the CS4231 interrupt. */
1661 spin_lock_irqsave(&chip->lock, flags);
1662 snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
1663 spin_unlock_irqrestore(&chip->lock, flags);
1664
d35a1b9e 1665 return IRQ_HANDLED;
b128254f
GC		 1666}
1667
1668/*
1669 * SBUS DMA routines
1670 */
1671
9e9abb4f
KH		 1672static int sbus_dma_request(struct cs4231_dma_control *dma_cont,
1673 dma_addr_t bus_addr, size_t len)
b128254f
GC		 1674{
1675 unsigned long flags;
1676 u32 test, csr;
1677 int err;
be9b7e8c 1678 struct sbus_dma_info *base = &dma_cont->sbus_info;
9e9abb4f 1679
b128254f
GC		 1680 if (len >= (1 << 24))
1681 return -EINVAL;
1682 spin_lock_irqsave(&base->lock, flags);
1683 csr = sbus_readl(base->regs + APCCSR);
1684 err = -EINVAL;
1685 test = APC_CDMA_READY;
9e9abb4f 1686 if (base->dir == APC_PLAY)
b128254f
GC		 1687 test = APC_PDMA_READY;
1688 if (!(csr & test))
1689 goto out;
1690 err = -EBUSY;
b128254f 1691 test = APC_XINT_CNVA;
9e9abb4f 1692 if (base->dir == APC_PLAY)
b128254f
GC		 1693 test = APC_XINT_PNVA;
1694 if (!(csr & test))
1695 goto out;
1696 err = 0;
1697 sbus_writel(bus_addr, base->regs + base->dir + APCNVA);
1698 sbus_writel(len, base->regs + base->dir + APCNC);
1699out:
1700 spin_unlock_irqrestore(&base->lock, flags);
1701 return err;
1702}
1703
be9b7e8c 1704static void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d)
b128254f
GC		 1705{
1706 unsigned long flags;
1707 u32 csr, test;
be9b7e8c 1708 struct sbus_dma_info *base = &dma_cont->sbus_info;
b128254f
GC		 1709
1710 spin_lock_irqsave(&base->lock, flags);
1711 csr = sbus_readl(base->regs + APCCSR);
1712 test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
1713 APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL |
1714 APC_XINT_PENA;
9e9abb4f 1715 if (base->dir == APC_RECORD)
b128254f
GC		 1716 test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
1717 APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL;
1718 csr |= test;
1719 sbus_writel(csr, base->regs + APCCSR);
1720 spin_unlock_irqrestore(&base->lock, flags);
1721}
1722
be9b7e8c 1723static void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
b128254f
GC		 1724{
1725 unsigned long flags;
1726 u32 csr, shift;
be9b7e8c 1727 struct sbus_dma_info *base = &dma_cont->sbus_info;
b128254f
GC		 1728
1729 spin_lock_irqsave(&base->lock, flags);
1730 if (!on) {
d35a1b9e
GC		 1731 sbus_writel(0, base->regs + base->dir + APCNC);
1732 sbus_writel(0, base->regs + base->dir + APCNVA);
9e9abb4f 1733 if (base->dir == APC_PLAY) {
3daadf33
GC		 1734 sbus_writel(0, base->regs + base->dir + APCC);
1735 sbus_writel(0, base->regs + base->dir + APCVA);
1736 }
d35a1b9e 1737
3daadf33 1738 udelay(1200);
9e9abb4f 1739 }
b128254f
GC		 1740 csr = sbus_readl(base->regs + APCCSR);
1741 shift = 0;
9e9abb4f 1742 if (base->dir == APC_PLAY)
b128254f
GC		 1743 shift = 1;
1744 if (on)
1745 csr &= ~(APC_CPAUSE << shift);
1746 else
9e9abb4f 1747 csr |= (APC_CPAUSE << shift);
b128254f
GC		 1748 sbus_writel(csr, base->regs + APCCSR);
1749 if (on)
1750 csr |= (APC_CDMA_READY << shift);
1751 else
1752 csr &= ~(APC_CDMA_READY << shift);
1753 sbus_writel(csr, base->regs + APCCSR);
9e9abb4f 1754
b128254f
GC		 1755 spin_unlock_irqrestore(&base->lock, flags);
1756}
1757
be9b7e8c 1758static unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont)
b128254f 1759{
be9b7e8c 1760 struct sbus_dma_info *base = &dma_cont->sbus_info;
b128254f 1761
9e9abb4f 1762 return sbus_readl(base->regs + base->dir + APCVA);
b128254f
GC		 1763}
1764
b128254f
GC		 1765/*
1766 * Init and exit routines
1767 */
1768
be9b7e8c 1769static int snd_cs4231_sbus_free(struct snd_cs4231 *chip)
1da177e4 1770{
2dc11581 1771 struct platform_device *op = chip->op;
ae251031 1772
1da177e4
LT		 1773 if (chip->irq[0])
1774 free_irq(chip->irq[0], chip);
1775
1776 if (chip->port)
ae251031 1777 of_iounmap(&op->resource[0], chip->port, chip->regs_size);
1da177e4 1778
1da177e4
LT		 1779 return 0;
1780}
1781
be9b7e8c 1782static int snd_cs4231_sbus_dev_free(struct snd_device *device)
1da177e4 1783{
be9b7e8c 1784 struct snd_cs4231 *cp = device->device_data;
1da177e4
LT		 1785
1786 return snd_cs4231_sbus_free(cp);
1787}
1788
be9b7e8c 1789static struct snd_device_ops snd_cs4231_sbus_dev_ops = {
1da177e4
LT		 1790 .dev_free = snd_cs4231_sbus_dev_free,
1791};
1792
32e02a7b
BP		 1793static int snd_cs4231_sbus_create(struct snd_card *card,
1794 struct platform_device *op,
1795 int dev)
1da177e4 1796{
c6c2d57b 1797 struct snd_cs4231 *chip = card->private_data;
1da177e4
LT		 1798 int err;
1799
1da177e4 1800 spin_lock_init(&chip->lock);
b128254f
GC		 1801 spin_lock_init(&chip->c_dma.sbus_info.lock);
1802 spin_lock_init(&chip->p_dma.sbus_info.lock);
12aa7579
IM		 1803 mutex_init(&chip->mce_mutex);
1804 mutex_init(&chip->open_mutex);
afc88ad6 1805 chip->op = op;
ae251031 1806 chip->regs_size = resource_size(&op->resource[0]);
1da177e4
LT		 1807 memcpy(&chip->image, &snd_cs4231_original_image,
1808 sizeof(snd_cs4231_original_image));
1809
ae251031
DM		 1810 chip->port = of_ioremap(&op->resource[0], 0,
1811 chip->regs_size, "cs4231");
1da177e4 1812 if (!chip->port) {
a131430c 1813 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
1da177e4
LT		 1814 return -EIO;
1815 }
1816
b128254f
GC		 1817 chip->c_dma.sbus_info.regs = chip->port;
1818 chip->p_dma.sbus_info.regs = chip->port;
1819 chip->c_dma.sbus_info.dir = APC_RECORD;
1820 chip->p_dma.sbus_info.dir = APC_PLAY;
1821
1822 chip->p_dma.prepare = sbus_dma_prepare;
1823 chip->p_dma.enable = sbus_dma_enable;
1824 chip->p_dma.request = sbus_dma_request;
1825 chip->p_dma.address = sbus_dma_addr;
b128254f
GC		 1826
1827 chip->c_dma.prepare = sbus_dma_prepare;
1828 chip->c_dma.enable = sbus_dma_enable;
1829 chip->c_dma.request = sbus_dma_request;
1830 chip->c_dma.address = sbus_dma_addr;
5a820fa7 1831
1636f8ac 1832 if (request_irq(op->archdata.irqs[0], snd_cs4231_sbus_interrupt,
65ca68b3 1833 IRQF_SHARED, "cs4231", chip)) {
c6387a48 1834 snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %d\n",
1636f8ac 1835 dev, op->archdata.irqs[0]);
1da177e4
LT		 1836 snd_cs4231_sbus_free(chip);
1837 return -EBUSY;
1838 }
1636f8ac 1839 chip->irq[0] = op->archdata.irqs[0];
1da177e4
LT		 1840
1841 if (snd_cs4231_probe(chip) < 0) {
1842 snd_cs4231_sbus_free(chip);
1843 return -ENODEV;
1844 }
1845 snd_cs4231_init(chip);
1846
1847 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
1848 chip, &snd_cs4231_sbus_dev_ops)) < 0) {
1849 snd_cs4231_sbus_free(chip);
1850 return err;
1851 }
1852
1da177e4
LT		 1853 return 0;
1854}
1855
32e02a7b 1856static int cs4231_sbus_probe(struct platform_device *op)
1da177e4 1857{
ae251031 1858 struct resource *rp = &op->resource[0];
be9b7e8c 1859 struct snd_card *card;
1da177e4
LT		 1860 int err;
1861
a2fefc35 1862 err = cs4231_attach_begin(op, &card);
1da177e4
LT		 1863 if (err)
1864 return err;
1865
5863aa65 1866 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
1da177e4
LT		 1867 card->shortname,
1868 rp->flags & 0xffL,
aa0a2ddc 1869 (unsigned long long)rp->start,
1636f8ac 1870 op->archdata.irqs[0]);
1da177e4 1871
ae251031 1872 err = snd_cs4231_sbus_create(card, op, dev);
c6c2d57b 1873 if (err < 0) {
1da177e4
LT		 1874 snd_card_free(card);
1875 return err;
1876 }
1877
c6c2d57b 1878 return cs4231_attach_finish(card);
1da177e4
LT		 1879}
1880#endif
1881
1882#ifdef EBUS_SUPPORT
b128254f 1883
9e9abb4f
KH		 1884static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event,
1885 void *cookie)
b128254f 1886{
be9b7e8c 1887 struct snd_cs4231 *chip = cookie;
9e9abb4f 1888
b128254f
GC		 1889 snd_cs4231_play_callback(chip);
1890}
1891
9e9abb4f
KH		 1892static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p,
1893 int event, void *cookie)
b128254f 1894{
be9b7e8c 1895 struct snd_cs4231 *chip = cookie;
b128254f
GC		 1896
1897 snd_cs4231_capture_callback(chip);
1898}
1899
1900/*
1901 * EBUS DMA wrappers
1902 */
1903
9e9abb4f
KH		 1904static int _ebus_dma_request(struct cs4231_dma_control *dma_cont,
1905 dma_addr_t bus_addr, size_t len)
b128254f
GC		 1906{
1907 return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len);
1908}
1909
be9b7e8c 1910static void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
b128254f
GC		 1911{
1912 ebus_dma_enable(&dma_cont->ebus_info, on);
1913}
1914
be9b7e8c 1915static void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir)
b128254f
GC		 1916{
1917 ebus_dma_prepare(&dma_cont->ebus_info, dir);
1918}
1919
be9b7e8c 1920static unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont)
b128254f
GC		 1921{
1922 return ebus_dma_addr(&dma_cont->ebus_info);
1923}
1924
b128254f
GC		 1925/*
1926 * Init and exit routines
1927 */
1928
be9b7e8c 1929static int snd_cs4231_ebus_free(struct snd_cs4231 *chip)
1da177e4 1930{
2dc11581 1931 struct platform_device *op = chip->op;
afc88ad6 1932
b128254f
GC		 1933 if (chip->c_dma.ebus_info.regs) {
1934 ebus_dma_unregister(&chip->c_dma.ebus_info);
afc88ad6 1935 of_iounmap(&op->resource[2], chip->c_dma.ebus_info.regs, 0x10);
1da177e4 1936 }
b128254f
GC		 1937 if (chip->p_dma.ebus_info.regs) {
1938 ebus_dma_unregister(&chip->p_dma.ebus_info);
afc88ad6 1939 of_iounmap(&op->resource[1], chip->p_dma.ebus_info.regs, 0x10);
1da177e4
LT		 1940 }
1941
1942 if (chip->port)
afc88ad6 1943 of_iounmap(&op->resource[0], chip->port, 0x10);
1da177e4 1944
1da177e4
LT		 1945 return 0;
1946}
1947
be9b7e8c 1948static int snd_cs4231_ebus_dev_free(struct snd_device *device)
1da177e4 1949{
be9b7e8c 1950 struct snd_cs4231 *cp = device->device_data;
1da177e4
LT		 1951
1952 return snd_cs4231_ebus_free(cp);
1953}
1954
be9b7e8c 1955static struct snd_device_ops snd_cs4231_ebus_dev_ops = {
1da177e4
LT		 1956 .dev_free = snd_cs4231_ebus_dev_free,
1957};
1958
32e02a7b
BP		 1959static int snd_cs4231_ebus_create(struct snd_card *card,
1960 struct platform_device *op,
1961 int dev)
1da177e4 1962{
c6c2d57b 1963 struct snd_cs4231 *chip = card->private_data;
1da177e4
LT		 1964 int err;
1965
1da177e4 1966 spin_lock_init(&chip->lock);
b128254f
GC		 1967 spin_lock_init(&chip->c_dma.ebus_info.lock);
1968 spin_lock_init(&chip->p_dma.ebus_info.lock);
12aa7579
IM		 1969 mutex_init(&chip->mce_mutex);
1970 mutex_init(&chip->open_mutex);
1da177e4 1971 chip->flags |= CS4231_FLAG_EBUS;
afc88ad6 1972 chip->op = op;
1da177e4
LT		 1973 memcpy(&chip->image, &snd_cs4231_original_image,
1974 sizeof(snd_cs4231_original_image));
b128254f
GC		 1975 strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)");
1976 chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
1977 chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback;
1978 chip->c_dma.ebus_info.client_cookie = chip;
1636f8ac 1979 chip->c_dma.ebus_info.irq = op->archdata.irqs[0];
b128254f
GC		 1980 strcpy(chip->p_dma.ebus_info.name, "cs4231(play)");
1981 chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
1982 chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback;
1983 chip->p_dma.ebus_info.client_cookie = chip;
1636f8ac 1984 chip->p_dma.ebus_info.irq = op->archdata.irqs[1];
b128254f
GC		 1985
1986 chip->p_dma.prepare = _ebus_dma_prepare;
1987 chip->p_dma.enable = _ebus_dma_enable;
1988 chip->p_dma.request = _ebus_dma_request;
1989 chip->p_dma.address = _ebus_dma_addr;
b128254f
GC		 1990
1991 chip->c_dma.prepare = _ebus_dma_prepare;
1992 chip->c_dma.enable = _ebus_dma_enable;
1993 chip->c_dma.request = _ebus_dma_request;
1994 chip->c_dma.address = _ebus_dma_addr;
1da177e4 1995
afc88ad6
DM		 1996 chip->port = of_ioremap(&op->resource[0], 0, 0x10, "cs4231");
1997 chip->p_dma.ebus_info.regs =
1998 of_ioremap(&op->resource[1], 0, 0x10, "cs4231_pdma");
1999 chip->c_dma.ebus_info.regs =
2000 of_ioremap(&op->resource[2], 0, 0x10, "cs4231_cdma");
9e9abb4f
KH		 2001 if (!chip->port || !chip->p_dma.ebus_info.regs ||
2002 !chip->c_dma.ebus_info.regs) {
1da177e4 2003 snd_cs4231_ebus_free(chip);
a131430c 2004 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
1da177e4
LT		 2005 return -EIO;
2006 }
2007
b128254f 2008 if (ebus_dma_register(&chip->c_dma.ebus_info)) {
1da177e4 2009 snd_cs4231_ebus_free(chip);
9e9abb4f
KH		 2010 snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n",
2011 dev);
1da177e4
LT		 2012 return -EBUSY;
2013 }
b128254f 2014 if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) {
1da177e4 2015 snd_cs4231_ebus_free(chip);
9e9abb4f
KH		 2016 snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n",
2017 dev);
1da177e4
LT		 2018 return -EBUSY;
2019 }
2020
b128254f 2021 if (ebus_dma_register(&chip->p_dma.ebus_info)) {
1da177e4 2022 snd_cs4231_ebus_free(chip);
9e9abb4f
KH		 2023 snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n",
2024 dev);
1da177e4
LT		 2025 return -EBUSY;
2026 }
b128254f 2027 if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) {
1da177e4 2028 snd_cs4231_ebus_free(chip);
a131430c 2029 snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
1da177e4
LT		 2030 return -EBUSY;
2031 }
2032
2033 if (snd_cs4231_probe(chip) < 0) {
2034 snd_cs4231_ebus_free(chip);
2035 return -ENODEV;
2036 }
2037 snd_cs4231_init(chip);
2038
2039 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
2040 chip, &snd_cs4231_ebus_dev_ops)) < 0) {
2041 snd_cs4231_ebus_free(chip);
2042 return err;
2043 }
2044
1da177e4
LT		 2045 return 0;
2046}
2047
32e02a7b 2048static int cs4231_ebus_probe(struct platform_device *op)
1da177e4 2049{
be9b7e8c 2050 struct snd_card *card;
1da177e4
LT		 2051 int err;
2052
a2fefc35 2053 err = cs4231_attach_begin(op, &card);
1da177e4
LT		 2054 if (err)
2055 return err;
2056
3f4528d6 2057 sprintf(card->longname, "%s at 0x%llx, irq %d",
1da177e4 2058 card->shortname,
afc88ad6 2059 op->resource[0].start,
1636f8ac 2060 op->archdata.irqs[0]);
1da177e4 2061
afc88ad6 2062 err = snd_cs4231_ebus_create(card, op, dev);
c6c2d57b 2063 if (err < 0) {
1da177e4
LT		 2064 snd_card_free(card);
2065 return err;
2066 }
2067
c6c2d57b 2068 return cs4231_attach_finish(card);
1da177e4
LT		 2069}
2070#endif
2071
32e02a7b 2072static int cs4231_probe(struct platform_device *op)
afc88ad6
DM		 2073{
2074#ifdef EBUS_SUPPORT
c23b8e7a 2075 if (of_node_name_eq(op->dev.of_node->parent, "ebus"))
f07eb223 2076 return cs4231_ebus_probe(op);
afc88ad6 2077#endif
1da177e4 2078#ifdef SBUS_SUPPORT
c23b8e7a
RH		 2079 if (of_node_name_eq(op->dev.of_node->parent, "sbus") ||
2080 of_node_name_eq(op->dev.of_node->parent, "sbi"))
f07eb223 2081 return cs4231_sbus_probe(op);
afc88ad6
DM		 2082#endif
2083 return -ENODEV;
2084}
2085
32e02a7b 2086static int cs4231_remove(struct platform_device *op)
afc88ad6
DM		 2087{
2088 struct snd_cs4231 *chip = dev_get_drvdata(&op->dev);
2089
2090 snd_card_free(chip->card);
2091
2092 return 0;
2093}
2094
fd098316 2095static const struct of_device_id cs4231_match[] = {
ae251031
DM		 2096 {
2097 .name = "SUNW,CS4231",
2098 },
afc88ad6
DM		 2099 {
2100 .name = "audio",
2101 .compatible = "SUNW,CS4231",
2102 },
ae251031
DM		 2103 {},
2104};
2105
2106MODULE_DEVICE_TABLE(of, cs4231_match);
2107
f07eb223 2108static struct platform_driver cs4231_driver = {
4018294b
GL		 2109 .driver = {
2110 .name = "audio",
4018294b
GL		 2111 .of_match_table = cs4231_match,
2112 },
ae251031 2113 .probe = cs4231_probe,
32e02a7b 2114 .remove = cs4231_remove,
ae251031 2115};
ae251031 2116
a09452ee 2117module_platform_driver(cs4231_driver);
Linux 6.x block layer and io_uring tree(s)