[linux-block.git] / sound / soc / ti / omap-dmic.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * omap-dmic.c  --  OMAP ASoC DMIC DAI driver
 *
 * Copyright (C) 2010 - 2011 Texas Instruments
 *
 * Author: David Lambert <dlambert@ti.com>
 *	   Misael Lopez Cruz <misael.lopez@ti.com>
 *	   Liam Girdwood <lrg@ti.com>
 *	   Peter Ujfalusi <peter.ujfalusi@ti.com>
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/of_device.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>

#include "omap-dmic.h"
#include "sdma-pcm.h"

struct omap_dmic {
	struct device *dev;
	void __iomem *io_base;
	struct clk *fclk;
	struct pm_qos_request pm_qos_req;
	int latency;
	int fclk_freq;
	int out_freq;
	int clk_div;
	int sysclk;
	int threshold;
	u32 ch_enabled;
	bool active;
	struct mutex mutex;

	struct snd_dmaengine_dai_dma_data dma_data;
};

static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
{
	writel_relaxed(val, dmic->io_base + reg);
}

static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
{
	return readl_relaxed(dmic->io_base + reg);
}

static inline void omap_dmic_start(struct omap_dmic *dmic)
{
	u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);

	/* Configure DMA controller */
	omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
			OMAP_DMIC_DMA_ENABLE);

	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled);
}

static inline void omap_dmic_stop(struct omap_dmic *dmic)
{
	u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
			ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);

	/* Disable DMA request generation */
	omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
			OMAP_DMIC_DMA_ENABLE);

}

static inline int dmic_is_enabled(struct omap_dmic *dmic)
{
	return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
						OMAP_DMIC_UP_ENABLE_MASK;
}

static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	int ret = 0;

	mutex_lock(&dmic->mutex);

	if (!snd_soc_dai_active(dai))
		dmic->active = 1;
	else
		ret = -EBUSY;

	mutex_unlock(&dmic->mutex);

	return ret;
}

static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
				    struct snd_soc_dai *dai)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&dmic->mutex);

	cpu_latency_qos_remove_request(&dmic->pm_qos_req);

	if (!snd_soc_dai_active(dai))
		dmic->active = 0;

	mutex_unlock(&dmic->mutex);
}

static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
{
	int divider = -EINVAL;

	/*
	 * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
	 * configuration.
	 */
	if (sample_rate == 192000) {
		if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
			divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
		else
			dev_err(dmic->dev,
				"invalid clock configuration for 192KHz\n");

		return divider;
	}

	switch (dmic->out_freq) {
	case 1536000:
		if (dmic->fclk_freq != 24576000)
			goto div_err;
		divider = 0x4; /* Divider: 16 */
		break;
	case 2400000:
		switch (dmic->fclk_freq) {
		case 12000000:
			divider = 0x5; /* Divider: 5 */
			break;
		case 19200000:
			divider = 0x0; /* Divider: 8 */
			break;
		case 24000000:
			divider = 0x2; /* Divider: 10 */
			break;
		default:
			goto div_err;
		}
		break;
	case 3072000:
		if (dmic->fclk_freq != 24576000)
			goto div_err;
		divider = 0x3; /* Divider: 8 */
		break;
	case 3840000:
		if (dmic->fclk_freq != 19200000)
			goto div_err;
		divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
		break;
	default:
		dev_err(dmic->dev, "invalid out frequency: %dHz\n",
			dmic->out_freq);
		break;
	}

	return divider;

div_err:
	dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
		dmic->out_freq, dmic->fclk_freq);
	return -EINVAL;
}

static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	struct snd_dmaengine_dai_dma_data *dma_data;
	int channels;

	dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
	if (dmic->clk_div < 0) {
		dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
			dmic->out_freq, dmic->fclk_freq);
		return -EINVAL;
	}

	dmic->ch_enabled = 0;
	channels = params_channels(params);
	switch (channels) {
	case 6:
		dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE;
		fallthrough;
	case 4:
		dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE;
		fallthrough;
	case 2:
		dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE;
		break;
	default:
		dev_err(dmic->dev, "invalid number of legacy channels\n");
		return -EINVAL;
	}

	/* packet size is threshold * channels */
	dma_data = snd_soc_dai_get_dma_data(dai, substream);
	dma_data->maxburst = dmic->threshold * channels;
	dmic->latency = (OMAP_DMIC_THRES_MAX - dmic->threshold) * USEC_PER_SEC /
			params_rate(params);

	return 0;
}

static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	u32 ctrl;

	if (cpu_latency_qos_request_active(&dmic->pm_qos_req))
		cpu_latency_qos_update_request(&dmic->pm_qos_req,
					       dmic->latency);

	/* Configure uplink threshold */
	omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);

	ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);

	/* Set dmic out format */
	ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK);
	ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
		 OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);

	/* Configure dmic clock divider */
	ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
	ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div);

	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);

	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
			ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
			OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);

	return 0;
}

static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
				  int cmd, struct snd_soc_dai *dai)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
		omap_dmic_start(dmic);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
		omap_dmic_stop(dmic);
		break;
	default:
		break;
	}

	return 0;
}

static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
				 unsigned int freq)
{
	struct clk *parent_clk, *mux;
	char *parent_clk_name;
	int ret = 0;

	switch (freq) {
	case 12000000:
	case 19200000:
	case 24000000:
	case 24576000:
		break;
	default:
		dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
		dmic->fclk_freq = 0;
		return -EINVAL;
	}

	if (dmic->sysclk == clk_id) {
		dmic->fclk_freq = freq;
		return 0;
	}

	/* re-parent not allowed if a stream is ongoing */
	if (dmic->active && dmic_is_enabled(dmic)) {
		dev_err(dmic->dev, "can't re-parent when DMIC active\n");
		return -EBUSY;
	}

	switch (clk_id) {
	case OMAP_DMIC_SYSCLK_PAD_CLKS:
		parent_clk_name = "pad_clks_ck";
		break;
	case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
		parent_clk_name = "slimbus_clk";
		break;
	case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
		parent_clk_name = "dmic_sync_mux_ck";
		break;
	default:
		dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
		return -EINVAL;
	}

	parent_clk = clk_get(dmic->dev, parent_clk_name);
	if (IS_ERR(parent_clk)) {
		dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
		return -ENODEV;
	}

	mux = clk_get_parent(dmic->fclk);
	if (IS_ERR(mux)) {
		dev_err(dmic->dev, "can't get fck mux parent\n");
		clk_put(parent_clk);
		return -ENODEV;
	}

	mutex_lock(&dmic->mutex);
	if (dmic->active) {
		/* disable clock while reparenting */
		pm_runtime_put_sync(dmic->dev);
		ret = clk_set_parent(mux, parent_clk);
		pm_runtime_get_sync(dmic->dev);
	} else {
		ret = clk_set_parent(mux, parent_clk);
	}
	mutex_unlock(&dmic->mutex);

	if (ret < 0) {
		dev_err(dmic->dev, "re-parent failed\n");
		goto err_busy;
	}

	dmic->sysclk = clk_id;
	dmic->fclk_freq = freq;

err_busy:
	clk_put(mux);
	clk_put(parent_clk);

	return ret;
}

static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
				    unsigned int freq)
{
	int ret = 0;

	if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
		dev_err(dmic->dev, "output clk_id (%d) not supported\n",
			clk_id);
		return -EINVAL;
	}

	switch (freq) {
	case 1536000:
	case 2400000:
	case 3072000:
	case 3840000:
		dmic->out_freq = freq;
		break;
	default:
		dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
		dmic->out_freq = 0;
		ret = -EINVAL;
	}

	return ret;
}

static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
				    unsigned int freq, int dir)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);

	if (dir == SND_SOC_CLOCK_IN)
		return omap_dmic_select_fclk(dmic, clk_id, freq);
	else if (dir == SND_SOC_CLOCK_OUT)
		return omap_dmic_select_outclk(dmic, clk_id, freq);

	dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
	return -EINVAL;
}

static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
	.startup	= omap_dmic_dai_startup,
	.shutdown	= omap_dmic_dai_shutdown,
	.hw_params	= omap_dmic_dai_hw_params,
	.prepare	= omap_dmic_dai_prepare,
	.trigger	= omap_dmic_dai_trigger,
	.set_sysclk	= omap_dmic_set_dai_sysclk,
};

static int omap_dmic_probe(struct snd_soc_dai *dai)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);

	pm_runtime_enable(dmic->dev);

	/* Disable lines while request is ongoing */
	pm_runtime_get_sync(dmic->dev);
	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
	pm_runtime_put_sync(dmic->dev);

	/* Configure DMIC threshold value */
	dmic->threshold = OMAP_DMIC_THRES_MAX - 3;

	snd_soc_dai_init_dma_data(dai, NULL, &dmic->dma_data);

	return 0;
}

static int omap_dmic_remove(struct snd_soc_dai *dai)
{
	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);

	pm_runtime_disable(dmic->dev);

	return 0;
}

static struct snd_soc_dai_driver omap_dmic_dai = {
	.name = "omap-dmic",
	.probe = omap_dmic_probe,
	.remove = omap_dmic_remove,
	.capture = {
		.channels_min = 2,
		.channels_max = 6,
		.rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
		.formats = SNDRV_PCM_FMTBIT_S32_LE,
		.sig_bits = 24,
	},
	.ops = &omap_dmic_dai_ops,
};

static const struct snd_soc_component_driver omap_dmic_component = {
	.name		= "omap-dmic",
};

static int asoc_dmic_probe(struct platform_device *pdev)
{
	struct omap_dmic *dmic;
	struct resource *res;
	int ret;

	dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
	if (!dmic)
		return -ENOMEM;

	platform_set_drvdata(pdev, dmic);
	dmic->dev = &pdev->dev;
	dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;

	mutex_init(&dmic->mutex);

	dmic->fclk = devm_clk_get(dmic->dev, "fck");
	if (IS_ERR(dmic->fclk)) {
		dev_err(dmic->dev, "cant get fck\n");
		return -ENODEV;
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	if (!res) {
		dev_err(dmic->dev, "invalid dma memory resource\n");
		return -ENODEV;
	}
	dmic->dma_data.addr = res->start + OMAP_DMIC_DATA_REG;

	dmic->dma_data.filter_data = "up_link";

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
	dmic->io_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(dmic->io_base))
		return PTR_ERR(dmic->io_base);


	ret = devm_snd_soc_register_component(&pdev->dev,
					      &omap_dmic_component,
					      &omap_dmic_dai, 1);
	if (ret)
		return ret;

	ret = sdma_pcm_platform_register(&pdev->dev, NULL, "up_link");
	if (ret)
		return ret;

	return 0;
}

static const struct of_device_id omap_dmic_of_match[] = {
	{ .compatible = "ti,omap4-dmic", },
	{ }
};
MODULE_DEVICE_TABLE(of, omap_dmic_of_match);

static struct platform_driver asoc_dmic_driver = {
	.driver = {
		.name = "omap-dmic",
		.of_match_table = omap_dmic_of_match,
	},
	.probe = asoc_dmic_probe,
};

module_platform_driver(asoc_dmic_driver);

MODULE_ALIAS("platform:omap-dmic");
MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
2b27bdcc	1	// SPDX-License-Identifier: GPL-2.0-only
fd26f947 PU	2	/*
	3	* omap-dmic.c -- OMAP ASoC DMIC DAI driver
	4	*
	5	* Copyright (C) 2010 - 2011 Texas Instruments
	6	*
	7	* Author: David Lambert <dlambert@ti.com>
	8	* Misael Lopez Cruz <misael.lopez@ti.com>
	9	* Liam Girdwood <lrg@ti.com>
	10	* Peter Ujfalusi <peter.ujfalusi@ti.com>
fd26f947 PU	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/module.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/err.h>
	17	#include <linux/clk.h>
	18	#include <linux/io.h>
	19	#include <linux/slab.h>
	20	#include <linux/pm_runtime.h>
2ec1be37	21	#include <linux/of_device.h>
fd26f947 PU	22
	23	#include <sound/core.h>
	24	#include <sound/pcm.h>
	25	#include <sound/pcm_params.h>
	26	#include <sound/initval.h>
	27	#include <sound/soc.h>
09ae3aaf	28	#include <sound/dmaengine_pcm.h>
fd26f947	29
fd26f947	30	#include "omap-dmic.h"
87dbec53	31	#include "sdma-pcm.h"
fd26f947 PU	32
	33	struct omap_dmic {
	34	struct device *dev;
	35	void __iomem *io_base;
	36	struct clk *fclk;
ffdcc363 PU	37	struct pm_qos_request pm_qos_req;
ffdcc363 PU	38	int latency;
fd26f947 PU	39	int fclk_freq;
	40	int out_freq;
	41	int clk_div;
	42	int sysclk;
	43	int threshold;
	44	u32 ch_enabled;
	45	bool active;
	46	struct mutex mutex;
fd26f947	47
09ae3aaf	48	struct snd_dmaengine_dai_dma_data dma_data;
fd26f947 PU	49	};
	50
	51	static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
	52	{
1b488a48	53	writel_relaxed(val, dmic->io_base + reg);
fd26f947 PU	54	}
	55
	56	static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
	57	{
1b488a48	58	return readl_relaxed(dmic->io_base + reg);
fd26f947 PU	59	}
	60
	61	static inline void omap_dmic_start(struct omap_dmic *dmic)
	62	{
	63	u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
	64
	65	/* Configure DMA controller */
	66	omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
	67	OMAP_DMIC_DMA_ENABLE);
	68
	69	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl \| dmic->ch_enabled);
	70	}
	71
	72	static inline void omap_dmic_stop(struct omap_dmic *dmic)
	73	{
	74	u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
	75	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
	76	ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);
	77
	78	/* Disable DMA request generation */
	79	omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
	80	OMAP_DMIC_DMA_ENABLE);
	81
	82	}
	83
	84	static inline int dmic_is_enabled(struct omap_dmic *dmic)
	85	{
	86	return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
	87	OMAP_DMIC_UP_ENABLE_MASK;
	88	}
	89
	90	static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
	91	struct snd_soc_dai *dai)
	92	{
	93	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	94	int ret = 0;
	95
	96	mutex_lock(&dmic->mutex);
	97
36ad1a87	98	if (!snd_soc_dai_active(dai))
fd26f947	99	dmic->active = 1;
7df6f255	100	else
fd26f947	101	ret = -EBUSY;
fd26f947 PU	102
	103	mutex_unlock(&dmic->mutex);
	104
	105	return ret;
	106	}
	107
	108	static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
	109	struct snd_soc_dai *dai)
	110	{
	111	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	112
	113	mutex_lock(&dmic->mutex);
	114
5371a79b	115	cpu_latency_qos_remove_request(&dmic->pm_qos_req);
ffdcc363	116
36ad1a87	117	if (!snd_soc_dai_active(dai))
fd26f947	118	dmic->active = 0;
fd26f947 PU	119
	120	mutex_unlock(&dmic->mutex);
	121	}
	122
	123	static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
	124	{
	125	int divider = -EINVAL;
	126
	127	/*
	128	* 192KHz rate is only supported with 19.2MHz/3.84MHz clock
	129	* configuration.
	130	*/
	131	if (sample_rate == 192000) {
	132	if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
	133	divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
	134	else
	135	dev_err(dmic->dev,
	136	"invalid clock configuration for 192KHz\n");
	137
	138	return divider;
	139	}
	140
	141	switch (dmic->out_freq) {
	142	case 1536000:
	143	if (dmic->fclk_freq != 24576000)
	144	goto div_err;
	145	divider = 0x4; /* Divider: 16 */
	146	break;
	147	case 2400000:
	148	switch (dmic->fclk_freq) {
	149	case 12000000:
	150	divider = 0x5; /* Divider: 5 */
	151	break;
	152	case 19200000:
	153	divider = 0x0; /* Divider: 8 */
	154	break;
	155	case 24000000:
	156	divider = 0x2; /* Divider: 10 */
	157	break;
	158	default:
	159	goto div_err;
	160	}
	161	break;
	162	case 3072000:
	163	if (dmic->fclk_freq != 24576000)
	164	goto div_err;
	165	divider = 0x3; /* Divider: 8 */
	166	break;
	167	case 3840000:
	168	if (dmic->fclk_freq != 19200000)
	169	goto div_err;
	170	divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
	171	break;
	172	default:
	173	dev_err(dmic->dev, "invalid out frequency: %dHz\n",
	174	dmic->out_freq);
	175	break;
	176	}
	177
	178	return divider;
	179
	180	div_err:
	181	dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
	182	dmic->out_freq, dmic->fclk_freq);
183	return -EINVAL;
184	}
185
186	static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
187	struct snd_pcm_hw_params *params,
188	struct snd_soc_dai *dai)
189	{
190	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
09ae3aaf	191	struct snd_dmaengine_dai_dma_data *dma_data;
fd26f947 PU	192	int channels;
	193
	194	dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
	195	if (dmic->clk_div < 0) {
	196	dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
	197	dmic->out_freq, dmic->fclk_freq);
	198	return -EINVAL;
	199	}
	200
	201	dmic->ch_enabled = 0;
	202	channels = params_channels(params);
	203	switch (channels) {
	204	case 6:
	205	dmic->ch_enabled \|= OMAP_DMIC_UP3_ENABLE;
df561f66	206	fallthrough;
fd26f947 PU	207	case 4:
fd26f947 PU	208	dmic->ch_enabled \|= OMAP_DMIC_UP2_ENABLE;
df561f66	209	fallthrough;
fd26f947 PU	210	case 2:
	211	dmic->ch_enabled \|= OMAP_DMIC_UP1_ENABLE;
	212	break;
	213	default:
	214	dev_err(dmic->dev, "invalid number of legacy channels\n");
	215	return -EINVAL;
	216	}
	217
	218	/* packet size is threshold * channels */
bcd6da7b	219	dma_data = snd_soc_dai_get_dma_data(dai, substream);
09ae3aaf	220	dma_data->maxburst = dmic->threshold * channels;
ffdcc363 PU	221	dmic->latency = (OMAP_DMIC_THRES_MAX - dmic->threshold) * USEC_PER_SEC /
ffdcc363 PU	222	params_rate(params);
fd26f947 PU	223
	224	return 0;
	225	}
	226
	227	static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
	228	struct snd_soc_dai *dai)
	229	{
	230	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	231	u32 ctrl;
	232
5371a79b RW	233	if (cpu_latency_qos_request_active(&dmic->pm_qos_req))
	234	cpu_latency_qos_update_request(&dmic->pm_qos_req,
	235	dmic->latency);
ffdcc363	236
fd26f947 PU	237	/* Configure uplink threshold */
	238	omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);
	239
	240	ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
	241
	242	/* Set dmic out format */
	243	ctrl &= ~(OMAP_DMIC_FORMAT \| OMAP_DMIC_POLAR_MASK);
	244	ctrl \|= (OMAP_DMICOUTFORMAT_LJUST \| OMAP_DMIC_POLAR1 \|
	245	OMAP_DMIC_POLAR2 \| OMAP_DMIC_POLAR3);
	246
	247	/* Configure dmic clock divider */
	248	ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
	249	ctrl \|= OMAP_DMIC_CLK_DIV(dmic->clk_div);
	250
	251	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);
	252
	253	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
	254	ctrl \| OMAP_DMICOUTFORMAT_LJUST \| OMAP_DMIC_POLAR1 \|
	255	OMAP_DMIC_POLAR2 \| OMAP_DMIC_POLAR3);
	256
	257	return 0;
	258	}
	259
	260	static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
	261	int cmd, struct snd_soc_dai *dai)
	262	{
	263	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	264
	265	switch (cmd) {
	266	case SNDRV_PCM_TRIGGER_START:
	267	omap_dmic_start(dmic);
	268	break;
	269	case SNDRV_PCM_TRIGGER_STOP:
	270	omap_dmic_stop(dmic);
	271	break;
	272	default:
	273	break;
	274	}
	275
	276	return 0;
	277	}
	278
	279	static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
	280	unsigned int freq)
	281	{
573eda59	282	struct clk parent_clk, mux;
fd26f947 PU	283	char *parent_clk_name;
	284	int ret = 0;
	285
	286	switch (freq) {
	287	case 12000000:
	288	case 19200000:
	289	case 24000000:
	290	case 24576000:
	291	break;
	292	default:
	293	dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
	294	dmic->fclk_freq = 0;
	295	return -EINVAL;
	296	}
	297
	298	if (dmic->sysclk == clk_id) {
	299	dmic->fclk_freq = freq;
	300	return 0;
	301	}
	302
	303	/* re-parent not allowed if a stream is ongoing */
	304	if (dmic->active && dmic_is_enabled(dmic)) {
	305	dev_err(dmic->dev, "can't re-parent when DMIC active\n");
	306	return -EBUSY;
	307	}
	308
	309	switch (clk_id) {
	310	case OMAP_DMIC_SYSCLK_PAD_CLKS:
	311	parent_clk_name = "pad_clks_ck";
	312	break;
	313	case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
	314	parent_clk_name = "slimbus_clk";
	315	break;
	316	case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
	317	parent_clk_name = "dmic_sync_mux_ck";
	318	break;
	319	default:
	320	dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
	321	return -EINVAL;
	322	}
	323
	324	parent_clk = clk_get(dmic->dev, parent_clk_name);
	325	if (IS_ERR(parent_clk)) {
	326	dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
	327	return -ENODEV;
	328	}
	329
573eda59 TK	330	mux = clk_get_parent(dmic->fclk);
	331	if (IS_ERR(mux)) {
	332	dev_err(dmic->dev, "can't get fck mux parent\n");
	333	clk_put(parent_clk);
	334	return -ENODEV;
	335	}
	336
fd26f947 PU	337	mutex_lock(&dmic->mutex);
	338	if (dmic->active) {
	339	/* disable clock while reparenting */
	340	pm_runtime_put_sync(dmic->dev);
573eda59	341	ret = clk_set_parent(mux, parent_clk);
fd26f947 PU	342	pm_runtime_get_sync(dmic->dev);
fd26f947 PU	343	} else {
573eda59	344	ret = clk_set_parent(mux, parent_clk);
fd26f947 PU	345	}
	346	mutex_unlock(&dmic->mutex);
	347
	348	if (ret < 0) {
	349	dev_err(dmic->dev, "re-parent failed\n");
	350	goto err_busy;
	351	}
	352
	353	dmic->sysclk = clk_id;
	354	dmic->fclk_freq = freq;
	355
	356	err_busy:
573eda59	357	clk_put(mux);
fd26f947 PU	358	clk_put(parent_clk);
	359
	360	return ret;
	361	}
	362
	363	static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
	364	unsigned int freq)
	365	{
	366	int ret = 0;
	367
	368	if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
	369	dev_err(dmic->dev, "output clk_id (%d) not supported\n",
	370	clk_id);
	371	return -EINVAL;
	372	}
	373
	374	switch (freq) {
	375	case 1536000:
	376	case 2400000:
	377	case 3072000:
	378	case 3840000:
	379	dmic->out_freq = freq;
	380	break;
	381	default:
	382	dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
	383	dmic->out_freq = 0;
	384	ret = -EINVAL;
	385	}
	386
	387	return ret;
	388	}
	389
	390	static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
	391	unsigned int freq, int dir)
	392	{
	393	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	394
	395	if (dir == SND_SOC_CLOCK_IN)
	396	return omap_dmic_select_fclk(dmic, clk_id, freq);
	397	else if (dir == SND_SOC_CLOCK_OUT)
	398	return omap_dmic_select_outclk(dmic, clk_id, freq);
	399
	400	dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
	401	return -EINVAL;
	402	}
	403
	404	static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
	405	.startup = omap_dmic_dai_startup,
	406	.shutdown = omap_dmic_dai_shutdown,
	407	.hw_params = omap_dmic_dai_hw_params,
	408	.prepare = omap_dmic_dai_prepare,
	409	.trigger = omap_dmic_dai_trigger,
	410	.set_sysclk = omap_dmic_set_dai_sysclk,
	411	};
	412
	413	static int omap_dmic_probe(struct snd_soc_dai *dai)
	414	{
	415	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	416
	417	pm_runtime_enable(dmic->dev);
	418
	419	/* Disable lines while request is ongoing */
	420	pm_runtime_get_sync(dmic->dev);
	421	omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
422	pm_runtime_put_sync(dmic->dev);
423
424	/* Configure DMIC threshold value */
425	dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
3802a259 PU	426
	427	snd_soc_dai_init_dma_data(dai, NULL, &dmic->dma_data);
	428
fd26f947 PU	429	return 0;
	430	}
	431
	432	static int omap_dmic_remove(struct snd_soc_dai *dai)
	433	{
	434	struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
	435
	436	pm_runtime_disable(dmic->dev);
	437
	438	return 0;
	439	}
	440
	441	static struct snd_soc_dai_driver omap_dmic_dai = {
	442	.name = "omap-dmic",
	443	.probe = omap_dmic_probe,
	444	.remove = omap_dmic_remove,
	445	.capture = {
	446	.channels_min = 2,
	447	.channels_max = 6,
	448	.rates = SNDRV_PCM_RATE_96000 \| SNDRV_PCM_RATE_192000,
	449	.formats = SNDRV_PCM_FMTBIT_S32_LE,
7df6f255	450	.sig_bits = 24,
fd26f947 PU	451	},
	452	.ops = &omap_dmic_dai_ops,
	453	};
	454
ed22853a KM	455	static const struct snd_soc_component_driver omap_dmic_component = {
	456	.name = "omap-dmic",
	457	};
	458
7ff60006	459	static int asoc_dmic_probe(struct platform_device *pdev)
fd26f947 PU	460	{
	461	struct omap_dmic *dmic;
	462	struct resource *res;
	463	int ret;
	464
	465	dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
	466	if (!dmic)
	467	return -ENOMEM;
	468
	469	platform_set_drvdata(pdev, dmic);
	470	dmic->dev = &pdev->dev;
	471	dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;
	472
	473	mutex_init(&dmic->mutex);
	474
9cb0fe9b	475	dmic->fclk = devm_clk_get(dmic->dev, "fck");
fd26f947	476	if (IS_ERR(dmic->fclk)) {
19118eb8	477	dev_err(dmic->dev, "cant get fck\n");
fd26f947 PU	478	return -ENODEV;
	479	}
	480
	481	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	482	if (!res) {
	483	dev_err(dmic->dev, "invalid dma memory resource\n");
9cb0fe9b	484	return -ENODEV;
fd26f947	485	}
09ae3aaf	486	dmic->dma_data.addr = res->start + OMAP_DMIC_DATA_REG;
fd26f947	487
2ebef447	488	dmic->dma_data.filter_data = "up_link";
fd26f947 PU	489
fd26f947 PU	490	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
673c24e9	491	dmic->io_base = devm_ioremap_resource(&pdev->dev, res);
9cb0fe9b HS	492	if (IS_ERR(dmic->io_base))
9cb0fe9b HS	493	return PTR_ERR(dmic->io_base);
fd26f947	494
fd26f947	495
159baadf MB	496	ret = devm_snd_soc_register_component(&pdev->dev,
	497	&omap_dmic_component,
	498	&omap_dmic_dai, 1);
fd26f947	499	if (ret)
9cb0fe9b	500	return ret;
fd26f947	501
87dbec53	502	ret = sdma_pcm_platform_register(&pdev->dev, NULL, "up_link");
18d7cfea	503	if (ret)
9cb0fe9b	504	return ret;
fd26f947 PU	505
	506	return 0;
	507	}
	508
2ec1be37 PU	509	static const struct of_device_id omap_dmic_of_match[] = {
	510	{ .compatible = "ti,omap4-dmic", },
	511	{ }
	512	};
	513	MODULE_DEVICE_TABLE(of, omap_dmic_of_match);
	514
fd26f947 PU	515	static struct platform_driver asoc_dmic_driver = {
	516	.driver = {
	517	.name = "omap-dmic",
2ec1be37	518	.of_match_table = omap_dmic_of_match,
fd26f947 PU	519	},
fd26f947 PU	520	.probe = asoc_dmic_probe,
fd26f947 PU	521	};
	522
	523	module_platform_driver(asoc_dmic_driver);
	524
	525	MODULE_ALIAS("platform:omap-dmic");
	526	MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
	527	MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
	528	MODULE_LICENSE("GPL");