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Merge tag 'scmi-fixes-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep...
[linux-2.6-block.git] / sound / soc / ti / davinci-mcasp.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
b67f4487
C		 2/*
3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 *
5 * Multi-channel Audio Serial Port Driver
6 *
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
8 * Suresh Rajashekara <suresh.r@ti.com>
9 * Steve Chen <schen@.mvista.com>
10 *
11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
12 * Copyright: (C) 2009 Texas Instruments, India
b67f4487
C		 13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/device.h>
5a0e3ad6 18#include <linux/slab.h>
b67f4487
C		 19#include <linux/delay.h>
20#include <linux/io.h>
ae726e93 21#include <linux/clk.h>
10884347 22#include <linux/pm_runtime.h>
3e3b8c34
HG		 23#include <linux/of.h>
24#include <linux/of_platform.h>
25#include <linux/of_device.h>
9759e7ef 26#include <linux/platform_data/davinci_asp.h>
a75a053f 27#include <linux/math64.h>
ca3d9433 28#include <linux/bitmap.h>
540f1ba7 29#include <linux/gpio/driver.h>
b67f4487 30
6479285d 31#include <sound/asoundef.h>
b67f4487
C		 32#include <sound/core.h>
33#include <sound/pcm.h>
34#include <sound/pcm_params.h>
35#include <sound/initval.h>
36#include <sound/soc.h>
453c4990 37#include <sound/dmaengine_pcm.h>
b67f4487 38
f3f9cfa8 39#include "edma-pcm.h"
f2055e14 40#include "sdma-pcm.h"
b67f4487
C		 41#include "davinci-mcasp.h"
42
0bf0e8ae
PU		 43#define MCASP_MAX_AFIFO_DEPTH 64
44
8ca51047 45#ifdef CONFIG_PM
1cc0c054
PU		 46static u32 context_regs[] = {
47 DAVINCI_MCASP_TXFMCTL_REG,
48 DAVINCI_MCASP_RXFMCTL_REG,
49 DAVINCI_MCASP_TXFMT_REG,
50 DAVINCI_MCASP_RXFMT_REG,
51 DAVINCI_MCASP_ACLKXCTL_REG,
52 DAVINCI_MCASP_ACLKRCTL_REG,
f114ce60
PU		 53 DAVINCI_MCASP_AHCLKXCTL_REG,
54 DAVINCI_MCASP_AHCLKRCTL_REG,
1cc0c054 55 DAVINCI_MCASP_PDIR_REG,
540f1ba7 56 DAVINCI_MCASP_PFUNC_REG,
f114ce60
PU		 57 DAVINCI_MCASP_RXMASK_REG,
58 DAVINCI_MCASP_TXMASK_REG,
59 DAVINCI_MCASP_RXTDM_REG,
60 DAVINCI_MCASP_TXTDM_REG,
1cc0c054
PU		 61};
62
790bb94b 63struct davinci_mcasp_context {
1cc0c054 64 u32 config_regs[ARRAY_SIZE(context_regs)];
f114ce60
PU		 65 u32 afifo_regs[2]; /* for read/write fifo control registers */
66 u32 *xrsr_regs; /* for serializer configuration */
6afda7f5 67 bool pm_state;
790bb94b 68};
8ca51047 69#endif
790bb94b 70
a75a053f
JS		 71struct davinci_mcasp_ruledata {
72 struct davinci_mcasp *mcasp;
73 int serializers;
74};
75
70091a3e 76struct davinci_mcasp {
453c4990 77 struct snd_dmaengine_dai_dma_data dma_data[2];
21400a72 78 void __iomem *base;
487dce88 79 u32 fifo_base;
21400a72 80 struct device *dev;
a7a3324a 81 struct snd_pcm_substream *substreams[2];
4a11ff26 82 unsigned int dai_fmt;
21400a72
PU		 83
84 /* McASP specific data */
85 int tdm_slots;
dd55ff83
JS		 86 u32 tdm_mask[2];
87 int slot_width;
21400a72 88 u8 op_mode;
bc184549 89 u8 dismod;
21400a72
PU		 90 u8 num_serializer;
91 u8 *serial_dir;
92 u8 version;
8267525c 93 u8 bclk_div;
4dcb5a0b 94 int streams;
a7a3324a 95 u32 irq_request[2];
9759e7ef 96 int dma_request[2];
21400a72 97
ab8b14b6
JS		 98 int sysclk_freq;
99 bool bclk_master;
764958f2 100 u32 auxclk_fs_ratio;
ab8b14b6 101
ca3d9433
PU		 102 unsigned long pdir; /* Pin direction bitfield */
103
21400a72
PU		 104 /* McASP FIFO related */
105 u8 txnumevt;
106 u8 rxnumevt;
107
cbc7956c
PU		 108 bool dat_port;
109
11277833
PU		 110 /* Used for comstraint setting on the second stream */
111 u32 channels;
112
540f1ba7
PU		 113#ifdef CONFIG_GPIOLIB
114 struct gpio_chip gpio_chip;
115#endif
116
61754717 117#ifdef CONFIG_PM
790bb94b 118 struct davinci_mcasp_context context;
21400a72 119#endif
a75a053f
JS		 120
121 struct davinci_mcasp_ruledata ruledata[2];
5935a056 122 struct snd_pcm_hw_constraint_list chconstr[2];
21400a72
PU		 123};
124
f68205a7
PU		 125static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
126 u32 val)
b67f4487 127{
f68205a7 128 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 129 __raw_writel(__raw_readl(reg) | val, reg);
130}
131
f68205a7
PU		 132static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
133 u32 val)
b67f4487 134{
f68205a7 135 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 136 __raw_writel((__raw_readl(reg) & ~(val)), reg);
137}
138
f68205a7
PU		 139static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
140 u32 val, u32 mask)
b67f4487 141{
f68205a7 142 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 143 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
144}
145
f68205a7
PU		 146static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
147 u32 val)
b67f4487 148{
f68205a7 149 __raw_writel(val, mcasp->base + offset);
b67f4487
C		 150}
151
f68205a7 152static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
b67f4487 153{
f68205a7 154 return (u32)__raw_readl(mcasp->base + offset);
b67f4487
C		 155}
156
f68205a7 157static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
b67f4487
C		 158{
159 int i = 0;
160
f68205a7 161 mcasp_set_bits(mcasp, ctl_reg, val);
b67f4487
C		 162
163 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
164 /* loop count is to avoid the lock-up */
165 for (i = 0; i < 1000; i++) {
f68205a7 166 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
b67f4487
C		 167 break;
168 }
169
f68205a7 170 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
b67f4487
C		 171 printk(KERN_ERR "GBLCTL write error\n");
172}
173
4dcb5a0b
PU		 174static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
175{
f68205a7
PU		 176 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
177 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
4dcb5a0b
PU		 178
179 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
180}
181
ca3d9433
PU		 182static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
183{
184 u32 bit = PIN_BIT_AMUTE;
185
186 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
187 if (enable)
188 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
189 else
190 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
191 }
192}
193
194static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
195{
196 u32 bit;
197
34a2a80f 198 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
ca3d9433
PU		 199 if (enable)
200 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
201 else
202 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
203 }
204}
205
70091a3e 206static void mcasp_start_rx(struct davinci_mcasp *mcasp)
b67f4487 207{
bb372af0
PU		 208 if (mcasp->rxnumevt) { /* enable FIFO */
209 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
210
211 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
212 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
213 }
214
44982735 215 /* Start clocks */
f68205a7
PU		 216 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
217 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
4dcb5a0b
PU		 218 /*
219 * When ASYNC == 0 the transmit and receive sections operate
220 * synchronously from the transmit clock and frame sync. We need to make
221 * sure that the TX signlas are enabled when starting reception.
222 */
223 if (mcasp_is_synchronous(mcasp)) {
f68205a7
PU		 224 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
225 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
34a2a80f 226 mcasp_set_clk_pdir(mcasp, true);
4dcb5a0b
PU		 227 }
228
44982735 229 /* Activate serializer(s) */
1003c27a 230 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
f68205a7 231 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
44982735 232 /* Release RX state machine */
f68205a7 233 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
44982735 234 /* Release Frame Sync generator */
f68205a7 235 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
4dcb5a0b 236 if (mcasp_is_synchronous(mcasp))
f68205a7 237 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
a7a3324a
MLC		 238
239 /* enable receive IRQs */
240 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
241 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
b67f4487
C		 242}
243
70091a3e 244static void mcasp_start_tx(struct davinci_mcasp *mcasp)
b67f4487 245{
6a99fb5f
C		 246 u32 cnt;
247
bb372af0
PU		 248 if (mcasp->txnumevt) { /* enable FIFO */
249 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
250
251 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
252 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
253 }
254
36bcecd0 255 /* Start clocks */
f68205a7
PU		 256 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
257 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
ca3d9433
PU		 258 mcasp_set_clk_pdir(mcasp, true);
259
36bcecd0 260 /* Activate serializer(s) */
1003c27a 261 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
f68205a7 262 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
b67f4487 263
36bcecd0 264 /* wait for XDATA to be cleared */
6a99fb5f 265 cnt = 0;
e2a0c9fa
PU		 266 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
267 (cnt < 100000))
6a99fb5f
C		 268 cnt++;
269
ca3d9433
PU		 270 mcasp_set_axr_pdir(mcasp, true);
271
36bcecd0
PU		 272 /* Release TX state machine */
273 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
274 /* Release Frame Sync generator */
275 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
a7a3324a
MLC		 276
277 /* enable transmit IRQs */
278 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
279 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
b67f4487
C		 280}
281
70091a3e 282static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
b67f4487 283{
4dcb5a0b
PU		 284 mcasp->streams++;
285
bb372af0 286 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
70091a3e 287 mcasp_start_tx(mcasp);
bb372af0 288 else
70091a3e 289 mcasp_start_rx(mcasp);
b67f4487
C		 290}
291
70091a3e 292static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
b67f4487 293{
a7a3324a
MLC		 294 /* disable IRQ sources */
295 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
296 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
297
4dcb5a0b
PU		 298 /*
299 * In synchronous mode stop the TX clocks if no other stream is
300 * running
301 */
ca3d9433
PU		 302 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
303 mcasp_set_clk_pdir(mcasp, false);
f68205a7 304 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
ca3d9433 305 }
4dcb5a0b 306
f68205a7
PU		 307 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
308 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
0380866a
PU		 309
310 if (mcasp->rxnumevt) { /* disable FIFO */
311 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
312
313 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
314 }
b67f4487
C		 315}
316
70091a3e 317static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
b67f4487 318{
4dcb5a0b
PU		 319 u32 val = 0;
320
a7a3324a
MLC		 321 /* disable IRQ sources */
322 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
323 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
324
4dcb5a0b
PU		 325 /*
326 * In synchronous mode keep TX clocks running if the capture stream is
327 * still running.
328 */
329 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
330 val = TXHCLKRST | TXCLKRST | TXFSRST;
ca3d9433
PU		 331 else
332 mcasp_set_clk_pdir(mcasp, false);
333
4dcb5a0b 334
f68205a7
PU		 335 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
336 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
0380866a
PU		 337
338 if (mcasp->txnumevt) { /* disable FIFO */
339 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
340
341 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
342 }
ca3d9433
PU		 343
344 mcasp_set_axr_pdir(mcasp, false);
b67f4487
C		 345}
346
70091a3e 347static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
b67f4487 348{
4dcb5a0b
PU		 349 mcasp->streams--;
350
0380866a 351 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
70091a3e 352 mcasp_stop_tx(mcasp);
0380866a 353 else
70091a3e 354 mcasp_stop_rx(mcasp);
b67f4487
C		 355}
356
a7a3324a
MLC		 357static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
358{
359 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
360 struct snd_pcm_substream *substream;
361 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
362 u32 handled_mask = 0;
363 u32 stat;
364
365 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
366 if (stat & XUNDRN & irq_mask) {
367 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
368 handled_mask |= XUNDRN;
369
370 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
dae35d1f
TI		 371 if (substream)
372 snd_pcm_stop_xrun(substream);
a7a3324a
MLC		 373 }
374
375 if (!handled_mask)
376 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
377 stat);
378
379 if (stat & XRERR)
380 handled_mask |= XRERR;
381
382 /* Ack the handled event only */
383 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
384
385 return IRQ_RETVAL(handled_mask);
386}
387
388static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
389{
390 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
391 struct snd_pcm_substream *substream;
392 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
393 u32 handled_mask = 0;
394 u32 stat;
395
396 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
397 if (stat & ROVRN & irq_mask) {
398 dev_warn(mcasp->dev, "Receive buffer overflow\n");
399 handled_mask |= ROVRN;
400
401 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
dae35d1f
TI		 402 if (substream)
403 snd_pcm_stop_xrun(substream);
a7a3324a
MLC		 404 }
405
406 if (!handled_mask)
407 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
408 stat);
409
410 if (stat & XRERR)
411 handled_mask |= XRERR;
412
413 /* Ack the handled event only */
414 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
415
416 return IRQ_RETVAL(handled_mask);
417}
418
5a1b8a80
PU		 419static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
420{
421 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
422 irqreturn_t ret = IRQ_NONE;
423
424 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
425 ret = davinci_mcasp_tx_irq_handler(irq, data);
426
427 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
428 ret |= davinci_mcasp_rx_irq_handler(irq, data);
429
430 return ret;
431}
432
b67f4487
C		 433static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
434 unsigned int fmt)
435{
70091a3e 436 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1d17a04e 437 int ret = 0;
6dfa9a4e 438 u32 data_delay;
83f12503 439 bool fs_pol_rising;
ffd950f7 440 bool inv_fs = false;
b67f4487 441
4a11ff26
PU		 442 if (!fmt)
443 return 0;
444
1d17a04e 445 pm_runtime_get_sync(mcasp->dev);
5296cf2d 446 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
188edc59
PU		 447 case SND_SOC_DAIFMT_DSP_A:
448 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
449 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
188edc59
PU		 450 /* 1st data bit occur one ACLK cycle after the frame sync */
451 data_delay = 1;
452 break;
5296cf2d
DM		 453 case SND_SOC_DAIFMT_DSP_B:
454 case SND_SOC_DAIFMT_AC97:
f68205a7
PU		 455 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
456 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
6dfa9a4e
PU		 457 /* No delay after FS */
458 data_delay = 0;
5296cf2d 459 break;
ffd950f7 460 case SND_SOC_DAIFMT_I2S:
5296cf2d 461 /* configure a full-word SYNC pulse (LRCLK) */
f68205a7
PU		 462 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
463 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
6dfa9a4e
PU		 464 /* 1st data bit occur one ACLK cycle after the frame sync */
465 data_delay = 1;
ffd950f7
PU		 466 /* FS need to be inverted */
467 inv_fs = true;
5296cf2d 468 break;
423761e0
PU		 469 case SND_SOC_DAIFMT_LEFT_J:
470 /* configure a full-word SYNC pulse (LRCLK) */
471 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
472 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
473 /* No delay after FS */
474 data_delay = 0;
475 break;
ffd950f7
PU		 476 default:
477 ret = -EINVAL;
478 goto out;
5296cf2d
DM		 479 }
480
6dfa9a4e
PU		 481 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
482 FSXDLY(3));
483 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
484 FSRDLY(3));
485
b67f4487
C		 486 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
487 case SND_SOC_DAIFMT_CBS_CFS:
488 /* codec is clock and frame slave */
f68205a7
PU		 489 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
490 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
b67f4487 491
f68205a7
PU		 492 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
493 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
b67f4487 494
ca3d9433
PU		 495 /* BCLK */
496 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
497 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
498 /* Frame Sync */
499 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
500 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
501
ab8b14b6 502 mcasp->bclk_master = 1;
b67f4487 503 break;
226e2f1b
PU		 504 case SND_SOC_DAIFMT_CBS_CFM:
505 /* codec is clock slave and frame master */
506 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
507 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
508
509 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
510 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
511
ca3d9433
PU		 512 /* BCLK */
513 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
514 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
515 /* Frame Sync */
516 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
517 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
518
226e2f1b
PU		 519 mcasp->bclk_master = 1;
520 break;
517ee6cf
C		 521 case SND_SOC_DAIFMT_CBM_CFS:
522 /* codec is clock master and frame slave */
f68205a7
PU		 523 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
524 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
517ee6cf 525
f68205a7
PU		 526 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
527 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
517ee6cf 528
ca3d9433
PU		 529 /* BCLK */
530 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
531 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
532 /* Frame Sync */
533 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
534 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
535
ab8b14b6 536 mcasp->bclk_master = 0;
517ee6cf 537 break;
b67f4487
C		 538 case SND_SOC_DAIFMT_CBM_CFM:
539 /* codec is clock and frame master */
f68205a7
PU		 540 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
541 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
b67f4487 542
f68205a7
PU		 543 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
544 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
b67f4487 545
ca3d9433
PU		 546 /* BCLK */
547 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
548 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
549 /* Frame Sync */
550 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
551 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
552
ab8b14b6 553 mcasp->bclk_master = 0;
b67f4487 554 break;
b67f4487 555 default:
1d17a04e
PU		 556 ret = -EINVAL;
557 goto out;
b67f4487
C		 558 }
559
560 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
561 case SND_SOC_DAIFMT_IB_NF:
f68205a7 562 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 563 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 564 fs_pol_rising = true;
b67f4487 565 break;
b67f4487 566 case SND_SOC_DAIFMT_NB_IF:
f68205a7 567 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 568 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 569 fs_pol_rising = false;
b67f4487 570 break;
b67f4487 571 case SND_SOC_DAIFMT_IB_IF:
f68205a7 572 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 573 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 574 fs_pol_rising = false;
b67f4487 575 break;
b67f4487 576 case SND_SOC_DAIFMT_NB_NF:
f68205a7 577 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
f68205a7 578 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 579 fs_pol_rising = true;
b67f4487 580 break;
b67f4487 581 default:
1d17a04e 582 ret = -EINVAL;
83f12503
PU		 583 goto out;
584 }
585
ffd950f7
PU		 586 if (inv_fs)
587 fs_pol_rising = !fs_pol_rising;
588
83f12503
PU		 589 if (fs_pol_rising) {
590 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
591 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
592 } else {
593 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
594 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
b67f4487 595 }
4a11ff26
PU		 596
597 mcasp->dai_fmt = fmt;
1d17a04e 598out:
6afda7f5 599 pm_runtime_put(mcasp->dev);
1d17a04e 600 return ret;
b67f4487
C		 601}
602
226e73e2 603static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
8813543e 604 int div, bool explicit)
4ed8c9b7 605{
6afda7f5 606 pm_runtime_get_sync(mcasp->dev);
4ed8c9b7 607 switch (div_id) {
20d4b107 608 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
f68205a7 609 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
4ed8c9b7 610 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
f68205a7 611 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
4ed8c9b7
DM		 612 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
613 break;
614
20d4b107 615 case MCASP_CLKDIV_BCLK: /* BCLK divider */
f68205a7 616 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
4ed8c9b7 617 ACLKXDIV(div - 1), ACLKXDIV_MASK);
f68205a7 618 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
4ed8c9b7 619 ACLKRDIV(div - 1), ACLKRDIV_MASK);
8813543e
JS		 620 if (explicit)
621 mcasp->bclk_div = div;
4ed8c9b7
DM		 622 break;
623
20d4b107
PU		 624 case MCASP_CLKDIV_BCLK_FS_RATIO:
625 /*
14a998be
JS		 626 * BCLK/LRCLK ratio descries how many bit-clock cycles
627 * fit into one frame. The clock ratio is given for a
628 * full period of data (for I2S format both left and
629 * right channels), so it has to be divided by number
630 * of tdm-slots (for I2S - divided by 2).
631 * Instead of storing this ratio, we calculate a new
632 * tdm_slot width by dividing the the ratio by the
633 * number of configured tdm slots.
634 */
635 mcasp->slot_width = div / mcasp->tdm_slots;
636 if (div % mcasp->tdm_slots)
637 dev_warn(mcasp->dev,
638 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
639 __func__, div, mcasp->tdm_slots);
1b3bc060
DM		 640 break;
641
4ed8c9b7
DM		 642 default:
643 return -EINVAL;
644 }
645
6afda7f5 646 pm_runtime_put(mcasp->dev);
4ed8c9b7
DM		 647 return 0;
648}
649
8813543e
JS		 650static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
651 int div)
652{
226e73e2
PU		 653 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
654
655 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
8813543e
JS		 656}
657
5b66aa2d
DM		 658static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
659 unsigned int freq, int dir)
660{
70091a3e 661 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
5b66aa2d 662
6afda7f5 663 pm_runtime_get_sync(mcasp->dev);
5b66aa2d 664 if (dir == SND_SOC_CLOCK_OUT) {
f68205a7
PU		 665 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
666 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
ca3d9433 667 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
5b66aa2d 668 } else {
f68205a7
PU		 669 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
670 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
ca3d9433 671 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
5b66aa2d
DM		 672 }
673
ab8b14b6
JS		 674 mcasp->sysclk_freq = freq;
675
6afda7f5 676 pm_runtime_put(mcasp->dev);
5b66aa2d
DM		 677 return 0;
678}
679
dd55ff83
JS		 680/* All serializers must have equal number of channels */
681static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
682 int serializers)
683{
684 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
685 unsigned int *list = (unsigned int *) cl->list;
686 int slots = mcasp->tdm_slots;
687 int i, count = 0;
688
689 if (mcasp->tdm_mask[stream])
690 slots = hweight32(mcasp->tdm_mask[stream]);
691
e4798d26 692 for (i = 1; i <= slots; i++)
dd55ff83
JS		 693 list[count++] = i;
694
695 for (i = 2; i <= serializers; i++)
696 list[count++] = i*slots;
697
698 cl->count = count;
699
700 return 0;
701}
702
703static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
704{
705 int rx_serializers = 0, tx_serializers = 0, ret, i;
706
707 for (i = 0; i < mcasp->num_serializer; i++)
708 if (mcasp->serial_dir[i] == TX_MODE)
709 tx_serializers++;
710 else if (mcasp->serial_dir[i] == RX_MODE)
711 rx_serializers++;
712
713 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
714 tx_serializers);
715 if (ret)
716 return ret;
717
718 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
719 rx_serializers);
720
721 return ret;
722}
723
724
725static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
726 unsigned int tx_mask,
727 unsigned int rx_mask,
728 int slots, int slot_width)
729{
730 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
731
732 dev_dbg(mcasp->dev,
733 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
734 __func__, tx_mask, rx_mask, slots, slot_width);
735
736 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
737 dev_err(mcasp->dev,
738 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
739 tx_mask, rx_mask, slots);
740 return -EINVAL;
741 }
742
743 if (slot_width &&
744 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
745 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
746 __func__, slot_width);
747 return -EINVAL;
748 }
749
750 mcasp->tdm_slots = slots;
1bdd5932
AD		 751 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
752 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
dd55ff83
JS		 753 mcasp->slot_width = slot_width;
754
755 return davinci_mcasp_set_ch_constraints(mcasp);
756}
757
70091a3e 758static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
14a998be 759 int sample_width)
b67f4487 760{
ba764b3d 761 u32 fmt;
14a998be
JS		 762 u32 tx_rotate = (sample_width / 4) & 0x7;
763 u32 mask = (1ULL << sample_width) - 1;
764 u32 slot_width = sample_width;
765
fe0a29e1
PU		 766 /*
767 * For captured data we should not rotate, inversion and masking is
768 * enoguh to get the data to the right position:
769 * Format data from bus after reverse (XRBUF)
770 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
771 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
772 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
773 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
774 */
775 u32 rx_rotate = 0;
b67f4487 776
1b3bc060 777 /*
14a998be
JS		 778 * Setting the tdm slot width either with set_clkdiv() or
779 * set_tdm_slot() allows us to for example send 32 bits per
780 * channel to the codec, while only 16 of them carry audio
781 * payload.
1b3bc060 782 */
14a998be 783 if (mcasp->slot_width) {
d742b925 784 /*
14a998be
JS		 785 * When we have more bclk then it is needed for the
786 * data, we need to use the rotation to move the
787 * received samples to have correct alignment.
d742b925 788 */
14a998be
JS		 789 slot_width = mcasp->slot_width;
790 rx_rotate = (slot_width - sample_width) / 4;
d742b925 791 }
1b3bc060 792
ba764b3d 793 /* mapping of the XSSZ bit-field as described in the datasheet */
14a998be 794 fmt = (slot_width >> 1) - 1;
b67f4487 795
70091a3e 796 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
f68205a7
PU		 797 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
798 RXSSZ(0x0F));
799 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
800 TXSSZ(0x0F));
801 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
802 TXROT(7));
803 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
804 RXROT(7));
805 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
f5023af6
YY		 806 }
807
f68205a7 808 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
0c31cf3e 809
b67f4487
C		 810 return 0;
811}
812
662ffae9 813static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
dd093a0f 814 int period_words, int channels)
b67f4487 815{
5f04c603 816 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
b67f4487 817 int i;
6a99fb5f
C		 818 u8 tx_ser = 0;
819 u8 rx_ser = 0;
70091a3e 820 u8 slots = mcasp->tdm_slots;
2952b27e 821 u8 max_active_serializers = (channels + slots - 1) / slots;
72383192 822 int active_serializers, numevt;
487dce88 823 u32 reg;
b67f4487 824 /* Default configuration */
40448e5e 825 if (mcasp->version < MCASP_VERSION_3)
f68205a7 826 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
b67f4487 827
b67f4487 828 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
f68205a7
PU		 829 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
830 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
b67f4487 831 } else {
f68205a7
PU		 832 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
833 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
b67f4487
C		 834 }
835
70091a3e 836 for (i = 0; i < mcasp->num_serializer; i++) {
f68205a7
PU		 837 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
838 mcasp->serial_dir[i]);
70091a3e 839 if (mcasp->serial_dir[i] == TX_MODE &&
2952b27e 840 tx_ser < max_active_serializers) {
19db62ea 841 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
bc184549 842 mcasp->dismod, DISMOD_MASK);
ca3d9433 843 set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
6a99fb5f 844 tx_ser++;
70091a3e 845 } else if (mcasp->serial_dir[i] == RX_MODE &&
2952b27e 846 rx_ser < max_active_serializers) {
ca3d9433 847 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
6a99fb5f 848 rx_ser++;
5dd17a3c
PU		 849 } else {
850 /* Inactive or unused pin, set it to inactive */
f68205a7
PU		 851 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
852 SRMOD_INACTIVE, SRMOD_MASK);
5dd17a3c
PU		 853 /* If unused, set DISMOD for the pin */
854 if (mcasp->serial_dir[i] != INACTIVE_MODE)
855 mcasp_mod_bits(mcasp,
856 DAVINCI_MCASP_XRSRCTL_REG(i),
857 mcasp->dismod, DISMOD_MASK);
ca3d9433 858 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
6a99fb5f
C		 859 }
860 }
861
0bf0e8ae
PU		 862 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
863 active_serializers = tx_ser;
864 numevt = mcasp->txnumevt;
865 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
866 } else {
867 active_serializers = rx_ser;
868 numevt = mcasp->rxnumevt;
869 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
870 }
ecf327c7 871
0bf0e8ae 872 if (active_serializers < max_active_serializers) {
70091a3e 873 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
0bf0e8ae
PU		 874 "enabled in mcasp (%d)\n", channels,
875 active_serializers * slots);
ecf327c7
DM		 876 return -EINVAL;
877 }
878
0bf0e8ae 879 /* AFIFO is not in use */
5f04c603
PU		 880 if (!numevt) {
881 /* Configure the burst size for platform drivers */
33445643
PU		 882 if (active_serializers > 1) {
883 /*
884 * If more than one serializers are in use we have one
885 * DMA request to provide data for all serializers.
886 * For example if three serializers are enabled the DMA
887 * need to transfer three words per DMA request.
888 */
33445643
PU		 889 dma_data->maxburst = active_serializers;
890 } else {
33445643
PU		 891 dma_data->maxburst = 0;
892 }
0bf0e8ae 893 return 0;
5f04c603 894 }
6a99fb5f 895
dd093a0f
PU		 896 if (period_words % active_serializers) {
897 dev_err(mcasp->dev, "Invalid combination of period words and "
898 "active serializers: %d, %d\n", period_words,
899 active_serializers);
900 return -EINVAL;
901 }
902
903 /*
904 * Calculate the optimal AFIFO depth for platform side:
905 * The number of words for numevt need to be in steps of active
906 * serializers.
907 */
72383192
PU		 908 numevt = (numevt / active_serializers) * active_serializers;
909
dd093a0f
PU		 910 while (period_words % numevt && numevt > 0)
911 numevt -= active_serializers;
912 if (numevt <= 0)
0bf0e8ae 913 numevt = active_serializers;
487dce88 914
0bf0e8ae
PU		 915 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
916 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
2952b27e 917
5f04c603 918 /* Configure the burst size for platform drivers */
33445643
PU		 919 if (numevt == 1)
920 numevt = 0;
5f04c603
PU		 921 dma_data->maxburst = numevt;
922
2952b27e 923 return 0;
b67f4487
C		 924}
925
18a4f557
MLC		 926static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
927 int channels)
b67f4487
C		 928{
929 int i, active_slots;
18a4f557
MLC		 930 int total_slots;
931 int active_serializers;
b67f4487 932 u32 mask = 0;
cbc7956c 933 u32 busel = 0;
b67f4487 934
18a4f557
MLC		 935 total_slots = mcasp->tdm_slots;
936
937 /*
938 * If more than one serializer is needed, then use them with
dd55ff83
JS		 939 * all the specified tdm_slots. Otherwise, one serializer can
940 * cope with the transaction using just as many slots as there
941 * are channels in the stream.
18a4f557 942 */
dd55ff83
JS		 943 if (mcasp->tdm_mask[stream]) {
944 active_slots = hweight32(mcasp->tdm_mask[stream]);
945 active_serializers = (channels + active_slots - 1) /
946 active_slots;
fd14f443 947 if (active_serializers == 1)
dd55ff83 948 active_slots = channels;
fd14f443
PU		 949 for (i = 0; i < total_slots; i++) {
950 if ((1 << i) & mcasp->tdm_mask[stream]) {
951 mask |= (1 << i);
952 if (--active_slots <= 0)
953 break;
dd55ff83
JS		 954 }
955 }
956 } else {
957 active_serializers = (channels + total_slots - 1) / total_slots;
958 if (active_serializers == 1)
959 active_slots = channels;
960 else
961 active_slots = total_slots;
b67f4487 962
dd55ff83
JS		 963 for (i = 0; i < active_slots; i++)
964 mask |= (1 << i);
965 }
5dd17a3c 966
f68205a7 967 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
6a99fb5f 968
cbc7956c
PU		 969 if (!mcasp->dat_port)
970 busel = TXSEL;
971
dd55ff83
JS		 972 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
973 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
974 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
975 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
976 FSXMOD(total_slots), FSXMOD(0x1FF));
977 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
978 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
979 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
980 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
981 FSRMOD(total_slots), FSRMOD(0x1FF));
0ad7d3a0
PU		 982 /*
983 * If McASP is set to be TX/RX synchronous and the playback is
984 * not running already we need to configure the TX slots in
985 * order to have correct FSX on the bus
986 */
987 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
988 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
989 FSXMOD(total_slots), FSXMOD(0x1FF));
dd55ff83 990 }
2c56c4c2
PU		 991
992 return 0;
b67f4487
C		 993}
994
995/* S/PDIF */
6479285d
DM		 996static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
997 unsigned int rate)
b67f4487 998{
6479285d
DM		 999 u32 cs_value = 0;
1000 u8 *cs_bytes = (u8*) &cs_value;
1001
b67f4487
C		 1002 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
1003 and LSB first */
f68205a7 1004 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
b67f4487
C		 1005
1006 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
f68205a7 1007 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
b67f4487
C		 1008
1009 /* Set the TX tdm : for all the slots */
f68205a7 1010 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
b67f4487
C		 1011
1012 /* Set the TX clock controls : div = 1 and internal */
f68205a7 1013 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
b67f4487 1014
f68205a7 1015 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
b67f4487
C		 1016
1017 /* Only 44100 and 48000 are valid, both have the same setting */
f68205a7 1018 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
b67f4487
C		 1019
1020 /* Enable the DIT */
f68205a7 1021 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
2c56c4c2 1022
6479285d
DM		 1023 /* Set S/PDIF channel status bits */
1024 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
1025 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
1026
1027 switch (rate) {
1028 case 22050:
1029 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
1030 break;
1031 case 24000:
1032 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
1033 break;
1034 case 32000:
1035 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
1036 break;
1037 case 44100:
1038 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
1039 break;
1040 case 48000:
1041 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
1042 break;
1043 case 88200:
1044 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
1045 break;
1046 case 96000:
1047 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
1048 break;
1049 case 176400:
1050 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
1051 break;
1052 case 192000:
1053 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
1054 break;
1055 default:
1056 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
1057 return -EINVAL;
1058 }
1059
1060 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
1061 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
1062
2c56c4c2 1063 return 0;
b67f4487
C		 1064}
1065
a75a053f 1066static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
764958f2 1067 unsigned int sysclk_freq,
3e9bee11 1068 unsigned int bclk_freq, bool set)
a75a053f 1069{
ddecd149
PU		 1070 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1071 int div = sysclk_freq / bclk_freq;
1072 int rem = sysclk_freq % bclk_freq;
764958f2 1073 int error_ppm;
ddecd149
PU		 1074 int aux_div = 1;
1075
1076 if (div > (ACLKXDIV_MASK + 1)) {
1077 if (reg & AHCLKXE) {
1078 aux_div = div / (ACLKXDIV_MASK + 1);
1079 if (div % (ACLKXDIV_MASK + 1))
1080 aux_div++;
1081
1082 sysclk_freq /= aux_div;
1083 div = sysclk_freq / bclk_freq;
1084 rem = sysclk_freq % bclk_freq;
1085 } else if (set) {
1086 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1087 sysclk_freq);
1088 }
1089 }
a75a053f
JS		 1090
1091 if (rem != 0) {
1092 if (div == 0 ||
ddecd149
PU		 1093 ((sysclk_freq / div) - bclk_freq) >
1094 (bclk_freq - (sysclk_freq / (div+1)))) {
a75a053f
JS		 1095 div++;
1096 rem = rem - bclk_freq;
1097 }
1098 }
3e9bee11
PU		 1099 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1100 (int)bclk_freq)) / div - 1000000;
a75a053f 1101
3e9bee11
PU		 1102 if (set) {
1103 if (error_ppm)
1104 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1105 error_ppm);
1106
1107 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
ddecd149
PU		 1108 if (reg & AHCLKXE)
1109 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1110 aux_div, 0);
3e9bee11 1111 }
a75a053f 1112
3e9bee11 1113 return error_ppm;
a75a053f
JS		 1114}
1115
5fcb457a
PU		 1116static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1117{
1118 if (!mcasp->txnumevt)
1119 return 0;
1120
1121 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1122}
1123
1124static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1125{
1126 if (!mcasp->rxnumevt)
1127 return 0;
1128
1129 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1130}
1131
1132static snd_pcm_sframes_t davinci_mcasp_delay(
1133 struct snd_pcm_substream *substream,
1134 struct snd_soc_dai *cpu_dai)
1135{
1136 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1137 u32 fifo_use;
1138
1139 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1140 fifo_use = davinci_mcasp_tx_delay(mcasp);
1141 else
1142 fifo_use = davinci_mcasp_rx_delay(mcasp);
1143
1144 /*
1145 * Divide the used locations with the channel count to get the
1146 * FIFO usage in samples (don't care about partial samples in the
1147 * buffer).
1148 */
1149 return fifo_use / substream->runtime->channels;
1150}
1151
b67f4487
C		 1152static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1153 struct snd_pcm_hw_params *params,
1154 struct snd_soc_dai *cpu_dai)
1155{
70091a3e 1156 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487 1157 int word_length;
a7e46bd9 1158 int channels = params_channels(params);
dd093a0f 1159 int period_size = params_period_size(params);
2c56c4c2 1160 int ret;
ab8b14b6 1161
4a11ff26
PU		 1162 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1163 if (ret)
1164 return ret;
1165
8267525c
DM		 1166 /*
1167 * If mcasp is BCLK master, and a BCLK divider was not provided by
1168 * the machine driver, we need to calculate the ratio.
1169 */
1170 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1f114f77 1171 int slots = mcasp->tdm_slots;
a75a053f
JS		 1172 int rate = params_rate(params);
1173 int sbits = params_width(params);
a75a053f 1174
dd55ff83
JS		 1175 if (mcasp->slot_width)
1176 sbits = mcasp->slot_width;
1177
764958f2
PU		 1178 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
1179 rate * sbits * slots, true);
ab8b14b6
JS		 1180 }
1181
dd093a0f
PU		 1182 ret = mcasp_common_hw_param(mcasp, substream->stream,
1183 period_size * channels, channels);
0f7d9a63
PU		 1184 if (ret)
1185 return ret;
1186
70091a3e 1187 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
6479285d 1188 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
b67f4487 1189 else
18a4f557
MLC		 1190 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1191 channels);
2c56c4c2
PU		 1192
1193 if (ret)
1194 return ret;
b67f4487
C		 1195
1196 switch (params_format(params)) {
0a9d1385 1197 case SNDRV_PCM_FORMAT_U8:
b67f4487 1198 case SNDRV_PCM_FORMAT_S8:
ba764b3d 1199 word_length = 8;
b67f4487
C		 1200 break;
1201
0a9d1385 1202 case SNDRV_PCM_FORMAT_U16_LE:
b67f4487 1203 case SNDRV_PCM_FORMAT_S16_LE:
ba764b3d 1204 word_length = 16;
b67f4487
C		 1205 break;
1206
21eb24d8
DM		 1207 case SNDRV_PCM_FORMAT_U24_3LE:
1208 case SNDRV_PCM_FORMAT_S24_3LE:
ba764b3d 1209 word_length = 24;
21eb24d8
DM		 1210 break;
1211
6b7fa011
DM		 1212 case SNDRV_PCM_FORMAT_U24_LE:
1213 case SNDRV_PCM_FORMAT_S24_LE:
182bef86
PU		 1214 word_length = 24;
1215 break;
1216
0a9d1385 1217 case SNDRV_PCM_FORMAT_U32_LE:
b67f4487 1218 case SNDRV_PCM_FORMAT_S32_LE:
ba764b3d 1219 word_length = 32;
b67f4487
C		 1220 break;
1221
1222 default:
1223 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1224 return -EINVAL;
1225 }
6a99fb5f 1226
70091a3e 1227 davinci_config_channel_size(mcasp, word_length);
b67f4487 1228
11277833
PU		 1229 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1230 mcasp->channels = channels;
1231
b67f4487
C		 1232 return 0;
1233}
1234
1235static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1236 int cmd, struct snd_soc_dai *cpu_dai)
1237{
70091a3e 1238 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487
C		 1239 int ret = 0;
1240
1241 switch (cmd) {
b67f4487 1242 case SNDRV_PCM_TRIGGER_RESUME:
e473b847
C		 1243 case SNDRV_PCM_TRIGGER_START:
1244 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
70091a3e 1245 davinci_mcasp_start(mcasp, substream->stream);
b67f4487 1246 break;
b67f4487 1247 case SNDRV_PCM_TRIGGER_SUSPEND:
a47979b5 1248 case SNDRV_PCM_TRIGGER_STOP:
b67f4487 1249 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
70091a3e 1250 davinci_mcasp_stop(mcasp, substream->stream);
b67f4487
C		 1251 break;
1252
1253 default:
1254 ret = -EINVAL;
1255 }
1256
1257 return ret;
1258}
1259
1e112c35
PU		 1260static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1261 struct snd_pcm_hw_rule *rule)
1262{
1263 struct davinci_mcasp_ruledata *rd = rule->private;
1264 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1265 struct snd_mask nfmt;
1266 int i, slot_width;
1267
1268 snd_mask_none(&nfmt);
1269 slot_width = rd->mcasp->slot_width;
1270
1271 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1272 if (snd_mask_test(fmt, i)) {
1273 if (snd_pcm_format_width(i) <= slot_width) {
1274 snd_mask_set(&nfmt, i);
1275 }
1276 }
1277 }
1278
1279 return snd_mask_refine(fmt, &nfmt);
1280}
1281
a75a053f
JS		 1282static const unsigned int davinci_mcasp_dai_rates[] = {
1283 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1284 88200, 96000, 176400, 192000,
1285};
1286
1287#define DAVINCI_MAX_RATE_ERROR_PPM 1000
1288
1289static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1290 struct snd_pcm_hw_rule *rule)
1291{
1292 struct davinci_mcasp_ruledata *rd = rule->private;
1293 struct snd_interval *ri =
1294 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1295 int sbits = params_width(params);
1f114f77 1296 int slots = rd->mcasp->tdm_slots;
518f6bab
JS		 1297 struct snd_interval range;
1298 int i;
a75a053f 1299
dd55ff83
JS		 1300 if (rd->mcasp->slot_width)
1301 sbits = rd->mcasp->slot_width;
1302
518f6bab
JS		 1303 snd_interval_any(&range);
1304 range.empty = 1;
a75a053f
JS		 1305
1306 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
518f6bab 1307 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
764958f2
PU		 1308 uint bclk_freq = sbits * slots *
1309 davinci_mcasp_dai_rates[i];
1310 unsigned int sysclk_freq;
a75a053f
JS		 1311 int ppm;
1312
764958f2
PU		 1313 if (rd->mcasp->auxclk_fs_ratio)
1314 sysclk_freq = davinci_mcasp_dai_rates[i] *
1315 rd->mcasp->auxclk_fs_ratio;
1316 else
1317 sysclk_freq = rd->mcasp->sysclk_freq;
1318
1319 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1320 bclk_freq, false);
518f6bab
JS		 1321 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1322 if (range.empty) {
1323 range.min = davinci_mcasp_dai_rates[i];
1324 range.empty = 0;
1325 }
1326 range.max = davinci_mcasp_dai_rates[i];
1327 }
a75a053f
JS		 1328 }
1329 }
518f6bab 1330
a75a053f 1331 dev_dbg(rd->mcasp->dev,
518f6bab
JS		 1332 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1333 ri->min, ri->max, range.min, range.max, sbits, slots);
a75a053f 1334
518f6bab
JS		 1335 return snd_interval_refine(hw_param_interval(params, rule->var),
1336 &range);
a75a053f
JS		 1337}
1338
1339static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1340 struct snd_pcm_hw_rule *rule)
1341{
1342 struct davinci_mcasp_ruledata *rd = rule->private;
1343 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1344 struct snd_mask nfmt;
1345 int rate = params_rate(params);
1f114f77 1346 int slots = rd->mcasp->tdm_slots;
a75a053f
JS		 1347 int i, count = 0;
1348
1349 snd_mask_none(&nfmt);
1350
9be072a6 1351 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
a75a053f 1352 if (snd_mask_test(fmt, i)) {
dd55ff83 1353 uint sbits = snd_pcm_format_width(i);
764958f2 1354 unsigned int sysclk_freq;
a75a053f
JS		 1355 int ppm;
1356
764958f2
PU		 1357 if (rd->mcasp->auxclk_fs_ratio)
1358 sysclk_freq = rate *
1359 rd->mcasp->auxclk_fs_ratio;
1360 else
1361 sysclk_freq = rd->mcasp->sysclk_freq;
1362
dd55ff83
JS		 1363 if (rd->mcasp->slot_width)
1364 sbits = rd->mcasp->slot_width;
1365
764958f2 1366 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
3e9bee11
PU		 1367 sbits * slots * rate,
1368 false);
a75a053f
JS		 1369 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1370 snd_mask_set(&nfmt, i);
1371 count++;
1372 }
1373 }
1374 }
1375 dev_dbg(rd->mcasp->dev,
1f114f77
JS		 1376 "%d possible sample format for %d Hz and %d tdm slots\n",
1377 count, rate, slots);
a75a053f
JS		 1378
1379 return snd_mask_refine(fmt, &nfmt);
1380}
1381
d43c17da
PU		 1382static int davinci_mcasp_hw_rule_min_periodsize(
1383 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1384{
1385 struct snd_interval *period_size = hw_param_interval(params,
1386 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1387 struct snd_interval frames;
1388
1389 snd_interval_any(&frames);
1390 frames.min = 64;
1391 frames.integer = 1;
1392
1393 return snd_interval_refine(period_size, &frames);
1394}
1395
11277833
PU		 1396static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1397 struct snd_soc_dai *cpu_dai)
1398{
1399 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
4cd9db08
PU		 1400 struct davinci_mcasp_ruledata *ruledata =
1401 &mcasp->ruledata[substream->stream];
11277833 1402 u32 max_channels = 0;
1e112c35 1403 int i, dir, ret;
dd55ff83
JS		 1404 int tdm_slots = mcasp->tdm_slots;
1405
19357366
PU		 1406 /* Do not allow more then one stream per direction */
1407 if (mcasp->substreams[substream->stream])
1408 return -EBUSY;
11277833 1409
a7a3324a
MLC		 1410 mcasp->substreams[substream->stream] = substream;
1411
19357366
PU		 1412 if (mcasp->tdm_mask[substream->stream])
1413 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1414
11277833
PU		 1415 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1416 return 0;
1417
1418 /*
1419 * Limit the maximum allowed channels for the first stream:
1420 * number of serializers for the direction * tdm slots per serializer
1421 */
1422 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1423 dir = TX_MODE;
1424 else
1425 dir = RX_MODE;
1426
1427 for (i = 0; i < mcasp->num_serializer; i++) {
1428 if (mcasp->serial_dir[i] == dir)
1429 max_channels++;
1430 }
4cd9db08 1431 ruledata->serializers = max_channels;
1e112c35 1432 ruledata->mcasp = mcasp;
dd55ff83 1433 max_channels *= tdm_slots;
11277833
PU		 1434 /*
1435 * If the already active stream has less channels than the calculated
1436 * limnit based on the seirializers * tdm_slots, we need to use that as
1437 * a constraint for the second stream.
1438 * Otherwise (first stream or less allowed channels) we use the
1439 * calculated constraint.
1440 */
1441 if (mcasp->channels && mcasp->channels < max_channels)
1442 max_channels = mcasp->channels;
dd55ff83
JS		 1443 /*
1444 * But we can always allow channels upto the amount of
1445 * the available tdm_slots.
1446 */
1447 if (max_channels < tdm_slots)
1448 max_channels = tdm_slots;
11277833
PU		 1449
1450 snd_pcm_hw_constraint_minmax(substream->runtime,
1451 SNDRV_PCM_HW_PARAM_CHANNELS,
e4798d26 1452 0, max_channels);
a75a053f 1453
dd55ff83
JS		 1454 snd_pcm_hw_constraint_list(substream->runtime,
1455 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1456 &mcasp->chconstr[substream->stream]);
1457
1e112c35
PU		 1458 if (mcasp->slot_width) {
1459 /* Only allow formats require <= slot_width bits on the bus */
1460 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1461 SNDRV_PCM_HW_PARAM_FORMAT,
1462 davinci_mcasp_hw_rule_slot_width,
1463 ruledata,
1464 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1465 if (ret)
1466 return ret;
1467 }
5935a056 1468
a75a053f
JS		 1469 /*
1470 * If we rely on implicit BCLK divider setting we should
1471 * set constraints based on what we can provide.
1472 */
1473 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
a75a053f
JS		 1474 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1475 SNDRV_PCM_HW_PARAM_RATE,
1476 davinci_mcasp_hw_rule_rate,
4cd9db08 1477 ruledata,
1f114f77 1478 SNDRV_PCM_HW_PARAM_FORMAT, -1);
a75a053f
JS		 1479 if (ret)
1480 return ret;
1481 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1482 SNDRV_PCM_HW_PARAM_FORMAT,
1483 davinci_mcasp_hw_rule_format,
4cd9db08 1484 ruledata,
1f114f77 1485 SNDRV_PCM_HW_PARAM_RATE, -1);
a75a053f
JS		 1486 if (ret)
1487 return ret;
1488 }
1489
d43c17da
PU		 1490 snd_pcm_hw_rule_add(substream->runtime, 0,
1491 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1492 davinci_mcasp_hw_rule_min_periodsize, NULL,
1493 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1494
11277833
PU		 1495 return 0;
1496}
1497
1498static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1499 struct snd_soc_dai *cpu_dai)
1500{
1501 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1502
a7a3324a
MLC		 1503 mcasp->substreams[substream->stream] = NULL;
1504
11277833
PU		 1505 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1506 return;
1507
1508 if (!cpu_dai->active)
1509 mcasp->channels = 0;
1510}
1511
85e7652d 1512static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
11277833
PU		 1513 .startup = davinci_mcasp_startup,
1514 .shutdown = davinci_mcasp_shutdown,
b67f4487 1515 .trigger = davinci_mcasp_trigger,
5fcb457a 1516 .delay = davinci_mcasp_delay,
b67f4487
C		 1517 .hw_params = davinci_mcasp_hw_params,
1518 .set_fmt = davinci_mcasp_set_dai_fmt,
4ed8c9b7 1519 .set_clkdiv = davinci_mcasp_set_clkdiv,
5b66aa2d 1520 .set_sysclk = davinci_mcasp_set_sysclk,
dd55ff83 1521 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
b67f4487
C		 1522};
1523
d5902f69
PU		 1524static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1525{
1526 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1527
9759e7ef
PU		 1528 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1529 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
d5902f69
PU		 1530
1531 return 0;
1532}
1533
ed29cd5e
PU		 1534#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1535
0a9d1385
BG		 1536#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1537 SNDRV_PCM_FMTBIT_U8 | \
1538 SNDRV_PCM_FMTBIT_S16_LE | \
1539 SNDRV_PCM_FMTBIT_U16_LE | \
21eb24d8
DM		 1540 SNDRV_PCM_FMTBIT_S24_LE | \
1541 SNDRV_PCM_FMTBIT_U24_LE | \
1542 SNDRV_PCM_FMTBIT_S24_3LE | \
1543 SNDRV_PCM_FMTBIT_U24_3LE | \
0a9d1385
BG		 1544 SNDRV_PCM_FMTBIT_S32_LE | \
1545 SNDRV_PCM_FMTBIT_U32_LE)
1546
f0fba2ad 1547static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
b67f4487 1548 {
f0fba2ad 1549 .name = "davinci-mcasp.0",
d5902f69 1550 .probe = davinci_mcasp_dai_probe,
b67f4487 1551 .playback = {
e4798d26 1552 .channels_min = 1,
2952b27e 1553 .channels_max = 32 * 16,
b67f4487 1554 .rates = DAVINCI_MCASP_RATES,
0a9d1385 1555 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 1556 },
1557 .capture = {
e4798d26 1558 .channels_min = 1,
2952b27e 1559 .channels_max = 32 * 16,
b67f4487 1560 .rates = DAVINCI_MCASP_RATES,
0a9d1385 1561 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 1562 },
1563 .ops = &davinci_mcasp_dai_ops,
1564
d75249f5 1565 .symmetric_samplebits = 1,
295c3405 1566 .symmetric_rates = 1,
b67f4487
C		 1567 },
1568 {
58e48d97 1569 .name = "davinci-mcasp.1",
d5902f69 1570 .probe = davinci_mcasp_dai_probe,
b67f4487
C		 1571 .playback = {
1572 .channels_min = 1,
1573 .channels_max = 384,
1574 .rates = DAVINCI_MCASP_RATES,
0a9d1385 1575 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 1576 },
1577 .ops = &davinci_mcasp_dai_ops,
1578 },
1579
1580};
b67f4487 1581
eeef0eda
KM		 1582static const struct snd_soc_component_driver davinci_mcasp_component = {
1583 .name = "davinci-mcasp",
1584};
1585
256ba181 1586/* Some HW specific values and defaults. The rest is filled in from DT. */
d1debafc 1587static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
256ba181
JS		 1588 .tx_dma_offset = 0x400,
1589 .rx_dma_offset = 0x400,
256ba181
JS		 1590 .version = MCASP_VERSION_1,
1591};
1592
d1debafc 1593static struct davinci_mcasp_pdata da830_mcasp_pdata = {
256ba181
JS		 1594 .tx_dma_offset = 0x2000,
1595 .rx_dma_offset = 0x2000,
256ba181
JS		 1596 .version = MCASP_VERSION_2,
1597};
1598
d1debafc 1599static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
256ba181
JS		 1600 .tx_dma_offset = 0,
1601 .rx_dma_offset = 0,
256ba181
JS		 1602 .version = MCASP_VERSION_3,
1603};
1604
d1debafc 1605static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
9ac0013c
PU		 1606 /* The CFG port offset will be calculated if it is needed */
1607 .tx_dma_offset = 0,
1608 .rx_dma_offset = 0,
453c4990
PU		 1609 .version = MCASP_VERSION_4,
1610};
1611
3e3b8c34
HG		 1612static const struct of_device_id mcasp_dt_ids[] = {
1613 {
1614 .compatible = "ti,dm646x-mcasp-audio",
256ba181 1615 .data = &dm646x_mcasp_pdata,
3e3b8c34
HG		 1616 },
1617 {
1618 .compatible = "ti,da830-mcasp-audio",
256ba181 1619 .data = &da830_mcasp_pdata,
3e3b8c34 1620 },
e5ec69da 1621 {
3af9e031 1622 .compatible = "ti,am33xx-mcasp-audio",
b14899da 1623 .data = &am33xx_mcasp_pdata,
e5ec69da 1624 },
453c4990
PU		 1625 {
1626 .compatible = "ti,dra7-mcasp-audio",
1627 .data = &dra7_mcasp_pdata,
1628 },
3e3b8c34
HG		 1629 { /* sentinel */ }
1630};
1631MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1632
ae726e93
PU		 1633static int mcasp_reparent_fck(struct platform_device *pdev)
1634{
1635 struct device_node *node = pdev->dev.of_node;
1636 struct clk *gfclk, *parent_clk;
1637 const char *parent_name;
1638 int ret;
1639
1640 if (!node)
1641 return 0;
1642
1643 parent_name = of_get_property(node, "fck_parent", NULL);
1644 if (!parent_name)
1645 return 0;
1646
c670254f
PU		 1647 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1648
ae726e93
PU		 1649 gfclk = clk_get(&pdev->dev, "fck");
1650 if (IS_ERR(gfclk)) {
1651 dev_err(&pdev->dev, "failed to get fck\n");
1652 return PTR_ERR(gfclk);
1653 }
1654
1655 parent_clk = clk_get(NULL, parent_name);
1656 if (IS_ERR(parent_clk)) {
1657 dev_err(&pdev->dev, "failed to get parent clock\n");
1658 ret = PTR_ERR(parent_clk);
1659 goto err1;
1660 }
1661
1662 ret = clk_set_parent(gfclk, parent_clk);
1663 if (ret) {
1664 dev_err(&pdev->dev, "failed to reparent fck\n");
1665 goto err2;
1666 }
1667
1668err2:
1669 clk_put(parent_clk);
1670err1:
1671 clk_put(gfclk);
1672 return ret;
1673}
1674
d1debafc 1675static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
3e3b8c34
HG		 1676 struct platform_device *pdev)
1677{
1678 struct device_node *np = pdev->dev.of_node;
d1debafc 1679 struct davinci_mcasp_pdata *pdata = NULL;
3e3b8c34 1680 const struct of_device_id *match =
ea421eb1 1681 of_match_device(mcasp_dt_ids, &pdev->dev);
4023fe6f 1682 struct of_phandle_args dma_spec;
3e3b8c34
HG		 1683
1684 const u32 *of_serial_dir32;
3e3b8c34
HG		 1685 u32 val;
1686 int i, ret = 0;
1687
1688 if (pdev->dev.platform_data) {
1689 pdata = pdev->dev.platform_data;
bc184549 1690 pdata->dismod = DISMOD_LOW;
3e3b8c34
HG		 1691 return pdata;
1692 } else if (match) {
272ee030
PU		 1693 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1694 GFP_KERNEL);
1695 if (!pdata) {
272ee030
PU		 1696 ret = -ENOMEM;
1697 return pdata;
1698 }
3e3b8c34
HG		 1699 } else {
1700 /* control shouldn't reach here. something is wrong */
1701 ret = -EINVAL;
1702 goto nodata;
1703 }
1704
3e3b8c34
HG		 1705 ret = of_property_read_u32(np, "op-mode", &val);
1706 if (ret >= 0)
1707 pdata->op_mode = val;
1708
1709 ret = of_property_read_u32(np, "tdm-slots", &val);
2952b27e
MB		 1710 if (ret >= 0) {
1711 if (val < 2 || val > 32) {
1712 dev_err(&pdev->dev,
1713 "tdm-slots must be in rage [2-32]\n");
1714 ret = -EINVAL;
1715 goto nodata;
1716 }
1717
3e3b8c34 1718 pdata->tdm_slots = val;
2952b27e 1719 }
3e3b8c34 1720
3e3b8c34
HG		 1721 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1722 val /= sizeof(u32);
3e3b8c34 1723 if (of_serial_dir32) {
1427e660
PU		 1724 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1725 (sizeof(*of_serial_dir) * val),
1726 GFP_KERNEL);
3e3b8c34
HG		 1727 if (!of_serial_dir) {
1728 ret = -ENOMEM;
1729 goto nodata;
1730 }
1731
1427e660 1732 for (i = 0; i < val; i++)
3e3b8c34
HG		 1733 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1734
1427e660 1735 pdata->num_serializer = val;
3e3b8c34
HG		 1736 pdata->serial_dir = of_serial_dir;
1737 }
1738
4023fe6f
JS		 1739 ret = of_property_match_string(np, "dma-names", "tx");
1740 if (ret < 0)
1741 goto nodata;
1742
1743 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1744 &dma_spec);
1745 if (ret < 0)
1746 goto nodata;
1747
1748 pdata->tx_dma_channel = dma_spec.args[0];
1749
caa1d794
PU		 1750 /* RX is not valid in DIT mode */
1751 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1752 ret = of_property_match_string(np, "dma-names", "rx");
1753 if (ret < 0)
1754 goto nodata;
4023fe6f 1755
caa1d794
PU		 1756 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1757 &dma_spec);
1758 if (ret < 0)
1759 goto nodata;
4023fe6f 1760
caa1d794
PU		 1761 pdata->rx_dma_channel = dma_spec.args[0];
1762 }
4023fe6f 1763
3e3b8c34
HG		 1764 ret = of_property_read_u32(np, "tx-num-evt", &val);
1765 if (ret >= 0)
1766 pdata->txnumevt = val;
1767
1768 ret = of_property_read_u32(np, "rx-num-evt", &val);
1769 if (ret >= 0)
1770 pdata->rxnumevt = val;
1771
1772 ret = of_property_read_u32(np, "sram-size-playback", &val);
1773 if (ret >= 0)
1774 pdata->sram_size_playback = val;
1775
1776 ret = of_property_read_u32(np, "sram-size-capture", &val);
1777 if (ret >= 0)
1778 pdata->sram_size_capture = val;
1779
bc184549
PU		 1780 ret = of_property_read_u32(np, "dismod", &val);
1781 if (ret >= 0) {
1782 if (val == 0 || val == 2 || val == 3) {
1783 pdata->dismod = DISMOD_VAL(val);
1784 } else {
1785 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);
1786 pdata->dismod = DISMOD_LOW;
1787 }
1788 } else {
1789 pdata->dismod = DISMOD_LOW;
1790 }
1791
3e3b8c34
HG		 1792 return pdata;
1793
1794nodata:
1795 if (ret < 0) {
1796 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1797 ret);
1798 pdata = NULL;
1799 }
1800 return pdata;
1801}
1802
9fbd58cf
JS		 1803enum {
1804 PCM_EDMA,
1805 PCM_SDMA,
1806};
1807static const char *sdma_prefix = "ti,omap";
1808
1809static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1810{
1811 struct dma_chan *chan;
1812 const char *tmp;
1813 int ret = PCM_EDMA;
1814
1815 if (!mcasp->dev->of_node)
1816 return PCM_EDMA;
1817
1818 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1819 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1820 if (IS_ERR(chan)) {
1821 if (PTR_ERR(chan) != -EPROBE_DEFER)
1822 dev_err(mcasp->dev,
1823 "Can't verify DMA configuration (%ld)\n",
1824 PTR_ERR(chan));
1825 return PTR_ERR(chan);
1826 }
befff4fb
TI		 1827 if (WARN_ON(!chan->device || !chan->device->dev))
1828 return -EINVAL;
9fbd58cf
JS		 1829
1830 if (chan->device->dev->of_node)
1831 ret = of_property_read_string(chan->device->dev->of_node,
1832 "compatible", &tmp);
1833 else
1834 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1835
1836 dma_release_channel(chan);
1837 if (ret)
1838 return ret;
1839
1840 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1841 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1842 return PCM_SDMA;
1843
1844 return PCM_EDMA;
1845}
1846
9ac0013c
PU		 1847static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1848{
1849 int i;
1850 u32 offset = 0;
1851
1852 if (pdata->version != MCASP_VERSION_4)
1853 return pdata->tx_dma_offset;
1854
1855 for (i = 0; i < pdata->num_serializer; i++) {
1856 if (pdata->serial_dir[i] == TX_MODE) {
1857 if (!offset) {
1858 offset = DAVINCI_MCASP_TXBUF_REG(i);
1859 } else {
1860 pr_err("%s: Only one serializer allowed!\n",
1861 __func__);
1862 break;
1863 }
1864 }
1865 }
1866
1867 return offset;
1868}
1869
1870static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1871{
1872 int i;
1873 u32 offset = 0;
1874
1875 if (pdata->version != MCASP_VERSION_4)
1876 return pdata->rx_dma_offset;
1877
1878 for (i = 0; i < pdata->num_serializer; i++) {
1879 if (pdata->serial_dir[i] == RX_MODE) {
1880 if (!offset) {
1881 offset = DAVINCI_MCASP_RXBUF_REG(i);
1882 } else {
1883 pr_err("%s: Only one serializer allowed!\n",
1884 __func__);
1885 break;
1886 }
1887 }
1888 }
1889
1890 return offset;
1891}
1892
540f1ba7
PU		 1893#ifdef CONFIG_GPIOLIB
1894static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset)
1895{
1896 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1897
1898 if (mcasp->num_serializer && offset < mcasp->num_serializer &&
1899 mcasp->serial_dir[offset] != INACTIVE_MODE) {
1900 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset);
1901 return -EBUSY;
1902 }
1903
1904 /* Do not change the PIN yet */
1905
1906 return pm_runtime_get_sync(mcasp->dev);
1907}
1908
1909static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset)
1910{
1911 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1912
1913 /* Set the direction to input */
1914 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1915
1916 /* Set the pin as McASP pin */
1917 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1918
1919 pm_runtime_put_sync(mcasp->dev);
1920}
1921
1922static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip,
1923 unsigned offset, int value)
1924{
1925 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1926 u32 val;
1927
1928 if (value)
1929 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1930 else
1931 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1932
1933 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
1934 if (!(val & BIT(offset))) {
1935 /* Set the pin as GPIO pin */
1936 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1937
1938 /* Set the direction to output */
1939 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1940 }
1941
1942 return 0;
1943}
1944
1945static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset,
1946 int value)
1947{
1948 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1949
1950 if (value)
1951 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1952 else
1953 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
1954}
1955
1956static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip,
1957 unsigned offset)
1958{
1959 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1960 u32 val;
1961
1962 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
1963 if (!(val & BIT(offset))) {
1964 /* Set the direction to input */
1965 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1966
1967 /* Set the pin as GPIO pin */
1968 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1969 }
1970
1971 return 0;
1972}
1973
1974static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset)
1975{
1976 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1977 u32 val;
1978
1979 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
1980 if (val & BIT(offset))
1981 return 1;
1982
1983 return 0;
1984}
1985
1986static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip,
1987 unsigned offset)
1988{
1989 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1990 u32 val;
1991
1992 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
1993 if (val & BIT(offset))
1994 return 0;
1995
1996 return 1;
1997}
1998
1999static const struct gpio_chip davinci_mcasp_template_chip = {
2000 .owner = THIS_MODULE,
2001 .request = davinci_mcasp_gpio_request,
2002 .free = davinci_mcasp_gpio_free,
2003 .direction_output = davinci_mcasp_gpio_direction_out,
2004 .set = davinci_mcasp_gpio_set,
2005 .direction_input = davinci_mcasp_gpio_direction_in,
2006 .get = davinci_mcasp_gpio_get,
2007 .get_direction = davinci_mcasp_gpio_get_direction,
2008 .base = -1,
2009 .ngpio = 32,
2010};
2011
2012static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2013{
2014 if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller"))
2015 return 0;
2016
2017 mcasp->gpio_chip = davinci_mcasp_template_chip;
2018 mcasp->gpio_chip.label = dev_name(mcasp->dev);
2019 mcasp->gpio_chip.parent = mcasp->dev;
2020#ifdef CONFIG_OF_GPIO
2021 mcasp->gpio_chip.of_node = mcasp->dev->of_node;
2022#endif
2023
2024 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
2025}
2026
2027#else /* CONFIG_GPIOLIB */
2028static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2029{
2030 return 0;
2031}
2032#endif /* CONFIG_GPIOLIB */
2033
764958f2
PU		 2034static int davinci_mcasp_get_dt_params(struct davinci_mcasp *mcasp)
2035{
2036 struct device_node *np = mcasp->dev->of_node;
2037 int ret;
2038 u32 val;
2039
2040 if (!np)
2041 return 0;
2042
2043 ret = of_property_read_u32(np, "auxclk-fs-ratio", &val);
2044 if (ret >= 0)
2045 mcasp->auxclk_fs_ratio = val;
2046
2047 return 0;
2048}
2049
b67f4487
C		 2050static int davinci_mcasp_probe(struct platform_device *pdev)
2051{
8de131f2 2052 struct snd_dmaengine_dai_dma_data *dma_data;
508a43fd 2053 struct resource *mem, *res, *dat;
d1debafc 2054 struct davinci_mcasp_pdata *pdata;
70091a3e 2055 struct davinci_mcasp *mcasp;
a7a3324a 2056 char *irq_name;
9759e7ef 2057 int *dma;
a7a3324a 2058 int irq;
96d31e2b 2059 int ret;
b67f4487 2060
3e3b8c34
HG		 2061 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
2062 dev_err(&pdev->dev, "No platform data supplied\n");
2063 return -EINVAL;
2064 }
2065
70091a3e 2066 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
96d31e2b 2067 GFP_KERNEL);
70091a3e 2068 if (!mcasp)
b67f4487
C		 2069 return -ENOMEM;
2070
3e3b8c34
HG		 2071 pdata = davinci_mcasp_set_pdata_from_of(pdev);
2072 if (!pdata) {
2073 dev_err(&pdev->dev, "no platform data\n");
2074 return -EINVAL;
2075 }
2076
256ba181 2077 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
b67f4487 2078 if (!mem) {
70091a3e 2079 dev_warn(mcasp->dev,
256ba181
JS		 2080 "\"mpu\" mem resource not found, using index 0\n");
2081 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2082 if (!mem) {
2083 dev_err(&pdev->dev, "no mem resource?\n");
2084 return -ENODEV;
2085 }
b67f4487
C		 2086 }
2087
508a43fd
AL		 2088 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
2089 if (IS_ERR(mcasp->base))
2090 return PTR_ERR(mcasp->base);
b67f4487 2091
10884347 2092 pm_runtime_enable(&pdev->dev);
b67f4487 2093
70091a3e 2094 mcasp->op_mode = pdata->op_mode;
1a5923da
PU		 2095 /* sanity check for tdm slots parameter */
2096 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
2097 if (pdata->tdm_slots < 2) {
2098 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2099 pdata->tdm_slots);
2100 mcasp->tdm_slots = 2;
2101 } else if (pdata->tdm_slots > 32) {
2102 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2103 pdata->tdm_slots);
2104 mcasp->tdm_slots = 32;
2105 } else {
2106 mcasp->tdm_slots = pdata->tdm_slots;
2107 }
2108 }
2109
70091a3e 2110 mcasp->num_serializer = pdata->num_serializer;
61754717 2111#ifdef CONFIG_PM
a86854d0
KC		 2112 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
2113 mcasp->num_serializer, sizeof(u32),
f114ce60 2114 GFP_KERNEL);
4243e045
CJ		 2115 if (!mcasp->context.xrsr_regs) {
2116 ret = -ENOMEM;
2117 goto err;
2118 }
f114ce60 2119#endif
70091a3e
PU		 2120 mcasp->serial_dir = pdata->serial_dir;
2121 mcasp->version = pdata->version;
2122 mcasp->txnumevt = pdata->txnumevt;
2123 mcasp->rxnumevt = pdata->rxnumevt;
bc184549 2124 mcasp->dismod = pdata->dismod;
487dce88 2125
70091a3e 2126 mcasp->dev = &pdev->dev;
b67f4487 2127
5a1b8a80
PU		 2128 irq = platform_get_irq_byname(pdev, "common");
2129 if (irq >= 0) {
ab1fffe3 2130 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
5a1b8a80 2131 dev_name(&pdev->dev));
0c8b794c
AY		 2132 if (!irq_name) {
2133 ret = -ENOMEM;
2134 goto err;
2135 }
5a1b8a80
PU		 2136 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2137 davinci_mcasp_common_irq_handler,
8f511ffb
PU		 2138 IRQF_ONESHOT | IRQF_SHARED,
2139 irq_name, mcasp);
5a1b8a80
PU		 2140 if (ret) {
2141 dev_err(&pdev->dev, "common IRQ request failed\n");
2142 goto err;
2143 }
2144
2145 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2146 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2147 }
2148
a7a3324a
MLC		 2149 irq = platform_get_irq_byname(pdev, "rx");
2150 if (irq >= 0) {
ab1fffe3 2151 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
a7a3324a 2152 dev_name(&pdev->dev));
0c8b794c
AY		 2153 if (!irq_name) {
2154 ret = -ENOMEM;
2155 goto err;
2156 }
a7a3324a
MLC		 2157 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2158 davinci_mcasp_rx_irq_handler,
2159 IRQF_ONESHOT, irq_name, mcasp);
2160 if (ret) {
2161 dev_err(&pdev->dev, "RX IRQ request failed\n");
2162 goto err;
2163 }
2164
2165 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2166 }
2167
2168 irq = platform_get_irq_byname(pdev, "tx");
2169 if (irq >= 0) {
ab1fffe3 2170 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
a7a3324a 2171 dev_name(&pdev->dev));
0c8b794c
AY		 2172 if (!irq_name) {
2173 ret = -ENOMEM;
2174 goto err;
2175 }
a7a3324a
MLC		 2176 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2177 davinci_mcasp_tx_irq_handler,
2178 IRQF_ONESHOT, irq_name, mcasp);
2179 if (ret) {
2180 dev_err(&pdev->dev, "TX IRQ request failed\n");
2181 goto err;
2182 }
2183
2184 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2185 }
2186
256ba181 2187 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
cbc7956c
PU		 2188 if (dat)
2189 mcasp->dat_port = true;
256ba181 2190
8de131f2 2191 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
cbc7956c 2192 if (dat)
9759e7ef 2193 dma_data->addr = dat->start;
cbc7956c 2194 else
9ac0013c 2195 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
453c4990 2196
9759e7ef 2197 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
b67f4487 2198 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
4023fe6f 2199 if (res)
9759e7ef 2200 *dma = res->start;
4023fe6f 2201 else
9759e7ef 2202 *dma = pdata->tx_dma_channel;
92e2a6f6 2203
8de131f2
PU		 2204 /* dmaengine filter data for DT and non-DT boot */
2205 if (pdev->dev.of_node)
2206 dma_data->filter_data = "tx";
2207 else
9759e7ef 2208 dma_data->filter_data = dma;
8de131f2 2209
caa1d794
PU		 2210 /* RX is not valid in DIT mode */
2211 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
caa1d794 2212 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
caa1d794 2213 if (dat)
9759e7ef 2214 dma_data->addr = dat->start;
caa1d794 2215 else
9ac0013c
PU		 2216 dma_data->addr =
2217 mem->start + davinci_mcasp_rxdma_offset(pdata);
caa1d794 2218
9759e7ef 2219 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
caa1d794
PU		 2220 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
2221 if (res)
9759e7ef 2222 *dma = res->start;
caa1d794 2223 else
9759e7ef 2224 *dma = pdata->rx_dma_channel;
caa1d794
PU		 2225
2226 /* dmaengine filter data for DT and non-DT boot */
2227 if (pdev->dev.of_node)
2228 dma_data->filter_data = "rx";
2229 else
9759e7ef 2230 dma_data->filter_data = dma;
caa1d794 2231 }
453c4990 2232
cbc7956c
PU		 2233 if (mcasp->version < MCASP_VERSION_3) {
2234 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
64ebdec3 2235 /* dma_params->dma_addr is pointing to the data port address */
cbc7956c
PU		 2236 mcasp->dat_port = true;
2237 } else {
2238 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2239 }
b67f4487 2240
dd55ff83
JS		 2241 /* Allocate memory for long enough list for all possible
2242 * scenarios. Maximum number tdm slots is 32 and there cannot
2243 * be more serializers than given in the configuration. The
2244 * serializer directions could be taken into account, but it
2245 * would make code much more complex and save only couple of
2246 * bytes.
2247 */
2248 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
a86854d0
KC		 2249 devm_kcalloc(mcasp->dev,
2250 32 + mcasp->num_serializer - 1,
2251 sizeof(unsigned int),
dd55ff83
JS		 2252 GFP_KERNEL);
2253
2254 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
a86854d0
KC		 2255 devm_kcalloc(mcasp->dev,
2256 32 + mcasp->num_serializer - 1,
2257 sizeof(unsigned int),
dd55ff83
JS		 2258 GFP_KERNEL);
2259
2260 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
1b8b68b0
CJ		 2261 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2262 ret = -ENOMEM;
2263 goto err;
2264 }
dd55ff83
JS		 2265
2266 ret = davinci_mcasp_set_ch_constraints(mcasp);
5935a056
JS		 2267 if (ret)
2268 goto err;
2269
70091a3e 2270 dev_set_drvdata(&pdev->dev, mcasp);
ae726e93
PU		 2271
2272 mcasp_reparent_fck(pdev);
2273
540f1ba7
PU		 2274 /* All PINS as McASP */
2275 pm_runtime_get_sync(mcasp->dev);
2276 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
2277 pm_runtime_put(mcasp->dev);
2278
2279 ret = davinci_mcasp_init_gpiochip(mcasp);
2280 if (ret)
2281 goto err;
2282
764958f2
PU		 2283 ret = davinci_mcasp_get_dt_params(mcasp);
2284 if (ret)
2285 return -EINVAL;
2286
b6bb3709
PU		 2287 ret = devm_snd_soc_register_component(&pdev->dev,
2288 &davinci_mcasp_component,
2289 &davinci_mcasp_dai[pdata->op_mode], 1);
b67f4487
C		 2290
2291 if (ret != 0)
b6bb3709 2292 goto err;
f08095a4 2293
9fbd58cf
JS		 2294 ret = davinci_mcasp_get_dma_type(mcasp);
2295 switch (ret) {
2296 case PCM_EDMA:
f3f9cfa8 2297 ret = edma_pcm_platform_register(&pdev->dev);
9fbd58cf
JS		 2298 break;
2299 case PCM_SDMA:
3e802e90 2300 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
9fbd58cf 2301 break;
d5c6c59a 2302 default:
9fbd58cf
JS		 2303 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2304 case -EPROBE_DEFER:
2305 goto err;
d5c6c59a
PU		 2306 break;
2307 }
2308
2309 if (ret) {
2310 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
b6bb3709 2311 goto err;
f08095a4
HG		 2312 }
2313
b67f4487
C		 2314 return 0;
2315
b6bb3709 2316err:
10884347 2317 pm_runtime_disable(&pdev->dev);
b67f4487
C		 2318 return ret;
2319}
2320
2321static int davinci_mcasp_remove(struct platform_device *pdev)
2322{
10884347 2323 pm_runtime_disable(&pdev->dev);
b67f4487 2324
b67f4487
C		 2325 return 0;
2326}
2327
61754717
PU		 2328#ifdef CONFIG_PM
2329static int davinci_mcasp_runtime_suspend(struct device *dev)
2330{
2331 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2332 struct davinci_mcasp_context *context = &mcasp->context;
2333 u32 reg;
2334 int i;
2335
2336 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2337 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2338
2339 if (mcasp->txnumevt) {
2340 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2341 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2342 }
2343 if (mcasp->rxnumevt) {
2344 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2345 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2346 }
2347
2348 for (i = 0; i < mcasp->num_serializer; i++)
2349 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2350 DAVINCI_MCASP_XRSRCTL_REG(i));
2351
2352 return 0;
2353}
2354
2355static int davinci_mcasp_runtime_resume(struct device *dev)
2356{
2357 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2358 struct davinci_mcasp_context *context = &mcasp->context;
2359 u32 reg;
2360 int i;
2361
2362 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2363 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2364
2365 if (mcasp->txnumevt) {
2366 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2367 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2368 }
2369 if (mcasp->rxnumevt) {
2370 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2371 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2372 }
2373
2374 for (i = 0; i < mcasp->num_serializer; i++)
2375 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2376 context->xrsr_regs[i]);
2377
2378 return 0;
2379}
2380
2381#endif
2382
2383static const struct dev_pm_ops davinci_mcasp_pm_ops = {
2384 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
2385 davinci_mcasp_runtime_resume,
2386 NULL)
2387};
2388
b67f4487
C		 2389static struct platform_driver davinci_mcasp_driver = {
2390 .probe = davinci_mcasp_probe,
2391 .remove = davinci_mcasp_remove,
2392 .driver = {
2393 .name = "davinci-mcasp",
61754717 2394 .pm = &davinci_mcasp_pm_ops,
ea421eb1 2395 .of_match_table = mcasp_dt_ids,
b67f4487
C		 2396 },
2397};
2398
f9b8a514 2399module_platform_driver(davinci_mcasp_driver);
b67f4487
C		 2400
2401MODULE_AUTHOR("Steve Chen");
2402MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2403MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)