[linux-2.6-block.git] / sound / soc / tegra / tegra20_das.h

/*
 * tegra20_das.h - Definitions for Tegra20 DAS driver
 *
 * Author: Stephen Warren <swarren@nvidia.com>
 * Copyright (C) 2010,2012 - NVIDIA, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#ifndef __TEGRA20_DAS_H__
#define __TEGRA20_DAS_H__

/* Register TEGRA20_DAS_DAP_CTRL_SEL */
#define TEGRA20_DAS_DAP_CTRL_SEL			0x00
#define TEGRA20_DAS_DAP_CTRL_SEL_COUNT			5
#define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE			4
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P		31
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S		1
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P	30
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S	1
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P	29
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S	1
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P		0
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S		5

/* Values for field TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */
#define TEGRA20_DAS_DAP_SEL_DAC1	0
#define TEGRA20_DAS_DAP_SEL_DAC2	1
#define TEGRA20_DAS_DAP_SEL_DAC3	2
#define TEGRA20_DAS_DAP_SEL_DAP1	16
#define TEGRA20_DAS_DAP_SEL_DAP2	17
#define TEGRA20_DAS_DAP_SEL_DAP3	18
#define TEGRA20_DAS_DAP_SEL_DAP4	19
#define TEGRA20_DAS_DAP_SEL_DAP5	20

/* Register TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL */
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL			0x40
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT		3
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE		4
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P	28
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S	4
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P	24
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S	4
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P	0
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S	4

/*
 * Values for:
 * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL
 * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL
 * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL
 */
#define TEGRA20_DAS_DAC_SEL_DAP1	0
#define TEGRA20_DAS_DAC_SEL_DAP2	1
#define TEGRA20_DAS_DAC_SEL_DAP3	2
#define TEGRA20_DAS_DAC_SEL_DAP4	3
#define TEGRA20_DAS_DAC_SEL_DAP5	4

/*
 * Names/IDs of the DACs/DAPs.
 */

#define TEGRA20_DAS_DAP_ID_1 0
#define TEGRA20_DAS_DAP_ID_2 1
#define TEGRA20_DAS_DAP_ID_3 2
#define TEGRA20_DAS_DAP_ID_4 3
#define TEGRA20_DAS_DAP_ID_5 4

#define TEGRA20_DAS_DAC_ID_1 0
#define TEGRA20_DAS_DAC_ID_2 1
#define TEGRA20_DAS_DAC_ID_3 2

struct tegra20_das {
	struct device *dev;
	struct regmap *regmap;
};

/*
 * Terminology:
 * DAS: Digital audio switch (HW module controlled by this driver)
 * DAP: Digital audio port (port/pins on Tegra device)
 * DAC: Digital audio controller (e.g. I2S or AC97 controller elsewhere)
 *
 * The Tegra DAS is a mux/cross-bar which can connect each DAP to a specific
 * DAC, or another DAP. When DAPs are connected, one must be the master and
 * one the slave. Each DAC allows selection of a specific DAP for input, to
 * cater for the case where N DAPs are connected to 1 DAC for broadcast
 * output.
 *
 * This driver is dumb; no attempt is made to ensure that a valid routing
 * configuration is programmed.
 */

/*
 * Connect a DAP to to a DAC
 * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
 * dac_sel: DAC to connect to: TEGRA20_DAS_DAP_SEL_DAC*
 */
extern int tegra20_das_connect_dap_to_dac(int dap_id, int dac_sel);

/*
 * Connect a DAP to to another DAP
 * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
 * other_dap_sel: DAP to connect to: TEGRA20_DAS_DAP_SEL_DAP*
 * master: Is this DAP the master (1) or slave (0)
 * sdata1rx: Is this DAP's SDATA1 pin RX (1) or TX (0)
 * sdata2rx: Is this DAP's SDATA2 pin RX (1) or TX (0)
 */
extern int tegra20_das_connect_dap_to_dap(int dap_id, int other_dap_sel,
					  int master, int sdata1rx,
					  int sdata2rx);

/*
 * Connect a DAC's input to a DAP
 * (DAC outputs are selected by the DAP)
 * dac_id: DAC ID to connect: TEGRA20_DAS_DAC_ID_*
 * dap_sel: DAP to receive input from: TEGRA20_DAS_DAC_SEL_DAP*
 */
extern int tegra20_das_connect_dac_to_dap(int dac_id, int dap_sel);

#endif
Commit	Line	Data
f0d8af4f	1	/*
ef280d39	2	* tegra20_das.h - Definitions for Tegra20 DAS driver
f0d8af4f SW	3	*
f0d8af4f SW	4	* Author: Stephen Warren <swarren@nvidia.com>
896637ac	5	* Copyright (C) 2010,2012 - NVIDIA, Inc.
f0d8af4f SW	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* version 2 as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	19	* 02110-1301 USA
	20	*
	21	*/
	22
896637ac SW	23	#ifndef __TEGRA20_DAS_H__
896637ac SW	24	#define __TEGRA20_DAS_H__
f0d8af4f	25
896637ac SW	26	/* Register TEGRA20_DAS_DAP_CTRL_SEL */
	27	#define TEGRA20_DAS_DAP_CTRL_SEL 0x00
	28	#define TEGRA20_DAS_DAP_CTRL_SEL_COUNT 5
	29	#define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE 4
	30	#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P 31
	31	#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S 1
	32	#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P 30
	33	#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S 1
	34	#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P 29
	35	#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S 1
	36	#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P 0
	37	#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S 5
f0d8af4f	38
896637ac SW	39	/* Values for field TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */
	40	#define TEGRA20_DAS_DAP_SEL_DAC1 0
	41	#define TEGRA20_DAS_DAP_SEL_DAC2 1
	42	#define TEGRA20_DAS_DAP_SEL_DAC3 2
	43	#define TEGRA20_DAS_DAP_SEL_DAP1 16
	44	#define TEGRA20_DAS_DAP_SEL_DAP2 17
	45	#define TEGRA20_DAS_DAP_SEL_DAP3 18
	46	#define TEGRA20_DAS_DAP_SEL_DAP4 19
	47	#define TEGRA20_DAS_DAP_SEL_DAP5 20
f0d8af4f	48
896637ac SW	49	/* Register TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL */
	50	#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL 0x40
	51	#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT 3
	52	#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE 4
	53	#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P 28
	54	#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S 4
	55	#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P 24
	56	#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S 4
	57	#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P 0
	58	#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S 4
f0d8af4f SW	59
	60	/*
	61	* Values for:
896637ac SW	62	* TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL
	63	* TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL
	64	* TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL
f0d8af4f	65	*/
896637ac SW	66	#define TEGRA20_DAS_DAC_SEL_DAP1 0
	67	#define TEGRA20_DAS_DAC_SEL_DAP2 1
	68	#define TEGRA20_DAS_DAC_SEL_DAP3 2
	69	#define TEGRA20_DAS_DAC_SEL_DAP4 3
	70	#define TEGRA20_DAS_DAC_SEL_DAP5 4
f0d8af4f SW	71
	72	/*
	73	* Names/IDs of the DACs/DAPs.
	74	*/
	75
896637ac SW	76	#define TEGRA20_DAS_DAP_ID_1 0
	77	#define TEGRA20_DAS_DAP_ID_2 1
	78	#define TEGRA20_DAS_DAP_ID_3 2
	79	#define TEGRA20_DAS_DAP_ID_4 3
	80	#define TEGRA20_DAS_DAP_ID_5 4
f0d8af4f	81
896637ac SW	82	#define TEGRA20_DAS_DAC_ID_1 0
	83	#define TEGRA20_DAS_DAC_ID_2 1
	84	#define TEGRA20_DAS_DAC_ID_3 2
f0d8af4f	85
896637ac	86	struct tegra20_das {
f0d8af4f	87	struct device *dev;
7203a625	88	struct regmap *regmap;
f0d8af4f SW	89	};
	90
	91	/*
	92	* Terminology:
	93	* DAS: Digital audio switch (HW module controlled by this driver)
	94	* DAP: Digital audio port (port/pins on Tegra device)
	95	* DAC: Digital audio controller (e.g. I2S or AC97 controller elsewhere)
7deb2b45	96	*
f0d8af4f SW	97	* The Tegra DAS is a mux/cross-bar which can connect each DAP to a specific
	98	* DAC, or another DAP. When DAPs are connected, one must be the master and
	99	* one the slave. Each DAC allows selection of a specific DAP for input, to
	100	* cater for the case where N DAPs are connected to 1 DAC for broadcast
	101	* output.
	102	*
	103	* This driver is dumb; no attempt is made to ensure that a valid routing
	104	* configuration is programmed.
	105	*/
	106
	107	/*
	108	* Connect a DAP to to a DAC
896637ac SW	109	* dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
896637ac SW	110	* dac_sel: DAC to connect to: TEGRA20_DAS_DAP_SEL_DAC*
f0d8af4f	111	*/
896637ac	112	extern int tegra20_das_connect_dap_to_dac(int dap_id, int dac_sel);
f0d8af4f SW	113
	114	/*
	115	* Connect a DAP to to another DAP
896637ac SW	116	* dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
896637ac SW	117	* other_dap_sel: DAP to connect to: TEGRA20_DAS_DAP_SEL_DAP*
f0d8af4f SW	118	* master: Is this DAP the master (1) or slave (0)
	119	* sdata1rx: Is this DAP's SDATA1 pin RX (1) or TX (0)
	120	* sdata2rx: Is this DAP's SDATA2 pin RX (1) or TX (0)
	121	*/
896637ac SW	122	extern int tegra20_das_connect_dap_to_dap(int dap_id, int other_dap_sel,
	123	int master, int sdata1rx,
	124	int sdata2rx);
f0d8af4f SW	125
	126	/*
	127	* Connect a DAC's input to a DAP
	128	* (DAC outputs are selected by the DAP)
896637ac SW	129	* dac_id: DAC ID to connect: TEGRA20_DAS_DAC_ID_*
896637ac SW	130	* dap_sel: DAP to receive input from: TEGRA20_DAS_DAC_SEL_DAP*
f0d8af4f	131	*/
896637ac	132	extern int tegra20_das_connect_dac_to_dap(int dac_id, int dap_sel);
f0d8af4f SW	133
f0d8af4f SW	134	#endif