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1 | /* |
2 | * tegra20_ac97.h - Definitions for the Tegra20 AC97 controller driver | |
3 | * | |
4 | * Copyright (c) 2012 Lucas Stach <dev@lynxeye.de> | |
5 | * | |
6 | * Partly based on code copyright/by: | |
7 | * | |
8 | * Copyright (c) 2011,2012 Toradex Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * version 2 as published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | */ | |
20 | ||
21 | #ifndef __TEGRA20_AC97_H__ | |
22 | #define __TEGRA20_AC97_H__ | |
23 | ||
24 | #include "tegra_pcm.h" | |
25 | ||
26 | #define TEGRA20_AC97_CTRL 0x00 | |
27 | #define TEGRA20_AC97_CMD 0x04 | |
28 | #define TEGRA20_AC97_STATUS1 0x08 | |
29 | /* ... */ | |
30 | #define TEGRA20_AC97_FIFO1_SCR 0x1c | |
31 | /* ... */ | |
32 | #define TEGRA20_AC97_FIFO_TX1 0x40 | |
33 | #define TEGRA20_AC97_FIFO_RX1 0x80 | |
34 | ||
35 | /* TEGRA20_AC97_CTRL */ | |
36 | #define TEGRA20_AC97_CTRL_STM2_EN (1 << 16) | |
37 | #define TEGRA20_AC97_CTRL_DOUBLE_SAMPLING_EN (1 << 11) | |
38 | #define TEGRA20_AC97_CTRL_IO_CNTRL_EN (1 << 10) | |
39 | #define TEGRA20_AC97_CTRL_HSET_DAC_EN (1 << 9) | |
40 | #define TEGRA20_AC97_CTRL_LINE2_DAC_EN (1 << 8) | |
41 | #define TEGRA20_AC97_CTRL_PCM_LFE_EN (1 << 7) | |
42 | #define TEGRA20_AC97_CTRL_PCM_SUR_EN (1 << 6) | |
43 | #define TEGRA20_AC97_CTRL_PCM_CEN_DAC_EN (1 << 5) | |
44 | #define TEGRA20_AC97_CTRL_LINE1_DAC_EN (1 << 4) | |
45 | #define TEGRA20_AC97_CTRL_PCM_DAC_EN (1 << 3) | |
46 | #define TEGRA20_AC97_CTRL_COLD_RESET (1 << 2) | |
47 | #define TEGRA20_AC97_CTRL_WARM_RESET (1 << 1) | |
48 | #define TEGRA20_AC97_CTRL_STM_EN (1 << 0) | |
49 | ||
50 | /* TEGRA20_AC97_CMD */ | |
51 | #define TEGRA20_AC97_CMD_CMD_ADDR_SHIFT 24 | |
52 | #define TEGRA20_AC97_CMD_CMD_ADDR_MASK (0xff << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) | |
53 | #define TEGRA20_AC97_CMD_CMD_DATA_SHIFT 8 | |
54 | #define TEGRA20_AC97_CMD_CMD_DATA_MASK (0xffff << TEGRA20_AC97_CMD_CMD_DATA_SHIFT) | |
55 | #define TEGRA20_AC97_CMD_CMD_ID_SHIFT 2 | |
56 | #define TEGRA20_AC97_CMD_CMD_ID_MASK (0x3 << TEGRA20_AC97_CMD_CMD_ID_SHIFT) | |
57 | #define TEGRA20_AC97_CMD_BUSY (1 << 0) | |
58 | ||
59 | /* TEGRA20_AC97_STATUS1 */ | |
60 | #define TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT 24 | |
61 | #define TEGRA20_AC97_STATUS1_STA_ADDR1_MASK (0xff << TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT) | |
62 | #define TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT 8 | |
63 | #define TEGRA20_AC97_STATUS1_STA_DATA1_MASK (0xffff << TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT) | |
64 | #define TEGRA20_AC97_STATUS1_STA_VALID1 (1 << 2) | |
65 | #define TEGRA20_AC97_STATUS1_STANDBY1 (1 << 1) | |
66 | #define TEGRA20_AC97_STATUS1_CODEC1_RDY (1 << 0) | |
67 | ||
68 | /* TEGRA20_AC97_FIFO1_SCR */ | |
69 | #define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT 27 | |
70 | #define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_MASK (0x1f << TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT) | |
71 | #define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT 22 | |
72 | #define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_MASK (0x1f << TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT) | |
73 | #define TEGRA20_AC97_FIFO_SCR_REC_OVERRUN_INT_STA (1 << 19) | |
74 | #define TEGRA20_AC97_FIFO_SCR_PB_UNDERRUN_INT_STA (1 << 18) | |
75 | #define TEGRA20_AC97_FIFO_SCR_REC_FORCE_MT (1 << 17) | |
76 | #define TEGRA20_AC97_FIFO_SCR_PB_FORCE_MT (1 << 16) | |
77 | #define TEGRA20_AC97_FIFO_SCR_REC_FULL_EN (1 << 15) | |
78 | #define TEGRA20_AC97_FIFO_SCR_REC_3QRT_FULL_EN (1 << 14) | |
79 | #define TEGRA20_AC97_FIFO_SCR_REC_QRT_FULL_EN (1 << 13) | |
80 | #define TEGRA20_AC97_FIFO_SCR_REC_EMPTY_EN (1 << 12) | |
81 | #define TEGRA20_AC97_FIFO_SCR_PB_NOT_FULL_EN (1 << 11) | |
82 | #define TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN (1 << 10) | |
83 | #define TEGRA20_AC97_FIFO_SCR_PB_3QRT_MT_EN (1 << 9) | |
84 | #define TEGRA20_AC97_FIFO_SCR_PB_EMPTY_MT_EN (1 << 8) | |
85 | ||
86 | struct tegra20_ac97 { | |
87 | struct clk *clk_ac97; | |
3489d506 LPC |
88 | struct snd_dmaengine_dai_dma_data capture_dma_data; |
89 | struct snd_dmaengine_dai_dma_data playback_dma_data; | |
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90 | struct regmap *regmap; |
91 | int reset_gpio; | |
92 | int sync_gpio; | |
609dad9b LS |
93 | }; |
94 | #endif /* __TEGRA20_AC97_H__ */ |