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e149ca29 | 1 | // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) |
8920153c LG |
2 | // |
3 | // This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | // redistributing this file, you may do so under either license. | |
5 | // | |
6 | // Copyright(c) 2018 Intel Corporation. All rights reserved. | |
7 | // | |
8 | // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> | |
9 | // | |
10 | ||
11 | #include "ops.h" | |
12 | #include "sof-priv.h" | |
ee1e79b7 | 13 | #include "sof-audio.h" |
8920153c | 14 | |
700d1677 RS |
15 | /* |
16 | * Helper function to determine the target DSP state during | |
17 | * system suspend. This function only cares about the device | |
18 | * D-states. Platform-specific substates, if any, should be | |
19 | * handled by the platform-specific parts. | |
20 | */ | |
21 | static u32 snd_sof_dsp_power_target(struct snd_sof_dev *sdev) | |
22 | { | |
23 | u32 target_dsp_state; | |
24 | ||
25 | switch (sdev->system_suspend_target) { | |
9d2d4627 PLB |
26 | case SOF_SUSPEND_S5: |
27 | case SOF_SUSPEND_S4: | |
28 | /* DSP should be in D3 if the system is suspending to S3+ */ | |
700d1677 RS |
29 | case SOF_SUSPEND_S3: |
30 | /* DSP should be in D3 if the system is suspending to S3 */ | |
31 | target_dsp_state = SOF_DSP_PM_D3; | |
32 | break; | |
33 | case SOF_SUSPEND_S0IX: | |
34 | /* | |
35 | * Currently, the only criterion for retaining the DSP in D0 | |
36 | * is that there are streams that ignored the suspend trigger. | |
37 | * Additional criteria such Soundwire clock-stop mode and | |
38 | * device suspend latency considerations will be added later. | |
39 | */ | |
40 | if (snd_sof_stream_suspend_ignored(sdev)) | |
41 | target_dsp_state = SOF_DSP_PM_D0; | |
42 | else | |
43 | target_dsp_state = SOF_DSP_PM_D3; | |
44 | break; | |
45 | default: | |
46 | /* This case would be during runtime suspend */ | |
47 | target_dsp_state = SOF_DSP_PM_D3; | |
48 | break; | |
49 | } | |
50 | ||
51 | return target_dsp_state; | |
52 | } | |
53 | ||
8920153c LG |
54 | #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE) |
55 | static void sof_cache_debugfs(struct snd_sof_dev *sdev) | |
56 | { | |
57 | struct snd_sof_dfsentry *dfse; | |
58 | ||
59 | list_for_each_entry(dfse, &sdev->dfsentry_list, list) { | |
60 | ||
61 | /* nothing to do if debugfs buffer is not IO mem */ | |
62 | if (dfse->type == SOF_DFSENTRY_TYPE_BUF) | |
63 | continue; | |
64 | ||
65 | /* cache memory that is only accessible in D0 */ | |
66 | if (dfse->access_type == SOF_DEBUGFS_ACCESS_D0_ONLY) | |
67 | memcpy_fromio(dfse->cache_buf, dfse->io_mem, | |
68 | dfse->size); | |
69 | } | |
70 | } | |
71 | #endif | |
72 | ||
73 | static int sof_resume(struct device *dev, bool runtime_resume) | |
74 | { | |
75 | struct snd_sof_dev *sdev = dev_get_drvdata(dev); | |
510758ee PU |
76 | const struct sof_ipc_pm_ops *pm_ops = sof_ipc_get_ops(sdev, pm); |
77 | const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg); | |
61e285ca | 78 | u32 old_state = sdev->dsp_power_state.state; |
8920153c LG |
79 | int ret; |
80 | ||
81 | /* do nothing if dsp resume callbacks are not set */ | |
c26fde3b DB |
82 | if (!runtime_resume && !sof_ops(sdev)->resume) |
83 | return 0; | |
84 | ||
85 | if (runtime_resume && !sof_ops(sdev)->runtime_resume) | |
8920153c LG |
86 | return 0; |
87 | ||
410e5e55 PLB |
88 | /* DSP was never successfully started, nothing to resume */ |
89 | if (sdev->first_boot) | |
90 | return 0; | |
91 | ||
8920153c LG |
92 | /* |
93 | * if the runtime_resume flag is set, call the runtime_resume routine | |
94 | * or else call the system resume routine | |
95 | */ | |
96 | if (runtime_resume) | |
97 | ret = snd_sof_dsp_runtime_resume(sdev); | |
98 | else | |
99 | ret = snd_sof_dsp_resume(sdev); | |
100 | if (ret < 0) { | |
101 | dev_err(sdev->dev, | |
102 | "error: failed to power up DSP after resume\n"); | |
103 | return ret; | |
104 | } | |
105 | ||
28d40e7a PU |
106 | if (sdev->dspless_mode_selected) { |
107 | sof_set_fw_state(sdev, SOF_DSPLESS_MODE); | |
108 | return 0; | |
109 | } | |
110 | ||
fc907cc5 RS |
111 | /* |
112 | * Nothing further to be done for platforms that support the low power | |
249ee180 LY |
113 | * D0 substate. Resume trace and return when resuming from |
114 | * low-power D0 substate | |
fc907cc5 RS |
115 | */ |
116 | if (!runtime_resume && sof_ops(sdev)->set_power_state && | |
249ee180 | 117 | old_state == SOF_DSP_PM_D0) { |
1dedbe4f | 118 | ret = sof_fw_trace_resume(sdev); |
249ee180 LY |
119 | if (ret < 0) |
120 | /* non fatal */ | |
121 | dev_warn(sdev->dev, | |
122 | "failed to enable trace after resume %d\n", ret); | |
fb9a8119 | 123 | return 0; |
249ee180 | 124 | } |
fb9a8119 | 125 | |
58a5c9a4 | 126 | sof_set_fw_state(sdev, SOF_FW_BOOT_PREPARE); |
6ca5cecb | 127 | |
8920153c LG |
128 | /* load the firmware */ |
129 | ret = snd_sof_load_firmware(sdev); | |
130 | if (ret < 0) { | |
131 | dev_err(sdev->dev, | |
132 | "error: failed to load DSP firmware after resume %d\n", | |
133 | ret); | |
e2406275 | 134 | sof_set_fw_state(sdev, SOF_FW_BOOT_FAILED); |
8920153c LG |
135 | return ret; |
136 | } | |
137 | ||
58a5c9a4 | 138 | sof_set_fw_state(sdev, SOF_FW_BOOT_IN_PROGRESS); |
6ca5cecb RS |
139 | |
140 | /* | |
141 | * Boot the firmware. The FW boot status will be modified | |
142 | * in snd_sof_run_firmware() depending on the outcome. | |
143 | */ | |
8920153c LG |
144 | ret = snd_sof_run_firmware(sdev); |
145 | if (ret < 0) { | |
146 | dev_err(sdev->dev, | |
147 | "error: failed to boot DSP firmware after resume %d\n", | |
148 | ret); | |
e2406275 | 149 | sof_set_fw_state(sdev, SOF_FW_BOOT_FAILED); |
8920153c LG |
150 | return ret; |
151 | } | |
152 | ||
758f24d4 | 153 | /* resume DMA trace */ |
1dedbe4f | 154 | ret = sof_fw_trace_resume(sdev); |
8920153c LG |
155 | if (ret < 0) { |
156 | /* non fatal */ | |
157 | dev_warn(sdev->dev, | |
158 | "warning: failed to init trace after resume %d\n", | |
159 | ret); | |
160 | } | |
161 | ||
162 | /* restore pipelines */ | |
510758ee | 163 | if (tplg_ops && tplg_ops->set_up_all_pipelines) { |
31cd6e46 RS |
164 | ret = tplg_ops->set_up_all_pipelines(sdev, false); |
165 | if (ret < 0) { | |
166 | dev_err(sdev->dev, "Failed to restore pipeline after resume %d\n", ret); | |
167 | return ret; | |
168 | } | |
8920153c LG |
169 | } |
170 | ||
1069967a PU |
171 | /* Notify clients not managed by pm framework about core resume */ |
172 | sof_resume_clients(sdev); | |
173 | ||
8920153c | 174 | /* notify DSP of system resume */ |
657774ac RS |
175 | if (pm_ops && pm_ops->ctx_restore) { |
176 | ret = pm_ops->ctx_restore(sdev); | |
177 | if (ret < 0) | |
178 | dev_err(sdev->dev, "ctx_restore IPC error during resume: %d\n", ret); | |
179 | } | |
8920153c LG |
180 | |
181 | return ret; | |
182 | } | |
183 | ||
184 | static int sof_suspend(struct device *dev, bool runtime_suspend) | |
185 | { | |
186 | struct snd_sof_dev *sdev = dev_get_drvdata(dev); | |
510758ee PU |
187 | const struct sof_ipc_pm_ops *pm_ops = sof_ipc_get_ops(sdev, pm); |
188 | const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg); | |
1069967a | 189 | pm_message_t pm_state; |
6f95eec6 | 190 | u32 target_state = snd_sof_dsp_power_target(sdev); |
8920153c LG |
191 | int ret; |
192 | ||
193 | /* do nothing if dsp suspend callback is not set */ | |
c26fde3b DB |
194 | if (!runtime_suspend && !sof_ops(sdev)->suspend) |
195 | return 0; | |
196 | ||
197 | if (runtime_suspend && !sof_ops(sdev)->runtime_suspend) | |
8920153c LG |
198 | return 0; |
199 | ||
d185e068 RS |
200 | if (tplg_ops && tplg_ops->tear_down_all_pipelines) |
201 | tplg_ops->tear_down_all_pipelines(sdev, false); | |
202 | ||
6ca5cecb | 203 | if (sdev->fw_state != SOF_FW_BOOT_COMPLETE) |
fb9a8119 | 204 | goto suspend; |
8920153c | 205 | |
a1ce6e43 | 206 | /* prepare for streams to be resumed properly upon resume */ |
7077a07a | 207 | if (!runtime_suspend) { |
8e84b6a4 | 208 | ret = snd_sof_dsp_hw_params_upon_resume(sdev); |
7077a07a RS |
209 | if (ret < 0) { |
210 | dev_err(sdev->dev, | |
211 | "error: setting hw_params flag during suspend %d\n", | |
212 | ret); | |
213 | return ret; | |
214 | } | |
215 | } | |
8920153c | 216 | |
1069967a | 217 | pm_state.event = target_state; |
fb9a8119 | 218 | |
61e285ca | 219 | /* Skip to platform-specific suspend if DSP is entering D0 */ |
1069967a | 220 | if (target_state == SOF_DSP_PM_D0) { |
1dedbe4f | 221 | sof_fw_trace_suspend(sdev, pm_state); |
1069967a PU |
222 | /* Notify clients not managed by pm framework about core suspend */ |
223 | sof_suspend_clients(sdev, pm_state); | |
fb9a8119 | 224 | goto suspend; |
1069967a | 225 | } |
fb9a8119 | 226 | |
758f24d4 | 227 | /* suspend DMA trace */ |
1dedbe4f | 228 | sof_fw_trace_suspend(sdev, pm_state); |
fb9a8119 | 229 | |
1069967a PU |
230 | /* Notify clients not managed by pm framework about core suspend */ |
231 | sof_suspend_clients(sdev, pm_state); | |
232 | ||
8920153c LG |
233 | #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE) |
234 | /* cache debugfs contents during runtime suspend */ | |
235 | if (runtime_suspend) | |
236 | sof_cache_debugfs(sdev); | |
237 | #endif | |
238 | /* notify DSP of upcoming power down */ | |
657774ac RS |
239 | if (pm_ops && pm_ops->ctx_save) { |
240 | ret = pm_ops->ctx_save(sdev); | |
241 | if (ret == -EBUSY || ret == -EAGAIN) { | |
242 | /* | |
243 | * runtime PM has logic to handle -EBUSY/-EAGAIN so | |
244 | * pass these errors up | |
245 | */ | |
246 | dev_err(sdev->dev, "ctx_save IPC error during suspend: %d\n", ret); | |
247 | return ret; | |
248 | } else if (ret < 0) { | |
249 | /* FW in unexpected state, continue to power down */ | |
250 | dev_warn(sdev->dev, "ctx_save IPC error: %d, proceeding with suspend\n", | |
251 | ret); | |
252 | } | |
8920153c LG |
253 | } |
254 | ||
fb9a8119 | 255 | suspend: |
6ca5cecb RS |
256 | |
257 | /* return if the DSP was not probed successfully */ | |
258 | if (sdev->fw_state == SOF_FW_BOOT_NOT_STARTED) | |
259 | return 0; | |
260 | ||
fb9a8119 | 261 | /* platform-specific suspend */ |
8920153c | 262 | if (runtime_suspend) |
1c38c922 | 263 | ret = snd_sof_dsp_runtime_suspend(sdev); |
8920153c | 264 | else |
61e285ca | 265 | ret = snd_sof_dsp_suspend(sdev, target_state); |
8920153c LG |
266 | if (ret < 0) |
267 | dev_err(sdev->dev, | |
268 | "error: failed to power down DSP during suspend %d\n", | |
269 | ret); | |
270 | ||
61e285ca RS |
271 | /* Do not reset FW state if DSP is in D0 */ |
272 | if (target_state == SOF_DSP_PM_D0) | |
fb9a8119 RS |
273 | return ret; |
274 | ||
6ca5cecb | 275 | /* reset FW state */ |
58a5c9a4 | 276 | sof_set_fw_state(sdev, SOF_FW_BOOT_NOT_STARTED); |
b640e8a4 | 277 | sdev->enabled_cores_mask = 0; |
6ca5cecb | 278 | |
8920153c LG |
279 | return ret; |
280 | } | |
281 | ||
3541aef1 MR |
282 | int snd_sof_dsp_power_down_notify(struct snd_sof_dev *sdev) |
283 | { | |
510758ee | 284 | const struct sof_ipc_pm_ops *pm_ops = sof_ipc_get_ops(sdev, pm); |
657774ac | 285 | |
3541aef1 | 286 | /* Notify DSP of upcoming power down */ |
657774ac RS |
287 | if (sof_ops(sdev)->remove && pm_ops && pm_ops->ctx_save) |
288 | return pm_ops->ctx_save(sdev); | |
3541aef1 MR |
289 | |
290 | return 0; | |
291 | } | |
292 | ||
8920153c LG |
293 | int snd_sof_runtime_suspend(struct device *dev) |
294 | { | |
295 | return sof_suspend(dev, true); | |
296 | } | |
297 | EXPORT_SYMBOL(snd_sof_runtime_suspend); | |
298 | ||
62fde977 KV |
299 | int snd_sof_runtime_idle(struct device *dev) |
300 | { | |
301 | struct snd_sof_dev *sdev = dev_get_drvdata(dev); | |
302 | ||
303 | return snd_sof_dsp_runtime_idle(sdev); | |
304 | } | |
305 | EXPORT_SYMBOL(snd_sof_runtime_idle); | |
306 | ||
8920153c LG |
307 | int snd_sof_runtime_resume(struct device *dev) |
308 | { | |
309 | return sof_resume(dev, true); | |
310 | } | |
311 | EXPORT_SYMBOL(snd_sof_runtime_resume); | |
312 | ||
313 | int snd_sof_resume(struct device *dev) | |
314 | { | |
315 | return sof_resume(dev, false); | |
316 | } | |
317 | EXPORT_SYMBOL(snd_sof_resume); | |
318 | ||
319 | int snd_sof_suspend(struct device *dev) | |
320 | { | |
321 | return sof_suspend(dev, false); | |
322 | } | |
323 | EXPORT_SYMBOL(snd_sof_suspend); | |
0b50b3b1 KJ |
324 | |
325 | int snd_sof_prepare(struct device *dev) | |
326 | { | |
327 | struct snd_sof_dev *sdev = dev_get_drvdata(dev); | |
43437d04 DB |
328 | const struct sof_dev_desc *desc = sdev->pdata->desc; |
329 | ||
330 | /* will suspend to S3 by default */ | |
331 | sdev->system_suspend_target = SOF_SUSPEND_S3; | |
332 | ||
4e1f8648 | 333 | /* |
b54b3a4e PU |
334 | * if the firmware is crashed or boot failed then we try to aim for S3 |
335 | * to reboot the firmware | |
4e1f8648 | 336 | */ |
b54b3a4e PU |
337 | if (sdev->fw_state == SOF_FW_CRASHED || |
338 | sdev->fw_state == SOF_FW_BOOT_FAILED) | |
4e1f8648 PU |
339 | return 0; |
340 | ||
43437d04 DB |
341 | if (!desc->use_acpi_target_states) |
342 | return 0; | |
0b50b3b1 KJ |
343 | |
344 | #if defined(CONFIG_ACPI) | |
a9330845 PLB |
345 | switch (acpi_target_system_state()) { |
346 | case ACPI_STATE_S0: | |
043ae13b | 347 | sdev->system_suspend_target = SOF_SUSPEND_S0IX; |
a9330845 PLB |
348 | break; |
349 | case ACPI_STATE_S1: | |
350 | case ACPI_STATE_S2: | |
351 | case ACPI_STATE_S3: | |
352 | sdev->system_suspend_target = SOF_SUSPEND_S3; | |
353 | break; | |
9d2d4627 PLB |
354 | case ACPI_STATE_S4: |
355 | sdev->system_suspend_target = SOF_SUSPEND_S4; | |
356 | break; | |
357 | case ACPI_STATE_S5: | |
358 | sdev->system_suspend_target = SOF_SUSPEND_S5; | |
359 | break; | |
a9330845 PLB |
360 | default: |
361 | break; | |
362 | } | |
0b50b3b1 KJ |
363 | #endif |
364 | ||
365 | return 0; | |
366 | } | |
367 | EXPORT_SYMBOL(snd_sof_prepare); | |
368 | ||
369 | void snd_sof_complete(struct device *dev) | |
370 | { | |
371 | struct snd_sof_dev *sdev = dev_get_drvdata(dev); | |
372 | ||
043ae13b | 373 | sdev->system_suspend_target = SOF_SUSPEND_NONE; |
0b50b3b1 KJ |
374 | } |
375 | EXPORT_SYMBOL(snd_sof_complete); |