[linux-2.6-block.git] / sound / soc / sof / intel / tgl.c

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright(c) 2020 Intel Corporation
//
// Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
//

/*
 * Hardware interface for audio DSP on Tigerlake.
 */

#include <sound/sof/ext_manifest4.h>
#include "../ipc4-priv.h"
#include "../ops.h"
#include "hda.h"
#include "hda-ipc.h"
#include "../sof-audio.h"

static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
	{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
	{"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
	{"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
};

static const struct snd_sof_debugfs_map tgl_ipc4_dsp_debugfs[] = {
	{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
	{"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
	{"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
	{"fw_regs", HDA_DSP_BAR,  SRAM_WINDOW_OFFSET(0), 0x1000, SOF_DEBUGFS_ACCESS_D0_ONLY},
};

static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core)
{
	const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;

	/* power up primary core if not already powered up and return */
	if (core == SOF_DSP_PRIMARY_CORE)
		return hda_dsp_enable_core(sdev, BIT(core));

	if (pm_ops->set_core_state)
		return pm_ops->set_core_state(sdev, core, true);

	return 0;
}

static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
{
	const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
	int ret;

	if (pm_ops->set_core_state) {
		ret = pm_ops->set_core_state(sdev, core, false);
		if (ret < 0)
			return ret;
	}

	/* power down primary core and return */
	if (core == SOF_DSP_PRIMARY_CORE)
		return hda_dsp_core_reset_power_down(sdev, BIT(core));

	return 0;
}

/* Tigerlake ops */
struct snd_sof_dsp_ops sof_tgl_ops;

int sof_tgl_ops_init(struct snd_sof_dev *sdev)
{
	/* common defaults */
	memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));

	/* probe/remove/shutdown */
	sof_tgl_ops.shutdown	= hda_dsp_shutdown_dma_flush;

	if (sdev->pdata->ipc_type == SOF_IPC_TYPE_3) {
		/* doorbell */
		sof_tgl_ops.irq_thread	= cnl_ipc_irq_thread;

		/* ipc */
		sof_tgl_ops.send_msg	= cnl_ipc_send_msg;

		/* debug */
		sof_tgl_ops.ipc_dump	= cnl_ipc_dump;
		sof_tgl_ops.debug_map	= tgl_dsp_debugfs;
		sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs);

		sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc3;
	}

	if (sdev->pdata->ipc_type == SOF_IPC_TYPE_4) {
		struct sof_ipc4_fw_data *ipc4_data;

		sdev->private = kzalloc(sizeof(*ipc4_data), GFP_KERNEL);
		if (!sdev->private)
			return -ENOMEM;

		ipc4_data = sdev->private;
		ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;

		ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;

		ipc4_data->fw_context_save = true;

		/* External library loading support */
		ipc4_data->load_library = hda_dsp_ipc4_load_library;

		/* doorbell */
		sof_tgl_ops.irq_thread	= cnl_ipc4_irq_thread;

		/* ipc */
		sof_tgl_ops.send_msg	= cnl_ipc4_send_msg;

		/* debug */
		sof_tgl_ops.ipc_dump	= cnl_ipc4_dump;
		sof_tgl_ops.dbg_dump	= hda_ipc4_dsp_dump;
		sof_tgl_ops.debug_map	= tgl_ipc4_dsp_debugfs;
		sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_ipc4_dsp_debugfs);

		sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
	}

	/* set DAI driver ops */
	hda_set_dai_drv_ops(sdev, &sof_tgl_ops);

	/* pre/post fw run */
	sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run;

	/* firmware run */
	sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax;

	/* dsp core get/put */
	sof_tgl_ops.core_get = tgl_dsp_core_get;
	sof_tgl_ops.core_put = tgl_dsp_core_put;

	return 0;
};

const struct sof_intel_dsp_desc tgl_chip_info = {
	/* Tigerlake , Alderlake */
	.cores_num = 4,
	.init_core_mask = 1,
	.host_managed_cores_mask = BIT(0),
	.ipc_req = CNL_DSP_REG_HIPCIDR,
	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
	.rom_init_timeout	= 300,
	.ssp_count = TGL_SSP_COUNT,
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
	.sdw_shim_base = SDW_SHIM_BASE,
	.sdw_alh_base = SDW_ALH_BASE,
	.d0i3_offset = SOF_HDA_VS_D0I3C,
	.read_sdw_lcount =  hda_sdw_check_lcount_common,
	.enable_sdw_irq	= hda_common_enable_sdw_irq,
	.check_sdw_irq	= hda_common_check_sdw_irq,
	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
	.sdw_process_wakeen = hda_sdw_process_wakeen_common,
	.check_ipc_irq	= hda_dsp_check_ipc_irq,
	.cl_init = cl_dsp_init,
	.power_down_dsp = hda_power_down_dsp,
	.disable_interrupts = hda_dsp_disable_interrupts,
	.hw_ip_version = SOF_INTEL_CAVS_2_5,
};

const struct sof_intel_dsp_desc tglh_chip_info = {
	/* Tigerlake-H */
	.cores_num = 2,
	.init_core_mask = 1,
	.host_managed_cores_mask = BIT(0),
	.ipc_req = CNL_DSP_REG_HIPCIDR,
	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
	.rom_init_timeout	= 300,
	.ssp_count = TGL_SSP_COUNT,
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
	.sdw_shim_base = SDW_SHIM_BASE,
	.sdw_alh_base = SDW_ALH_BASE,
	.d0i3_offset = SOF_HDA_VS_D0I3C,
	.read_sdw_lcount =  hda_sdw_check_lcount_common,
	.enable_sdw_irq	= hda_common_enable_sdw_irq,
	.check_sdw_irq	= hda_common_check_sdw_irq,
	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
	.sdw_process_wakeen = hda_sdw_process_wakeen_common,
	.check_ipc_irq	= hda_dsp_check_ipc_irq,
	.cl_init = cl_dsp_init,
	.power_down_dsp = hda_power_down_dsp,
	.disable_interrupts = hda_dsp_disable_interrupts,
	.hw_ip_version = SOF_INTEL_CAVS_2_5,
};

const struct sof_intel_dsp_desc ehl_chip_info = {
	/* Elkhartlake */
	.cores_num = 4,
	.init_core_mask = 1,
	.host_managed_cores_mask = BIT(0),
	.ipc_req = CNL_DSP_REG_HIPCIDR,
	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
	.rom_init_timeout	= 300,
	.ssp_count = TGL_SSP_COUNT,
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
	.sdw_shim_base = SDW_SHIM_BASE,
	.sdw_alh_base = SDW_ALH_BASE,
	.d0i3_offset = SOF_HDA_VS_D0I3C,
	.read_sdw_lcount =  hda_sdw_check_lcount_common,
	.enable_sdw_irq	= hda_common_enable_sdw_irq,
	.check_sdw_irq	= hda_common_check_sdw_irq,
	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
	.sdw_process_wakeen = hda_sdw_process_wakeen_common,
	.check_ipc_irq	= hda_dsp_check_ipc_irq,
	.cl_init = cl_dsp_init,
	.power_down_dsp = hda_power_down_dsp,
	.disable_interrupts = hda_dsp_disable_interrupts,
	.hw_ip_version = SOF_INTEL_CAVS_2_5,
};

const struct sof_intel_dsp_desc adls_chip_info = {
	/* Alderlake-S */
	.cores_num = 2,
	.init_core_mask = BIT(0),
	.host_managed_cores_mask = BIT(0),
	.ipc_req = CNL_DSP_REG_HIPCIDR,
	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
	.rom_init_timeout	= 300,
	.ssp_count = TGL_SSP_COUNT,
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
	.sdw_shim_base = SDW_SHIM_BASE,
	.sdw_alh_base = SDW_ALH_BASE,
	.d0i3_offset = SOF_HDA_VS_D0I3C,
	.read_sdw_lcount =  hda_sdw_check_lcount_common,
	.enable_sdw_irq	= hda_common_enable_sdw_irq,
	.check_sdw_irq	= hda_common_check_sdw_irq,
	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
	.sdw_process_wakeen = hda_sdw_process_wakeen_common,
	.check_ipc_irq	= hda_dsp_check_ipc_irq,
	.cl_init = cl_dsp_init,
	.power_down_dsp = hda_power_down_dsp,
	.disable_interrupts = hda_dsp_disable_interrupts,
	.hw_ip_version = SOF_INTEL_CAVS_2_5,
};
Commit	Line	Data
8b98491a RS	1	// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8b98491a RS	2	//
293ad281	3	// Copyright(c) 2020 Intel Corporation
8b98491a RS	4	//
	5	// Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
	6	//
	7
	8	/*
	9	* Hardware interface for audio DSP on Tigerlake.
	10	*/
	11
a4cfdebd RS	12	#include <sound/sof/ext_manifest4.h>
a4cfdebd RS	13	#include "../ipc4-priv.h"
8b98491a RS	14	#include "../ops.h"
	15	#include "hda.h"
	16	#include "hda-ipc.h"
	17	#include "../sof-audio.h"
	18
	19	static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
	20	{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
	21	{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
	22	{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
	23	};
	24
25ab9c40 PU	25	static const struct snd_sof_debugfs_map tgl_ipc4_dsp_debugfs[] = {
	26	{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
	27	{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
	28	{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
	29	{"fw_regs", HDA_DSP_BAR, SRAM_WINDOW_OFFSET(0), 0x1000, SOF_DEBUGFS_ACCESS_D0_ONLY},
	30	};
	31
41dd63cc RS	32	static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core)
41dd63cc RS	33	{
7a567740	34	const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
41dd63cc RS	35
	36	/* power up primary core if not already powered up and return */
	37	if (core == SOF_DSP_PRIMARY_CORE)
	38	return hda_dsp_enable_core(sdev, BIT(core));
	39
7a567740 PU	40	if (pm_ops->set_core_state)
	41	return pm_ops->set_core_state(sdev, core, true);
	42
	43	return 0;
41dd63cc RS	44	}
	45
	46	static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
	47	{
7a567740	48	const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
1b167ba8 RW	49	int ret;
	50
	51	if (pm_ops->set_core_state) {
	52	ret = pm_ops->set_core_state(sdev, core, false);
	53	if (ret < 0)
	54	return ret;
	55	}
41dd63cc RS	56
	57	/* power down primary core and return */
	58	if (core == SOF_DSP_PRIMARY_CORE)
	59	return hda_dsp_core_reset_power_down(sdev, BIT(core));
	60
7a567740	61	return 0;
41dd63cc RS	62	}
41dd63cc RS	63
8b98491a	64	/* Tigerlake ops */
37e809d5	65	struct snd_sof_dsp_ops sof_tgl_ops;
8b98491a	66
37e809d5 PLB	67	int sof_tgl_ops_init(struct snd_sof_dev *sdev)
	68	{
	69	/* common defaults */
	70	memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
8b98491a	71
37e809d5	72	/* probe/remove/shutdown */
2aa2a5ea	73	sof_tgl_ops.shutdown = hda_dsp_shutdown_dma_flush;
f71f59dd	74
a8fffb94	75	if (sdev->pdata->ipc_type == SOF_IPC_TYPE_3) {
e3105c0c RS	76	/* doorbell */
e3105c0c RS	77	sof_tgl_ops.irq_thread = cnl_ipc_irq_thread;
8b98491a	78
e3105c0c RS	79	/* ipc */
e3105c0c RS	80	sof_tgl_ops.send_msg = cnl_ipc_send_msg;
a996a333 PU	81
	82	/* debug */
	83	sof_tgl_ops.ipc_dump = cnl_ipc_dump;
25ab9c40 PU	84	sof_tgl_ops.debug_map = tgl_dsp_debugfs;
25ab9c40 PU	85	sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs);
996b07ef RS	86
996b07ef RS	87	sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc3;
e3105c0c RS	88	}
e3105c0c RS	89
a8fffb94	90	if (sdev->pdata->ipc_type == SOF_IPC_TYPE_4) {
a4cfdebd RS	91	struct sof_ipc4_fw_data *ipc4_data;
a4cfdebd RS	92
9b689653	93	sdev->private = kzalloc(sizeof(*ipc4_data), GFP_KERNEL);
a4cfdebd RS	94	if (!sdev->private)
	95	return -ENOMEM;
	96
	97	ipc4_data = sdev->private;
	98	ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
	99
cc4a3a19 PU	100	ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
cc4a3a19 PU	101
855a4772 RW	102	ipc4_data->fw_context_save = true;
855a4772 RW	103
3ab2c21e PU	104	/* External library loading support */
	105	ipc4_data->load_library = hda_dsp_ipc4_load_library;
	106
e3105c0c RS	107	/* doorbell */
	108	sof_tgl_ops.irq_thread = cnl_ipc4_irq_thread;
	109
	110	/* ipc */
	111	sof_tgl_ops.send_msg = cnl_ipc4_send_msg;
a996a333 PU	112
	113	/* debug */
	114	sof_tgl_ops.ipc_dump = cnl_ipc4_dump;
eb6e5dab	115	sof_tgl_ops.dbg_dump = hda_ipc4_dsp_dump;
25ab9c40 PU	116	sof_tgl_ops.debug_map = tgl_ipc4_dsp_debugfs;
25ab9c40 PU	117	sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_ipc4_dsp_debugfs);
996b07ef RS	118
996b07ef RS	119	sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
e3105c0c	120	}
8b98491a	121
51ec71dc RS	122	/* set DAI driver ops */
	123	hda_set_dai_drv_ops(sdev, &sof_tgl_ops);
	124
8b98491a	125	/* pre/post fw run */
37e809d5	126	sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run;
8b98491a	127
37e809d5 PLB	128	/* firmware run */
37e809d5 PLB	129	sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax;
edbaaada	130
9ea80748	131	/* dsp core get/put */
37e809d5 PLB	132	sof_tgl_ops.core_get = tgl_dsp_core_get;
37e809d5 PLB	133	sof_tgl_ops.core_put = tgl_dsp_core_put;
8b98491a	134
37e809d5	135	return 0;
8b98491a	136	};
8b98491a RS	137
8b98491a RS	138	const struct sof_intel_dsp_desc tgl_chip_info = {
4ad03f89	139	/* Tigerlake , Alderlake */
8b98491a RS	140	.cores_num = 4,
8b98491a RS	141	.init_core_mask = 1,
fde10655	142	.host_managed_cores_mask = BIT(0),
8b98491a RS	143	.ipc_req = CNL_DSP_REG_HIPCIDR,
	144	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	145	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	146	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	147	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
71778f79	148	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
8b98491a	149	.rom_init_timeout = 300,
9ccbc2e1	150	.ssp_count = TGL_SSP_COUNT,
8b98491a	151	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
1cbf6443 BL	152	.sdw_shim_base = SDW_SHIM_BASE,
1cbf6443 BL	153	.sdw_alh_base = SDW_ALH_BASE,
f8632adc	154	.d0i3_offset = SOF_HDA_VS_D0I3C,
625339ca	155	.read_sdw_lcount = hda_sdw_check_lcount_common,
8ebc9074	156	.enable_sdw_irq = hda_common_enable_sdw_irq,
198fa4bc	157	.check_sdw_irq = hda_common_check_sdw_irq,
9362ab78	158	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
3b7bd0c1	159	.sdw_process_wakeen = hda_sdw_process_wakeen_common,
3dee239e	160	.check_ipc_irq = hda_dsp_check_ipc_irq,
ab222a4a	161	.cl_init = cl_dsp_init,
c714031f	162	.power_down_dsp = hda_power_down_dsp,
b2520dbc	163	.disable_interrupts = hda_dsp_disable_interrupts,
03cf7262	164	.hw_ip_version = SOF_INTEL_CAVS_2_5,
8b98491a	165	};
30ee3738 RW	166
	167	const struct sof_intel_dsp_desc tglh_chip_info = {
	168	/* Tigerlake-H */
	169	.cores_num = 2,
	170	.init_core_mask = 1,
	171	.host_managed_cores_mask = BIT(0),
	172	.ipc_req = CNL_DSP_REG_HIPCIDR,
	173	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	174	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	175	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	176	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
71778f79	177	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
30ee3738	178	.rom_init_timeout = 300,
9ccbc2e1	179	.ssp_count = TGL_SSP_COUNT,
30ee3738	180	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
1cbf6443 BL	181	.sdw_shim_base = SDW_SHIM_BASE,
1cbf6443 BL	182	.sdw_alh_base = SDW_ALH_BASE,
f8632adc	183	.d0i3_offset = SOF_HDA_VS_D0I3C,
625339ca	184	.read_sdw_lcount = hda_sdw_check_lcount_common,
8ebc9074	185	.enable_sdw_irq = hda_common_enable_sdw_irq,
198fa4bc	186	.check_sdw_irq = hda_common_check_sdw_irq,
9362ab78	187	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
3b7bd0c1	188	.sdw_process_wakeen = hda_sdw_process_wakeen_common,
3dee239e	189	.check_ipc_irq = hda_dsp_check_ipc_irq,
ab222a4a	190	.cl_init = cl_dsp_init,
c714031f	191	.power_down_dsp = hda_power_down_dsp,
b2520dbc	192	.disable_interrupts = hda_dsp_disable_interrupts,
03cf7262	193	.hw_ip_version = SOF_INTEL_CAVS_2_5,
30ee3738	194	};
6c2b6bb0	195
8bb84ca8 PLB	196	const struct sof_intel_dsp_desc ehl_chip_info = {
	197	/* Elkhartlake */
	198	.cores_num = 4,
	199	.init_core_mask = 1,
	200	.host_managed_cores_mask = BIT(0),
	201	.ipc_req = CNL_DSP_REG_HIPCIDR,
	202	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	203	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	204	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	205	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
71778f79	206	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
8bb84ca8	207	.rom_init_timeout = 300,
9ccbc2e1	208	.ssp_count = TGL_SSP_COUNT,
8bb84ca8	209	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
1cbf6443 BL	210	.sdw_shim_base = SDW_SHIM_BASE,
1cbf6443 BL	211	.sdw_alh_base = SDW_ALH_BASE,
f8632adc	212	.d0i3_offset = SOF_HDA_VS_D0I3C,
625339ca	213	.read_sdw_lcount = hda_sdw_check_lcount_common,
8ebc9074	214	.enable_sdw_irq = hda_common_enable_sdw_irq,
198fa4bc	215	.check_sdw_irq = hda_common_check_sdw_irq,
9362ab78	216	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
3b7bd0c1	217	.sdw_process_wakeen = hda_sdw_process_wakeen_common,
3dee239e	218	.check_ipc_irq = hda_dsp_check_ipc_irq,
ab222a4a	219	.cl_init = cl_dsp_init,
c714031f	220	.power_down_dsp = hda_power_down_dsp,
b2520dbc	221	.disable_interrupts = hda_dsp_disable_interrupts,
03cf7262	222	.hw_ip_version = SOF_INTEL_CAVS_2_5,
8bb84ca8	223	};
8bb84ca8	224
6c2b6bb0 KV	225	const struct sof_intel_dsp_desc adls_chip_info = {
	226	/* Alderlake-S */
	227	.cores_num = 2,
	228	.init_core_mask = BIT(0),
	229	.host_managed_cores_mask = BIT(0),
	230	.ipc_req = CNL_DSP_REG_HIPCIDR,
	231	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	232	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	233	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	234	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
71778f79	235	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
6c2b6bb0	236	.rom_init_timeout = 300,
9ccbc2e1	237	.ssp_count = TGL_SSP_COUNT,
6c2b6bb0	238	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
1cbf6443 BL	239	.sdw_shim_base = SDW_SHIM_BASE,
1cbf6443 BL	240	.sdw_alh_base = SDW_ALH_BASE,
f8632adc	241	.d0i3_offset = SOF_HDA_VS_D0I3C,
625339ca	242	.read_sdw_lcount = hda_sdw_check_lcount_common,
8ebc9074	243	.enable_sdw_irq = hda_common_enable_sdw_irq,
198fa4bc	244	.check_sdw_irq = hda_common_check_sdw_irq,
9362ab78	245	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
3b7bd0c1	246	.sdw_process_wakeen = hda_sdw_process_wakeen_common,
3dee239e	247	.check_ipc_irq = hda_dsp_check_ipc_irq,
ab222a4a	248	.cl_init = cl_dsp_init,
c714031f	249	.power_down_dsp = hda_power_down_dsp,
b2520dbc	250	.disable_interrupts = hda_dsp_disable_interrupts,
03cf7262	251	.hw_ip_version = SOF_INTEL_CAVS_2_5,
6c2b6bb0	252	};