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8b98491a RS |
1 | // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) |
2 | // | |
3 | // Copyright(c) 2020 Intel Corporation. All rights reserved. | |
4 | // | |
5 | // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> | |
6 | // | |
7 | ||
8 | /* | |
9 | * Hardware interface for audio DSP on Tigerlake. | |
10 | */ | |
11 | ||
a4cfdebd RS |
12 | #include <sound/sof/ext_manifest4.h> |
13 | #include "../ipc4-priv.h" | |
8b98491a RS |
14 | #include "../ops.h" |
15 | #include "hda.h" | |
16 | #include "hda-ipc.h" | |
17 | #include "../sof-audio.h" | |
18 | ||
19 | static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { | |
20 | {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, | |
21 | {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, | |
22 | {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, | |
23 | }; | |
24 | ||
41dd63cc RS |
25 | static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core) |
26 | { | |
7a567740 | 27 | const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; |
41dd63cc RS |
28 | |
29 | /* power up primary core if not already powered up and return */ | |
30 | if (core == SOF_DSP_PRIMARY_CORE) | |
31 | return hda_dsp_enable_core(sdev, BIT(core)); | |
32 | ||
7a567740 PU |
33 | if (pm_ops->set_core_state) |
34 | return pm_ops->set_core_state(sdev, core, true); | |
35 | ||
36 | return 0; | |
41dd63cc RS |
37 | } |
38 | ||
39 | static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core) | |
40 | { | |
7a567740 | 41 | const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; |
41dd63cc RS |
42 | |
43 | /* power down primary core and return */ | |
44 | if (core == SOF_DSP_PRIMARY_CORE) | |
45 | return hda_dsp_core_reset_power_down(sdev, BIT(core)); | |
46 | ||
7a567740 PU |
47 | if (pm_ops->set_core_state) |
48 | return pm_ops->set_core_state(sdev, core, false); | |
49 | ||
50 | return 0; | |
41dd63cc RS |
51 | } |
52 | ||
8b98491a | 53 | /* Tigerlake ops */ |
37e809d5 PLB |
54 | struct snd_sof_dsp_ops sof_tgl_ops; |
55 | EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); | |
8b98491a | 56 | |
37e809d5 PLB |
57 | int sof_tgl_ops_init(struct snd_sof_dev *sdev) |
58 | { | |
59 | /* common defaults */ | |
60 | memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); | |
8b98491a | 61 | |
37e809d5 PLB |
62 | /* probe/remove/shutdown */ |
63 | sof_tgl_ops.shutdown = hda_dsp_shutdown; | |
f71f59dd | 64 | |
e3105c0c RS |
65 | if (sdev->pdata->ipc_type == SOF_IPC) { |
66 | /* doorbell */ | |
67 | sof_tgl_ops.irq_thread = cnl_ipc_irq_thread; | |
8b98491a | 68 | |
e3105c0c RS |
69 | /* ipc */ |
70 | sof_tgl_ops.send_msg = cnl_ipc_send_msg; | |
71 | } | |
72 | ||
73 | if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) { | |
a4cfdebd RS |
74 | struct sof_ipc4_fw_data *ipc4_data; |
75 | ||
76 | sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL); | |
77 | if (!sdev->private) | |
78 | return -ENOMEM; | |
79 | ||
80 | ipc4_data = sdev->private; | |
81 | ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; | |
82 | ||
cc4a3a19 PU |
83 | ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; |
84 | ||
e3105c0c RS |
85 | /* doorbell */ |
86 | sof_tgl_ops.irq_thread = cnl_ipc4_irq_thread; | |
87 | ||
88 | /* ipc */ | |
89 | sof_tgl_ops.send_msg = cnl_ipc4_send_msg; | |
90 | } | |
8b98491a | 91 | |
51ec71dc RS |
92 | /* set DAI driver ops */ |
93 | hda_set_dai_drv_ops(sdev, &sof_tgl_ops); | |
94 | ||
8b98491a | 95 | /* debug */ |
37e809d5 PLB |
96 | sof_tgl_ops.debug_map = tgl_dsp_debugfs; |
97 | sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs); | |
98 | sof_tgl_ops.ipc_dump = cnl_ipc_dump; | |
8b98491a RS |
99 | |
100 | /* pre/post fw run */ | |
37e809d5 | 101 | sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run; |
8b98491a | 102 | |
37e809d5 PLB |
103 | /* firmware run */ |
104 | sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax; | |
edbaaada | 105 | |
9ea80748 | 106 | /* dsp core get/put */ |
37e809d5 PLB |
107 | sof_tgl_ops.core_get = tgl_dsp_core_get; |
108 | sof_tgl_ops.core_put = tgl_dsp_core_put; | |
8b98491a | 109 | |
37e809d5 | 110 | return 0; |
8b98491a | 111 | }; |
37e809d5 | 112 | EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); |
8b98491a RS |
113 | |
114 | const struct sof_intel_dsp_desc tgl_chip_info = { | |
4ad03f89 | 115 | /* Tigerlake , Alderlake */ |
8b98491a RS |
116 | .cores_num = 4, |
117 | .init_core_mask = 1, | |
fde10655 | 118 | .host_managed_cores_mask = BIT(0), |
8b98491a RS |
119 | .ipc_req = CNL_DSP_REG_HIPCIDR, |
120 | .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, | |
121 | .ipc_ack = CNL_DSP_REG_HIPCIDA, | |
122 | .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, | |
123 | .ipc_ctl = CNL_DSP_REG_HIPCCTL, | |
71778f79 | 124 | .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
8b98491a | 125 | .rom_init_timeout = 300, |
9ccbc2e1 | 126 | .ssp_count = TGL_SSP_COUNT, |
8b98491a | 127 | .ssp_base_offset = CNL_SSP_BASE_OFFSET, |
1cbf6443 BL |
128 | .sdw_shim_base = SDW_SHIM_BASE, |
129 | .sdw_alh_base = SDW_ALH_BASE, | |
198fa4bc | 130 | .check_sdw_irq = hda_common_check_sdw_irq, |
3dee239e | 131 | .check_ipc_irq = hda_dsp_check_ipc_irq, |
ab222a4a | 132 | .cl_init = cl_dsp_init, |
03cf7262 | 133 | .hw_ip_version = SOF_INTEL_CAVS_2_5, |
8b98491a RS |
134 | }; |
135 | EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); | |
30ee3738 RW |
136 | |
137 | const struct sof_intel_dsp_desc tglh_chip_info = { | |
138 | /* Tigerlake-H */ | |
139 | .cores_num = 2, | |
140 | .init_core_mask = 1, | |
141 | .host_managed_cores_mask = BIT(0), | |
142 | .ipc_req = CNL_DSP_REG_HIPCIDR, | |
143 | .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, | |
144 | .ipc_ack = CNL_DSP_REG_HIPCIDA, | |
145 | .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, | |
146 | .ipc_ctl = CNL_DSP_REG_HIPCCTL, | |
71778f79 | 147 | .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
30ee3738 | 148 | .rom_init_timeout = 300, |
9ccbc2e1 | 149 | .ssp_count = TGL_SSP_COUNT, |
30ee3738 | 150 | .ssp_base_offset = CNL_SSP_BASE_OFFSET, |
1cbf6443 BL |
151 | .sdw_shim_base = SDW_SHIM_BASE, |
152 | .sdw_alh_base = SDW_ALH_BASE, | |
198fa4bc | 153 | .check_sdw_irq = hda_common_check_sdw_irq, |
3dee239e | 154 | .check_ipc_irq = hda_dsp_check_ipc_irq, |
ab222a4a | 155 | .cl_init = cl_dsp_init, |
03cf7262 | 156 | .hw_ip_version = SOF_INTEL_CAVS_2_5, |
30ee3738 RW |
157 | }; |
158 | EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); | |
6c2b6bb0 | 159 | |
8bb84ca8 PLB |
160 | const struct sof_intel_dsp_desc ehl_chip_info = { |
161 | /* Elkhartlake */ | |
162 | .cores_num = 4, | |
163 | .init_core_mask = 1, | |
164 | .host_managed_cores_mask = BIT(0), | |
165 | .ipc_req = CNL_DSP_REG_HIPCIDR, | |
166 | .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, | |
167 | .ipc_ack = CNL_DSP_REG_HIPCIDA, | |
168 | .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, | |
169 | .ipc_ctl = CNL_DSP_REG_HIPCCTL, | |
71778f79 | 170 | .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
8bb84ca8 | 171 | .rom_init_timeout = 300, |
9ccbc2e1 | 172 | .ssp_count = TGL_SSP_COUNT, |
8bb84ca8 | 173 | .ssp_base_offset = CNL_SSP_BASE_OFFSET, |
1cbf6443 BL |
174 | .sdw_shim_base = SDW_SHIM_BASE, |
175 | .sdw_alh_base = SDW_ALH_BASE, | |
198fa4bc | 176 | .check_sdw_irq = hda_common_check_sdw_irq, |
3dee239e | 177 | .check_ipc_irq = hda_dsp_check_ipc_irq, |
ab222a4a | 178 | .cl_init = cl_dsp_init, |
03cf7262 | 179 | .hw_ip_version = SOF_INTEL_CAVS_2_5, |
8bb84ca8 PLB |
180 | }; |
181 | EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); | |
182 | ||
6c2b6bb0 KV |
183 | const struct sof_intel_dsp_desc adls_chip_info = { |
184 | /* Alderlake-S */ | |
185 | .cores_num = 2, | |
186 | .init_core_mask = BIT(0), | |
187 | .host_managed_cores_mask = BIT(0), | |
188 | .ipc_req = CNL_DSP_REG_HIPCIDR, | |
189 | .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, | |
190 | .ipc_ack = CNL_DSP_REG_HIPCIDA, | |
191 | .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, | |
192 | .ipc_ctl = CNL_DSP_REG_HIPCCTL, | |
71778f79 | 193 | .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
6c2b6bb0 | 194 | .rom_init_timeout = 300, |
9ccbc2e1 | 195 | .ssp_count = TGL_SSP_COUNT, |
6c2b6bb0 | 196 | .ssp_base_offset = CNL_SSP_BASE_OFFSET, |
1cbf6443 BL |
197 | .sdw_shim_base = SDW_SHIM_BASE, |
198 | .sdw_alh_base = SDW_ALH_BASE, | |
198fa4bc | 199 | .check_sdw_irq = hda_common_check_sdw_irq, |
3dee239e | 200 | .check_ipc_irq = hda_dsp_check_ipc_irq, |
ab222a4a | 201 | .cl_init = cl_dsp_init, |
03cf7262 | 202 | .hw_ip_version = SOF_INTEL_CAVS_2_5, |
6c2b6bb0 KV |
203 | }; |
204 | EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); |