[linux-2.6-block.git] / sound / soc / sof / intel / tgl.c

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright(c) 2020 Intel Corporation. All rights reserved.
//
// Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
//

/*
 * Hardware interface for audio DSP on Tigerlake.
 */

#include <sound/sof/ext_manifest4.h>
#include "../ipc4-priv.h"
#include "../ops.h"
#include "hda.h"
#include "hda-ipc.h"
#include "../sof-audio.h"

static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
	{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
	{"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
	{"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
};

static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core)
{
	const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;

	/* power up primary core if not already powered up and return */
	if (core == SOF_DSP_PRIMARY_CORE)
		return hda_dsp_enable_core(sdev, BIT(core));

	if (pm_ops->set_core_state)
		return pm_ops->set_core_state(sdev, core, true);

	return 0;
}

static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
{
	const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;

	/* power down primary core and return */
	if (core == SOF_DSP_PRIMARY_CORE)
		return hda_dsp_core_reset_power_down(sdev, BIT(core));

	if (pm_ops->set_core_state)
		return pm_ops->set_core_state(sdev, core, false);

	return 0;
}

/* Tigerlake ops */
struct snd_sof_dsp_ops sof_tgl_ops;
EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);

int sof_tgl_ops_init(struct snd_sof_dev *sdev)
{
	/* common defaults */
	memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));

	/* probe/remove/shutdown */
	sof_tgl_ops.shutdown	= hda_dsp_shutdown;

	if (sdev->pdata->ipc_type == SOF_IPC) {
		/* doorbell */
		sof_tgl_ops.irq_thread	= cnl_ipc_irq_thread;

		/* ipc */
		sof_tgl_ops.send_msg	= cnl_ipc_send_msg;

		/* debug */
		sof_tgl_ops.ipc_dump	= cnl_ipc_dump;
	}

	if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
		struct sof_ipc4_fw_data *ipc4_data;

		sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL);
		if (!sdev->private)
			return -ENOMEM;

		ipc4_data = sdev->private;
		ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;

		ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;

		/* External library loading support */
		ipc4_data->load_library = hda_dsp_ipc4_load_library;

		/* doorbell */
		sof_tgl_ops.irq_thread	= cnl_ipc4_irq_thread;

		/* ipc */
		sof_tgl_ops.send_msg	= cnl_ipc4_send_msg;

		/* debug */
		sof_tgl_ops.ipc_dump	= cnl_ipc4_dump;
	}

	/* set DAI driver ops */
	hda_set_dai_drv_ops(sdev, &sof_tgl_ops);

	/* debug */
	sof_tgl_ops.debug_map	= tgl_dsp_debugfs;
	sof_tgl_ops.debug_map_count	= ARRAY_SIZE(tgl_dsp_debugfs);

	/* pre/post fw run */
	sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run;

	/* firmware run */
	sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax;

	/* dsp core get/put */
	sof_tgl_ops.core_get = tgl_dsp_core_get;
	sof_tgl_ops.core_put = tgl_dsp_core_put;

	return 0;
};
EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);

const struct sof_intel_dsp_desc tgl_chip_info = {
	/* Tigerlake , Alderlake */
	.cores_num = 4,
	.init_core_mask = 1,
	.host_managed_cores_mask = BIT(0),
	.ipc_req = CNL_DSP_REG_HIPCIDR,
	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
	.rom_init_timeout	= 300,
	.ssp_count = TGL_SSP_COUNT,
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
	.sdw_shim_base = SDW_SHIM_BASE,
	.sdw_alh_base = SDW_ALH_BASE,
	.d0i3_offset = SOF_HDA_VS_D0I3C,
	.enable_sdw_irq	= hda_common_enable_sdw_irq,
	.check_sdw_irq	= hda_common_check_sdw_irq,
	.check_ipc_irq	= hda_dsp_check_ipc_irq,
	.cl_init = cl_dsp_init,
	.power_down_dsp = hda_power_down_dsp,
	.disable_interrupts = hda_dsp_disable_interrupts,
	.hw_ip_version = SOF_INTEL_CAVS_2_5,
};
EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

const struct sof_intel_dsp_desc tglh_chip_info = {
	/* Tigerlake-H */
	.cores_num = 2,
	.init_core_mask = 1,
	.host_managed_cores_mask = BIT(0),
	.ipc_req = CNL_DSP_REG_HIPCIDR,
	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
	.rom_init_timeout	= 300,
	.ssp_count = TGL_SSP_COUNT,
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
	.sdw_shim_base = SDW_SHIM_BASE,
	.sdw_alh_base = SDW_ALH_BASE,
	.d0i3_offset = SOF_HDA_VS_D0I3C,
	.enable_sdw_irq	= hda_common_enable_sdw_irq,
	.check_sdw_irq	= hda_common_check_sdw_irq,
	.check_ipc_irq	= hda_dsp_check_ipc_irq,
	.cl_init = cl_dsp_init,
	.power_down_dsp = hda_power_down_dsp,
	.disable_interrupts = hda_dsp_disable_interrupts,
	.hw_ip_version = SOF_INTEL_CAVS_2_5,
};
EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

const struct sof_intel_dsp_desc ehl_chip_info = {
	/* Elkhartlake */
	.cores_num = 4,
	.init_core_mask = 1,
	.host_managed_cores_mask = BIT(0),
	.ipc_req = CNL_DSP_REG_HIPCIDR,
	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
	.rom_init_timeout	= 300,
	.ssp_count = TGL_SSP_COUNT,
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
	.sdw_shim_base = SDW_SHIM_BASE,
	.sdw_alh_base = SDW_ALH_BASE,
	.d0i3_offset = SOF_HDA_VS_D0I3C,
	.enable_sdw_irq	= hda_common_enable_sdw_irq,
	.check_sdw_irq	= hda_common_check_sdw_irq,
	.check_ipc_irq	= hda_dsp_check_ipc_irq,
	.cl_init = cl_dsp_init,
	.power_down_dsp = hda_power_down_dsp,
	.disable_interrupts = hda_dsp_disable_interrupts,
	.hw_ip_version = SOF_INTEL_CAVS_2_5,
};
EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

const struct sof_intel_dsp_desc adls_chip_info = {
	/* Alderlake-S */
	.cores_num = 2,
	.init_core_mask = BIT(0),
	.host_managed_cores_mask = BIT(0),
	.ipc_req = CNL_DSP_REG_HIPCIDR,
	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
	.rom_init_timeout	= 300,
	.ssp_count = TGL_SSP_COUNT,
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
	.sdw_shim_base = SDW_SHIM_BASE,
	.sdw_alh_base = SDW_ALH_BASE,
	.d0i3_offset = SOF_HDA_VS_D0I3C,
	.enable_sdw_irq	= hda_common_enable_sdw_irq,
	.check_sdw_irq	= hda_common_check_sdw_irq,
	.check_ipc_irq	= hda_dsp_check_ipc_irq,
	.cl_init = cl_dsp_init,
	.power_down_dsp = hda_power_down_dsp,
	.disable_interrupts = hda_dsp_disable_interrupts,
	.hw_ip_version = SOF_INTEL_CAVS_2_5,
};
EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
Commit	Line	Data
8b98491a RS	1	// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
	2	//
	3	// Copyright(c) 2020 Intel Corporation. All rights reserved.
	4	//
	5	// Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
	6	//
	7
	8	/*
	9	* Hardware interface for audio DSP on Tigerlake.
	10	*/
	11
a4cfdebd RS	12	#include <sound/sof/ext_manifest4.h>
a4cfdebd RS	13	#include "../ipc4-priv.h"
8b98491a RS	14	#include "../ops.h"
	15	#include "hda.h"
	16	#include "hda-ipc.h"
	17	#include "../sof-audio.h"
	18
	19	static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
	20	{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
	21	{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
	22	{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
	23	};
	24
41dd63cc RS	25	static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core)
41dd63cc RS	26	{
7a567740	27	const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
41dd63cc RS	28
	29	/* power up primary core if not already powered up and return */
	30	if (core == SOF_DSP_PRIMARY_CORE)
	31	return hda_dsp_enable_core(sdev, BIT(core));
	32
7a567740 PU	33	if (pm_ops->set_core_state)
	34	return pm_ops->set_core_state(sdev, core, true);
	35
	36	return 0;
41dd63cc RS	37	}
	38
	39	static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
	40	{
7a567740	41	const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
41dd63cc RS	42
	43	/* power down primary core and return */
	44	if (core == SOF_DSP_PRIMARY_CORE)
	45	return hda_dsp_core_reset_power_down(sdev, BIT(core));
	46
7a567740 PU	47	if (pm_ops->set_core_state)
	48	return pm_ops->set_core_state(sdev, core, false);
	49
	50	return 0;
41dd63cc RS	51	}
41dd63cc RS	52
8b98491a	53	/* Tigerlake ops */
37e809d5 PLB	54	struct snd_sof_dsp_ops sof_tgl_ops;
37e809d5 PLB	55	EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
8b98491a	56
37e809d5 PLB	57	int sof_tgl_ops_init(struct snd_sof_dev *sdev)
	58	{
	59	/* common defaults */
	60	memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
8b98491a	61
37e809d5 PLB	62	/* probe/remove/shutdown */
37e809d5 PLB	63	sof_tgl_ops.shutdown = hda_dsp_shutdown;
f71f59dd	64
e3105c0c RS	65	if (sdev->pdata->ipc_type == SOF_IPC) {
	66	/* doorbell */
	67	sof_tgl_ops.irq_thread = cnl_ipc_irq_thread;
8b98491a	68
e3105c0c RS	69	/* ipc */
e3105c0c RS	70	sof_tgl_ops.send_msg = cnl_ipc_send_msg;
a996a333 PU	71
	72	/* debug */
	73	sof_tgl_ops.ipc_dump = cnl_ipc_dump;
e3105c0c RS	74	}
	75
	76	if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
a4cfdebd RS	77	struct sof_ipc4_fw_data *ipc4_data;
	78
	79	sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL);
	80	if (!sdev->private)
	81	return -ENOMEM;
	82
	83	ipc4_data = sdev->private;
	84	ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
	85
cc4a3a19 PU	86	ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
cc4a3a19 PU	87
3ab2c21e PU	88	/* External library loading support */
	89	ipc4_data->load_library = hda_dsp_ipc4_load_library;
	90
e3105c0c RS	91	/* doorbell */
	92	sof_tgl_ops.irq_thread = cnl_ipc4_irq_thread;
	93
	94	/* ipc */
	95	sof_tgl_ops.send_msg = cnl_ipc4_send_msg;
a996a333 PU	96
	97	/* debug */
	98	sof_tgl_ops.ipc_dump = cnl_ipc4_dump;
e3105c0c	99	}
8b98491a	100
51ec71dc RS	101	/* set DAI driver ops */
	102	hda_set_dai_drv_ops(sdev, &sof_tgl_ops);
	103
8b98491a	104	/* debug */
37e809d5 PLB	105	sof_tgl_ops.debug_map = tgl_dsp_debugfs;
37e809d5 PLB	106	sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs);
8b98491a RS	107
8b98491a RS	108	/* pre/post fw run */
37e809d5	109	sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run;
8b98491a	110
37e809d5 PLB	111	/* firmware run */
37e809d5 PLB	112	sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax;
edbaaada	113
9ea80748	114	/* dsp core get/put */
37e809d5 PLB	115	sof_tgl_ops.core_get = tgl_dsp_core_get;
37e809d5 PLB	116	sof_tgl_ops.core_put = tgl_dsp_core_put;
8b98491a	117
37e809d5	118	return 0;
8b98491a	119	};
37e809d5	120	EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
8b98491a RS	121
8b98491a RS	122	const struct sof_intel_dsp_desc tgl_chip_info = {
4ad03f89	123	/* Tigerlake , Alderlake */
8b98491a RS	124	.cores_num = 4,
8b98491a RS	125	.init_core_mask = 1,
fde10655	126	.host_managed_cores_mask = BIT(0),
8b98491a RS	127	.ipc_req = CNL_DSP_REG_HIPCIDR,
	128	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	129	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	130	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	131	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
71778f79	132	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
8b98491a	133	.rom_init_timeout = 300,
9ccbc2e1	134	.ssp_count = TGL_SSP_COUNT,
8b98491a	135	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
1cbf6443 BL	136	.sdw_shim_base = SDW_SHIM_BASE,
1cbf6443 BL	137	.sdw_alh_base = SDW_ALH_BASE,
f8632adc	138	.d0i3_offset = SOF_HDA_VS_D0I3C,
8ebc9074	139	.enable_sdw_irq = hda_common_enable_sdw_irq,
198fa4bc	140	.check_sdw_irq = hda_common_check_sdw_irq,
3dee239e	141	.check_ipc_irq = hda_dsp_check_ipc_irq,
ab222a4a	142	.cl_init = cl_dsp_init,
c714031f	143	.power_down_dsp = hda_power_down_dsp,
b2520dbc	144	.disable_interrupts = hda_dsp_disable_interrupts,
03cf7262	145	.hw_ip_version = SOF_INTEL_CAVS_2_5,
8b98491a RS	146	};
8b98491a RS	147	EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
30ee3738 RW	148
	149	const struct sof_intel_dsp_desc tglh_chip_info = {
	150	/* Tigerlake-H */
	151	.cores_num = 2,
	152	.init_core_mask = 1,
	153	.host_managed_cores_mask = BIT(0),
	154	.ipc_req = CNL_DSP_REG_HIPCIDR,
	155	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	156	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	157	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	158	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
71778f79	159	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
30ee3738	160	.rom_init_timeout = 300,
9ccbc2e1	161	.ssp_count = TGL_SSP_COUNT,
30ee3738	162	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
1cbf6443 BL	163	.sdw_shim_base = SDW_SHIM_BASE,
1cbf6443 BL	164	.sdw_alh_base = SDW_ALH_BASE,
f8632adc	165	.d0i3_offset = SOF_HDA_VS_D0I3C,
8ebc9074	166	.enable_sdw_irq = hda_common_enable_sdw_irq,
198fa4bc	167	.check_sdw_irq = hda_common_check_sdw_irq,
3dee239e	168	.check_ipc_irq = hda_dsp_check_ipc_irq,
ab222a4a	169	.cl_init = cl_dsp_init,
c714031f	170	.power_down_dsp = hda_power_down_dsp,
b2520dbc	171	.disable_interrupts = hda_dsp_disable_interrupts,
03cf7262	172	.hw_ip_version = SOF_INTEL_CAVS_2_5,
30ee3738 RW	173	};
30ee3738 RW	174	EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
6c2b6bb0	175
8bb84ca8 PLB	176	const struct sof_intel_dsp_desc ehl_chip_info = {
	177	/* Elkhartlake */
	178	.cores_num = 4,
	179	.init_core_mask = 1,
	180	.host_managed_cores_mask = BIT(0),
	181	.ipc_req = CNL_DSP_REG_HIPCIDR,
	182	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	183	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	184	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	185	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
71778f79	186	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
8bb84ca8	187	.rom_init_timeout = 300,
9ccbc2e1	188	.ssp_count = TGL_SSP_COUNT,
8bb84ca8	189	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
1cbf6443 BL	190	.sdw_shim_base = SDW_SHIM_BASE,
1cbf6443 BL	191	.sdw_alh_base = SDW_ALH_BASE,
f8632adc	192	.d0i3_offset = SOF_HDA_VS_D0I3C,
8ebc9074	193	.enable_sdw_irq = hda_common_enable_sdw_irq,
198fa4bc	194	.check_sdw_irq = hda_common_check_sdw_irq,
3dee239e	195	.check_ipc_irq = hda_dsp_check_ipc_irq,
ab222a4a	196	.cl_init = cl_dsp_init,
c714031f	197	.power_down_dsp = hda_power_down_dsp,
b2520dbc	198	.disable_interrupts = hda_dsp_disable_interrupts,
03cf7262	199	.hw_ip_version = SOF_INTEL_CAVS_2_5,
8bb84ca8 PLB	200	};
	201	EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
	202
6c2b6bb0 KV	203	const struct sof_intel_dsp_desc adls_chip_info = {
	204	/* Alderlake-S */
	205	.cores_num = 2,
	206	.init_core_mask = BIT(0),
	207	.host_managed_cores_mask = BIT(0),
	208	.ipc_req = CNL_DSP_REG_HIPCIDR,
	209	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	210	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	211	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	212	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
71778f79	213	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
6c2b6bb0	214	.rom_init_timeout = 300,
9ccbc2e1	215	.ssp_count = TGL_SSP_COUNT,
6c2b6bb0	216	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
1cbf6443 BL	217	.sdw_shim_base = SDW_SHIM_BASE,
1cbf6443 BL	218	.sdw_alh_base = SDW_ALH_BASE,
f8632adc	219	.d0i3_offset = SOF_HDA_VS_D0I3C,
8ebc9074	220	.enable_sdw_irq = hda_common_enable_sdw_irq,
198fa4bc	221	.check_sdw_irq = hda_common_check_sdw_irq,
3dee239e	222	.check_ipc_irq = hda_dsp_check_ipc_irq,
ab222a4a	223	.cl_init = cl_dsp_init,
c714031f	224	.power_down_dsp = hda_power_down_dsp,
b2520dbc	225	.disable_interrupts = hda_dsp_disable_interrupts,
03cf7262	226	.hw_ip_version = SOF_INTEL_CAVS_2_5,
6c2b6bb0 KV	227	};
6c2b6bb0 KV	228	EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);