[linux-2.6-block.git] / sound / soc / sof / intel / tgl.c

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright(c) 2020 Intel Corporation. All rights reserved.
//
// Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
//

/*
 * Hardware interface for audio DSP on Tigerlake.
 */

#include <sound/sof/ext_manifest4.h>
#include "../ipc4-priv.h"
#include "../ops.h"
#include "hda.h"
#include "hda-ipc.h"
#include "../sof-audio.h"

static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
	{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
	{"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
	{"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
};

static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core)
{
	const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;

	/* power up primary core if not already powered up and return */
	if (core == SOF_DSP_PRIMARY_CORE)
		return hda_dsp_enable_core(sdev, BIT(core));

	if (pm_ops->set_core_state)
		return pm_ops->set_core_state(sdev, core, true);

	return 0;
}

static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
{
	const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
	int ret;

	if (pm_ops->set_core_state) {
		ret = pm_ops->set_core_state(sdev, core, false);
		if (ret < 0)
			return ret;
	}

	/* power down primary core and return */
	if (core == SOF_DSP_PRIMARY_CORE)
		return hda_dsp_core_reset_power_down(sdev, BIT(core));

	return 0;
}

/* Tigerlake ops */
struct snd_sof_dsp_ops sof_tgl_ops;
EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);

int sof_tgl_ops_init(struct snd_sof_dev *sdev)
{
	/* common defaults */
	memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));

	/* probe/remove/shutdown */
	sof_tgl_ops.shutdown	= hda_dsp_shutdown_dma_flush;

	if (sdev->pdata->ipc_type == SOF_IPC) {
		/* doorbell */
		sof_tgl_ops.irq_thread	= cnl_ipc_irq_thread;

		/* ipc */
		sof_tgl_ops.send_msg	= cnl_ipc_send_msg;

		/* debug */
		sof_tgl_ops.ipc_dump	= cnl_ipc_dump;

		sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc3;
	}

	if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
		struct sof_ipc4_fw_data *ipc4_data;

		sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL);
		if (!sdev->private)
			return -ENOMEM;

		ipc4_data = sdev->private;
		ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;

		ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;

		/* External library loading support */
		ipc4_data->load_library = hda_dsp_ipc4_load_library;

		/* doorbell */
		sof_tgl_ops.irq_thread	= cnl_ipc4_irq_thread;

		/* ipc */
		sof_tgl_ops.send_msg	= cnl_ipc4_send_msg;

		/* debug */
		sof_tgl_ops.ipc_dump	= cnl_ipc4_dump;

		sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
	}

	/* set DAI driver ops */
	hda_set_dai_drv_ops(sdev, &sof_tgl_ops);

	/* debug */
	sof_tgl_ops.debug_map	= tgl_dsp_debugfs;
	sof_tgl_ops.debug_map_count	= ARRAY_SIZE(tgl_dsp_debugfs);

	/* pre/post fw run */
	sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run;

	/* firmware run */
	sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax;

	/* dsp core get/put */
	sof_tgl_ops.core_get = tgl_dsp_core_get;
	sof_tgl_ops.core_put = tgl_dsp_core_put;

	return 0;
};
EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);

const struct sof_intel_dsp_desc tgl_chip_info = {
	/* Tigerlake , Alderlake */
	.cores_num = 4,
	.init_core_mask = 1,
	.host_managed_cores_mask = BIT(0),
	.ipc_req = CNL_DSP_REG_HIPCIDR,
	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
	.rom_init_timeout	= 300,
	.ssp_count = TGL_SSP_COUNT,
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
	.sdw_shim_base = SDW_SHIM_BASE,
	.sdw_alh_base = SDW_ALH_BASE,
	.d0i3_offset = SOF_HDA_VS_D0I3C,
	.read_sdw_lcount =  hda_sdw_check_lcount_common,
	.enable_sdw_irq	= hda_common_enable_sdw_irq,
	.check_sdw_irq	= hda_common_check_sdw_irq,
	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
	.check_ipc_irq	= hda_dsp_check_ipc_irq,
	.cl_init = cl_dsp_init,
	.power_down_dsp = hda_power_down_dsp,
	.disable_interrupts = hda_dsp_disable_interrupts,
	.hw_ip_version = SOF_INTEL_CAVS_2_5,
};
EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

const struct sof_intel_dsp_desc tglh_chip_info = {
	/* Tigerlake-H */
	.cores_num = 2,
	.init_core_mask = 1,
	.host_managed_cores_mask = BIT(0),
	.ipc_req = CNL_DSP_REG_HIPCIDR,
	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
	.rom_init_timeout	= 300,
	.ssp_count = TGL_SSP_COUNT,
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
	.sdw_shim_base = SDW_SHIM_BASE,
	.sdw_alh_base = SDW_ALH_BASE,
	.d0i3_offset = SOF_HDA_VS_D0I3C,
	.read_sdw_lcount =  hda_sdw_check_lcount_common,
	.enable_sdw_irq	= hda_common_enable_sdw_irq,
	.check_sdw_irq	= hda_common_check_sdw_irq,
	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
	.check_ipc_irq	= hda_dsp_check_ipc_irq,
	.cl_init = cl_dsp_init,
	.power_down_dsp = hda_power_down_dsp,
	.disable_interrupts = hda_dsp_disable_interrupts,
	.hw_ip_version = SOF_INTEL_CAVS_2_5,
};
EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

const struct sof_intel_dsp_desc ehl_chip_info = {
	/* Elkhartlake */
	.cores_num = 4,
	.init_core_mask = 1,
	.host_managed_cores_mask = BIT(0),
	.ipc_req = CNL_DSP_REG_HIPCIDR,
	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
	.rom_init_timeout	= 300,
	.ssp_count = TGL_SSP_COUNT,
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
	.sdw_shim_base = SDW_SHIM_BASE,
	.sdw_alh_base = SDW_ALH_BASE,
	.d0i3_offset = SOF_HDA_VS_D0I3C,
	.read_sdw_lcount =  hda_sdw_check_lcount_common,
	.enable_sdw_irq	= hda_common_enable_sdw_irq,
	.check_sdw_irq	= hda_common_check_sdw_irq,
	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
	.check_ipc_irq	= hda_dsp_check_ipc_irq,
	.cl_init = cl_dsp_init,
	.power_down_dsp = hda_power_down_dsp,
	.disable_interrupts = hda_dsp_disable_interrupts,
	.hw_ip_version = SOF_INTEL_CAVS_2_5,
};
EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

const struct sof_intel_dsp_desc adls_chip_info = {
	/* Alderlake-S */
	.cores_num = 2,
	.init_core_mask = BIT(0),
	.host_managed_cores_mask = BIT(0),
	.ipc_req = CNL_DSP_REG_HIPCIDR,
	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
	.rom_init_timeout	= 300,
	.ssp_count = TGL_SSP_COUNT,
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
	.sdw_shim_base = SDW_SHIM_BASE,
	.sdw_alh_base = SDW_ALH_BASE,
	.d0i3_offset = SOF_HDA_VS_D0I3C,
	.read_sdw_lcount =  hda_sdw_check_lcount_common,
	.enable_sdw_irq	= hda_common_enable_sdw_irq,
	.check_sdw_irq	= hda_common_check_sdw_irq,
	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
	.check_ipc_irq	= hda_dsp_check_ipc_irq,
	.cl_init = cl_dsp_init,
	.power_down_dsp = hda_power_down_dsp,
	.disable_interrupts = hda_dsp_disable_interrupts,
	.hw_ip_version = SOF_INTEL_CAVS_2_5,
};
EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
Commit	Line	Data
8b98491a RS	1	// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
	2	//
	3	// Copyright(c) 2020 Intel Corporation. All rights reserved.
	4	//
	5	// Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
	6	//
	7
	8	/*
	9	* Hardware interface for audio DSP on Tigerlake.
	10	*/
	11
a4cfdebd RS	12	#include <sound/sof/ext_manifest4.h>
a4cfdebd RS	13	#include "../ipc4-priv.h"
8b98491a RS	14	#include "../ops.h"
	15	#include "hda.h"
	16	#include "hda-ipc.h"
	17	#include "../sof-audio.h"
	18
	19	static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
	20	{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
	21	{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
	22	{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
	23	};
	24
41dd63cc RS	25	static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core)
41dd63cc RS	26	{
7a567740	27	const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
41dd63cc RS	28
	29	/* power up primary core if not already powered up and return */
	30	if (core == SOF_DSP_PRIMARY_CORE)
	31	return hda_dsp_enable_core(sdev, BIT(core));
	32
7a567740 PU	33	if (pm_ops->set_core_state)
	34	return pm_ops->set_core_state(sdev, core, true);
	35
	36	return 0;
41dd63cc RS	37	}
	38
	39	static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
	40	{
7a567740	41	const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
1b167ba8 RW	42	int ret;
	43
	44	if (pm_ops->set_core_state) {
	45	ret = pm_ops->set_core_state(sdev, core, false);
	46	if (ret < 0)
	47	return ret;
	48	}
41dd63cc RS	49
	50	/* power down primary core and return */
	51	if (core == SOF_DSP_PRIMARY_CORE)
	52	return hda_dsp_core_reset_power_down(sdev, BIT(core));
	53
7a567740	54	return 0;
41dd63cc RS	55	}
41dd63cc RS	56
8b98491a	57	/* Tigerlake ops */
37e809d5 PLB	58	struct snd_sof_dsp_ops sof_tgl_ops;
37e809d5 PLB	59	EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
8b98491a	60
37e809d5 PLB	61	int sof_tgl_ops_init(struct snd_sof_dev *sdev)
	62	{
	63	/* common defaults */
	64	memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
8b98491a	65
37e809d5	66	/* probe/remove/shutdown */
2aa2a5ea	67	sof_tgl_ops.shutdown = hda_dsp_shutdown_dma_flush;
f71f59dd	68
e3105c0c RS	69	if (sdev->pdata->ipc_type == SOF_IPC) {
	70	/* doorbell */
	71	sof_tgl_ops.irq_thread = cnl_ipc_irq_thread;
8b98491a	72
e3105c0c RS	73	/* ipc */
e3105c0c RS	74	sof_tgl_ops.send_msg = cnl_ipc_send_msg;
a996a333 PU	75
	76	/* debug */
	77	sof_tgl_ops.ipc_dump = cnl_ipc_dump;
996b07ef RS	78
996b07ef RS	79	sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc3;
e3105c0c RS	80	}
	81
	82	if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
a4cfdebd RS	83	struct sof_ipc4_fw_data *ipc4_data;
	84
	85	sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL);
	86	if (!sdev->private)
	87	return -ENOMEM;
	88
	89	ipc4_data = sdev->private;
	90	ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
	91
cc4a3a19 PU	92	ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
cc4a3a19 PU	93
3ab2c21e PU	94	/* External library loading support */
	95	ipc4_data->load_library = hda_dsp_ipc4_load_library;
	96
e3105c0c RS	97	/* doorbell */
	98	sof_tgl_ops.irq_thread = cnl_ipc4_irq_thread;
	99
	100	/* ipc */
	101	sof_tgl_ops.send_msg = cnl_ipc4_send_msg;
a996a333 PU	102
	103	/* debug */
	104	sof_tgl_ops.ipc_dump = cnl_ipc4_dump;
996b07ef RS	105
996b07ef RS	106	sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
e3105c0c	107	}
8b98491a	108
51ec71dc RS	109	/* set DAI driver ops */
	110	hda_set_dai_drv_ops(sdev, &sof_tgl_ops);
	111
8b98491a	112	/* debug */
37e809d5 PLB	113	sof_tgl_ops.debug_map = tgl_dsp_debugfs;
37e809d5 PLB	114	sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs);
8b98491a RS	115
8b98491a RS	116	/* pre/post fw run */
37e809d5	117	sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run;
8b98491a	118
37e809d5 PLB	119	/* firmware run */
37e809d5 PLB	120	sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax;
edbaaada	121
9ea80748	122	/* dsp core get/put */
37e809d5 PLB	123	sof_tgl_ops.core_get = tgl_dsp_core_get;
37e809d5 PLB	124	sof_tgl_ops.core_put = tgl_dsp_core_put;
8b98491a	125
37e809d5	126	return 0;
8b98491a	127	};
37e809d5	128	EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
8b98491a RS	129
8b98491a RS	130	const struct sof_intel_dsp_desc tgl_chip_info = {
4ad03f89	131	/* Tigerlake , Alderlake */
8b98491a RS	132	.cores_num = 4,
8b98491a RS	133	.init_core_mask = 1,
fde10655	134	.host_managed_cores_mask = BIT(0),
8b98491a RS	135	.ipc_req = CNL_DSP_REG_HIPCIDR,
	136	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	137	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	138	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	139	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
71778f79	140	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
8b98491a	141	.rom_init_timeout = 300,
9ccbc2e1	142	.ssp_count = TGL_SSP_COUNT,
8b98491a	143	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
1cbf6443 BL	144	.sdw_shim_base = SDW_SHIM_BASE,
1cbf6443 BL	145	.sdw_alh_base = SDW_ALH_BASE,
f8632adc	146	.d0i3_offset = SOF_HDA_VS_D0I3C,
625339ca	147	.read_sdw_lcount = hda_sdw_check_lcount_common,
8ebc9074	148	.enable_sdw_irq = hda_common_enable_sdw_irq,
198fa4bc	149	.check_sdw_irq = hda_common_check_sdw_irq,
9362ab78	150	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
3dee239e	151	.check_ipc_irq = hda_dsp_check_ipc_irq,
ab222a4a	152	.cl_init = cl_dsp_init,
c714031f	153	.power_down_dsp = hda_power_down_dsp,
b2520dbc	154	.disable_interrupts = hda_dsp_disable_interrupts,
03cf7262	155	.hw_ip_version = SOF_INTEL_CAVS_2_5,
8b98491a RS	156	};
8b98491a RS	157	EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
30ee3738 RW	158
	159	const struct sof_intel_dsp_desc tglh_chip_info = {
	160	/* Tigerlake-H */
	161	.cores_num = 2,
	162	.init_core_mask = 1,
	163	.host_managed_cores_mask = BIT(0),
	164	.ipc_req = CNL_DSP_REG_HIPCIDR,
	165	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	166	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	167	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	168	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
71778f79	169	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
30ee3738	170	.rom_init_timeout = 300,
9ccbc2e1	171	.ssp_count = TGL_SSP_COUNT,
30ee3738	172	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
1cbf6443 BL	173	.sdw_shim_base = SDW_SHIM_BASE,
1cbf6443 BL	174	.sdw_alh_base = SDW_ALH_BASE,
f8632adc	175	.d0i3_offset = SOF_HDA_VS_D0I3C,
625339ca	176	.read_sdw_lcount = hda_sdw_check_lcount_common,
8ebc9074	177	.enable_sdw_irq = hda_common_enable_sdw_irq,
198fa4bc	178	.check_sdw_irq = hda_common_check_sdw_irq,
9362ab78	179	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
3dee239e	180	.check_ipc_irq = hda_dsp_check_ipc_irq,
ab222a4a	181	.cl_init = cl_dsp_init,
c714031f	182	.power_down_dsp = hda_power_down_dsp,
b2520dbc	183	.disable_interrupts = hda_dsp_disable_interrupts,
03cf7262	184	.hw_ip_version = SOF_INTEL_CAVS_2_5,
30ee3738 RW	185	};
30ee3738 RW	186	EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
6c2b6bb0	187
8bb84ca8 PLB	188	const struct sof_intel_dsp_desc ehl_chip_info = {
	189	/* Elkhartlake */
	190	.cores_num = 4,
	191	.init_core_mask = 1,
	192	.host_managed_cores_mask = BIT(0),
	193	.ipc_req = CNL_DSP_REG_HIPCIDR,
	194	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	195	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	196	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	197	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
71778f79	198	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
8bb84ca8	199	.rom_init_timeout = 300,
9ccbc2e1	200	.ssp_count = TGL_SSP_COUNT,
8bb84ca8	201	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
1cbf6443 BL	202	.sdw_shim_base = SDW_SHIM_BASE,
1cbf6443 BL	203	.sdw_alh_base = SDW_ALH_BASE,
f8632adc	204	.d0i3_offset = SOF_HDA_VS_D0I3C,
625339ca	205	.read_sdw_lcount = hda_sdw_check_lcount_common,
8ebc9074	206	.enable_sdw_irq = hda_common_enable_sdw_irq,
198fa4bc	207	.check_sdw_irq = hda_common_check_sdw_irq,
9362ab78	208	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
3dee239e	209	.check_ipc_irq = hda_dsp_check_ipc_irq,
ab222a4a	210	.cl_init = cl_dsp_init,
c714031f	211	.power_down_dsp = hda_power_down_dsp,
b2520dbc	212	.disable_interrupts = hda_dsp_disable_interrupts,
03cf7262	213	.hw_ip_version = SOF_INTEL_CAVS_2_5,
8bb84ca8 PLB	214	};
	215	EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
	216
6c2b6bb0 KV	217	const struct sof_intel_dsp_desc adls_chip_info = {
	218	/* Alderlake-S */
	219	.cores_num = 2,
	220	.init_core_mask = BIT(0),
	221	.host_managed_cores_mask = BIT(0),
	222	.ipc_req = CNL_DSP_REG_HIPCIDR,
	223	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	224	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	225	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	226	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
71778f79	227	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
6c2b6bb0	228	.rom_init_timeout = 300,
9ccbc2e1	229	.ssp_count = TGL_SSP_COUNT,
6c2b6bb0	230	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
1cbf6443 BL	231	.sdw_shim_base = SDW_SHIM_BASE,
1cbf6443 BL	232	.sdw_alh_base = SDW_ALH_BASE,
f8632adc	233	.d0i3_offset = SOF_HDA_VS_D0I3C,
625339ca	234	.read_sdw_lcount = hda_sdw_check_lcount_common,
8ebc9074	235	.enable_sdw_irq = hda_common_enable_sdw_irq,
198fa4bc	236	.check_sdw_irq = hda_common_check_sdw_irq,
9362ab78	237	.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
3dee239e	238	.check_ipc_irq = hda_dsp_check_ipc_irq,
ab222a4a	239	.cl_init = cl_dsp_init,
c714031f	240	.power_down_dsp = hda_power_down_dsp,
b2520dbc	241	.disable_interrupts = hda_dsp_disable_interrupts,
03cf7262	242	.hw_ip_version = SOF_INTEL_CAVS_2_5,
6c2b6bb0 KV	243	};
6c2b6bb0 KV	244	EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);