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8b98491a RS |
1 | // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) |
2 | // | |
3 | // Copyright(c) 2020 Intel Corporation. All rights reserved. | |
4 | // | |
5 | // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> | |
6 | // | |
7 | ||
8 | /* | |
9 | * Hardware interface for audio DSP on Tigerlake. | |
10 | */ | |
11 | ||
a4cfdebd RS |
12 | #include <sound/sof/ext_manifest4.h> |
13 | #include "../ipc4-priv.h" | |
8b98491a RS |
14 | #include "../ops.h" |
15 | #include "hda.h" | |
16 | #include "hda-ipc.h" | |
17 | #include "../sof-audio.h" | |
18 | ||
19 | static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { | |
20 | {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, | |
21 | {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, | |
22 | {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, | |
23 | }; | |
24 | ||
41dd63cc RS |
25 | static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core) |
26 | { | |
7a567740 | 27 | const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; |
41dd63cc RS |
28 | |
29 | /* power up primary core if not already powered up and return */ | |
30 | if (core == SOF_DSP_PRIMARY_CORE) | |
31 | return hda_dsp_enable_core(sdev, BIT(core)); | |
32 | ||
7a567740 PU |
33 | if (pm_ops->set_core_state) |
34 | return pm_ops->set_core_state(sdev, core, true); | |
35 | ||
36 | return 0; | |
41dd63cc RS |
37 | } |
38 | ||
39 | static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core) | |
40 | { | |
7a567740 | 41 | const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; |
1b167ba8 RW |
42 | int ret; |
43 | ||
44 | if (pm_ops->set_core_state) { | |
45 | ret = pm_ops->set_core_state(sdev, core, false); | |
46 | if (ret < 0) | |
47 | return ret; | |
48 | } | |
41dd63cc RS |
49 | |
50 | /* power down primary core and return */ | |
51 | if (core == SOF_DSP_PRIMARY_CORE) | |
52 | return hda_dsp_core_reset_power_down(sdev, BIT(core)); | |
53 | ||
7a567740 | 54 | return 0; |
41dd63cc RS |
55 | } |
56 | ||
8b98491a | 57 | /* Tigerlake ops */ |
37e809d5 PLB |
58 | struct snd_sof_dsp_ops sof_tgl_ops; |
59 | EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); | |
8b98491a | 60 | |
37e809d5 PLB |
61 | int sof_tgl_ops_init(struct snd_sof_dev *sdev) |
62 | { | |
63 | /* common defaults */ | |
64 | memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); | |
8b98491a | 65 | |
37e809d5 | 66 | /* probe/remove/shutdown */ |
2aa2a5ea | 67 | sof_tgl_ops.shutdown = hda_dsp_shutdown_dma_flush; |
f71f59dd | 68 | |
a8fffb94 | 69 | if (sdev->pdata->ipc_type == SOF_IPC_TYPE_3) { |
e3105c0c RS |
70 | /* doorbell */ |
71 | sof_tgl_ops.irq_thread = cnl_ipc_irq_thread; | |
8b98491a | 72 | |
e3105c0c RS |
73 | /* ipc */ |
74 | sof_tgl_ops.send_msg = cnl_ipc_send_msg; | |
a996a333 PU |
75 | |
76 | /* debug */ | |
77 | sof_tgl_ops.ipc_dump = cnl_ipc_dump; | |
996b07ef RS |
78 | |
79 | sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc3; | |
e3105c0c RS |
80 | } |
81 | ||
a8fffb94 | 82 | if (sdev->pdata->ipc_type == SOF_IPC_TYPE_4) { |
a4cfdebd RS |
83 | struct sof_ipc4_fw_data *ipc4_data; |
84 | ||
9b689653 | 85 | sdev->private = kzalloc(sizeof(*ipc4_data), GFP_KERNEL); |
a4cfdebd RS |
86 | if (!sdev->private) |
87 | return -ENOMEM; | |
88 | ||
89 | ipc4_data = sdev->private; | |
90 | ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; | |
91 | ||
cc4a3a19 PU |
92 | ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; |
93 | ||
3ab2c21e PU |
94 | /* External library loading support */ |
95 | ipc4_data->load_library = hda_dsp_ipc4_load_library; | |
96 | ||
e3105c0c RS |
97 | /* doorbell */ |
98 | sof_tgl_ops.irq_thread = cnl_ipc4_irq_thread; | |
99 | ||
100 | /* ipc */ | |
101 | sof_tgl_ops.send_msg = cnl_ipc4_send_msg; | |
a996a333 PU |
102 | |
103 | /* debug */ | |
104 | sof_tgl_ops.ipc_dump = cnl_ipc4_dump; | |
eb6e5dab | 105 | sof_tgl_ops.dbg_dump = hda_ipc4_dsp_dump; |
996b07ef RS |
106 | |
107 | sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc4; | |
e3105c0c | 108 | } |
8b98491a | 109 | |
51ec71dc RS |
110 | /* set DAI driver ops */ |
111 | hda_set_dai_drv_ops(sdev, &sof_tgl_ops); | |
112 | ||
8b98491a | 113 | /* debug */ |
37e809d5 PLB |
114 | sof_tgl_ops.debug_map = tgl_dsp_debugfs; |
115 | sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs); | |
8b98491a RS |
116 | |
117 | /* pre/post fw run */ | |
37e809d5 | 118 | sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run; |
8b98491a | 119 | |
37e809d5 PLB |
120 | /* firmware run */ |
121 | sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax; | |
edbaaada | 122 | |
9ea80748 | 123 | /* dsp core get/put */ |
37e809d5 PLB |
124 | sof_tgl_ops.core_get = tgl_dsp_core_get; |
125 | sof_tgl_ops.core_put = tgl_dsp_core_put; | |
8b98491a | 126 | |
37e809d5 | 127 | return 0; |
8b98491a | 128 | }; |
37e809d5 | 129 | EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); |
8b98491a RS |
130 | |
131 | const struct sof_intel_dsp_desc tgl_chip_info = { | |
4ad03f89 | 132 | /* Tigerlake , Alderlake */ |
8b98491a RS |
133 | .cores_num = 4, |
134 | .init_core_mask = 1, | |
fde10655 | 135 | .host_managed_cores_mask = BIT(0), |
8b98491a RS |
136 | .ipc_req = CNL_DSP_REG_HIPCIDR, |
137 | .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, | |
138 | .ipc_ack = CNL_DSP_REG_HIPCIDA, | |
139 | .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, | |
140 | .ipc_ctl = CNL_DSP_REG_HIPCCTL, | |
71778f79 | 141 | .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
8b98491a | 142 | .rom_init_timeout = 300, |
9ccbc2e1 | 143 | .ssp_count = TGL_SSP_COUNT, |
8b98491a | 144 | .ssp_base_offset = CNL_SSP_BASE_OFFSET, |
1cbf6443 BL |
145 | .sdw_shim_base = SDW_SHIM_BASE, |
146 | .sdw_alh_base = SDW_ALH_BASE, | |
f8632adc | 147 | .d0i3_offset = SOF_HDA_VS_D0I3C, |
625339ca | 148 | .read_sdw_lcount = hda_sdw_check_lcount_common, |
8ebc9074 | 149 | .enable_sdw_irq = hda_common_enable_sdw_irq, |
198fa4bc | 150 | .check_sdw_irq = hda_common_check_sdw_irq, |
9362ab78 | 151 | .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, |
3dee239e | 152 | .check_ipc_irq = hda_dsp_check_ipc_irq, |
ab222a4a | 153 | .cl_init = cl_dsp_init, |
c714031f | 154 | .power_down_dsp = hda_power_down_dsp, |
b2520dbc | 155 | .disable_interrupts = hda_dsp_disable_interrupts, |
03cf7262 | 156 | .hw_ip_version = SOF_INTEL_CAVS_2_5, |
8b98491a RS |
157 | }; |
158 | EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); | |
30ee3738 RW |
159 | |
160 | const struct sof_intel_dsp_desc tglh_chip_info = { | |
161 | /* Tigerlake-H */ | |
162 | .cores_num = 2, | |
163 | .init_core_mask = 1, | |
164 | .host_managed_cores_mask = BIT(0), | |
165 | .ipc_req = CNL_DSP_REG_HIPCIDR, | |
166 | .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, | |
167 | .ipc_ack = CNL_DSP_REG_HIPCIDA, | |
168 | .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, | |
169 | .ipc_ctl = CNL_DSP_REG_HIPCCTL, | |
71778f79 | 170 | .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
30ee3738 | 171 | .rom_init_timeout = 300, |
9ccbc2e1 | 172 | .ssp_count = TGL_SSP_COUNT, |
30ee3738 | 173 | .ssp_base_offset = CNL_SSP_BASE_OFFSET, |
1cbf6443 BL |
174 | .sdw_shim_base = SDW_SHIM_BASE, |
175 | .sdw_alh_base = SDW_ALH_BASE, | |
f8632adc | 176 | .d0i3_offset = SOF_HDA_VS_D0I3C, |
625339ca | 177 | .read_sdw_lcount = hda_sdw_check_lcount_common, |
8ebc9074 | 178 | .enable_sdw_irq = hda_common_enable_sdw_irq, |
198fa4bc | 179 | .check_sdw_irq = hda_common_check_sdw_irq, |
9362ab78 | 180 | .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, |
3dee239e | 181 | .check_ipc_irq = hda_dsp_check_ipc_irq, |
ab222a4a | 182 | .cl_init = cl_dsp_init, |
c714031f | 183 | .power_down_dsp = hda_power_down_dsp, |
b2520dbc | 184 | .disable_interrupts = hda_dsp_disable_interrupts, |
03cf7262 | 185 | .hw_ip_version = SOF_INTEL_CAVS_2_5, |
30ee3738 RW |
186 | }; |
187 | EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); | |
6c2b6bb0 | 188 | |
8bb84ca8 PLB |
189 | const struct sof_intel_dsp_desc ehl_chip_info = { |
190 | /* Elkhartlake */ | |
191 | .cores_num = 4, | |
192 | .init_core_mask = 1, | |
193 | .host_managed_cores_mask = BIT(0), | |
194 | .ipc_req = CNL_DSP_REG_HIPCIDR, | |
195 | .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, | |
196 | .ipc_ack = CNL_DSP_REG_HIPCIDA, | |
197 | .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, | |
198 | .ipc_ctl = CNL_DSP_REG_HIPCCTL, | |
71778f79 | 199 | .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
8bb84ca8 | 200 | .rom_init_timeout = 300, |
9ccbc2e1 | 201 | .ssp_count = TGL_SSP_COUNT, |
8bb84ca8 | 202 | .ssp_base_offset = CNL_SSP_BASE_OFFSET, |
1cbf6443 BL |
203 | .sdw_shim_base = SDW_SHIM_BASE, |
204 | .sdw_alh_base = SDW_ALH_BASE, | |
f8632adc | 205 | .d0i3_offset = SOF_HDA_VS_D0I3C, |
625339ca | 206 | .read_sdw_lcount = hda_sdw_check_lcount_common, |
8ebc9074 | 207 | .enable_sdw_irq = hda_common_enable_sdw_irq, |
198fa4bc | 208 | .check_sdw_irq = hda_common_check_sdw_irq, |
9362ab78 | 209 | .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, |
3dee239e | 210 | .check_ipc_irq = hda_dsp_check_ipc_irq, |
ab222a4a | 211 | .cl_init = cl_dsp_init, |
c714031f | 212 | .power_down_dsp = hda_power_down_dsp, |
b2520dbc | 213 | .disable_interrupts = hda_dsp_disable_interrupts, |
03cf7262 | 214 | .hw_ip_version = SOF_INTEL_CAVS_2_5, |
8bb84ca8 PLB |
215 | }; |
216 | EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); | |
217 | ||
6c2b6bb0 KV |
218 | const struct sof_intel_dsp_desc adls_chip_info = { |
219 | /* Alderlake-S */ | |
220 | .cores_num = 2, | |
221 | .init_core_mask = BIT(0), | |
222 | .host_managed_cores_mask = BIT(0), | |
223 | .ipc_req = CNL_DSP_REG_HIPCIDR, | |
224 | .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, | |
225 | .ipc_ack = CNL_DSP_REG_HIPCIDA, | |
226 | .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, | |
227 | .ipc_ctl = CNL_DSP_REG_HIPCCTL, | |
71778f79 | 228 | .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
6c2b6bb0 | 229 | .rom_init_timeout = 300, |
9ccbc2e1 | 230 | .ssp_count = TGL_SSP_COUNT, |
6c2b6bb0 | 231 | .ssp_base_offset = CNL_SSP_BASE_OFFSET, |
1cbf6443 BL |
232 | .sdw_shim_base = SDW_SHIM_BASE, |
233 | .sdw_alh_base = SDW_ALH_BASE, | |
f8632adc | 234 | .d0i3_offset = SOF_HDA_VS_D0I3C, |
625339ca | 235 | .read_sdw_lcount = hda_sdw_check_lcount_common, |
8ebc9074 | 236 | .enable_sdw_irq = hda_common_enable_sdw_irq, |
198fa4bc | 237 | .check_sdw_irq = hda_common_check_sdw_irq, |
9362ab78 | 238 | .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, |
3dee239e | 239 | .check_ipc_irq = hda_dsp_check_ipc_irq, |
ab222a4a | 240 | .cl_init = cl_dsp_init, |
c714031f | 241 | .power_down_dsp = hda_power_down_dsp, |
b2520dbc | 242 | .disable_interrupts = hda_dsp_disable_interrupts, |
03cf7262 | 243 | .hw_ip_version = SOF_INTEL_CAVS_2_5, |
6c2b6bb0 KV |
244 | }; |
245 | EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); |