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8b98491a RS |
1 | // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) |
2 | // | |
293ad281 | 3 | // Copyright(c) 2020 Intel Corporation |
8b98491a RS |
4 | // |
5 | // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> | |
6 | // | |
7 | ||
8 | /* | |
9 | * Hardware interface for audio DSP on Tigerlake. | |
10 | */ | |
11 | ||
a4cfdebd RS |
12 | #include <sound/sof/ext_manifest4.h> |
13 | #include "../ipc4-priv.h" | |
8b98491a RS |
14 | #include "../ops.h" |
15 | #include "hda.h" | |
16 | #include "hda-ipc.h" | |
17 | #include "../sof-audio.h" | |
18 | ||
19 | static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { | |
20 | {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, | |
21 | {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, | |
22 | {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, | |
23 | }; | |
24 | ||
25ab9c40 PU |
25 | static const struct snd_sof_debugfs_map tgl_ipc4_dsp_debugfs[] = { |
26 | {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, | |
27 | {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, | |
28 | {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, | |
29 | {"fw_regs", HDA_DSP_BAR, SRAM_WINDOW_OFFSET(0), 0x1000, SOF_DEBUGFS_ACCESS_D0_ONLY}, | |
30 | }; | |
31 | ||
41dd63cc RS |
32 | static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core) |
33 | { | |
7a567740 | 34 | const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; |
41dd63cc RS |
35 | |
36 | /* power up primary core if not already powered up and return */ | |
37 | if (core == SOF_DSP_PRIMARY_CORE) | |
38 | return hda_dsp_enable_core(sdev, BIT(core)); | |
39 | ||
7a567740 PU |
40 | if (pm_ops->set_core_state) |
41 | return pm_ops->set_core_state(sdev, core, true); | |
42 | ||
43 | return 0; | |
41dd63cc RS |
44 | } |
45 | ||
46 | static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core) | |
47 | { | |
7a567740 | 48 | const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; |
1b167ba8 RW |
49 | int ret; |
50 | ||
51 | if (pm_ops->set_core_state) { | |
52 | ret = pm_ops->set_core_state(sdev, core, false); | |
53 | if (ret < 0) | |
54 | return ret; | |
55 | } | |
41dd63cc RS |
56 | |
57 | /* power down primary core and return */ | |
58 | if (core == SOF_DSP_PRIMARY_CORE) | |
59 | return hda_dsp_core_reset_power_down(sdev, BIT(core)); | |
60 | ||
7a567740 | 61 | return 0; |
41dd63cc RS |
62 | } |
63 | ||
8b98491a | 64 | /* Tigerlake ops */ |
37e809d5 PLB |
65 | struct snd_sof_dsp_ops sof_tgl_ops; |
66 | EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); | |
8b98491a | 67 | |
37e809d5 PLB |
68 | int sof_tgl_ops_init(struct snd_sof_dev *sdev) |
69 | { | |
70 | /* common defaults */ | |
71 | memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); | |
8b98491a | 72 | |
37e809d5 | 73 | /* probe/remove/shutdown */ |
2aa2a5ea | 74 | sof_tgl_ops.shutdown = hda_dsp_shutdown_dma_flush; |
f71f59dd | 75 | |
a8fffb94 | 76 | if (sdev->pdata->ipc_type == SOF_IPC_TYPE_3) { |
e3105c0c RS |
77 | /* doorbell */ |
78 | sof_tgl_ops.irq_thread = cnl_ipc_irq_thread; | |
8b98491a | 79 | |
e3105c0c RS |
80 | /* ipc */ |
81 | sof_tgl_ops.send_msg = cnl_ipc_send_msg; | |
a996a333 PU |
82 | |
83 | /* debug */ | |
84 | sof_tgl_ops.ipc_dump = cnl_ipc_dump; | |
25ab9c40 PU |
85 | sof_tgl_ops.debug_map = tgl_dsp_debugfs; |
86 | sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs); | |
996b07ef RS |
87 | |
88 | sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc3; | |
e3105c0c RS |
89 | } |
90 | ||
a8fffb94 | 91 | if (sdev->pdata->ipc_type == SOF_IPC_TYPE_4) { |
a4cfdebd RS |
92 | struct sof_ipc4_fw_data *ipc4_data; |
93 | ||
9b689653 | 94 | sdev->private = kzalloc(sizeof(*ipc4_data), GFP_KERNEL); |
a4cfdebd RS |
95 | if (!sdev->private) |
96 | return -ENOMEM; | |
97 | ||
98 | ipc4_data = sdev->private; | |
99 | ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; | |
100 | ||
cc4a3a19 PU |
101 | ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; |
102 | ||
855a4772 RW |
103 | ipc4_data->fw_context_save = true; |
104 | ||
3ab2c21e PU |
105 | /* External library loading support */ |
106 | ipc4_data->load_library = hda_dsp_ipc4_load_library; | |
107 | ||
e3105c0c RS |
108 | /* doorbell */ |
109 | sof_tgl_ops.irq_thread = cnl_ipc4_irq_thread; | |
110 | ||
111 | /* ipc */ | |
112 | sof_tgl_ops.send_msg = cnl_ipc4_send_msg; | |
a996a333 PU |
113 | |
114 | /* debug */ | |
115 | sof_tgl_ops.ipc_dump = cnl_ipc4_dump; | |
eb6e5dab | 116 | sof_tgl_ops.dbg_dump = hda_ipc4_dsp_dump; |
25ab9c40 PU |
117 | sof_tgl_ops.debug_map = tgl_ipc4_dsp_debugfs; |
118 | sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_ipc4_dsp_debugfs); | |
996b07ef RS |
119 | |
120 | sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc4; | |
e3105c0c | 121 | } |
8b98491a | 122 | |
51ec71dc RS |
123 | /* set DAI driver ops */ |
124 | hda_set_dai_drv_ops(sdev, &sof_tgl_ops); | |
125 | ||
8b98491a | 126 | /* pre/post fw run */ |
37e809d5 | 127 | sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run; |
8b98491a | 128 | |
37e809d5 PLB |
129 | /* firmware run */ |
130 | sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax; | |
edbaaada | 131 | |
9ea80748 | 132 | /* dsp core get/put */ |
37e809d5 PLB |
133 | sof_tgl_ops.core_get = tgl_dsp_core_get; |
134 | sof_tgl_ops.core_put = tgl_dsp_core_put; | |
8b98491a | 135 | |
37e809d5 | 136 | return 0; |
8b98491a | 137 | }; |
37e809d5 | 138 | EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); |
8b98491a RS |
139 | |
140 | const struct sof_intel_dsp_desc tgl_chip_info = { | |
4ad03f89 | 141 | /* Tigerlake , Alderlake */ |
8b98491a RS |
142 | .cores_num = 4, |
143 | .init_core_mask = 1, | |
fde10655 | 144 | .host_managed_cores_mask = BIT(0), |
8b98491a RS |
145 | .ipc_req = CNL_DSP_REG_HIPCIDR, |
146 | .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, | |
147 | .ipc_ack = CNL_DSP_REG_HIPCIDA, | |
148 | .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, | |
149 | .ipc_ctl = CNL_DSP_REG_HIPCCTL, | |
71778f79 | 150 | .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
8b98491a | 151 | .rom_init_timeout = 300, |
9ccbc2e1 | 152 | .ssp_count = TGL_SSP_COUNT, |
8b98491a | 153 | .ssp_base_offset = CNL_SSP_BASE_OFFSET, |
1cbf6443 BL |
154 | .sdw_shim_base = SDW_SHIM_BASE, |
155 | .sdw_alh_base = SDW_ALH_BASE, | |
f8632adc | 156 | .d0i3_offset = SOF_HDA_VS_D0I3C, |
625339ca | 157 | .read_sdw_lcount = hda_sdw_check_lcount_common, |
8ebc9074 | 158 | .enable_sdw_irq = hda_common_enable_sdw_irq, |
198fa4bc | 159 | .check_sdw_irq = hda_common_check_sdw_irq, |
9362ab78 | 160 | .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, |
3dee239e | 161 | .check_ipc_irq = hda_dsp_check_ipc_irq, |
ab222a4a | 162 | .cl_init = cl_dsp_init, |
c714031f | 163 | .power_down_dsp = hda_power_down_dsp, |
b2520dbc | 164 | .disable_interrupts = hda_dsp_disable_interrupts, |
03cf7262 | 165 | .hw_ip_version = SOF_INTEL_CAVS_2_5, |
8b98491a RS |
166 | }; |
167 | EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); | |
30ee3738 RW |
168 | |
169 | const struct sof_intel_dsp_desc tglh_chip_info = { | |
170 | /* Tigerlake-H */ | |
171 | .cores_num = 2, | |
172 | .init_core_mask = 1, | |
173 | .host_managed_cores_mask = BIT(0), | |
174 | .ipc_req = CNL_DSP_REG_HIPCIDR, | |
175 | .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, | |
176 | .ipc_ack = CNL_DSP_REG_HIPCIDA, | |
177 | .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, | |
178 | .ipc_ctl = CNL_DSP_REG_HIPCCTL, | |
71778f79 | 179 | .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
30ee3738 | 180 | .rom_init_timeout = 300, |
9ccbc2e1 | 181 | .ssp_count = TGL_SSP_COUNT, |
30ee3738 | 182 | .ssp_base_offset = CNL_SSP_BASE_OFFSET, |
1cbf6443 BL |
183 | .sdw_shim_base = SDW_SHIM_BASE, |
184 | .sdw_alh_base = SDW_ALH_BASE, | |
f8632adc | 185 | .d0i3_offset = SOF_HDA_VS_D0I3C, |
625339ca | 186 | .read_sdw_lcount = hda_sdw_check_lcount_common, |
8ebc9074 | 187 | .enable_sdw_irq = hda_common_enable_sdw_irq, |
198fa4bc | 188 | .check_sdw_irq = hda_common_check_sdw_irq, |
9362ab78 | 189 | .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, |
3dee239e | 190 | .check_ipc_irq = hda_dsp_check_ipc_irq, |
ab222a4a | 191 | .cl_init = cl_dsp_init, |
c714031f | 192 | .power_down_dsp = hda_power_down_dsp, |
b2520dbc | 193 | .disable_interrupts = hda_dsp_disable_interrupts, |
03cf7262 | 194 | .hw_ip_version = SOF_INTEL_CAVS_2_5, |
30ee3738 RW |
195 | }; |
196 | EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); | |
6c2b6bb0 | 197 | |
8bb84ca8 PLB |
198 | const struct sof_intel_dsp_desc ehl_chip_info = { |
199 | /* Elkhartlake */ | |
200 | .cores_num = 4, | |
201 | .init_core_mask = 1, | |
202 | .host_managed_cores_mask = BIT(0), | |
203 | .ipc_req = CNL_DSP_REG_HIPCIDR, | |
204 | .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, | |
205 | .ipc_ack = CNL_DSP_REG_HIPCIDA, | |
206 | .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, | |
207 | .ipc_ctl = CNL_DSP_REG_HIPCCTL, | |
71778f79 | 208 | .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
8bb84ca8 | 209 | .rom_init_timeout = 300, |
9ccbc2e1 | 210 | .ssp_count = TGL_SSP_COUNT, |
8bb84ca8 | 211 | .ssp_base_offset = CNL_SSP_BASE_OFFSET, |
1cbf6443 BL |
212 | .sdw_shim_base = SDW_SHIM_BASE, |
213 | .sdw_alh_base = SDW_ALH_BASE, | |
f8632adc | 214 | .d0i3_offset = SOF_HDA_VS_D0I3C, |
625339ca | 215 | .read_sdw_lcount = hda_sdw_check_lcount_common, |
8ebc9074 | 216 | .enable_sdw_irq = hda_common_enable_sdw_irq, |
198fa4bc | 217 | .check_sdw_irq = hda_common_check_sdw_irq, |
9362ab78 | 218 | .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, |
3dee239e | 219 | .check_ipc_irq = hda_dsp_check_ipc_irq, |
ab222a4a | 220 | .cl_init = cl_dsp_init, |
c714031f | 221 | .power_down_dsp = hda_power_down_dsp, |
b2520dbc | 222 | .disable_interrupts = hda_dsp_disable_interrupts, |
03cf7262 | 223 | .hw_ip_version = SOF_INTEL_CAVS_2_5, |
8bb84ca8 PLB |
224 | }; |
225 | EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); | |
226 | ||
6c2b6bb0 KV |
227 | const struct sof_intel_dsp_desc adls_chip_info = { |
228 | /* Alderlake-S */ | |
229 | .cores_num = 2, | |
230 | .init_core_mask = BIT(0), | |
231 | .host_managed_cores_mask = BIT(0), | |
232 | .ipc_req = CNL_DSP_REG_HIPCIDR, | |
233 | .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, | |
234 | .ipc_ack = CNL_DSP_REG_HIPCIDA, | |
235 | .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, | |
236 | .ipc_ctl = CNL_DSP_REG_HIPCCTL, | |
71778f79 | 237 | .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
6c2b6bb0 | 238 | .rom_init_timeout = 300, |
9ccbc2e1 | 239 | .ssp_count = TGL_SSP_COUNT, |
6c2b6bb0 | 240 | .ssp_base_offset = CNL_SSP_BASE_OFFSET, |
1cbf6443 BL |
241 | .sdw_shim_base = SDW_SHIM_BASE, |
242 | .sdw_alh_base = SDW_ALH_BASE, | |
f8632adc | 243 | .d0i3_offset = SOF_HDA_VS_D0I3C, |
625339ca | 244 | .read_sdw_lcount = hda_sdw_check_lcount_common, |
8ebc9074 | 245 | .enable_sdw_irq = hda_common_enable_sdw_irq, |
198fa4bc | 246 | .check_sdw_irq = hda_common_check_sdw_irq, |
9362ab78 | 247 | .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, |
3dee239e | 248 | .check_ipc_irq = hda_dsp_check_ipc_irq, |
ab222a4a | 249 | .cl_init = cl_dsp_init, |
c714031f | 250 | .power_down_dsp = hda_power_down_dsp, |
b2520dbc | 251 | .disable_interrupts = hda_dsp_disable_interrupts, |
03cf7262 | 252 | .hw_ip_version = SOF_INTEL_CAVS_2_5, |
6c2b6bb0 KV |
253 | }; |
254 | EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); |