projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| e149ca29 | 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ |
| dd96daca LG |
2 | /* |
| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
| 4 | * redistributing this file, you may do so under either license. | |
| 5 | * | |
| 293ad281 | 6 | * Copyright(c) 2017 Intel Corporation |
| dd96daca LG |
7 | * |
| 8 | * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __SOF_INTEL_HDA_H | |
| 12 | #define __SOF_INTEL_HDA_H | |
| 13 | ||
| d5263dbb | 14 | #include <linux/completion.h> |
| 51dfed1e PLB |
15 | #include <linux/soundwire/sdw.h> |
| 16 | #include <linux/soundwire/sdw_intel.h> | |
| 4c414da9 | 17 | #include <sound/compress_driver.h> |
| dd96daca LG |
18 | #include <sound/hda_codec.h> |
| 19 | #include <sound/hdaudio_ext.h> | |
| 3dc0d709 | 20 | #include "../sof-client-probes.h" |
| 051744b1 | 21 | #include "../sof-audio.h" |
| dd96daca LG |
22 | #include "shim.h" |
| 23 | ||
| 24 | /* PCI registers */ | |
| 25 | #define PCI_TCSEL 0x44 | |
| 26 | #define PCI_PGCTL PCI_TCSEL | |
| 27 | #define PCI_CGCTL 0x48 | |
| 28 | ||
| 29 | /* PCI_PGCTL bits */ | |
| 30 | #define PCI_PGCTL_ADSPPGD BIT(2) | |
| 31 | #define PCI_PGCTL_LSRMD_MASK BIT(4) | |
| 32 | ||
| 33 | /* PCI_CGCTL bits */ | |
| 34 | #define PCI_CGCTL_MISCBDCGE_MASK BIT(6) | |
| 35 | #define PCI_CGCTL_ADSPDCGE BIT(1) | |
| 36 | ||
| 37 | /* Legacy HDA registers and bits used - widths are variable */ | |
| 38 | #define SOF_HDA_GCAP 0x0 | |
| 39 | #define SOF_HDA_GCTL 0x8 | |
| 40 | /* accept unsol. response enable */ | |
| 41 | #define SOF_HDA_GCTL_UNSOL BIT(8) | |
| 42 | #define SOF_HDA_LLCH 0x14 | |
| 43 | #define SOF_HDA_INTCTL 0x20 | |
| 44 | #define SOF_HDA_INTSTS 0x24 | |
| 45 | #define SOF_HDA_WAKESTS 0x0E | |
| 46 | #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) | |
| 47 | #define SOF_HDA_RIRBSTS 0x5d | |
| dd96daca LG |
48 | |
| 49 | /* SOF_HDA_GCTL register bist */ | |
| 50 | #define SOF_HDA_GCTL_RESET BIT(0) | |
| 51 | ||
| 7c11af9f | 52 | /* SOF_HDA_INCTL regs */ |
| dd96daca LG |
53 | #define SOF_HDA_INT_GLOBAL_EN BIT(31) |
| 54 | #define SOF_HDA_INT_CTRL_EN BIT(30) | |
| 55 | #define SOF_HDA_INT_ALL_STREAM 0xff | |
| 56 | ||
| 7c11af9f BL |
57 | /* SOF_HDA_INTSTS regs */ |
| 58 | #define SOF_HDA_INTSTS_GIS BIT(31) | |
| 59 | ||
| dd96daca LG |
60 | #define SOF_HDA_MAX_CAPS 10 |
| 61 | #define SOF_HDA_CAP_ID_OFF 16 | |
| 62 | #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ | |
| 63 | SOF_HDA_CAP_ID_OFF) | |
| 64 | #define SOF_HDA_CAP_NEXT_MASK 0xFFFF | |
| 65 | ||
| 66 | #define SOF_HDA_GTS_CAP_ID 0x1 | |
| 67 | #define SOF_HDA_ML_CAP_ID 0x2 | |
| 68 | ||
| 69 | #define SOF_HDA_PP_CAP_ID 0x3 | |
| 70 | #define SOF_HDA_REG_PP_PPCH 0x10 | |
| 71 | #define SOF_HDA_REG_PP_PPCTL 0x04 | |
| f1fd9d0e | 72 | #define SOF_HDA_REG_PP_PPSTS 0x08 |
| dd96daca LG |
73 | #define SOF_HDA_PPCTL_PIE BIT(31) |
| 74 | #define SOF_HDA_PPCTL_GPROCEN BIT(30) | |
| 75 | ||
| 62f8f766 KJ |
76 | /*Vendor Specific Registers*/ |
| 77 | #define SOF_HDA_VS_D0I3C 0x104A | |
| 78 | ||
| 79 | /* D0I3C Register fields */ | |
| 80 | #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */ | |
| 81 | #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */ | |
| 82 | ||
| dd96daca LG |
83 | /* DPIB entry size: 8 Bytes = 2 DWords */ |
| 84 | #define SOF_HDA_DPIB_ENTRY_SIZE 0x8 | |
| 85 | ||
| 86 | #define SOF_HDA_SPIB_CAP_ID 0x4 | |
| 87 | #define SOF_HDA_DRSM_CAP_ID 0x5 | |
| 88 | ||
| 89 | #define SOF_HDA_SPIB_BASE 0x08 | |
| 90 | #define SOF_HDA_SPIB_INTERVAL 0x08 | |
| 91 | #define SOF_HDA_SPIB_SPIB 0x00 | |
| 92 | #define SOF_HDA_SPIB_MAXFIFO 0x04 | |
| 93 | ||
| 94 | #define SOF_HDA_PPHC_BASE 0x10 | |
| 95 | #define SOF_HDA_PPHC_INTERVAL 0x10 | |
| 96 | ||
| 97 | #define SOF_HDA_PPLC_BASE 0x10 | |
| 98 | #define SOF_HDA_PPLC_MULTI 0x10 | |
| 99 | #define SOF_HDA_PPLC_INTERVAL 0x10 | |
| 100 | ||
| 101 | #define SOF_HDA_DRSM_BASE 0x08 | |
| 102 | #define SOF_HDA_DRSM_INTERVAL 0x08 | |
| 103 | ||
| 104 | /* Descriptor error interrupt */ | |
| 105 | #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 | |
| 106 | ||
| 107 | /* FIFO error interrupt */ | |
| 108 | #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 | |
| 109 | ||
| 110 | /* Buffer completion interrupt */ | |
| 111 | #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 | |
| 112 | ||
| 113 | #define SOF_HDA_CL_DMA_SD_INT_MASK \ | |
| 114 | (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ | |
| 115 | SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ | |
| 116 | SOF_HDA_CL_DMA_SD_INT_COMPLETE) | |
| 117 | #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ | |
| 118 | ||
| 119 | /* Intel HD Audio Code Loader DMA Registers */ | |
| 120 | #define SOF_HDA_ADSP_LOADER_BASE 0x80 | |
| 121 | #define SOF_HDA_ADSP_DPLBASE 0x70 | |
| 122 | #define SOF_HDA_ADSP_DPUBASE 0x74 | |
| 123 | #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 | |
| 124 | ||
| 125 | /* Stream Registers */ | |
| 38bf0780 PLB |
126 | #define SOF_HDA_ADSP_REG_SD_CTL 0x00 |
| 127 | #define SOF_HDA_ADSP_REG_SD_STS 0x03 | |
| 128 | #define SOF_HDA_ADSP_REG_SD_LPIB 0x04 | |
| 129 | #define SOF_HDA_ADSP_REG_SD_CBL 0x08 | |
| 130 | #define SOF_HDA_ADSP_REG_SD_LVI 0x0C | |
| 131 | #define SOF_HDA_ADSP_REG_SD_FIFOW 0x0E | |
| 132 | #define SOF_HDA_ADSP_REG_SD_FIFOSIZE 0x10 | |
| 133 | #define SOF_HDA_ADSP_REG_SD_FORMAT 0x12 | |
| 134 | #define SOF_HDA_ADSP_REG_SD_FIFOL 0x14 | |
| 135 | #define SOF_HDA_ADSP_REG_SD_BDLPL 0x18 | |
| 136 | #define SOF_HDA_ADSP_REG_SD_BDLPU 0x1C | |
| dd96daca LG |
137 | #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 |
| 138 | ||
| 369ea9f8 PU |
139 | /* SDxFIFOS FIFOS */ |
| 140 | #define SOF_HDA_SD_FIFOSIZE_FIFOS_MASK GENMASK(15, 0) | |
| 141 | ||
| dd96daca LG |
142 | /* CL: Software Position Based FIFO Capability Registers */ |
| 143 | #define SOF_DSP_REG_CL_SPBFIFO \ | |
| 144 | (SOF_HDA_ADSP_LOADER_BASE + 0x20) | |
| 145 | #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 | |
| 146 | #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 | |
| 147 | #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 | |
| 148 | #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc | |
| 149 | ||
| 150 | /* Stream Number */ | |
| 151 | #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 | |
| 152 | #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ | |
| 153 | GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ | |
| 154 | SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) | |
| 155 | ||
| 156 | #define HDA_DSP_HDA_BAR 0 | |
| 157 | #define HDA_DSP_PP_BAR 1 | |
| 158 | #define HDA_DSP_SPIB_BAR 2 | |
| 159 | #define HDA_DSP_DRSM_BAR 3 | |
| 160 | #define HDA_DSP_BAR 4 | |
| 161 | ||
| 162 | #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) | |
| 163 | ||
| 164 | #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) | |
| 165 | ||
| 166 | #define HDA_DSP_PANIC_OFFSET(x) \ | |
| 167 | (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) | |
| 168 | ||
| 169 | /* SRAM window 0 FW "registers" */ | |
| 170 | #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) | |
| 171 | #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) | |
| 172 | /* FW and ROM share offset 4 */ | |
| 173 | #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) | |
| 174 | #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) | |
| 175 | #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) | |
| 176 | ||
| 177 | #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 | |
| 178 | ||
| 179 | #define HDA_DSP_STREAM_RESET_TIMEOUT 300 | |
| 7bcaf0f2 ZY |
180 | /* |
| 181 | * Timeout in us, for setting the stream RUN bit, during | |
| 182 | * start/stop the stream. The timeout expires if new RUN bit | |
| 183 | * value cannot be read back within the specified time. | |
| 184 | */ | |
| 185 | #define HDA_DSP_STREAM_RUN_TIMEOUT 300 | |
| dd96daca LG |
186 | |
| 187 | #define HDA_DSP_SPIB_ENABLE 1 | |
| 188 | #define HDA_DSP_SPIB_DISABLE 0 | |
| 189 | ||
| 190 | #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) | |
| 191 | ||
| 192 | #define HDA_DSP_STACK_DUMP_SIZE 32 | |
| 193 | ||
| 15d8370c PU |
194 | /* ROM/FW status register */ |
| 195 | #define FSR_STATE_MASK GENMASK(23, 0) | |
| 196 | #define FSR_WAIT_STATE_MASK GENMASK(27, 24) | |
| 197 | #define FSR_MODULE_MASK GENMASK(30, 28) | |
| 198 | #define FSR_HALTED BIT(31) | |
| 199 | #define FSR_TO_STATE_CODE(x) ((x) & FSR_STATE_MASK) | |
| 200 | #define FSR_TO_WAIT_STATE_CODE(x) (((x) & FSR_WAIT_STATE_MASK) >> 24) | |
| 201 | #define FSR_TO_MODULE_CODE(x) (((x) & FSR_MODULE_MASK) >> 28) | |
| 202 | ||
| 203 | /* Wait states */ | |
| 204 | #define FSR_WAIT_FOR_IPC_BUSY 0x1 | |
| 205 | #define FSR_WAIT_FOR_IPC_DONE 0x2 | |
| 206 | #define FSR_WAIT_FOR_CACHE_INVALIDATION 0x3 | |
| 207 | #define FSR_WAIT_FOR_LP_SRAM_OFF 0x4 | |
| 208 | #define FSR_WAIT_FOR_DMA_BUFFER_FULL 0x5 | |
| 209 | #define FSR_WAIT_FOR_CSE_CSR 0x6 | |
| 210 | ||
| 211 | /* Module codes */ | |
| 212 | #define FSR_MOD_ROM 0x0 | |
| 213 | #define FSR_MOD_ROM_BYP 0x1 | |
| 214 | #define FSR_MOD_BASE_FW 0x2 | |
| 215 | #define FSR_MOD_LP_BOOT 0x3 | |
| 216 | #define FSR_MOD_BRNGUP 0x4 | |
| 217 | #define FSR_MOD_ROM_EXT 0x5 | |
| 218 | ||
| 219 | /* State codes (module dependent) */ | |
| 220 | /* Module independent states */ | |
| 221 | #define FSR_STATE_INIT 0x0 | |
| 222 | #define FSR_STATE_INIT_DONE 0x1 | |
| 223 | #define FSR_STATE_FW_ENTERED 0x5 | |
| 224 | ||
| 225 | /* ROM states */ | |
| 226 | #define FSR_STATE_ROM_INIT FSR_STATE_INIT | |
| 227 | #define FSR_STATE_ROM_INIT_DONE FSR_STATE_INIT_DONE | |
| 228 | #define FSR_STATE_ROM_CSE_MANIFEST_LOADED 0x2 | |
| 229 | #define FSR_STATE_ROM_FW_MANIFEST_LOADED 0x3 | |
| 230 | #define FSR_STATE_ROM_FW_FW_LOADED 0x4 | |
| 231 | #define FSR_STATE_ROM_FW_ENTERED FSR_STATE_FW_ENTERED | |
| 232 | #define FSR_STATE_ROM_VERIFY_FEATURE_MASK 0x6 | |
| 233 | #define FSR_STATE_ROM_GET_LOAD_OFFSET 0x7 | |
| 234 | #define FSR_STATE_ROM_FETCH_ROM_EXT 0x8 | |
| 235 | #define FSR_STATE_ROM_FETCH_ROM_EXT_DONE 0x9 | |
| c712be34 | 236 | #define FSR_STATE_ROM_BASEFW_ENTERED 0xf /* SKL */ |
| 15d8370c PU |
237 | |
| 238 | /* (ROM) CSE states */ | |
| 239 | #define FSR_STATE_ROM_CSE_IMR_REQUEST 0x10 | |
| 240 | #define FSR_STATE_ROM_CSE_IMR_GRANTED 0x11 | |
| 241 | #define FSR_STATE_ROM_CSE_VALIDATE_IMAGE_REQUEST 0x12 | |
| 242 | #define FSR_STATE_ROM_CSE_IMAGE_VALIDATED 0x13 | |
| 243 | ||
| 244 | #define FSR_STATE_ROM_CSE_IPC_IFACE_INIT 0x20 | |
| 245 | #define FSR_STATE_ROM_CSE_IPC_RESET_PHASE_1 0x21 | |
| 246 | #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL_ENTRY 0x22 | |
| 247 | #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL 0x23 | |
| 248 | #define FSR_STATE_ROM_CSE_IPC_DOWN 0x24 | |
| 249 | ||
| 250 | /* BRINGUP (or BRNGUP) states */ | |
| 251 | #define FSR_STATE_BRINGUP_INIT FSR_STATE_INIT | |
| 252 | #define FSR_STATE_BRINGUP_INIT_DONE FSR_STATE_INIT_DONE | |
| 253 | #define FSR_STATE_BRINGUP_HPSRAM_LOAD 0x2 | |
| 254 | #define FSR_STATE_BRINGUP_UNPACK_START 0X3 | |
| 255 | #define FSR_STATE_BRINGUP_IMR_RESTORE 0x4 | |
| 256 | #define FSR_STATE_BRINGUP_FW_ENTERED FSR_STATE_FW_ENTERED | |
| 257 | ||
| dd96daca | 258 | /* ROM status/error values */ |
| dd96daca LG |
259 | #define HDA_DSP_ROM_CSE_ERROR 40 |
| 260 | #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 | |
| 261 | #define HDA_DSP_ROM_IMR_TO_SMALL 42 | |
| 262 | #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 | |
| 263 | #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 | |
| 264 | #define HDA_DSP_ROM_IPC_FATAL_ERROR 45 | |
| 265 | #define HDA_DSP_ROM_L2_CACHE_ERROR 46 | |
| 266 | #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 | |
| 267 | #define HDA_DSP_ROM_API_PTR_INVALID 50 | |
| 268 | #define HDA_DSP_ROM_BASEFW_INCOMPAT 51 | |
| 269 | #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 | |
| 270 | #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 | |
| 271 | #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 | |
| 272 | #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 | |
| 273 | #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 | |
| 274 | #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 | |
| 2a68ff84 PU |
275 | |
| 276 | #define HDA_DSP_ROM_IPC_CONTROL 0x01000000 | |
| 277 | #define HDA_DSP_ROM_IPC_PURGE_FW 0x00004000 | |
| dd96daca LG |
278 | |
| 279 | /* various timeout values */ | |
| 280 | #define HDA_DSP_PU_TIMEOUT 50 | |
| 281 | #define HDA_DSP_PD_TIMEOUT 50 | |
| 282 | #define HDA_DSP_RESET_TIMEOUT_US 50000 | |
| 283 | #define HDA_DSP_BASEFW_TIMEOUT_US 3000000 | |
| 284 | #define HDA_DSP_INIT_TIMEOUT_US 500000 | |
| 285 | #define HDA_DSP_CTRL_RESET_TIMEOUT 100 | |
| 286 | #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ | |
| 287 | #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ | |
| 92f4beb7 | 288 | #define HDA_DSP_REG_POLL_RETRY_COUNT 50 |
| dd96daca | 289 | |
| 9d201b69 PLB |
290 | #define HDA_DSP_ADSPIC_IPC BIT(0) |
| 291 | #define HDA_DSP_ADSPIS_IPC BIT(0) | |
| dd96daca LG |
292 | |
| 293 | /* Intel HD Audio General DSP Registers */ | |
| 294 | #define HDA_DSP_GEN_BASE 0x0 | |
| 295 | #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) | |
| 296 | #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) | |
| 297 | #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) | |
| 298 | #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) | |
| 299 | #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) | |
| 300 | ||
| 8ebc9074 | 301 | #define HDA_DSP_REG_ADSPIC2_SNDW BIT(5) |
| 722ba5f1 BL |
302 | #define HDA_DSP_REG_ADSPIS2_SNDW BIT(5) |
| 303 | ||
| dd96daca LG |
304 | /* Intel HD Audio Inter-Processor Communication Registers */ |
| 305 | #define HDA_DSP_IPC_BASE 0x40 | |
| 306 | #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) | |
| 307 | #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) | |
| 308 | #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) | |
| 309 | #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) | |
| 310 | #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) | |
| 311 | ||
| 43b2ab90 RS |
312 | /* Intel Vendor Specific Registers */ |
| 313 | #define HDA_VS_INTEL_EM2 0x1030 | |
| 314 | #define HDA_VS_INTEL_EM2_L1SEN BIT(13) | |
| 847fd278 | 315 | #define HDA_VS_INTEL_LTRP 0x1048 |
| aca961f1 | 316 | #define HDA_VS_INTEL_LTRP_GB_MASK 0x3F |
| 43b2ab90 | 317 | |
| dd96daca LG |
318 | /* HIPCI */ |
| 319 | #define HDA_DSP_REG_HIPCI_BUSY BIT(31) | |
| 320 | #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF | |
| 321 | ||
| 322 | /* HIPCIE */ | |
| 323 | #define HDA_DSP_REG_HIPCIE_DONE BIT(30) | |
| 324 | #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF | |
| 325 | ||
| 326 | /* HIPCCTL */ | |
| 327 | #define HDA_DSP_REG_HIPCCTL_DONE BIT(1) | |
| 328 | #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) | |
| 329 | ||
| 330 | /* HIPCT */ | |
| 331 | #define HDA_DSP_REG_HIPCT_BUSY BIT(31) | |
| 332 | #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF | |
| 333 | ||
| 334 | /* HIPCTE */ | |
| 335 | #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF | |
| 336 | ||
| 9d201b69 PLB |
337 | #define HDA_DSP_ADSPIC_CL_DMA BIT(1) |
| 338 | #define HDA_DSP_ADSPIS_CL_DMA BIT(1) | |
| dd96daca LG |
339 | |
| 340 | /* Delay before scheduling D0i3 entry */ | |
| 341 | #define BXT_D0I3_DELAY 5000 | |
| 342 | ||
| 343 | #define FW_CL_STREAM_NUMBER 0x1 | |
| b2539ef0 | 344 | #define HDA_FW_BOOT_ATTEMPTS 3 |
| dd96daca LG |
345 | |
| 346 | /* ADSPCS - Audio DSP Control & Status */ | |
| 347 | ||
| 348 | /* | |
| 349 | * Core Reset - asserted high | |
| 350 | * CRST Mask for a given core mask pattern, cm | |
| 351 | */ | |
| 352 | #define HDA_DSP_ADSPCS_CRST_SHIFT 0 | |
| 353 | #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) | |
| 354 | ||
| 355 | /* | |
| 356 | * Core run/stall - when set to '1' core is stalled | |
| 357 | * CSTALL Mask for a given core mask pattern, cm | |
| 358 | */ | |
| 359 | #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 | |
| 360 | #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) | |
| 361 | ||
| 362 | /* | |
| 363 | * Set Power Active - when set to '1' turn cores on | |
| 364 | * SPA Mask for a given core mask pattern, cm | |
| 365 | */ | |
| 366 | #define HDA_DSP_ADSPCS_SPA_SHIFT 16 | |
| 367 | #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) | |
| 368 | ||
| 369 | /* | |
| 370 | * Current Power Active - power status of cores, set by hardware | |
| 371 | * CPA Mask for a given core mask pattern, cm | |
| 372 | */ | |
| 373 | #define HDA_DSP_ADSPCS_CPA_SHIFT 24 | |
| 374 | #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) | |
| 375 | ||
| dd96daca LG |
376 | /* |
| 377 | * Mask for a given number of cores | |
| 378 | * nc = number of supported cores | |
| 379 | */ | |
| 380 | #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) | |
| 381 | ||
| 382 | /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ | |
| 383 | #define CNL_DSP_IPC_BASE 0xc0 | |
| 384 | #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) | |
| 385 | #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) | |
| 386 | #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) | |
| 387 | #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) | |
| 388 | #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) | |
| 0267de58 | 389 | #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18) |
| dd96daca LG |
390 | #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) |
| 391 | ||
| 392 | /* HIPCI */ | |
| 393 | #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) | |
| 394 | #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF | |
| 395 | ||
| 396 | /* HIPCIE */ | |
| 397 | #define CNL_DSP_REG_HIPCIDA_DONE BIT(31) | |
| 398 | #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF | |
| 399 | ||
| 400 | /* HIPCCTL */ | |
| 401 | #define CNL_DSP_REG_HIPCCTL_DONE BIT(1) | |
| 402 | #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) | |
| 403 | ||
| 404 | /* HIPCT */ | |
| 405 | #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) | |
| 406 | #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF | |
| 407 | ||
| 408 | /* HIPCTDA */ | |
| 409 | #define CNL_DSP_REG_HIPCTDA_DONE BIT(31) | |
| 410 | #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF | |
| 411 | ||
| 412 | /* HIPCTDD */ | |
| 413 | #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF | |
| 414 | ||
| 415 | /* BDL */ | |
| 416 | #define HDA_DSP_BDL_SIZE 4096 | |
| 417 | #define HDA_DSP_MAX_BDL_ENTRIES \ | |
| 418 | (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) | |
| 419 | ||
| 420 | /* Number of DAIs */ | |
| 0f7b6a43 RS |
421 | #define SOF_SKL_NUM_DAIS_NOCODEC 8 |
| 422 | ||
| 45f3c2f8 | 423 | #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) |
| a6947c9d | 424 | #define SOF_SKL_NUM_DAIS 15 |
| dd96daca | 425 | #else |
| 0f7b6a43 | 426 | #define SOF_SKL_NUM_DAIS SOF_SKL_NUM_DAIS_NOCODEC |
| dd96daca LG |
427 | #endif |
| 428 | ||
| 429 | /* Intel HD Audio SRAM Window 0*/ | |
| e2379d4a | 430 | #define HDA_DSP_SRAM_REG_ROM_STATUS_SKL 0x8000 |
| dd96daca LG |
431 | #define HDA_ADSP_SRAM0_BASE_SKL 0x8000 |
| 432 | ||
| 433 | /* Firmware status window */ | |
| 434 | #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL | |
| 435 | #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) | |
| 436 | ||
| df7e0de5 ZY |
437 | /* Host Device Memory Space */ |
| 438 | #define APL_SSP_BASE_OFFSET 0x2000 | |
| 439 | #define CNL_SSP_BASE_OFFSET 0x10000 | |
| 440 | ||
| 441 | /* Host Device Memory Size of a Single SSP */ | |
| 442 | #define SSP_DEV_MEM_SIZE 0x1000 | |
| 443 | ||
| b095fe47 ZY |
444 | /* SSP Count of the Platform */ |
| 445 | #define APL_SSP_COUNT 6 | |
| 446 | #define CNL_SSP_COUNT 3 | |
| ec836daa | 447 | #define ICL_SSP_COUNT 6 |
| 9ccbc2e1 PLB |
448 | #define TGL_SSP_COUNT 3 |
| 449 | #define MTL_SSP_COUNT 3 | |
| b095fe47 | 450 | |
| 74ed4097 ZY |
451 | /* SSP Registers */ |
| 452 | #define SSP_SSC1_OFFSET 0x4 | |
| bd586a02 PLB |
453 | #define SSP_SET_SCLK_CONSUMER BIT(25) |
| 454 | #define SSP_SET_SFRM_CONSUMER BIT(24) | |
| 455 | #define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER) | |
| 74ed4097 | 456 | |
| 5a7543d0 PLB |
457 | #define HDA_EXT_ADDR 0 |
| 458 | #define HDA_EXT_CODEC(x) ((x) & BIT(HDA_EXT_ADDR)) | |
| c99fafdf KV |
459 | #define HDA_IDISP_ADDR 2 |
| 460 | #define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR)) | |
| dd96daca LG |
461 | |
| 462 | struct sof_intel_dsp_bdl { | |
| 463 | __le32 addr_l; | |
| 464 | __le32 addr_h; | |
| 465 | __le32 size; | |
| 466 | __le32 ioc; | |
| 467 | } __attribute((packed)); | |
| 468 | ||
| 469 | #define SOF_HDA_PLAYBACK_STREAMS 16 | |
| 470 | #define SOF_HDA_CAPTURE_STREAMS 16 | |
| 471 | #define SOF_HDA_PLAYBACK 0 | |
| 472 | #define SOF_HDA_CAPTURE 1 | |
| 473 | ||
| 89a400bd RS |
474 | /* stream flags */ |
| 475 | #define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1 | |
| 476 | ||
| 63e51fd3 RS |
477 | /* |
| 478 | * Time in ms for opportunistic D0I3 entry delay. | |
| 479 | * This has been deliberately chosen to be long to avoid race conditions. | |
| 480 | * Could be optimized in future. | |
| 481 | */ | |
| 482 | #define SOF_HDA_D0I3_WORK_DELAY_MS 5000 | |
| 483 | ||
| 61e285ca RS |
484 | /* HDA DSP D0 substate */ |
| 485 | enum sof_hda_D0_substate { | |
| 486 | SOF_HDA_DSP_PM_D0I0, /* default D0 substate */ | |
| 487 | SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */ | |
| 488 | }; | |
| 489 | ||
| dd96daca LG |
490 | /* represents DSP HDA controller frontend - i.e. host facing control */ |
| 491 | struct sof_intel_hda_dev { | |
| 2a68ff84 | 492 | bool imrboot_supported; |
| 57724db1 | 493 | bool skip_imr_boot; |
| 5d5d915b | 494 | bool booted_from_imr; |
| 2a68ff84 | 495 | |
| 776100a4 | 496 | int boot_iteration; |
| dd96daca LG |
497 | |
| 498 | struct hda_bus hbus; | |
| 499 | ||
| 500 | /* hw config */ | |
| 501 | const struct sof_intel_dsp_desc *desc; | |
| 502 | ||
| 503 | /* trace */ | |
| 504 | struct hdac_ext_stream *dtrace_stream; | |
| 505 | ||
| 506 | /* if position update IPC needed */ | |
| 507 | u32 no_ipc_position; | |
| 508 | ||
| e8e55dbe KJ |
509 | /* the maximum number of streams (playback + capture) supported */ |
| 510 | u32 stream_max; | |
| 511 | ||
| 16299326 | 512 | /* PM related */ |
| ae9db908 | 513 | bool l1_disabled;/* is DMI link L1 disabled? */ |
| 16299326 | 514 | |
| dd96daca LG |
515 | /* DMIC device */ |
| 516 | struct platform_device *dmic_dev; | |
| 63e51fd3 RS |
517 | |
| 518 | /* delayed work to enter D0I3 opportunistically */ | |
| 519 | struct delayed_work d0i3_work; | |
| 51dfed1e PLB |
520 | |
| 521 | /* ACPI information stored between scan and probe steps */ | |
| 522 | struct sdw_intel_acpi_info info; | |
| 523 | ||
| 524 | /* sdw context allocated by SoundWire driver */ | |
| 525 | struct sdw_intel_ctx *sdw; | |
| edbaaada FO |
526 | |
| 527 | /* FW clock config, 0:HPRO, 1:LPRO */ | |
| 528 | bool clk_config_lpro; | |
| 95fa7a62 | 529 | |
| c712be34 PLB |
530 | wait_queue_head_t waitq; |
| 531 | bool code_loading; | |
| 532 | ||
| 95fa7a62 PLB |
533 | /* Intel NHLT information */ |
| 534 | struct nhlt_acpi_table *nhlt; | |
| 483e4cdf PU |
535 | |
| 536 | /* | |
| 537 | * Pointing to the IPC message if immediate sending was not possible | |
| 538 | * because the downlink communication channel was BUSY at the time. | |
| 539 | * The message will be re-tried when the channel becomes free (the ACK | |
| 540 | * is received from the DSP for the previous message) | |
| 541 | */ | |
| 542 | struct snd_sof_ipc_msg *delayed_ipc_tx_msg; | |
| dd96daca LG |
543 | }; |
| 544 | ||
| 545 | static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) | |
| 546 | { | |
| 547 | struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; | |
| 548 | ||
| 549 | return &hda->hbus.core; | |
| 550 | } | |
| 551 | ||
| 552 | static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) | |
| 553 | { | |
| 554 | struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; | |
| 555 | ||
| 556 | return &hda->hbus; | |
| 557 | } | |
| 558 | ||
| 559 | struct sof_intel_hda_stream { | |
| 7623ae79 | 560 | struct snd_sof_dev *sdev; |
| 7d88b960 PLB |
561 | struct hdac_ext_stream hext_stream; |
| 562 | struct sof_intel_stream sof_intel_stream; | |
| 6b2239e3 | 563 | int host_reserved; /* reserve host DMA channel */ |
| 89a400bd | 564 | u32 flags; |
| d5263dbb | 565 | struct completion ioc; |
| dd96daca LG |
566 | }; |
| 567 | ||
| f5dbba9f | 568 | #define hstream_to_sof_hda_stream(hstream) \ |
| 7d88b960 | 569 | container_of(hstream, struct sof_intel_hda_stream, hext_stream) |
| f5dbba9f | 570 | |
| dd96daca LG |
571 | #define bus_to_sof_hda(bus) \ |
| 572 | container_of(bus, struct sof_intel_hda_dev, hbus.core) | |
| 573 | ||
| 574 | #define SOF_STREAM_SD_OFFSET(s) \ | |
| 575 | (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ | |
| 576 | + SOF_HDA_ADSP_LOADER_BASE) | |
| 577 | ||
| 2b1acedc RS |
578 | #define SOF_STREAM_SD_OFFSET_CRST 0x1 |
| 579 | ||
| d69f9ecb PLB |
580 | /* |
| 581 | * DAI support | |
| 582 | */ | |
| 583 | bool hda_is_chain_dma_supported(struct snd_sof_dev *sdev, u32 dai_type); | |
| 584 | ||
| dd96daca LG |
585 | /* |
| 586 | * DSP Core services. | |
| 587 | */ | |
| f1977d5b | 588 | int hda_dsp_probe_early(struct snd_sof_dev *sdev); |
| dd96daca | 589 | int hda_dsp_probe(struct snd_sof_dev *sdev); |
| e4d09de3 | 590 | void hda_dsp_remove(struct snd_sof_dev *sdev); |
| 264aeb99 | 591 | void hda_dsp_remove_late(struct snd_sof_dev *sdev); |
| 537b4a0c | 592 | int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask); |
| dd96daca | 593 | int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); |
| dd96daca | 594 | int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); |
| dd96daca LG |
595 | int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, |
| 596 | unsigned int core_mask); | |
| c714031f | 597 | int hda_power_down_dsp(struct snd_sof_dev *sdev); |
| 9cdcbc9f | 598 | int hda_dsp_core_get(struct snd_sof_dev *sdev, int core); |
| dd96daca LG |
599 | void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); |
| 600 | void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); | |
| 556eb416 | 601 | bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask); |
| dd96daca | 602 | |
| 996b07ef RS |
603 | int hda_dsp_set_power_state_ipc3(struct snd_sof_dev *sdev, |
| 604 | const struct sof_dsp_power_state *target_state); | |
| 605 | int hda_dsp_set_power_state_ipc4(struct snd_sof_dev *sdev, | |
| 606 | const struct sof_dsp_power_state *target_state); | |
| 62f8f766 | 607 | |
| 61e285ca | 608 | int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state); |
| dd96daca | 609 | int hda_dsp_resume(struct snd_sof_dev *sdev); |
| 1c38c922 | 610 | int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); |
| dd96daca | 611 | int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); |
| 62fde977 | 612 | int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); |
| 2aa2a5ea | 613 | int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev); |
| 22aa9e02 | 614 | int hda_dsp_shutdown(struct snd_sof_dev *sdev); |
| 7077a07a | 615 | int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); |
| dd96daca | 616 | void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); |
| eb6e5dab | 617 | void hda_ipc4_dsp_dump(struct snd_sof_dev *sdev, u32 flags); |
| f3da49f0 | 618 | void hda_ipc_dump(struct snd_sof_dev *sdev); |
| f1fd9d0e | 619 | void hda_ipc_irq_dump(struct snd_sof_dev *sdev); |
| 63e51fd3 | 620 | void hda_dsp_d0i3_work(struct work_struct *work); |
| b2520dbc | 621 | int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev); |
| 0bfbe91a PLB |
622 | bool hda_check_ipc_irq(struct snd_sof_dev *sdev); |
| 623 | u32 hda_get_interface_mask(struct snd_sof_dev *sdev); | |
| dd96daca LG |
624 | |
| 625 | /* | |
| 626 | * DSP PCM Operations. | |
| 627 | */ | |
| 49d7948e CR |
628 | u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate); |
| 629 | u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits); | |
| dd96daca LG |
630 | int hda_dsp_pcm_open(struct snd_sof_dev *sdev, |
| 631 | struct snd_pcm_substream *substream); | |
| 632 | int hda_dsp_pcm_close(struct snd_sof_dev *sdev, | |
| 633 | struct snd_pcm_substream *substream); | |
| 634 | int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, | |
| 635 | struct snd_pcm_substream *substream, | |
| 636 | struct snd_pcm_hw_params *params, | |
| 31f60a0c | 637 | struct snd_sof_platform_stream_params *platform_params); |
| 93146bc2 RS |
638 | int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, |
| 639 | struct snd_pcm_substream *substream); | |
| dd96daca LG |
640 | int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, |
| 641 | struct snd_pcm_substream *substream, int cmd); | |
| 642 | snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, | |
| 643 | struct snd_pcm_substream *substream); | |
| 6c26b505 | 644 | int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); |
| dd96daca LG |
645 | |
| 646 | /* | |
| 647 | * DSP Stream Operations. | |
| 648 | */ | |
| 649 | ||
| 650 | int hda_dsp_stream_init(struct snd_sof_dev *sdev); | |
| 651 | void hda_dsp_stream_free(struct snd_sof_dev *sdev); | |
| 652 | int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, | |
| 7d88b960 | 653 | struct hdac_ext_stream *hext_stream, |
| dd96daca LG |
654 | struct snd_dma_buffer *dmab, |
| 655 | struct snd_pcm_hw_params *params); | |
| 7d88b960 PLB |
656 | int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, |
| 657 | struct hdac_ext_stream *hext_stream, | |
| aca961f1 RS |
658 | struct snd_dma_buffer *dmab, |
| 659 | struct snd_pcm_hw_params *params); | |
| dd96daca | 660 | int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, |
| 7d88b960 | 661 | struct hdac_ext_stream *hext_stream, int cmd); |
| dd96daca LG |
662 | irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); |
| 663 | int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, | |
| 664 | struct snd_dma_buffer *dmab, | |
| 7d88b960 | 665 | struct hdac_stream *hstream); |
| 7c11af9f BL |
666 | bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev); |
| 667 | bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev); | |
| dd96daca | 668 | |
| a37a9224 PU |
669 | snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream, |
| 670 | int direction, bool can_sleep); | |
| 67b182be PU |
671 | u64 hda_dsp_get_stream_llp(struct snd_sof_dev *sdev, |
| 672 | struct snd_soc_component *component, | |
| 673 | struct snd_pcm_substream *substream); | |
| fd6f6a06 PU |
674 | u64 hda_dsp_get_stream_ldp(struct snd_sof_dev *sdev, |
| 675 | struct snd_soc_component *component, | |
| 676 | struct snd_pcm_substream *substream); | |
| a37a9224 | 677 | |
| dd96daca | 678 | struct hdac_ext_stream * |
| 89a400bd | 679 | hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags); |
| dd96daca LG |
680 | int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); |
| 681 | int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, | |
| 7d88b960 | 682 | struct hdac_ext_stream *hext_stream, |
| dd96daca LG |
683 | int enable, u32 size); |
| 684 | ||
| 6a0ba071 | 685 | int hda_ipc_msg_data(struct snd_sof_dev *sdev, |
| 1b905942 | 686 | struct snd_sof_pcm_stream *sps, |
| 6a0ba071 | 687 | void *p, size_t sz); |
| 29e3aa0b | 688 | int hda_set_stream_data_offset(struct snd_sof_dev *sdev, |
| 249f186d | 689 | struct snd_sof_pcm_stream *sps, |
| 29e3aa0b | 690 | size_t posn_offset); |
| dd96daca LG |
691 | |
| 692 | /* | |
| 693 | * DSP IPC Operations. | |
| 694 | */ | |
| 695 | int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, | |
| 696 | struct snd_sof_ipc_msg *msg); | |
| 697 | void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); | |
| 6eebd390 DB |
698 | int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); |
| 699 | int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); | |
| 700 | ||
| dd96daca LG |
701 | irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); |
| 702 | int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); | |
| 703 | ||
| 3dc26828 | 704 | void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level); |
| 0bfbe91a PLB |
705 | void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level, |
| 706 | u32 flags); | |
| 3dc26828 | 707 | |
| dd96daca LG |
708 | /* |
| 709 | * DSP Code loader. | |
| 710 | */ | |
| 711 | int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); | |
| acf705a4 | 712 | int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev); |
| b4e4c0b9 | 713 | int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream); |
| 6cbf0861 PLB |
714 | |
| 715 | struct hdac_ext_stream *hda_cl_prepare(struct device *dev, unsigned int format, | |
| 716 | unsigned int size, struct snd_dma_buffer *dmab, | |
| 717 | int direction, bool is_iccmax); | |
| 718 | int hda_cl_trigger(struct device *dev, struct hdac_ext_stream *hext_stream, int cmd); | |
| 719 | ||
| 720 | int hda_cl_cleanup(struct device *dev, struct snd_dma_buffer *dmab, | |
| b4e4c0b9 | 721 | struct hdac_ext_stream *hext_stream); |
| ab222a4a | 722 | int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot); |
| 406fed80 | 723 | #define HDA_CL_STREAM_FORMAT 0x40 |
| dd96daca LG |
724 | |
| 725 | /* pre and post fw run ops */ | |
| 726 | int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); | |
| 727 | int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); | |
| 728 | ||
| edbaaada FO |
729 | /* parse platform specific ext manifest ops */ |
| 730 | int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev, | |
| 731 | const struct sof_ext_man_elem_header *hdr); | |
| 732 | ||
| dd96daca LG |
733 | /* |
| 734 | * HDA Controller Operations. | |
| 735 | */ | |
| 736 | int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); | |
| 737 | void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); | |
| 738 | void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); | |
| 739 | int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); | |
| 740 | void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); | |
| 741 | int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); | |
| b48b77d8 | 742 | int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev); |
| 13063a2c | 743 | void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); |
| dd96daca LG |
744 | /* |
| 745 | * HDA bus operations. | |
| 746 | */ | |
| afae0942 PLB |
747 | void sof_hda_bus_init(struct snd_sof_dev *sdev, struct device *dev); |
| 748 | void sof_hda_bus_exit(struct snd_sof_dev *sdev); | |
| dd96daca | 749 | |
| dc1d964a | 750 | #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) |
| dd96daca LG |
751 | /* |
| 752 | * HDA Codec operations. | |
| 753 | */ | |
| 834c69d3 | 754 | void hda_codec_probe_bus(struct snd_sof_dev *sdev); |
| 31ba0c07 | 755 | void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable); |
| fd15f2f5 | 756 | void hda_codec_jack_check(struct snd_sof_dev *sdev); |
| 580803a7 | 757 | void hda_codec_check_for_state_change(struct snd_sof_dev *sdev); |
| ad09e446 | 758 | void hda_codec_init_cmd_io(struct snd_sof_dev *sdev); |
| 3400afcf | 759 | void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev); |
| bf2d764b | 760 | void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev); |
| 3400afcf | 761 | void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev); |
| ad09e446 PLB |
762 | void hda_codec_detect_mask(struct snd_sof_dev *sdev); |
| 763 | void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev); | |
| 87f42300 | 764 | bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev); |
| 3246a6c9 | 765 | void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status); |
| d4bfba1e | 766 | void hda_codec_device_remove(struct snd_sof_dev *sdev); |
| dd96daca | 767 | |
| dc1d964a PLB |
768 | #else |
| 769 | ||
| 770 | static inline void hda_codec_probe_bus(struct snd_sof_dev *sdev) { } | |
| 771 | static inline void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable) { } | |
| 772 | static inline void hda_codec_jack_check(struct snd_sof_dev *sdev) { } | |
| 580803a7 | 773 | static inline void hda_codec_check_for_state_change(struct snd_sof_dev *sdev) { } |
| ad09e446 | 774 | static inline void hda_codec_init_cmd_io(struct snd_sof_dev *sdev) { } |
| 3400afcf | 775 | static inline void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev) { } |
| bf2d764b | 776 | static inline void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev) { } |
| 3400afcf | 777 | static inline void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev) { } |
| ad09e446 PLB |
778 | static inline void hda_codec_detect_mask(struct snd_sof_dev *sdev) { } |
| 779 | static inline void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev) { } | |
| 87f42300 | 780 | static inline bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev) { return false; } |
| 3246a6c9 | 781 | static inline void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status) { } |
| d4bfba1e | 782 | static inline void hda_codec_device_remove(struct snd_sof_dev *sdev) { } |
| dc1d964a PLB |
783 | |
| 784 | #endif /* CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC */ | |
| dd96daca | 785 | |
| 2c6c809c | 786 | #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) && IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) |
| dd96daca | 787 | |
| 23ee0903 | 788 | void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable); |
| dd96daca LG |
789 | int hda_codec_i915_init(struct snd_sof_dev *sdev); |
| 790 | int hda_codec_i915_exit(struct snd_sof_dev *sdev); | |
| 791 | ||
| 792 | #else | |
| 793 | ||
| 834c69d3 | 794 | static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable) { } |
| dd96daca LG |
795 | static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } |
| 796 | static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } | |
| 797 | ||
| 139c7feb | 798 | #endif |
| dd96daca LG |
799 | |
| 800 | /* | |
| 801 | * Trace Control. | |
| 802 | */ | |
| 4b49cbd1 | 803 | int hda_dsp_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, |
| bab05b50 | 804 | struct sof_ipc_dma_trace_params_ext *dtrace_params); |
| dd96daca LG |
805 | int hda_dsp_trace_release(struct snd_sof_dev *sdev); |
| 806 | int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); | |
| 807 | ||
| 51dfed1e PLB |
808 | /* |
| 809 | * SoundWire support | |
| 810 | */ | |
| 811 | #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) | |
| 812 | ||
| 625339ca | 813 | int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev); |
| d3e7c32b | 814 | int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev); |
| 0bfbe91a | 815 | int hda_sdw_check_lcount(struct snd_sof_dev *sdev); |
| 51dfed1e | 816 | int hda_sdw_startup(struct snd_sof_dev *sdev); |
| 8ebc9074 | 817 | void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable); |
| 51dfed1e | 818 | void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable); |
| 9362ab78 | 819 | bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev); |
| 3b7bd0c1 | 820 | void hda_sdw_process_wakeen_common(struct snd_sof_dev *sdev); |
| bbd19cdc | 821 | void hda_sdw_process_wakeen(struct snd_sof_dev *sdev); |
| 198fa4bc | 822 | bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev); |
| 51dfed1e PLB |
823 | |
| 824 | #else | |
| 825 | ||
| 625339ca PLB |
826 | static inline int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev) |
| 827 | { | |
| 828 | return 0; | |
| 829 | } | |
| 830 | ||
| d3e7c32b PLB |
831 | static inline int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev) |
| 832 | { | |
| 833 | return 0; | |
| 834 | } | |
| 835 | ||
| 0bfbe91a PLB |
836 | static inline int hda_sdw_check_lcount(struct snd_sof_dev *sdev) |
| 837 | { | |
| 838 | return 0; | |
| 839 | } | |
| 840 | ||
| 51dfed1e PLB |
841 | static inline int hda_sdw_startup(struct snd_sof_dev *sdev) |
| 842 | { | |
| 843 | return 0; | |
| 844 | } | |
| 845 | ||
| 8ebc9074 PLB |
846 | static inline void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) |
| 847 | { | |
| 848 | } | |
| 849 | ||
| 51dfed1e PLB |
850 | static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) |
| 851 | { | |
| 852 | } | |
| 853 | ||
| 9362ab78 PLB |
854 | static inline bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev) |
| 855 | { | |
| 856 | return false; | |
| 857 | } | |
| 858 | ||
| 3b7bd0c1 PLB |
859 | static inline void hda_sdw_process_wakeen_common(struct snd_sof_dev *sdev) |
| 860 | { | |
| 861 | } | |
| 862 | ||
| bbd19cdc RW |
863 | static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) |
| 864 | { | |
| 865 | } | |
| 198fa4bc BL |
866 | |
| 867 | static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) | |
| 868 | { | |
| 869 | return false; | |
| 870 | } | |
| 871 | ||
| 51dfed1e PLB |
872 | #endif |
| 873 | ||
| 2960ee5c PLB |
874 | int sdw_hda_dai_hw_params(struct snd_pcm_substream *substream, |
| 875 | struct snd_pcm_hw_params *params, | |
| 876 | struct snd_soc_dai *cpu_dai, | |
| 8bc3b56c PLB |
877 | int link_id, |
| 878 | int intel_alh_id); | |
| 2960ee5c PLB |
879 | |
| 880 | int sdw_hda_dai_hw_free(struct snd_pcm_substream *substream, | |
| 881 | struct snd_soc_dai *cpu_dai, | |
| 882 | int link_id); | |
| 883 | ||
| 884 | int sdw_hda_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
| 885 | struct snd_soc_dai *cpu_dai); | |
| 886 | ||
| dd96daca LG |
887 | /* common dai driver */ |
| 888 | extern struct snd_soc_dai_driver skl_dai[]; | |
| f09e9284 | 889 | int hda_dsp_dais_suspend(struct snd_sof_dev *sdev); |
| dd96daca LG |
890 | |
| 891 | /* | |
| 892 | * Platform Specific HW abstraction Ops. | |
| 893 | */ | |
| 6032eefc | 894 | extern const struct snd_sof_dsp_ops sof_hda_common_ops; |
| 37e809d5 | 895 | |
| e2379d4a PLB |
896 | extern struct snd_sof_dsp_ops sof_skl_ops; |
| 897 | int sof_skl_ops_init(struct snd_sof_dev *sdev); | |
| 856601e5 | 898 | extern struct snd_sof_dsp_ops sof_apl_ops; |
| 37e809d5 | 899 | int sof_apl_ops_init(struct snd_sof_dev *sdev); |
| 856601e5 | 900 | extern struct snd_sof_dsp_ops sof_cnl_ops; |
| 37e809d5 | 901 | int sof_cnl_ops_init(struct snd_sof_dev *sdev); |
| 856601e5 | 902 | extern struct snd_sof_dsp_ops sof_tgl_ops; |
| 37e809d5 | 903 | int sof_tgl_ops_init(struct snd_sof_dev *sdev); |
| 856601e5 | 904 | extern struct snd_sof_dsp_ops sof_icl_ops; |
| 37e809d5 | 905 | int sof_icl_ops_init(struct snd_sof_dev *sdev); |
| 064520e8 BL |
906 | extern struct snd_sof_dsp_ops sof_mtl_ops; |
| 907 | int sof_mtl_ops_init(struct snd_sof_dev *sdev); | |
| c22d5327 PLB |
908 | extern struct snd_sof_dsp_ops sof_lnl_ops; |
| 909 | int sof_lnl_ops_init(struct snd_sof_dev *sdev); | |
| dd96daca | 910 | |
| e2379d4a | 911 | extern const struct sof_intel_dsp_desc skl_chip_info; |
| dd96daca LG |
912 | extern const struct sof_intel_dsp_desc apl_chip_info; |
| 913 | extern const struct sof_intel_dsp_desc cnl_chip_info; | |
| 630be964 | 914 | extern const struct sof_intel_dsp_desc icl_chip_info; |
| 1205c81e | 915 | extern const struct sof_intel_dsp_desc tgl_chip_info; |
| 30ee3738 | 916 | extern const struct sof_intel_dsp_desc tglh_chip_info; |
| 61732690 | 917 | extern const struct sof_intel_dsp_desc ehl_chip_info; |
| 6fd99035 | 918 | extern const struct sof_intel_dsp_desc jsl_chip_info; |
| 6c2b6bb0 | 919 | extern const struct sof_intel_dsp_desc adls_chip_info; |
| 064520e8 | 920 | extern const struct sof_intel_dsp_desc mtl_chip_info; |
| a00be6dc | 921 | extern const struct sof_intel_dsp_desc arl_s_chip_info; |
| 64a63d99 | 922 | extern const struct sof_intel_dsp_desc lnl_chip_info; |
| 3f8c8027 | 923 | extern const struct sof_intel_dsp_desc ptl_chip_info; |
| dd96daca | 924 | |
| 3dc0d709 PU |
925 | /* Probes support */ |
| 926 | #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) | |
| 927 | int hda_probes_register(struct snd_sof_dev *sdev); | |
| 928 | void hda_probes_unregister(struct snd_sof_dev *sdev); | |
| 929 | #else | |
| 930 | static inline int hda_probes_register(struct snd_sof_dev *sdev) | |
| 931 | { | |
| 932 | return 0; | |
| 933 | } | |
| 934 | ||
| 935 | static inline void hda_probes_unregister(struct snd_sof_dev *sdev) | |
| 936 | { | |
| 937 | } | |
| 938 | #endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */ | |
| 939 | ||
| 940 | /* SOF client registration for HDA platforms */ | |
| 941 | int hda_register_clients(struct snd_sof_dev *sdev); | |
| 942 | void hda_unregister_clients(struct snd_sof_dev *sdev); | |
| 943 | ||
| 285880a2 | 944 | /* machine driver select */ |
| cb515f10 GL |
945 | struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev); |
| 946 | void hda_set_mach_params(struct snd_soc_acpi_mach *mach, | |
| 17e9d6b0 | 947 | struct snd_sof_dev *sdev); |
| 285880a2 | 948 | |
| 194fe0fc PLB |
949 | /* PCI driver selection and probe */ |
| 950 | int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id); | |
| 951 | ||
| 0acb48dd RS |
952 | struct snd_sof_dai; |
| 953 | struct sof_ipc_dai_config; | |
| 0acb48dd | 954 | |
| 288fad2f PLB |
955 | #define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */ |
| 956 | #define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS (1) /* recommended if VC0 only */ | |
| 957 | #define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE (2) /* recommended with VC0 or VC1 */ | |
| 958 | ||
| 959 | extern int sof_hda_position_quirk; | |
| 960 | ||
| 51ec71dc | 961 | void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops); |
| 1da51943 | 962 | void hda_ops_free(struct snd_sof_dev *sdev); |
| 51ec71dc | 963 | |
| c712be34 PLB |
964 | /* SKL/KBL */ |
| 965 | int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev); | |
| 556eb416 PLB |
966 | int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask); |
| 967 | ||
| e3105c0c RS |
968 | /* IPC4 */ |
| 969 | irqreturn_t cnl_ipc4_irq_thread(int irq, void *context); | |
| 970 | int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); | |
| 971 | irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context); | |
| 483e4cdf | 972 | bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev); |
| 3e6b6ed3 RW |
973 | void hda_dsp_ipc4_schedule_d0i3_work(struct sof_intel_hda_dev *hdev, |
| 974 | struct snd_sof_ipc_msg *msg); | |
| e3105c0c | 975 | int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); |
| 32b97c07 | 976 | void hda_ipc4_dump(struct snd_sof_dev *sdev); |
| 2a1be12c | 977 | extern struct sdw_intel_ops sdw_callback; |
| e3105c0c | 978 | |
| 3ab2c21e PU |
979 | struct sof_ipc4_fw_library; |
| 980 | int hda_dsp_ipc4_load_library(struct snd_sof_dev *sdev, | |
| 981 | struct sof_ipc4_fw_library *fw_lib, bool reload); | |
| 2ae49c6f RS |
982 | |
| 983 | /** | |
| 984 | * struct hda_dai_widget_dma_ops - DAI DMA ops optional by default unless specified otherwise | |
| 985 | * @get_hext_stream: Mandatory function pointer to get the saved pointer to struct hdac_ext_stream | |
| 986 | * @assign_hext_stream: Function pointer to assign a hdac_ext_stream | |
| 987 | * @release_hext_stream: Function pointer to release the hdac_ext_stream | |
| 988 | * @setup_hext_stream: Function pointer for hdac_ext_stream setup | |
| 989 | * @reset_hext_stream: Function pointer for hdac_ext_stream reset | |
| 990 | * @pre_trigger: Function pointer for DAI DMA pre-trigger actions | |
| 991 | * @trigger: Function pointer for DAI DMA trigger actions | |
| 992 | * @post_trigger: Function pointer for DAI DMA post-trigger actions | |
| 2205c63d | 993 | * @codec_dai_set_stream: Function pointer to set codec-side stream information |
| 767cda3f PLB |
994 | * @calc_stream_format: Function pointer to determine stream format from hw_params and |
| 995 | * for HDaudio codec DAI from the .sig bits | |
| d1bf5847 PLB |
996 | * @get_hlink: Mandatory function pointer to retrieve hlink, mainly to program LOSIDV |
| 997 | * for legacy HDaudio links or program HDaudio Extended Link registers. | |
| 2ae49c6f RS |
998 | */ |
| 999 | struct hda_dai_widget_dma_ops { | |
| 1000 | struct hdac_ext_stream *(*get_hext_stream)(struct snd_sof_dev *sdev, | |
| 1001 | struct snd_soc_dai *cpu_dai, | |
| 1002 | struct snd_pcm_substream *substream); | |
| 1003 | struct hdac_ext_stream *(*assign_hext_stream)(struct snd_sof_dev *sdev, | |
| 1004 | struct snd_soc_dai *cpu_dai, | |
| 1005 | struct snd_pcm_substream *substream); | |
| 1006 | void (*release_hext_stream)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, | |
| 1007 | struct snd_pcm_substream *substream); | |
| 1008 | void (*setup_hext_stream)(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream, | |
| 1009 | unsigned int format_val); | |
| 1010 | void (*reset_hext_stream)(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_sream); | |
| 1011 | int (*pre_trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, | |
| 1012 | struct snd_pcm_substream *substream, int cmd); | |
| 1013 | int (*trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, | |
| 1014 | struct snd_pcm_substream *substream, int cmd); | |
| 1015 | int (*post_trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, | |
| 1016 | struct snd_pcm_substream *substream, int cmd); | |
| 2205c63d PLB |
1017 | void (*codec_dai_set_stream)(struct snd_sof_dev *sdev, |
| 1018 | struct snd_pcm_substream *substream, | |
| 1019 | struct hdac_stream *hstream); | |
| 767cda3f PLB |
1020 | unsigned int (*calc_stream_format)(struct snd_sof_dev *sdev, |
| 1021 | struct snd_pcm_substream *substream, | |
| 1022 | struct snd_pcm_hw_params *params); | |
| d1bf5847 PLB |
1023 | struct hdac_ext_link * (*get_hlink)(struct snd_sof_dev *sdev, |
| 1024 | struct snd_pcm_substream *substream); | |
| 2ae49c6f | 1025 | }; |
| 80afde34 RS |
1026 | |
| 1027 | const struct hda_dai_widget_dma_ops * | |
| 1028 | hda_select_dai_widget_ops(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget); | |
| 2b009fa0 RS |
1029 | int hda_dai_config(struct snd_soc_dapm_widget *w, unsigned int flags, |
| 1030 | struct snd_sof_dai_config_data *data); | |
| 90219f1b RS |
1031 | int hda_link_dma_cleanup(struct snd_pcm_substream *substream, struct hdac_ext_stream *hext_stream, |
| 1032 | struct snd_soc_dai *cpu_dai); | |
| 80afde34 | 1033 | |
| 2ac9e09b PLB |
1034 | static inline struct snd_sof_dev *widget_to_sdev(struct snd_soc_dapm_widget *w) |
| 1035 | { | |
| 1036 | struct snd_sof_widget *swidget = w->dobj.private; | |
| 1037 | struct snd_soc_component *component = swidget->scomp; | |
| 1038 | ||
| 1039 | return snd_soc_component_get_drvdata(component); | |
| 1040 | } | |
| 1041 | ||
| dd96daca | 1042 | #endif |