projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| e149ca29 | 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ |
| dd96daca LG |
2 | /* |
| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
| 4 | * redistributing this file, you may do so under either license. | |
| 5 | * | |
| 6 | * Copyright(c) 2017 Intel Corporation. All rights reserved. | |
| 7 | * | |
| 8 | * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __SOF_INTEL_HDA_H | |
| 12 | #define __SOF_INTEL_HDA_H | |
| 13 | ||
| 51dfed1e PLB |
14 | #include <linux/soundwire/sdw.h> |
| 15 | #include <linux/soundwire/sdw_intel.h> | |
| 4c414da9 | 16 | #include <sound/compress_driver.h> |
| dd96daca LG |
17 | #include <sound/hda_codec.h> |
| 18 | #include <sound/hdaudio_ext.h> | |
| 3dc0d709 | 19 | #include "../sof-client-probes.h" |
| 051744b1 | 20 | #include "../sof-audio.h" |
| dd96daca LG |
21 | #include "shim.h" |
| 22 | ||
| 23 | /* PCI registers */ | |
| 24 | #define PCI_TCSEL 0x44 | |
| 25 | #define PCI_PGCTL PCI_TCSEL | |
| 26 | #define PCI_CGCTL 0x48 | |
| 27 | ||
| 28 | /* PCI_PGCTL bits */ | |
| 29 | #define PCI_PGCTL_ADSPPGD BIT(2) | |
| 30 | #define PCI_PGCTL_LSRMD_MASK BIT(4) | |
| 31 | ||
| 32 | /* PCI_CGCTL bits */ | |
| 33 | #define PCI_CGCTL_MISCBDCGE_MASK BIT(6) | |
| 34 | #define PCI_CGCTL_ADSPDCGE BIT(1) | |
| 35 | ||
| 36 | /* Legacy HDA registers and bits used - widths are variable */ | |
| 37 | #define SOF_HDA_GCAP 0x0 | |
| 38 | #define SOF_HDA_GCTL 0x8 | |
| 39 | /* accept unsol. response enable */ | |
| 40 | #define SOF_HDA_GCTL_UNSOL BIT(8) | |
| 41 | #define SOF_HDA_LLCH 0x14 | |
| 42 | #define SOF_HDA_INTCTL 0x20 | |
| 43 | #define SOF_HDA_INTSTS 0x24 | |
| 44 | #define SOF_HDA_WAKESTS 0x0E | |
| 45 | #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) | |
| 46 | #define SOF_HDA_RIRBSTS 0x5d | |
| dd96daca LG |
47 | |
| 48 | /* SOF_HDA_GCTL register bist */ | |
| 49 | #define SOF_HDA_GCTL_RESET BIT(0) | |
| 50 | ||
| 7c11af9f | 51 | /* SOF_HDA_INCTL regs */ |
| dd96daca LG |
52 | #define SOF_HDA_INT_GLOBAL_EN BIT(31) |
| 53 | #define SOF_HDA_INT_CTRL_EN BIT(30) | |
| 54 | #define SOF_HDA_INT_ALL_STREAM 0xff | |
| 55 | ||
| 7c11af9f BL |
56 | /* SOF_HDA_INTSTS regs */ |
| 57 | #define SOF_HDA_INTSTS_GIS BIT(31) | |
| 58 | ||
| dd96daca LG |
59 | #define SOF_HDA_MAX_CAPS 10 |
| 60 | #define SOF_HDA_CAP_ID_OFF 16 | |
| 61 | #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ | |
| 62 | SOF_HDA_CAP_ID_OFF) | |
| 63 | #define SOF_HDA_CAP_NEXT_MASK 0xFFFF | |
| 64 | ||
| 65 | #define SOF_HDA_GTS_CAP_ID 0x1 | |
| 66 | #define SOF_HDA_ML_CAP_ID 0x2 | |
| 67 | ||
| 68 | #define SOF_HDA_PP_CAP_ID 0x3 | |
| 69 | #define SOF_HDA_REG_PP_PPCH 0x10 | |
| 70 | #define SOF_HDA_REG_PP_PPCTL 0x04 | |
| f1fd9d0e | 71 | #define SOF_HDA_REG_PP_PPSTS 0x08 |
| dd96daca LG |
72 | #define SOF_HDA_PPCTL_PIE BIT(31) |
| 73 | #define SOF_HDA_PPCTL_GPROCEN BIT(30) | |
| 74 | ||
| 62f8f766 KJ |
75 | /*Vendor Specific Registers*/ |
| 76 | #define SOF_HDA_VS_D0I3C 0x104A | |
| 77 | ||
| 78 | /* D0I3C Register fields */ | |
| 79 | #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */ | |
| 80 | #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */ | |
| 81 | ||
| dd96daca LG |
82 | /* DPIB entry size: 8 Bytes = 2 DWords */ |
| 83 | #define SOF_HDA_DPIB_ENTRY_SIZE 0x8 | |
| 84 | ||
| 85 | #define SOF_HDA_SPIB_CAP_ID 0x4 | |
| 86 | #define SOF_HDA_DRSM_CAP_ID 0x5 | |
| 87 | ||
| 88 | #define SOF_HDA_SPIB_BASE 0x08 | |
| 89 | #define SOF_HDA_SPIB_INTERVAL 0x08 | |
| 90 | #define SOF_HDA_SPIB_SPIB 0x00 | |
| 91 | #define SOF_HDA_SPIB_MAXFIFO 0x04 | |
| 92 | ||
| 93 | #define SOF_HDA_PPHC_BASE 0x10 | |
| 94 | #define SOF_HDA_PPHC_INTERVAL 0x10 | |
| 95 | ||
| 96 | #define SOF_HDA_PPLC_BASE 0x10 | |
| 97 | #define SOF_HDA_PPLC_MULTI 0x10 | |
| 98 | #define SOF_HDA_PPLC_INTERVAL 0x10 | |
| 99 | ||
| 100 | #define SOF_HDA_DRSM_BASE 0x08 | |
| 101 | #define SOF_HDA_DRSM_INTERVAL 0x08 | |
| 102 | ||
| 103 | /* Descriptor error interrupt */ | |
| 104 | #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 | |
| 105 | ||
| 106 | /* FIFO error interrupt */ | |
| 107 | #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 | |
| 108 | ||
| 109 | /* Buffer completion interrupt */ | |
| 110 | #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 | |
| 111 | ||
| 112 | #define SOF_HDA_CL_DMA_SD_INT_MASK \ | |
| 113 | (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ | |
| 114 | SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ | |
| 115 | SOF_HDA_CL_DMA_SD_INT_COMPLETE) | |
| 116 | #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ | |
| 117 | ||
| 118 | /* Intel HD Audio Code Loader DMA Registers */ | |
| 119 | #define SOF_HDA_ADSP_LOADER_BASE 0x80 | |
| 120 | #define SOF_HDA_ADSP_DPLBASE 0x70 | |
| 121 | #define SOF_HDA_ADSP_DPUBASE 0x74 | |
| 122 | #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 | |
| 123 | ||
| 124 | /* Stream Registers */ | |
| 38bf0780 PLB |
125 | #define SOF_HDA_ADSP_REG_SD_CTL 0x00 |
| 126 | #define SOF_HDA_ADSP_REG_SD_STS 0x03 | |
| 127 | #define SOF_HDA_ADSP_REG_SD_LPIB 0x04 | |
| 128 | #define SOF_HDA_ADSP_REG_SD_CBL 0x08 | |
| 129 | #define SOF_HDA_ADSP_REG_SD_LVI 0x0C | |
| 130 | #define SOF_HDA_ADSP_REG_SD_FIFOW 0x0E | |
| 131 | #define SOF_HDA_ADSP_REG_SD_FIFOSIZE 0x10 | |
| 132 | #define SOF_HDA_ADSP_REG_SD_FORMAT 0x12 | |
| 133 | #define SOF_HDA_ADSP_REG_SD_FIFOL 0x14 | |
| 134 | #define SOF_HDA_ADSP_REG_SD_BDLPL 0x18 | |
| 135 | #define SOF_HDA_ADSP_REG_SD_BDLPU 0x1C | |
| dd96daca LG |
136 | #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 |
| 137 | ||
| 138 | /* CL: Software Position Based FIFO Capability Registers */ | |
| 139 | #define SOF_DSP_REG_CL_SPBFIFO \ | |
| 140 | (SOF_HDA_ADSP_LOADER_BASE + 0x20) | |
| 141 | #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 | |
| 142 | #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 | |
| 143 | #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 | |
| 144 | #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc | |
| 145 | ||
| 146 | /* Stream Number */ | |
| 147 | #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 | |
| 148 | #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ | |
| 149 | GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ | |
| 150 | SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) | |
| 151 | ||
| 152 | #define HDA_DSP_HDA_BAR 0 | |
| 153 | #define HDA_DSP_PP_BAR 1 | |
| 154 | #define HDA_DSP_SPIB_BAR 2 | |
| 155 | #define HDA_DSP_DRSM_BAR 3 | |
| 156 | #define HDA_DSP_BAR 4 | |
| 157 | ||
| 158 | #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) | |
| 159 | ||
| 160 | #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) | |
| 161 | ||
| 162 | #define HDA_DSP_PANIC_OFFSET(x) \ | |
| 163 | (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) | |
| 164 | ||
| 165 | /* SRAM window 0 FW "registers" */ | |
| 166 | #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) | |
| 167 | #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) | |
| 168 | /* FW and ROM share offset 4 */ | |
| 169 | #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) | |
| 170 | #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) | |
| 171 | #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) | |
| 172 | ||
| 173 | #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 | |
| 174 | ||
| 175 | #define HDA_DSP_STREAM_RESET_TIMEOUT 300 | |
| 7bcaf0f2 ZY |
176 | /* |
| 177 | * Timeout in us, for setting the stream RUN bit, during | |
| 178 | * start/stop the stream. The timeout expires if new RUN bit | |
| 179 | * value cannot be read back within the specified time. | |
| 180 | */ | |
| 181 | #define HDA_DSP_STREAM_RUN_TIMEOUT 300 | |
| dd96daca LG |
182 | |
| 183 | #define HDA_DSP_SPIB_ENABLE 1 | |
| 184 | #define HDA_DSP_SPIB_DISABLE 0 | |
| 185 | ||
| 186 | #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) | |
| 187 | ||
| 188 | #define HDA_DSP_STACK_DUMP_SIZE 32 | |
| 189 | ||
| 15d8370c PU |
190 | /* ROM/FW status register */ |
| 191 | #define FSR_STATE_MASK GENMASK(23, 0) | |
| 192 | #define FSR_WAIT_STATE_MASK GENMASK(27, 24) | |
| 193 | #define FSR_MODULE_MASK GENMASK(30, 28) | |
| 194 | #define FSR_HALTED BIT(31) | |
| 195 | #define FSR_TO_STATE_CODE(x) ((x) & FSR_STATE_MASK) | |
| 196 | #define FSR_TO_WAIT_STATE_CODE(x) (((x) & FSR_WAIT_STATE_MASK) >> 24) | |
| 197 | #define FSR_TO_MODULE_CODE(x) (((x) & FSR_MODULE_MASK) >> 28) | |
| 198 | ||
| 199 | /* Wait states */ | |
| 200 | #define FSR_WAIT_FOR_IPC_BUSY 0x1 | |
| 201 | #define FSR_WAIT_FOR_IPC_DONE 0x2 | |
| 202 | #define FSR_WAIT_FOR_CACHE_INVALIDATION 0x3 | |
| 203 | #define FSR_WAIT_FOR_LP_SRAM_OFF 0x4 | |
| 204 | #define FSR_WAIT_FOR_DMA_BUFFER_FULL 0x5 | |
| 205 | #define FSR_WAIT_FOR_CSE_CSR 0x6 | |
| 206 | ||
| 207 | /* Module codes */ | |
| 208 | #define FSR_MOD_ROM 0x0 | |
| 209 | #define FSR_MOD_ROM_BYP 0x1 | |
| 210 | #define FSR_MOD_BASE_FW 0x2 | |
| 211 | #define FSR_MOD_LP_BOOT 0x3 | |
| 212 | #define FSR_MOD_BRNGUP 0x4 | |
| 213 | #define FSR_MOD_ROM_EXT 0x5 | |
| 214 | ||
| 215 | /* State codes (module dependent) */ | |
| 216 | /* Module independent states */ | |
| 217 | #define FSR_STATE_INIT 0x0 | |
| 218 | #define FSR_STATE_INIT_DONE 0x1 | |
| 219 | #define FSR_STATE_FW_ENTERED 0x5 | |
| 220 | ||
| 221 | /* ROM states */ | |
| 222 | #define FSR_STATE_ROM_INIT FSR_STATE_INIT | |
| 223 | #define FSR_STATE_ROM_INIT_DONE FSR_STATE_INIT_DONE | |
| 224 | #define FSR_STATE_ROM_CSE_MANIFEST_LOADED 0x2 | |
| 225 | #define FSR_STATE_ROM_FW_MANIFEST_LOADED 0x3 | |
| 226 | #define FSR_STATE_ROM_FW_FW_LOADED 0x4 | |
| 227 | #define FSR_STATE_ROM_FW_ENTERED FSR_STATE_FW_ENTERED | |
| 228 | #define FSR_STATE_ROM_VERIFY_FEATURE_MASK 0x6 | |
| 229 | #define FSR_STATE_ROM_GET_LOAD_OFFSET 0x7 | |
| 230 | #define FSR_STATE_ROM_FETCH_ROM_EXT 0x8 | |
| 231 | #define FSR_STATE_ROM_FETCH_ROM_EXT_DONE 0x9 | |
| c712be34 | 232 | #define FSR_STATE_ROM_BASEFW_ENTERED 0xf /* SKL */ |
| 15d8370c PU |
233 | |
| 234 | /* (ROM) CSE states */ | |
| 235 | #define FSR_STATE_ROM_CSE_IMR_REQUEST 0x10 | |
| 236 | #define FSR_STATE_ROM_CSE_IMR_GRANTED 0x11 | |
| 237 | #define FSR_STATE_ROM_CSE_VALIDATE_IMAGE_REQUEST 0x12 | |
| 238 | #define FSR_STATE_ROM_CSE_IMAGE_VALIDATED 0x13 | |
| 239 | ||
| 240 | #define FSR_STATE_ROM_CSE_IPC_IFACE_INIT 0x20 | |
| 241 | #define FSR_STATE_ROM_CSE_IPC_RESET_PHASE_1 0x21 | |
| 242 | #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL_ENTRY 0x22 | |
| 243 | #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL 0x23 | |
| 244 | #define FSR_STATE_ROM_CSE_IPC_DOWN 0x24 | |
| 245 | ||
| 246 | /* BRINGUP (or BRNGUP) states */ | |
| 247 | #define FSR_STATE_BRINGUP_INIT FSR_STATE_INIT | |
| 248 | #define FSR_STATE_BRINGUP_INIT_DONE FSR_STATE_INIT_DONE | |
| 249 | #define FSR_STATE_BRINGUP_HPSRAM_LOAD 0x2 | |
| 250 | #define FSR_STATE_BRINGUP_UNPACK_START 0X3 | |
| 251 | #define FSR_STATE_BRINGUP_IMR_RESTORE 0x4 | |
| 252 | #define FSR_STATE_BRINGUP_FW_ENTERED FSR_STATE_FW_ENTERED | |
| 253 | ||
| dd96daca | 254 | /* ROM status/error values */ |
| dd96daca LG |
255 | #define HDA_DSP_ROM_CSE_ERROR 40 |
| 256 | #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 | |
| 257 | #define HDA_DSP_ROM_IMR_TO_SMALL 42 | |
| 258 | #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 | |
| 259 | #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 | |
| 260 | #define HDA_DSP_ROM_IPC_FATAL_ERROR 45 | |
| 261 | #define HDA_DSP_ROM_L2_CACHE_ERROR 46 | |
| 262 | #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 | |
| 263 | #define HDA_DSP_ROM_API_PTR_INVALID 50 | |
| 264 | #define HDA_DSP_ROM_BASEFW_INCOMPAT 51 | |
| 265 | #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 | |
| 266 | #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 | |
| 267 | #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 | |
| 268 | #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 | |
| 269 | #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 | |
| 270 | #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 | |
| 2a68ff84 PU |
271 | |
| 272 | #define HDA_DSP_ROM_IPC_CONTROL 0x01000000 | |
| 273 | #define HDA_DSP_ROM_IPC_PURGE_FW 0x00004000 | |
| dd96daca LG |
274 | |
| 275 | /* various timeout values */ | |
| 276 | #define HDA_DSP_PU_TIMEOUT 50 | |
| 277 | #define HDA_DSP_PD_TIMEOUT 50 | |
| 278 | #define HDA_DSP_RESET_TIMEOUT_US 50000 | |
| 279 | #define HDA_DSP_BASEFW_TIMEOUT_US 3000000 | |
| 280 | #define HDA_DSP_INIT_TIMEOUT_US 500000 | |
| 281 | #define HDA_DSP_CTRL_RESET_TIMEOUT 100 | |
| 282 | #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ | |
| 283 | #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ | |
| 92f4beb7 | 284 | #define HDA_DSP_REG_POLL_RETRY_COUNT 50 |
| dd96daca | 285 | |
| 9d201b69 PLB |
286 | #define HDA_DSP_ADSPIC_IPC BIT(0) |
| 287 | #define HDA_DSP_ADSPIS_IPC BIT(0) | |
| dd96daca LG |
288 | |
| 289 | /* Intel HD Audio General DSP Registers */ | |
| 290 | #define HDA_DSP_GEN_BASE 0x0 | |
| 291 | #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) | |
| 292 | #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) | |
| 293 | #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) | |
| 294 | #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) | |
| 295 | #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) | |
| 296 | ||
| 8ebc9074 | 297 | #define HDA_DSP_REG_ADSPIC2_SNDW BIT(5) |
| 722ba5f1 BL |
298 | #define HDA_DSP_REG_ADSPIS2_SNDW BIT(5) |
| 299 | ||
| dd96daca LG |
300 | /* Intel HD Audio Inter-Processor Communication Registers */ |
| 301 | #define HDA_DSP_IPC_BASE 0x40 | |
| 302 | #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) | |
| 303 | #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) | |
| 304 | #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) | |
| 305 | #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) | |
| 306 | #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) | |
| 307 | ||
| 43b2ab90 RS |
308 | /* Intel Vendor Specific Registers */ |
| 309 | #define HDA_VS_INTEL_EM2 0x1030 | |
| 310 | #define HDA_VS_INTEL_EM2_L1SEN BIT(13) | |
| 847fd278 | 311 | #define HDA_VS_INTEL_LTRP 0x1048 |
| aca961f1 | 312 | #define HDA_VS_INTEL_LTRP_GB_MASK 0x3F |
| 43b2ab90 | 313 | |
| dd96daca LG |
314 | /* HIPCI */ |
| 315 | #define HDA_DSP_REG_HIPCI_BUSY BIT(31) | |
| 316 | #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF | |
| 317 | ||
| 318 | /* HIPCIE */ | |
| 319 | #define HDA_DSP_REG_HIPCIE_DONE BIT(30) | |
| 320 | #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF | |
| 321 | ||
| 322 | /* HIPCCTL */ | |
| 323 | #define HDA_DSP_REG_HIPCCTL_DONE BIT(1) | |
| 324 | #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) | |
| 325 | ||
| 326 | /* HIPCT */ | |
| 327 | #define HDA_DSP_REG_HIPCT_BUSY BIT(31) | |
| 328 | #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF | |
| 329 | ||
| 330 | /* HIPCTE */ | |
| 331 | #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF | |
| 332 | ||
| 9d201b69 PLB |
333 | #define HDA_DSP_ADSPIC_CL_DMA BIT(1) |
| 334 | #define HDA_DSP_ADSPIS_CL_DMA BIT(1) | |
| dd96daca LG |
335 | |
| 336 | /* Delay before scheduling D0i3 entry */ | |
| 337 | #define BXT_D0I3_DELAY 5000 | |
| 338 | ||
| 339 | #define FW_CL_STREAM_NUMBER 0x1 | |
| b2539ef0 | 340 | #define HDA_FW_BOOT_ATTEMPTS 3 |
| dd96daca LG |
341 | |
| 342 | /* ADSPCS - Audio DSP Control & Status */ | |
| 343 | ||
| 344 | /* | |
| 345 | * Core Reset - asserted high | |
| 346 | * CRST Mask for a given core mask pattern, cm | |
| 347 | */ | |
| 348 | #define HDA_DSP_ADSPCS_CRST_SHIFT 0 | |
| 349 | #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) | |
| 350 | ||
| 351 | /* | |
| 352 | * Core run/stall - when set to '1' core is stalled | |
| 353 | * CSTALL Mask for a given core mask pattern, cm | |
| 354 | */ | |
| 355 | #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 | |
| 356 | #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) | |
| 357 | ||
| 358 | /* | |
| 359 | * Set Power Active - when set to '1' turn cores on | |
| 360 | * SPA Mask for a given core mask pattern, cm | |
| 361 | */ | |
| 362 | #define HDA_DSP_ADSPCS_SPA_SHIFT 16 | |
| 363 | #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) | |
| 364 | ||
| 365 | /* | |
| 366 | * Current Power Active - power status of cores, set by hardware | |
| 367 | * CPA Mask for a given core mask pattern, cm | |
| 368 | */ | |
| 369 | #define HDA_DSP_ADSPCS_CPA_SHIFT 24 | |
| 370 | #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) | |
| 371 | ||
| dd96daca LG |
372 | /* |
| 373 | * Mask for a given number of cores | |
| 374 | * nc = number of supported cores | |
| 375 | */ | |
| 376 | #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) | |
| 377 | ||
| 378 | /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ | |
| 379 | #define CNL_DSP_IPC_BASE 0xc0 | |
| 380 | #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) | |
| 381 | #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) | |
| 382 | #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) | |
| 383 | #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) | |
| 384 | #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) | |
| 0267de58 | 385 | #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18) |
| dd96daca LG |
386 | #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) |
| 387 | ||
| 388 | /* HIPCI */ | |
| 389 | #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) | |
| 390 | #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF | |
| 391 | ||
| 392 | /* HIPCIE */ | |
| 393 | #define CNL_DSP_REG_HIPCIDA_DONE BIT(31) | |
| 394 | #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF | |
| 395 | ||
| 396 | /* HIPCCTL */ | |
| 397 | #define CNL_DSP_REG_HIPCCTL_DONE BIT(1) | |
| 398 | #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) | |
| 399 | ||
| 400 | /* HIPCT */ | |
| 401 | #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) | |
| 402 | #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF | |
| 403 | ||
| 404 | /* HIPCTDA */ | |
| 405 | #define CNL_DSP_REG_HIPCTDA_DONE BIT(31) | |
| 406 | #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF | |
| 407 | ||
| 408 | /* HIPCTDD */ | |
| 409 | #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF | |
| 410 | ||
| 411 | /* BDL */ | |
| 412 | #define HDA_DSP_BDL_SIZE 4096 | |
| 413 | #define HDA_DSP_MAX_BDL_ENTRIES \ | |
| 414 | (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) | |
| 415 | ||
| 416 | /* Number of DAIs */ | |
| 417 | #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) | |
| a6947c9d | 418 | #define SOF_SKL_NUM_DAIS 15 |
| dd96daca LG |
419 | #else |
| 420 | #define SOF_SKL_NUM_DAIS 8 | |
| 421 | #endif | |
| 422 | ||
| 423 | /* Intel HD Audio SRAM Window 0*/ | |
| e2379d4a | 424 | #define HDA_DSP_SRAM_REG_ROM_STATUS_SKL 0x8000 |
| dd96daca LG |
425 | #define HDA_ADSP_SRAM0_BASE_SKL 0x8000 |
| 426 | ||
| 427 | /* Firmware status window */ | |
| 428 | #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL | |
| 429 | #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) | |
| 430 | ||
| df7e0de5 ZY |
431 | /* Host Device Memory Space */ |
| 432 | #define APL_SSP_BASE_OFFSET 0x2000 | |
| 433 | #define CNL_SSP_BASE_OFFSET 0x10000 | |
| 434 | ||
| 435 | /* Host Device Memory Size of a Single SSP */ | |
| 436 | #define SSP_DEV_MEM_SIZE 0x1000 | |
| 437 | ||
| b095fe47 ZY |
438 | /* SSP Count of the Platform */ |
| 439 | #define APL_SSP_COUNT 6 | |
| 440 | #define CNL_SSP_COUNT 3 | |
| ec836daa | 441 | #define ICL_SSP_COUNT 6 |
| 9ccbc2e1 PLB |
442 | #define TGL_SSP_COUNT 3 |
| 443 | #define MTL_SSP_COUNT 3 | |
| b095fe47 | 444 | |
| 74ed4097 ZY |
445 | /* SSP Registers */ |
| 446 | #define SSP_SSC1_OFFSET 0x4 | |
| bd586a02 PLB |
447 | #define SSP_SET_SCLK_CONSUMER BIT(25) |
| 448 | #define SSP_SET_SFRM_CONSUMER BIT(24) | |
| 449 | #define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER) | |
| 74ed4097 | 450 | |
| c99fafdf KV |
451 | #define HDA_IDISP_ADDR 2 |
| 452 | #define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR)) | |
| dd96daca LG |
453 | |
| 454 | struct sof_intel_dsp_bdl { | |
| 455 | __le32 addr_l; | |
| 456 | __le32 addr_h; | |
| 457 | __le32 size; | |
| 458 | __le32 ioc; | |
| 459 | } __attribute((packed)); | |
| 460 | ||
| 461 | #define SOF_HDA_PLAYBACK_STREAMS 16 | |
| 462 | #define SOF_HDA_CAPTURE_STREAMS 16 | |
| 463 | #define SOF_HDA_PLAYBACK 0 | |
| 464 | #define SOF_HDA_CAPTURE 1 | |
| 465 | ||
| 89a400bd RS |
466 | /* stream flags */ |
| 467 | #define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1 | |
| 468 | ||
| 63e51fd3 RS |
469 | /* |
| 470 | * Time in ms for opportunistic D0I3 entry delay. | |
| 471 | * This has been deliberately chosen to be long to avoid race conditions. | |
| 472 | * Could be optimized in future. | |
| 473 | */ | |
| 474 | #define SOF_HDA_D0I3_WORK_DELAY_MS 5000 | |
| 475 | ||
| 61e285ca RS |
476 | /* HDA DSP D0 substate */ |
| 477 | enum sof_hda_D0_substate { | |
| 478 | SOF_HDA_DSP_PM_D0I0, /* default D0 substate */ | |
| 479 | SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */ | |
| 480 | }; | |
| 481 | ||
| dd96daca LG |
482 | /* represents DSP HDA controller frontend - i.e. host facing control */ |
| 483 | struct sof_intel_hda_dev { | |
| 2a68ff84 | 484 | bool imrboot_supported; |
| 57724db1 | 485 | bool skip_imr_boot; |
| 5d5d915b | 486 | bool booted_from_imr; |
| 2a68ff84 | 487 | |
| 776100a4 | 488 | int boot_iteration; |
| dd96daca LG |
489 | |
| 490 | struct hda_bus hbus; | |
| 491 | ||
| 492 | /* hw config */ | |
| 493 | const struct sof_intel_dsp_desc *desc; | |
| 494 | ||
| 495 | /* trace */ | |
| 496 | struct hdac_ext_stream *dtrace_stream; | |
| 497 | ||
| 498 | /* if position update IPC needed */ | |
| 499 | u32 no_ipc_position; | |
| 500 | ||
| e8e55dbe KJ |
501 | /* the maximum number of streams (playback + capture) supported */ |
| 502 | u32 stream_max; | |
| 503 | ||
| 16299326 | 504 | /* PM related */ |
| ae9db908 | 505 | bool l1_disabled;/* is DMI link L1 disabled? */ |
| 16299326 | 506 | |
| dd96daca LG |
507 | /* DMIC device */ |
| 508 | struct platform_device *dmic_dev; | |
| 63e51fd3 RS |
509 | |
| 510 | /* delayed work to enter D0I3 opportunistically */ | |
| 511 | struct delayed_work d0i3_work; | |
| 51dfed1e PLB |
512 | |
| 513 | /* ACPI information stored between scan and probe steps */ | |
| 514 | struct sdw_intel_acpi_info info; | |
| 515 | ||
| 516 | /* sdw context allocated by SoundWire driver */ | |
| 517 | struct sdw_intel_ctx *sdw; | |
| edbaaada FO |
518 | |
| 519 | /* FW clock config, 0:HPRO, 1:LPRO */ | |
| 520 | bool clk_config_lpro; | |
| 95fa7a62 | 521 | |
| c712be34 PLB |
522 | wait_queue_head_t waitq; |
| 523 | bool code_loading; | |
| 524 | ||
| 95fa7a62 PLB |
525 | /* Intel NHLT information */ |
| 526 | struct nhlt_acpi_table *nhlt; | |
| 483e4cdf PU |
527 | |
| 528 | /* | |
| 529 | * Pointing to the IPC message if immediate sending was not possible | |
| 530 | * because the downlink communication channel was BUSY at the time. | |
| 531 | * The message will be re-tried when the channel becomes free (the ACK | |
| 532 | * is received from the DSP for the previous message) | |
| 533 | */ | |
| 534 | struct snd_sof_ipc_msg *delayed_ipc_tx_msg; | |
| dd96daca LG |
535 | }; |
| 536 | ||
| 537 | static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) | |
| 538 | { | |
| 539 | struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; | |
| 540 | ||
| 541 | return &hda->hbus.core; | |
| 542 | } | |
| 543 | ||
| 544 | static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) | |
| 545 | { | |
| 546 | struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; | |
| 547 | ||
| 548 | return &hda->hbus; | |
| 549 | } | |
| 550 | ||
| 551 | struct sof_intel_hda_stream { | |
| 7623ae79 | 552 | struct snd_sof_dev *sdev; |
| 7d88b960 PLB |
553 | struct hdac_ext_stream hext_stream; |
| 554 | struct sof_intel_stream sof_intel_stream; | |
| 6b2239e3 | 555 | int host_reserved; /* reserve host DMA channel */ |
| 89a400bd | 556 | u32 flags; |
| dd96daca LG |
557 | }; |
| 558 | ||
| f5dbba9f | 559 | #define hstream_to_sof_hda_stream(hstream) \ |
| 7d88b960 | 560 | container_of(hstream, struct sof_intel_hda_stream, hext_stream) |
| f5dbba9f | 561 | |
| dd96daca LG |
562 | #define bus_to_sof_hda(bus) \ |
| 563 | container_of(bus, struct sof_intel_hda_dev, hbus.core) | |
| 564 | ||
| 565 | #define SOF_STREAM_SD_OFFSET(s) \ | |
| 566 | (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ | |
| 567 | + SOF_HDA_ADSP_LOADER_BASE) | |
| 568 | ||
| 2b1acedc RS |
569 | #define SOF_STREAM_SD_OFFSET_CRST 0x1 |
| 570 | ||
| dd96daca LG |
571 | /* |
| 572 | * DSP Core services. | |
| 573 | */ | |
| 574 | int hda_dsp_probe(struct snd_sof_dev *sdev); | |
| 575 | int hda_dsp_remove(struct snd_sof_dev *sdev); | |
| 537b4a0c | 576 | int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask); |
| dd96daca | 577 | int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); |
| dd96daca | 578 | int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); |
| dd96daca LG |
579 | int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, |
| 580 | unsigned int core_mask); | |
| c714031f | 581 | int hda_power_down_dsp(struct snd_sof_dev *sdev); |
| 9cdcbc9f | 582 | int hda_dsp_core_get(struct snd_sof_dev *sdev, int core); |
| dd96daca LG |
583 | void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); |
| 584 | void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); | |
| 556eb416 | 585 | bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask); |
| dd96daca | 586 | |
| 996b07ef RS |
587 | int hda_dsp_set_power_state_ipc3(struct snd_sof_dev *sdev, |
| 588 | const struct sof_dsp_power_state *target_state); | |
| 589 | int hda_dsp_set_power_state_ipc4(struct snd_sof_dev *sdev, | |
| 590 | const struct sof_dsp_power_state *target_state); | |
| 62f8f766 | 591 | |
| 61e285ca | 592 | int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state); |
| dd96daca | 593 | int hda_dsp_resume(struct snd_sof_dev *sdev); |
| 1c38c922 | 594 | int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); |
| dd96daca | 595 | int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); |
| 62fde977 | 596 | int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); |
| 2aa2a5ea | 597 | int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev); |
| 22aa9e02 | 598 | int hda_dsp_shutdown(struct snd_sof_dev *sdev); |
| 7077a07a | 599 | int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); |
| dd96daca | 600 | void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); |
| f3da49f0 | 601 | void hda_ipc_dump(struct snd_sof_dev *sdev); |
| f1fd9d0e | 602 | void hda_ipc_irq_dump(struct snd_sof_dev *sdev); |
| 63e51fd3 | 603 | void hda_dsp_d0i3_work(struct work_struct *work); |
| b2520dbc | 604 | int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev); |
| dd96daca LG |
605 | |
| 606 | /* | |
| 607 | * DSP PCM Operations. | |
| 608 | */ | |
| 49d7948e CR |
609 | u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate); |
| 610 | u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits); | |
| dd96daca LG |
611 | int hda_dsp_pcm_open(struct snd_sof_dev *sdev, |
| 612 | struct snd_pcm_substream *substream); | |
| 613 | int hda_dsp_pcm_close(struct snd_sof_dev *sdev, | |
| 614 | struct snd_pcm_substream *substream); | |
| 615 | int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, | |
| 616 | struct snd_pcm_substream *substream, | |
| 617 | struct snd_pcm_hw_params *params, | |
| 31f60a0c | 618 | struct snd_sof_platform_stream_params *platform_params); |
| 93146bc2 RS |
619 | int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, |
| 620 | struct snd_pcm_substream *substream); | |
| dd96daca LG |
621 | int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, |
| 622 | struct snd_pcm_substream *substream, int cmd); | |
| 623 | snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, | |
| 624 | struct snd_pcm_substream *substream); | |
| 6c26b505 | 625 | int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); |
| dd96daca LG |
626 | |
| 627 | /* | |
| 628 | * DSP Stream Operations. | |
| 629 | */ | |
| 630 | ||
| 631 | int hda_dsp_stream_init(struct snd_sof_dev *sdev); | |
| 632 | void hda_dsp_stream_free(struct snd_sof_dev *sdev); | |
| 633 | int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, | |
| 7d88b960 | 634 | struct hdac_ext_stream *hext_stream, |
| dd96daca LG |
635 | struct snd_dma_buffer *dmab, |
| 636 | struct snd_pcm_hw_params *params); | |
| 7d88b960 PLB |
637 | int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, |
| 638 | struct hdac_ext_stream *hext_stream, | |
| aca961f1 RS |
639 | struct snd_dma_buffer *dmab, |
| 640 | struct snd_pcm_hw_params *params); | |
| dd96daca | 641 | int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, |
| 7d88b960 | 642 | struct hdac_ext_stream *hext_stream, int cmd); |
| dd96daca LG |
643 | irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); |
| 644 | int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, | |
| 645 | struct snd_dma_buffer *dmab, | |
| 7d88b960 | 646 | struct hdac_stream *hstream); |
| 7c11af9f BL |
647 | bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev); |
| 648 | bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev); | |
| dd96daca | 649 | |
| a37a9224 PU |
650 | snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream, |
| 651 | int direction, bool can_sleep); | |
| 652 | ||
| dd96daca | 653 | struct hdac_ext_stream * |
| 89a400bd | 654 | hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags); |
| dd96daca LG |
655 | int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); |
| 656 | int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, | |
| 7d88b960 | 657 | struct hdac_ext_stream *hext_stream, |
| dd96daca LG |
658 | int enable, u32 size); |
| 659 | ||
| 6a0ba071 | 660 | int hda_ipc_msg_data(struct snd_sof_dev *sdev, |
| 1b905942 | 661 | struct snd_sof_pcm_stream *sps, |
| 6a0ba071 | 662 | void *p, size_t sz); |
| 29e3aa0b | 663 | int hda_set_stream_data_offset(struct snd_sof_dev *sdev, |
| 249f186d | 664 | struct snd_sof_pcm_stream *sps, |
| 29e3aa0b | 665 | size_t posn_offset); |
| dd96daca LG |
666 | |
| 667 | /* | |
| 668 | * DSP IPC Operations. | |
| 669 | */ | |
| 670 | int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, | |
| 671 | struct snd_sof_ipc_msg *msg); | |
| 672 | void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); | |
| 6eebd390 DB |
673 | int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); |
| 674 | int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); | |
| 675 | ||
| dd96daca LG |
676 | irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); |
| 677 | int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); | |
| 678 | ||
| 679 | /* | |
| 680 | * DSP Code loader. | |
| 681 | */ | |
| 682 | int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); | |
| acf705a4 | 683 | int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev); |
| b4e4c0b9 RS |
684 | int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream); |
| 685 | struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format, | |
| 686 | unsigned int size, struct snd_dma_buffer *dmab, | |
| 687 | int direction); | |
| 688 | int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, | |
| 689 | struct hdac_ext_stream *hext_stream); | |
| ab222a4a | 690 | int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot); |
| 406fed80 | 691 | #define HDA_CL_STREAM_FORMAT 0x40 |
| dd96daca LG |
692 | |
| 693 | /* pre and post fw run ops */ | |
| 694 | int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); | |
| 695 | int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); | |
| 696 | ||
| edbaaada FO |
697 | /* parse platform specific ext manifest ops */ |
| 698 | int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev, | |
| 699 | const struct sof_ext_man_elem_header *hdr); | |
| 700 | ||
| dd96daca LG |
701 | /* |
| 702 | * HDA Controller Operations. | |
| 703 | */ | |
| 704 | int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); | |
| 705 | void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); | |
| 706 | void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); | |
| 707 | int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); | |
| 708 | void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); | |
| 709 | int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); | |
| b48b77d8 | 710 | int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev); |
| 13063a2c | 711 | void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); |
| dd96daca LG |
712 | /* |
| 713 | * HDA bus operations. | |
| 714 | */ | |
| afae0942 PLB |
715 | void sof_hda_bus_init(struct snd_sof_dev *sdev, struct device *dev); |
| 716 | void sof_hda_bus_exit(struct snd_sof_dev *sdev); | |
| dd96daca | 717 | |
| dc1d964a | 718 | #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) |
| dd96daca LG |
719 | /* |
| 720 | * HDA Codec operations. | |
| 721 | */ | |
| 834c69d3 | 722 | void hda_codec_probe_bus(struct snd_sof_dev *sdev); |
| 31ba0c07 | 723 | void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable); |
| fd15f2f5 | 724 | void hda_codec_jack_check(struct snd_sof_dev *sdev); |
| 580803a7 | 725 | void hda_codec_check_for_state_change(struct snd_sof_dev *sdev); |
| ad09e446 | 726 | void hda_codec_init_cmd_io(struct snd_sof_dev *sdev); |
| 3400afcf | 727 | void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev); |
| bf2d764b | 728 | void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev); |
| 3400afcf | 729 | void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev); |
| ad09e446 PLB |
730 | void hda_codec_detect_mask(struct snd_sof_dev *sdev); |
| 731 | void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev); | |
| 87f42300 | 732 | bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev); |
| 3246a6c9 | 733 | void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status); |
| d4bfba1e | 734 | void hda_codec_device_remove(struct snd_sof_dev *sdev); |
| dd96daca | 735 | |
| dc1d964a PLB |
736 | #else |
| 737 | ||
| 738 | static inline void hda_codec_probe_bus(struct snd_sof_dev *sdev) { } | |
| 739 | static inline void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable) { } | |
| 740 | static inline void hda_codec_jack_check(struct snd_sof_dev *sdev) { } | |
| 580803a7 | 741 | static inline void hda_codec_check_for_state_change(struct snd_sof_dev *sdev) { } |
| ad09e446 | 742 | static inline void hda_codec_init_cmd_io(struct snd_sof_dev *sdev) { } |
| 3400afcf | 743 | static inline void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev) { } |
| bf2d764b | 744 | static inline void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev) { } |
| 3400afcf | 745 | static inline void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev) { } |
| ad09e446 PLB |
746 | static inline void hda_codec_detect_mask(struct snd_sof_dev *sdev) { } |
| 747 | static inline void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev) { } | |
| 87f42300 | 748 | static inline bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev) { return false; } |
| 3246a6c9 | 749 | static inline void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status) { } |
| d4bfba1e | 750 | static inline void hda_codec_device_remove(struct snd_sof_dev *sdev) { } |
| dc1d964a PLB |
751 | |
| 752 | #endif /* CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC */ | |
| dd96daca | 753 | |
| 2c6c809c | 754 | #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) && IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) |
| dd96daca | 755 | |
| 23ee0903 | 756 | void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable); |
| dd96daca LG |
757 | int hda_codec_i915_init(struct snd_sof_dev *sdev); |
| 758 | int hda_codec_i915_exit(struct snd_sof_dev *sdev); | |
| 759 | ||
| 760 | #else | |
| 761 | ||
| 834c69d3 | 762 | static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable) { } |
| dd96daca LG |
763 | static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } |
| 764 | static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } | |
| 765 | ||
| 139c7feb | 766 | #endif |
| dd96daca LG |
767 | |
| 768 | /* | |
| 769 | * Trace Control. | |
| 770 | */ | |
| 4b49cbd1 | 771 | int hda_dsp_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, |
| bab05b50 | 772 | struct sof_ipc_dma_trace_params_ext *dtrace_params); |
| dd96daca LG |
773 | int hda_dsp_trace_release(struct snd_sof_dev *sdev); |
| 774 | int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); | |
| 775 | ||
| 51dfed1e PLB |
776 | /* |
| 777 | * SoundWire support | |
| 778 | */ | |
| 779 | #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) | |
| 780 | ||
| 625339ca | 781 | int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev); |
| 51dfed1e | 782 | int hda_sdw_startup(struct snd_sof_dev *sdev); |
| 8ebc9074 | 783 | void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable); |
| 51dfed1e | 784 | void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable); |
| bbd19cdc | 785 | void hda_sdw_process_wakeen(struct snd_sof_dev *sdev); |
| 198fa4bc | 786 | bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev); |
| 51dfed1e PLB |
787 | |
| 788 | #else | |
| 789 | ||
| 625339ca PLB |
790 | static inline int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev) |
| 791 | { | |
| 792 | return 0; | |
| 793 | } | |
| 794 | ||
| 51dfed1e PLB |
795 | static inline int hda_sdw_startup(struct snd_sof_dev *sdev) |
| 796 | { | |
| 797 | return 0; | |
| 798 | } | |
| 799 | ||
| 8ebc9074 PLB |
800 | static inline void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) |
| 801 | { | |
| 802 | } | |
| 803 | ||
| 51dfed1e PLB |
804 | static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) |
| 805 | { | |
| 806 | } | |
| 807 | ||
| bbd19cdc RW |
808 | static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) |
| 809 | { | |
| 810 | } | |
| 198fa4bc BL |
811 | |
| 812 | static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) | |
| 813 | { | |
| 814 | return false; | |
| 815 | } | |
| 816 | ||
| 51dfed1e PLB |
817 | #endif |
| 818 | ||
| dd96daca LG |
819 | /* common dai driver */ |
| 820 | extern struct snd_soc_dai_driver skl_dai[]; | |
| f09e9284 | 821 | int hda_dsp_dais_suspend(struct snd_sof_dev *sdev); |
| dd96daca LG |
822 | |
| 823 | /* | |
| 824 | * Platform Specific HW abstraction Ops. | |
| 825 | */ | |
| 37e809d5 PLB |
826 | extern struct snd_sof_dsp_ops sof_hda_common_ops; |
| 827 | ||
| e2379d4a PLB |
828 | extern struct snd_sof_dsp_ops sof_skl_ops; |
| 829 | int sof_skl_ops_init(struct snd_sof_dev *sdev); | |
| 856601e5 | 830 | extern struct snd_sof_dsp_ops sof_apl_ops; |
| 37e809d5 | 831 | int sof_apl_ops_init(struct snd_sof_dev *sdev); |
| 856601e5 | 832 | extern struct snd_sof_dsp_ops sof_cnl_ops; |
| 37e809d5 | 833 | int sof_cnl_ops_init(struct snd_sof_dev *sdev); |
| 856601e5 | 834 | extern struct snd_sof_dsp_ops sof_tgl_ops; |
| 37e809d5 | 835 | int sof_tgl_ops_init(struct snd_sof_dev *sdev); |
| 856601e5 | 836 | extern struct snd_sof_dsp_ops sof_icl_ops; |
| 37e809d5 | 837 | int sof_icl_ops_init(struct snd_sof_dev *sdev); |
| 064520e8 BL |
838 | extern struct snd_sof_dsp_ops sof_mtl_ops; |
| 839 | int sof_mtl_ops_init(struct snd_sof_dev *sdev); | |
| dd96daca | 840 | |
| e2379d4a | 841 | extern const struct sof_intel_dsp_desc skl_chip_info; |
| dd96daca LG |
842 | extern const struct sof_intel_dsp_desc apl_chip_info; |
| 843 | extern const struct sof_intel_dsp_desc cnl_chip_info; | |
| 630be964 | 844 | extern const struct sof_intel_dsp_desc icl_chip_info; |
| 1205c81e | 845 | extern const struct sof_intel_dsp_desc tgl_chip_info; |
| 30ee3738 | 846 | extern const struct sof_intel_dsp_desc tglh_chip_info; |
| 61732690 | 847 | extern const struct sof_intel_dsp_desc ehl_chip_info; |
| 6fd99035 | 848 | extern const struct sof_intel_dsp_desc jsl_chip_info; |
| 6c2b6bb0 | 849 | extern const struct sof_intel_dsp_desc adls_chip_info; |
| 064520e8 | 850 | extern const struct sof_intel_dsp_desc mtl_chip_info; |
| dd96daca | 851 | |
| 3dc0d709 PU |
852 | /* Probes support */ |
| 853 | #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) | |
| 854 | int hda_probes_register(struct snd_sof_dev *sdev); | |
| 855 | void hda_probes_unregister(struct snd_sof_dev *sdev); | |
| 856 | #else | |
| 857 | static inline int hda_probes_register(struct snd_sof_dev *sdev) | |
| 858 | { | |
| 859 | return 0; | |
| 860 | } | |
| 861 | ||
| 862 | static inline void hda_probes_unregister(struct snd_sof_dev *sdev) | |
| 863 | { | |
| 864 | } | |
| 865 | #endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */ | |
| 866 | ||
| 867 | /* SOF client registration for HDA platforms */ | |
| 868 | int hda_register_clients(struct snd_sof_dev *sdev); | |
| 869 | void hda_unregister_clients(struct snd_sof_dev *sdev); | |
| 870 | ||
| 285880a2 | 871 | /* machine driver select */ |
| cb515f10 GL |
872 | struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev); |
| 873 | void hda_set_mach_params(struct snd_soc_acpi_mach *mach, | |
| 17e9d6b0 | 874 | struct snd_sof_dev *sdev); |
| 285880a2 | 875 | |
| 194fe0fc PLB |
876 | /* PCI driver selection and probe */ |
| 877 | int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id); | |
| 878 | ||
| 0acb48dd RS |
879 | struct snd_sof_dai; |
| 880 | struct sof_ipc_dai_config; | |
| 0acb48dd | 881 | |
| 288fad2f PLB |
882 | #define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */ |
| 883 | #define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS (1) /* recommended if VC0 only */ | |
| 884 | #define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE (2) /* recommended with VC0 or VC1 */ | |
| 885 | ||
| 886 | extern int sof_hda_position_quirk; | |
| 887 | ||
| 51ec71dc | 888 | void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops); |
| 1da51943 | 889 | void hda_ops_free(struct snd_sof_dev *sdev); |
| 51ec71dc | 890 | |
| c712be34 PLB |
891 | /* SKL/KBL */ |
| 892 | int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev); | |
| 556eb416 PLB |
893 | int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask); |
| 894 | ||
| e3105c0c RS |
895 | /* IPC4 */ |
| 896 | irqreturn_t cnl_ipc4_irq_thread(int irq, void *context); | |
| 897 | int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); | |
| 898 | irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context); | |
| 483e4cdf | 899 | bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev); |
| 3e6b6ed3 RW |
900 | void hda_dsp_ipc4_schedule_d0i3_work(struct sof_intel_hda_dev *hdev, |
| 901 | struct snd_sof_ipc_msg *msg); | |
| e3105c0c | 902 | int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); |
| 32b97c07 | 903 | void hda_ipc4_dump(struct snd_sof_dev *sdev); |
| 2a1be12c | 904 | extern struct sdw_intel_ops sdw_callback; |
| e3105c0c | 905 | |
| 3ab2c21e PU |
906 | struct sof_ipc4_fw_library; |
| 907 | int hda_dsp_ipc4_load_library(struct snd_sof_dev *sdev, | |
| 908 | struct sof_ipc4_fw_library *fw_lib, bool reload); | |
| 2ae49c6f RS |
909 | |
| 910 | /** | |
| 911 | * struct hda_dai_widget_dma_ops - DAI DMA ops optional by default unless specified otherwise | |
| 912 | * @get_hext_stream: Mandatory function pointer to get the saved pointer to struct hdac_ext_stream | |
| 913 | * @assign_hext_stream: Function pointer to assign a hdac_ext_stream | |
| 914 | * @release_hext_stream: Function pointer to release the hdac_ext_stream | |
| 915 | * @setup_hext_stream: Function pointer for hdac_ext_stream setup | |
| 916 | * @reset_hext_stream: Function pointer for hdac_ext_stream reset | |
| 917 | * @pre_trigger: Function pointer for DAI DMA pre-trigger actions | |
| 918 | * @trigger: Function pointer for DAI DMA trigger actions | |
| 919 | * @post_trigger: Function pointer for DAI DMA post-trigger actions | |
| 920 | */ | |
| 921 | struct hda_dai_widget_dma_ops { | |
| 922 | struct hdac_ext_stream *(*get_hext_stream)(struct snd_sof_dev *sdev, | |
| 923 | struct snd_soc_dai *cpu_dai, | |
| 924 | struct snd_pcm_substream *substream); | |
| 925 | struct hdac_ext_stream *(*assign_hext_stream)(struct snd_sof_dev *sdev, | |
| 926 | struct snd_soc_dai *cpu_dai, | |
| 927 | struct snd_pcm_substream *substream); | |
| 928 | void (*release_hext_stream)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, | |
| 929 | struct snd_pcm_substream *substream); | |
| 930 | void (*setup_hext_stream)(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream, | |
| 931 | unsigned int format_val); | |
| 932 | void (*reset_hext_stream)(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_sream); | |
| 933 | int (*pre_trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, | |
| 934 | struct snd_pcm_substream *substream, int cmd); | |
| 935 | int (*trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, | |
| 936 | struct snd_pcm_substream *substream, int cmd); | |
| 937 | int (*post_trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, | |
| 938 | struct snd_pcm_substream *substream, int cmd); | |
| 939 | }; | |
| 80afde34 RS |
940 | |
| 941 | const struct hda_dai_widget_dma_ops * | |
| 942 | hda_select_dai_widget_ops(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget); | |
| 2b009fa0 RS |
943 | int hda_dai_config(struct snd_soc_dapm_widget *w, unsigned int flags, |
| 944 | struct snd_sof_dai_config_data *data); | |
| 80afde34 | 945 | |
| dd96daca | 946 | #endif |