[linux-2.6-block.git] / sound / soc / sof / intel / hda.c

// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license.  When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
//	    Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
//	    Rander Wang <rander.wang@intel.com>
//          Keyon Jie <yang.jie@linux.intel.com>
//

/*
 * Hardware interface for generic Intel audio DSP HDA IP
 */

#include <sound/hdaudio_ext.h>
#include <sound/hda_register.h>

#include <linux/module.h>
#include <sound/sof.h>
#include <sound/sof/xtensa.h>
#include "../ops.h"
#include "hda.h"
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
#include "../../codecs/hdac_hda.h"
#endif

#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
#include <sound/soc-acpi-intel-match.h>
#endif

/* platform specific devices */
#include "shim.h"

#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
#define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)

/*
 * Debug
 */

struct hda_dsp_msg_code {
	u32 code;
	const char *msg;
};

static const struct hda_dsp_msg_code hda_dsp_rom_msg[] = {
	{HDA_DSP_ROM_FW_MANIFEST_LOADED, "status: manifest loaded"},
	{HDA_DSP_ROM_FW_FW_LOADED, "status: fw loaded"},
	{HDA_DSP_ROM_FW_ENTERED, "status: fw entered"},
	{HDA_DSP_ROM_CSE_ERROR, "error: cse error"},
	{HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"},
	{HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"},
	{HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"},
	{HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"},
	{HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"},
	{HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"},
	{HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"},
	{HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"},
	{HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"},
	{HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"},
	{HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"},
	{HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"},
	{HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"},
	{HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"},
	{HDA_DSP_ROM_NULL_FW_ENTRY,	"error: null FW entry point"},
};

static void hda_dsp_get_status_skl(struct snd_sof_dev *sdev)
{
	u32 status;
	int i;

	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
				  HDA_ADSP_FW_STATUS_SKL);

	for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
		if (status == hda_dsp_rom_msg[i].code) {
			dev_err(sdev->dev, "%s - code %8.8x\n",
				hda_dsp_rom_msg[i].msg, status);
			return;
		}
	}

	/* not for us, must be generic sof message */
	dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
}

static void hda_dsp_get_status(struct snd_sof_dev *sdev)
{
	u32 status;
	int i;

	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
				  HDA_DSP_SRAM_REG_ROM_STATUS);

	for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
		if (status == hda_dsp_rom_msg[i].code) {
			dev_err(sdev->dev, "%s - code %8.8x\n",
				hda_dsp_rom_msg[i].msg, status);
			return;
		}
	}

	/* not for us, must be generic sof message */
	dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
}

static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
				  struct sof_ipc_dsp_oops_xtensa *xoops,
				  struct sof_ipc_panic_info *panic_info,
				  u32 *stack, size_t stack_words)
{
	u32 offset = sdev->dsp_oops_offset;

	/* first read registers */
	sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));

	/* note: variable AR register array is not read */

	/* then get panic info */
	offset += xoops->arch_hdr.totalsize;
	sof_block_read(sdev, sdev->mmio_bar, offset,
		       panic_info, sizeof(*panic_info));

	/* then get the stack */
	offset += sizeof(*panic_info);
	sof_block_read(sdev, sdev->mmio_bar, offset, stack,
		       stack_words * sizeof(u32));
}

void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags)
{
	struct sof_ipc_dsp_oops_xtensa xoops;
	struct sof_ipc_panic_info panic_info;
	u32 stack[HDA_DSP_STACK_DUMP_SIZE];
	u32 status, panic;

	/* try APL specific status message types first */
	hda_dsp_get_status_skl(sdev);

	/* now try generic SOF status messages */
	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
				  HDA_ADSP_ERROR_CODE_SKL);

	/*TODO: Check: there is no define in spec, but it is used in the code*/
	panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
				 HDA_ADSP_ERROR_CODE_SKL + 0x4);

	if (sdev->boot_complete) {
		hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
				      HDA_DSP_STACK_DUMP_SIZE);
		snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
				   stack, HDA_DSP_STACK_DUMP_SIZE);
	} else {
		dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
			status, panic);
		hda_dsp_get_status_skl(sdev);
	}
}

void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
{
	struct sof_ipc_dsp_oops_xtensa xoops;
	struct sof_ipc_panic_info panic_info;
	u32 stack[HDA_DSP_STACK_DUMP_SIZE];
	u32 status, panic;

	/* try APL specific status message types first */
	hda_dsp_get_status(sdev);

	/* now try generic SOF status messages */
	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
				  HDA_DSP_SRAM_REG_FW_STATUS);
	panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP);

	if (sdev->boot_complete) {
		hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
				      HDA_DSP_STACK_DUMP_SIZE);
		snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
				   stack, HDA_DSP_STACK_DUMP_SIZE);
	} else {
		dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
			status, panic);
		hda_dsp_get_status(sdev);
	}
}

void hda_ipc_irq_dump(struct snd_sof_dev *sdev)
{
	struct hdac_bus *bus = sof_to_bus(sdev);
	u32 adspis;
	u32 intsts;
	u32 intctl;
	u32 ppsts;
	u8 rirbsts;

	/* read key IRQ stats and config registers */
	adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
	intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
	intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL);
	ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS);
	rirbsts = snd_hdac_chip_readb(bus, RIRBSTS);

	dev_err(sdev->dev,
		"error: hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n",
		intsts, intctl, rirbsts);
	dev_err(sdev->dev,
		"error: dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n",
		ppsts, adspis);
}

void hda_ipc_dump(struct snd_sof_dev *sdev)
{
	u32 hipcie;
	u32 hipct;
	u32 hipcctl;

	hda_ipc_irq_dump(sdev);

	/* read IPC status */
	hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
	hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
	hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);

	/* dump the IPC regs */
	/* TODO: parse the raw msg */
	dev_err(sdev->dev,
		"error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
		hipcie, hipct, hipcctl);
}

static int hda_init(struct snd_sof_dev *sdev)
{
	struct hda_bus *hbus;
	struct hdac_bus *bus;
	struct pci_dev *pci = to_pci_dev(sdev->dev);
	int ret;

	hbus = sof_to_hbus(sdev);
	bus = sof_to_bus(sdev);

	/* HDA bus init */
	sof_hda_bus_init(bus, &pci->dev);

	/* Workaround for a communication error on CFL (bko#199007) and CNL */
	if (IS_CFL(pci) || IS_CNL(pci))
		bus->polling_mode = 1;

	bus->use_posbuf = 1;
	bus->bdl_pos_adj = 0;

	mutex_init(&hbus->prepare_mutex);
	hbus->pci = pci;
	hbus->mixer_assigned = -1;
	hbus->modelname = "sofbus";

	/* initialise hdac bus */
	bus->addr = pci_resource_start(pci, 0);
#if IS_ENABLED(CONFIG_PCI)
	bus->remap_addr = pci_ioremap_bar(pci, 0);
#endif
	if (!bus->remap_addr) {
		dev_err(bus->dev, "error: ioremap error\n");
		return -ENXIO;
	}

	/* HDA base */
	sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr;

	/* get controller capabilities */
	ret = hda_dsp_ctrl_get_caps(sdev);
	if (ret < 0)
		dev_err(sdev->dev, "error: get caps error\n");

	return ret;
}

#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)

static const char *fixup_tplg_name(struct snd_sof_dev *sdev,
				   const char *sof_tplg_filename)
{
	const char *tplg_filename = NULL;
	char *filename;
	char *split_ext;

	filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL);
	if (!filename)
		return NULL;

	/* this assumes a .tplg extension */
	split_ext = strsep(&filename, ".");
	if (split_ext) {
		tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
					       "%s-idisp.tplg", split_ext);
		if (!tplg_filename)
			return NULL;
	}
	return tplg_filename;
}

#endif

static int hda_init_caps(struct snd_sof_dev *sdev)
{
	struct hdac_bus *bus = sof_to_bus(sdev);
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	struct hdac_ext_link *hlink;
	struct snd_soc_acpi_mach_params *mach_params;
	struct snd_soc_acpi_mach *hda_mach;
	struct snd_sof_pdata *pdata = sdev->pdata;
	struct snd_soc_acpi_mach *mach;
	const char *tplg_filename;
	int codec_num = 0;
	int i;
#endif
	int ret = 0;

	device_disable_async_suspend(bus->dev);

	/* check if dsp is there */
	if (bus->ppcap)
		dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n");

	ret = hda_dsp_ctrl_init_chip(sdev, true);
	if (ret < 0) {
		dev_err(bus->dev, "error: init chip failed with ret: %d\n",
			ret);
		return ret;
	}

#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	if (bus->mlcap)
		snd_hdac_ext_bus_get_ml_capabilities(bus);

	/* init i915 and HDMI codecs */
	ret = hda_codec_i915_init(sdev);
	if (ret < 0) {
		dev_err(sdev->dev, "error: no HDMI audio devices found\n");
		return ret;
	}

	/* codec detection */
	if (!bus->codec_mask) {
		dev_info(bus->dev, "no hda codecs found!\n");
	} else {
		dev_info(bus->dev, "hda codecs found, mask %lx\n",
			 bus->codec_mask);

		for (i = 0; i < HDA_MAX_CODECS; i++) {
			if (bus->codec_mask & (1 << i))
				codec_num++;
		}

		/*
		 * If no machine driver is found, then:
		 *
		 * hda machine driver is used if :
		 * 1. there is one HDMI codec and one external HDAudio codec
		 * 2. only HDMI codec
		 */
		if (!pdata->machine && codec_num <= 2 &&
		    HDA_IDISP_CODEC(bus->codec_mask)) {
			hda_mach = snd_soc_acpi_intel_hda_machines;
			pdata->machine = hda_mach;

			/* topology: use the info from hda_machines */
			pdata->tplg_filename =
				hda_mach->sof_tplg_filename;

			/* firmware: pick the first in machine list */
			mach = pdata->desc->machines;
			pdata->fw_filename = mach->sof_fw_filename;

			dev_info(bus->dev, "using HDA machine driver %s now\n",
				 hda_mach->drv_name);

			/* fixup topology file for HDMI only platforms */
			if (codec_num == 1) {
				/* use local variable for readability */
				tplg_filename = pdata->tplg_filename;
				tplg_filename = fixup_tplg_name(sdev, tplg_filename);
				if (!tplg_filename) {
					hda_codec_i915_exit(sdev);
					return ret;
				}
				pdata->tplg_filename = tplg_filename;
			}
		}
	}

	/* used by hda machine driver to create dai links */
	if (pdata->machine) {
		mach_params = (struct snd_soc_acpi_mach_params *)
			&pdata->machine->mach_params;
		mach_params->codec_mask = bus->codec_mask;
		mach_params->platform = dev_name(sdev->dev);
	}

	/* create codec instances */
	hda_codec_probe_bus(sdev);

	hda_codec_i915_put(sdev);

	/*
	 * we are done probing so decrement link counts
	 */
	list_for_each_entry(hlink, &bus->hlink_list, list)
		snd_hdac_ext_bus_link_put(bus, hlink);
#endif
	return 0;
}

static const struct sof_intel_dsp_desc
	*get_chip_info(struct snd_sof_pdata *pdata)
{
	const struct sof_dev_desc *desc = pdata->desc;
	const struct sof_intel_dsp_desc *chip_info;

	chip_info = desc->chip_info;

	return chip_info;
}

int hda_dsp_probe(struct snd_sof_dev *sdev)
{
	struct pci_dev *pci = to_pci_dev(sdev->dev);
	struct sof_intel_hda_dev *hdev;
	struct hdac_bus *bus;
	const struct sof_intel_dsp_desc *chip;
	int ret = 0;

	/*
	 * detect DSP by checking class/subclass/prog-id information
	 * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required
	 * class=04 subclass 01 prog-if 00: DSP is present
	 *   (and may be required e.g. for DMIC or SSP support)
	 * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works
	 */
	if (pci->class == 0x040300) {
		dev_err(sdev->dev, "error: the DSP is not enabled on this platform, aborting probe\n");
		return -ENODEV;
	} else if (pci->class != 0x040100 && pci->class != 0x040380) {
		dev_err(sdev->dev, "error: unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", pci->class);
		return -ENODEV;
	}
	dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", pci->class);

	chip = get_chip_info(sdev->pdata);
	if (!chip) {
		dev_err(sdev->dev, "error: no such device supported, chip id:%x\n",
			pci->device);
		ret = -EIO;
		goto err;
	}

	hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL);
	if (!hdev)
		return -ENOMEM;
	sdev->pdata->hw_pdata = hdev;
	hdev->desc = chip;

	hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",
						       PLATFORM_DEVID_NONE,
						       NULL, 0);
	if (IS_ERR(hdev->dmic_dev)) {
		dev_err(sdev->dev, "error: failed to create DMIC device\n");
		return PTR_ERR(hdev->dmic_dev);
	}

	/*
	 * use position update IPC if either it is forced
	 * or we don't have other choice
	 */
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION)
	hdev->no_ipc_position = 0;
#else
	hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0;
#endif

	/* set up HDA base */
	bus = sof_to_bus(sdev);
	ret = hda_init(sdev);
	if (ret < 0)
		goto hdac_bus_unmap;

	/* DSP base */
#if IS_ENABLED(CONFIG_PCI)
	sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR);
#endif
	if (!sdev->bar[HDA_DSP_BAR]) {
		dev_err(sdev->dev, "error: ioremap error\n");
		ret = -ENXIO;
		goto hdac_bus_unmap;
	}

	sdev->mmio_bar = HDA_DSP_BAR;
	sdev->mailbox_bar = HDA_DSP_BAR;

	/* allow 64bit DMA address if supported by H/W */
	if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(64))) {
		dev_dbg(sdev->dev, "DMA mask is 64 bit\n");
		dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(64));
	} else {
		dev_dbg(sdev->dev, "DMA mask is 32 bit\n");
		dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
		dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
	}

	/* init streams */
	ret = hda_dsp_stream_init(sdev);
	if (ret < 0) {
		dev_err(sdev->dev, "error: failed to init streams\n");
		/*
		 * not all errors are due to memory issues, but trying
		 * to free everything does not harm
		 */
		goto free_streams;
	}

	/*
	 * register our IRQ
	 * let's try to enable msi firstly
	 * if it fails, use legacy interrupt mode
	 * TODO: support interrupt mode selection with kernel parameter
	 *       support msi multiple vectors
	 */
	ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI);
	if (ret < 0) {
		dev_info(sdev->dev, "use legacy interrupt mode\n");
		/*
		 * in IO-APIC mode, hda->irq and ipc_irq are using the same
		 * irq number of pci->irq
		 */
		hdev->irq = pci->irq;
		sdev->ipc_irq = pci->irq;
		sdev->msi_enabled = 0;
	} else {
		dev_info(sdev->dev, "use msi interrupt mode\n");
		hdev->irq = pci_irq_vector(pci, 0);
		/* ipc irq number is the same of hda irq */
		sdev->ipc_irq = hdev->irq;
		sdev->msi_enabled = 1;
	}

	dev_dbg(sdev->dev, "using HDA IRQ %d\n", hdev->irq);
	ret = request_threaded_irq(hdev->irq, hda_dsp_stream_interrupt,
				   hda_dsp_stream_threaded_handler,
				   IRQF_SHARED, "AudioHDA", bus);
	if (ret < 0) {
		dev_err(sdev->dev, "error: failed to register HDA IRQ %d\n",
			hdev->irq);
		goto free_irq_vector;
	}

	dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq);
	ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_ipc_irq_handler,
				   sof_ops(sdev)->irq_thread, IRQF_SHARED,
				   "AudioDSP", sdev);
	if (ret < 0) {
		dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n",
			sdev->ipc_irq);
		goto free_hda_irq;
	}

	pci_set_master(pci);
	synchronize_irq(pci->irq);

	/*
	 * clear TCSEL to clear playback on some HD Audio
	 * codecs. PCI TCSEL is defined in the Intel manuals.
	 */
	snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);

	/* init HDA capabilities */
	ret = hda_init_caps(sdev);
	if (ret < 0)
		goto free_ipc_irq;

	/* enable ppcap interrupt */
	hda_dsp_ctrl_ppcap_enable(sdev, true);
	hda_dsp_ctrl_ppcap_int_enable(sdev, true);

	/* initialize waitq for code loading */
	init_waitqueue_head(&sdev->waitq);

	/* set default mailbox offset for FW ready message */
	sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET;

	return 0;

free_ipc_irq:
	free_irq(sdev->ipc_irq, sdev);
free_hda_irq:
	free_irq(hdev->irq, bus);
free_irq_vector:
	if (sdev->msi_enabled)
		pci_free_irq_vectors(pci);
free_streams:
	hda_dsp_stream_free(sdev);
/* dsp_unmap: not currently used */
	iounmap(sdev->bar[HDA_DSP_BAR]);
hdac_bus_unmap:
	iounmap(bus->remap_addr);
err:
	return ret;
}

int hda_dsp_remove(struct snd_sof_dev *sdev)
{
	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
	struct hdac_bus *bus = sof_to_bus(sdev);
	struct pci_dev *pci = to_pci_dev(sdev->dev);
	const struct sof_intel_dsp_desc *chip = hda->desc;

#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	/* codec removal, invoke bus_device_remove */
	snd_hdac_ext_bus_device_remove(bus);
#endif

	if (!IS_ERR_OR_NULL(hda->dmic_dev))
		platform_device_unregister(hda->dmic_dev);

	/* disable DSP IRQ */
	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
				SOF_HDA_PPCTL_PIE, 0);

	/* disable CIE and GIE interrupts */
	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
				SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0);

	/* disable cores */
	if (chip)
		hda_dsp_core_reset_power_down(sdev, chip->cores_mask);

	/* disable DSP */
	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
				SOF_HDA_PPCTL_GPROCEN, 0);

	free_irq(sdev->ipc_irq, sdev);
	free_irq(hda->irq, bus);
	if (sdev->msi_enabled)
		pci_free_irq_vectors(pci);

	hda_dsp_stream_free(sdev);
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	snd_hdac_link_free_all(bus);
#endif

	iounmap(sdev->bar[HDA_DSP_BAR]);
	iounmap(bus->remap_addr);

#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	snd_hdac_ext_bus_exit(bus);
#endif
	hda_codec_i915_exit(sdev);

	return 0;
}

MODULE_LICENSE("Dual BSD/GPL");
Commit	Line	Data
dd96daca LG	1	// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
	2	//
	3	// This file is provided under a dual BSD/GPLv2 license. When using or
	4	// redistributing this file, you may do so under either license.
	5	//
	6	// Copyright(c) 2018 Intel Corporation. All rights reserved.
	7	//
	8	// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
	9	// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
	10	// Rander Wang <rander.wang@intel.com>
	11	// Keyon Jie <yang.jie@linux.intel.com>
	12	//
	13
	14	/*
	15	* Hardware interface for generic Intel audio DSP HDA IP
	16	*/
	17
dd96daca	18	#include <sound/hdaudio_ext.h>
f1fd9d0e KV	19	#include <sound/hda_register.h>
f1fd9d0e KV	20
dd96daca	21	#include <linux/module.h>
dd96daca LG	22	#include <sound/sof.h>
	23	#include <sound/sof/xtensa.h>
	24	#include "../ops.h"
	25	#include "hda.h"
	26	#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
	27	#include "../../codecs/hdac_hda.h"
	28	#endif
	29
	30	#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	31	#include <sound/soc-acpi-intel-match.h>
	32	#endif
	33
	34	/* platform specific devices */
	35	#include "shim.h"
	36
64ca9d9f BL	37	#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
	38	#define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
	39
dd96daca LG	40	/*
	41	* Debug
	42	*/
	43
	44	struct hda_dsp_msg_code {
	45	u32 code;
	46	const char *msg;
	47	};
	48
	49	static const struct hda_dsp_msg_code hda_dsp_rom_msg[] = {
	50	{HDA_DSP_ROM_FW_MANIFEST_LOADED, "status: manifest loaded"},
	51	{HDA_DSP_ROM_FW_FW_LOADED, "status: fw loaded"},
	52	{HDA_DSP_ROM_FW_ENTERED, "status: fw entered"},
	53	{HDA_DSP_ROM_CSE_ERROR, "error: cse error"},
	54	{HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"},
	55	{HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"},
	56	{HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"},
	57	{HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"},
	58	{HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"},
	59	{HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"},
	60	{HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"},
	61	{HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"},
07f80454	62	{HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"},
dd96daca LG	63	{HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"},
	64	{HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"},
	65	{HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"},
	66	{HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"},
	67	{HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"},
	68	{HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"},
	69	};
	70
	71	static void hda_dsp_get_status_skl(struct snd_sof_dev *sdev)
	72	{
	73	u32 status;
	74	int i;
	75
	76	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
	77	HDA_ADSP_FW_STATUS_SKL);
	78
	79	for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
	80	if (status == hda_dsp_rom_msg[i].code) {
	81	dev_err(sdev->dev, "%s - code %8.8x\n",
	82	hda_dsp_rom_msg[i].msg, status);
	83	return;
	84	}
	85	}
	86
	87	/* not for us, must be generic sof message */
	88	dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
	89	}
	90
	91	static void hda_dsp_get_status(struct snd_sof_dev *sdev)
	92	{
	93	u32 status;
	94	int i;
	95
	96	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
	97	HDA_DSP_SRAM_REG_ROM_STATUS);
	98
	99	for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
	100	if (status == hda_dsp_rom_msg[i].code) {
	101	dev_err(sdev->dev, "%s - code %8.8x\n",
	102	hda_dsp_rom_msg[i].msg, status);
	103	return;
	104	}
	105	}
	106
	107	/* not for us, must be generic sof message */
	108	dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
	109	}
	110
	111	static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
	112	struct sof_ipc_dsp_oops_xtensa *xoops,
	113	struct sof_ipc_panic_info *panic_info,
	114	u32 *stack, size_t stack_words)
	115	{
14104eb6 KV	116	u32 offset = sdev->dsp_oops_offset;
14104eb6 KV	117
dd96daca	118	/* first read registers */
14104eb6 KV	119	sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
	120
	121	/* note: variable AR register array is not read */
dd96daca LG	122
dd96daca LG	123	/* then get panic info */
14104eb6 KV	124	offset += xoops->arch_hdr.totalsize;
	125	sof_block_read(sdev, sdev->mmio_bar, offset,
	126	panic_info, sizeof(*panic_info));
dd96daca LG	127
dd96daca LG	128	/* then get the stack */
14104eb6 KV	129	offset += sizeof(*panic_info);
14104eb6 KV	130	sof_block_read(sdev, sdev->mmio_bar, offset, stack,
dd96daca LG	131	stack_words * sizeof(u32));
	132	}
	133
	134	void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags)
	135	{
	136	struct sof_ipc_dsp_oops_xtensa xoops;
	137	struct sof_ipc_panic_info panic_info;
	138	u32 stack[HDA_DSP_STACK_DUMP_SIZE];
	139	u32 status, panic;
	140
	141	/* try APL specific status message types first */
	142	hda_dsp_get_status_skl(sdev);
	143
	144	/* now try generic SOF status messages */
	145	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
	146	HDA_ADSP_ERROR_CODE_SKL);
	147
	148	/TODO: Check: there is no define in spec, but it is used in the code/
	149	panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
	150	HDA_ADSP_ERROR_CODE_SKL + 0x4);
	151
	152	if (sdev->boot_complete) {
	153	hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
	154	HDA_DSP_STACK_DUMP_SIZE);
	155	snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
	156	stack, HDA_DSP_STACK_DUMP_SIZE);
	157	} else {
	158	dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
	159	status, panic);
	160	hda_dsp_get_status_skl(sdev);
	161	}
	162	}
	163
	164	void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
	165	{
	166	struct sof_ipc_dsp_oops_xtensa xoops;
	167	struct sof_ipc_panic_info panic_info;
	168	u32 stack[HDA_DSP_STACK_DUMP_SIZE];
	169	u32 status, panic;
	170
	171	/* try APL specific status message types first */
	172	hda_dsp_get_status(sdev);
	173
	174	/* now try generic SOF status messages */
	175	status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
	176	HDA_DSP_SRAM_REG_FW_STATUS);
	177	panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP);
	178
	179	if (sdev->boot_complete) {
	180	hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
	181	HDA_DSP_STACK_DUMP_SIZE);
	182	snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
	183	stack, HDA_DSP_STACK_DUMP_SIZE);
	184	} else {
	185	dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
	186	status, panic);
	187	hda_dsp_get_status(sdev);
	188	}
	189	}
	190
f1fd9d0e KV	191	void hda_ipc_irq_dump(struct snd_sof_dev *sdev)
	192	{
	193	struct hdac_bus *bus = sof_to_bus(sdev);
	194	u32 adspis;
	195	u32 intsts;
	196	u32 intctl;
	197	u32 ppsts;
	198	u8 rirbsts;
	199
	200	/* read key IRQ stats and config registers */
	201	adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
	202	intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
	203	intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL);
	204	ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS);
	205	rirbsts = snd_hdac_chip_readb(bus, RIRBSTS);
	206
	207	dev_err(sdev->dev,
	208	"error: hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n",
	209	intsts, intctl, rirbsts);
	210	dev_err(sdev->dev,
	211	"error: dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n",
	212	ppsts, adspis);
	213	}
	214
f3da49f0 PX	215	void hda_ipc_dump(struct snd_sof_dev *sdev)
	216	{
	217	u32 hipcie;
	218	u32 hipct;
	219	u32 hipcctl;
	220
f1fd9d0e KV	221	hda_ipc_irq_dump(sdev);
f1fd9d0e KV	222
f3da49f0 PX	223	/* read IPC status */
	224	hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
	225	hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
	226	hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
	227
	228	/* dump the IPC regs */
	229	/* TODO: parse the raw msg */
	230	dev_err(sdev->dev,
	231	"error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
	232	hipcie, hipct, hipcctl);
	233	}
	234
dd96daca LG	235	static int hda_init(struct snd_sof_dev *sdev)
	236	{
	237	struct hda_bus *hbus;
	238	struct hdac_bus *bus;
dd96daca LG	239	struct pci_dev *pci = to_pci_dev(sdev->dev);
	240	int ret;
	241
	242	hbus = sof_to_hbus(sdev);
	243	bus = sof_to_bus(sdev);
	244
	245	/* HDA bus init */
d4ff1b39	246	sof_hda_bus_init(bus, &pci->dev);
64ca9d9f BL	247
	248	/* Workaround for a communication error on CFL (bko#199007) and CNL */
	249	if (IS_CFL(pci) \|\| IS_CNL(pci))
	250	bus->polling_mode = 1;
	251
dd96daca LG	252	bus->use_posbuf = 1;
	253	bus->bdl_pos_adj = 0;
	254
	255	mutex_init(&hbus->prepare_mutex);
	256	hbus->pci = pci;
	257	hbus->mixer_assigned = -1;
	258	hbus->modelname = "sofbus";
	259
	260	/* initialise hdac bus */
	261	bus->addr = pci_resource_start(pci, 0);
ad169f9f	262	#if IS_ENABLED(CONFIG_PCI)
dd96daca	263	bus->remap_addr = pci_ioremap_bar(pci, 0);
ad169f9f	264	#endif
dd96daca LG	265	if (!bus->remap_addr) {
	266	dev_err(bus->dev, "error: ioremap error\n");
	267	return -ENXIO;
	268	}
	269
	270	/* HDA base */
	271	sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr;
	272
	273	/* get controller capabilities */
	274	ret = hda_dsp_ctrl_get_caps(sdev);
	275	if (ret < 0)
	276	dev_err(sdev->dev, "error: get caps error\n");
	277
	278	return ret;
	279	}
	280
	281	#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	282
	283	static const char fixup_tplg_name(struct snd_sof_dev sdev,
	284	const char *sof_tplg_filename)
	285	{
	286	const char *tplg_filename = NULL;
	287	char *filename;
	288	char *split_ext;
	289
	290	filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL);
	291	if (!filename)
	292	return NULL;
	293
	294	/* this assumes a .tplg extension */
	295	split_ext = strsep(&filename, ".");
	296	if (split_ext) {
	297	tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
	298	"%s-idisp.tplg", split_ext);
	299	if (!tplg_filename)
	300	return NULL;
	301	}
	302	return tplg_filename;
	303	}
	304
be1b577d ZY	305	#endif
be1b577d ZY	306
dd96daca LG	307	static int hda_init_caps(struct snd_sof_dev *sdev)
	308	{
	309	struct hdac_bus *bus = sof_to_bus(sdev);
be1b577d	310	#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
dd96daca LG	311	struct hdac_ext_link *hlink;
	312	struct snd_soc_acpi_mach_params *mach_params;
	313	struct snd_soc_acpi_mach *hda_mach;
	314	struct snd_sof_pdata *pdata = sdev->pdata;
	315	struct snd_soc_acpi_mach *mach;
	316	const char *tplg_filename;
	317	int codec_num = 0;
dd96daca	318	int i;
be1b577d ZY	319	#endif
be1b577d ZY	320	int ret = 0;
dd96daca LG	321
	322	device_disable_async_suspend(bus->dev);
	323
	324	/* check if dsp is there */
	325	if (bus->ppcap)
	326	dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n");
	327
be1b577d ZY	328	ret = hda_dsp_ctrl_init_chip(sdev, true);
	329	if (ret < 0) {
	330	dev_err(bus->dev, "error: init chip failed with ret: %d\n",
	331	ret);
	332	return ret;
	333	}
	334
	335	#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
dd96daca LG	336	if (bus->mlcap)
	337	snd_hdac_ext_bus_get_ml_capabilities(bus);
	338
	339	/* init i915 and HDMI codecs */
	340	ret = hda_codec_i915_init(sdev);
	341	if (ret < 0) {
	342	dev_err(sdev->dev, "error: no HDMI audio devices found\n");
	343	return ret;
	344	}
	345
dd96daca LG	346	/* codec detection */
	347	if (!bus->codec_mask) {
	348	dev_info(bus->dev, "no hda codecs found!\n");
	349	} else {
	350	dev_info(bus->dev, "hda codecs found, mask %lx\n",
	351	bus->codec_mask);
	352
	353	for (i = 0; i < HDA_MAX_CODECS; i++) {
	354	if (bus->codec_mask & (1 << i))
	355	codec_num++;
	356	}
	357
	358	/*
	359	* If no machine driver is found, then:
	360	*
	361	* hda machine driver is used if :
	362	* 1. there is one HDMI codec and one external HDAudio codec
	363	* 2. only HDMI codec
	364	*/
	365	if (!pdata->machine && codec_num <= 2 &&
	366	HDA_IDISP_CODEC(bus->codec_mask)) {
	367	hda_mach = snd_soc_acpi_intel_hda_machines;
	368	pdata->machine = hda_mach;
	369
	370	/* topology: use the info from hda_machines */
	371	pdata->tplg_filename =
	372	hda_mach->sof_tplg_filename;
	373
	374	/* firmware: pick the first in machine list */
	375	mach = pdata->desc->machines;
	376	pdata->fw_filename = mach->sof_fw_filename;
	377
	378	dev_info(bus->dev, "using HDA machine driver %s now\n",
	379	hda_mach->drv_name);
	380
	381	/* fixup topology file for HDMI only platforms */
	382	if (codec_num == 1) {
	383	/* use local variable for readability */
	384	tplg_filename = pdata->tplg_filename;
	385	tplg_filename = fixup_tplg_name(sdev, tplg_filename);
be1b577d ZY	386	if (!tplg_filename) {
	387	hda_codec_i915_exit(sdev);
	388	return ret;
	389	}
dd96daca LG	390	pdata->tplg_filename = tplg_filename;
	391	}
	392	}
	393	}
	394
	395	/* used by hda machine driver to create dai links */
	396	if (pdata->machine) {
	397	mach_params = (struct snd_soc_acpi_mach_params *)
	398	&pdata->machine->mach_params;
	399	mach_params->codec_mask = bus->codec_mask;
	400	mach_params->platform = dev_name(sdev->dev);
	401	}
	402
	403	/* create codec instances */
	404	hda_codec_probe_bus(sdev);
	405
	406	hda_codec_i915_put(sdev);
	407
	408	/*
	409	* we are done probing so decrement link counts
	410	*/
	411	list_for_each_entry(hlink, &bus->hlink_list, list)
	412	snd_hdac_ext_bus_link_put(bus, hlink);
be1b577d	413	#endif
dd96daca LG	414	return 0;
	415	}
	416
dd96daca LG	417	static const struct sof_intel_dsp_desc
	418	get_chip_info(struct snd_sof_pdata pdata)
	419	{
	420	const struct sof_dev_desc *desc = pdata->desc;
	421	const struct sof_intel_dsp_desc *chip_info;
	422
	423	chip_info = desc->chip_info;
	424
	425	return chip_info;
	426	}
	427
	428	int hda_dsp_probe(struct snd_sof_dev *sdev)
	429	{
	430	struct pci_dev *pci = to_pci_dev(sdev->dev);
	431	struct sof_intel_hda_dev *hdev;
	432	struct hdac_bus *bus;
dd96daca	433	const struct sof_intel_dsp_desc *chip;
be1b577d	434	int ret = 0;
dd96daca LG	435
	436	/*
	437	* detect DSP by checking class/subclass/prog-id information
	438	* class=04 subclass 03 prog-if 00: no DSP, legacy driver is required
	439	* class=04 subclass 01 prog-if 00: DSP is present
	440	* (and may be required e.g. for DMIC or SSP support)
	441	* class=04 subclass 03 prog-if 80: either of DSP or legacy mode works
	442	*/
	443	if (pci->class == 0x040300) {
	444	dev_err(sdev->dev, "error: the DSP is not enabled on this platform, aborting probe\n");
	445	return -ENODEV;
	446	} else if (pci->class != 0x040100 && pci->class != 0x040380) {
	447	dev_err(sdev->dev, "error: unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", pci->class);
	448	return -ENODEV;
	449	}
	450	dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", pci->class);
	451
	452	chip = get_chip_info(sdev->pdata);
	453	if (!chip) {
	454	dev_err(sdev->dev, "error: no such device supported, chip id:%x\n",
	455	pci->device);
	456	ret = -EIO;
	457	goto err;
	458	}
	459
	460	hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL);
	461	if (!hdev)
	462	return -ENOMEM;
	463	sdev->pdata->hw_pdata = hdev;
	464	hdev->desc = chip;
	465
	466	hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",
	467	PLATFORM_DEVID_NONE,
	468	NULL, 0);
	469	if (IS_ERR(hdev->dmic_dev)) {
	470	dev_err(sdev->dev, "error: failed to create DMIC device\n");
	471	return PTR_ERR(hdev->dmic_dev);
	472	}
	473
	474	/*
	475	* use position update IPC if either it is forced
	476	* or we don't have other choice
	477	*/
	478	#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION)
	479	hdev->no_ipc_position = 0;
	480	#else
	481	hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0;
	482	#endif
	483
	484	/* set up HDA base */
	485	bus = sof_to_bus(sdev);
	486	ret = hda_init(sdev);
	487	if (ret < 0)
	488	goto hdac_bus_unmap;
	489
	490	/* DSP base */
ad169f9f	491	#if IS_ENABLED(CONFIG_PCI)
dd96daca	492	sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR);
ad169f9f	493	#endif
dd96daca LG	494	if (!sdev->bar[HDA_DSP_BAR]) {
	495	dev_err(sdev->dev, "error: ioremap error\n");
	496	ret = -ENXIO;
	497	goto hdac_bus_unmap;
	498	}
	499
	500	sdev->mmio_bar = HDA_DSP_BAR;
	501	sdev->mailbox_bar = HDA_DSP_BAR;
	502
	503	/* allow 64bit DMA address if supported by H/W */
	504	if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(64))) {
	505	dev_dbg(sdev->dev, "DMA mask is 64 bit\n");
	506	dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(64));
	507	} else {
	508	dev_dbg(sdev->dev, "DMA mask is 32 bit\n");
	509	dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
	510	dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
	511	}
	512
	513	/* init streams */
	514	ret = hda_dsp_stream_init(sdev);
	515	if (ret < 0) {
	516	dev_err(sdev->dev, "error: failed to init streams\n");
	517	/*
	518	* not all errors are due to memory issues, but trying
	519	* to free everything does not harm
	520	*/
	521	goto free_streams;
	522	}
	523
	524	/*
	525	* register our IRQ
	526	* let's try to enable msi firstly
	527	* if it fails, use legacy interrupt mode
	528	* TODO: support interrupt mode selection with kernel parameter
	529	* support msi multiple vectors
	530	*/
	531	ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI);
	532	if (ret < 0) {
	533	dev_info(sdev->dev, "use legacy interrupt mode\n");
	534	/*
	535	* in IO-APIC mode, hda->irq and ipc_irq are using the same
	536	* irq number of pci->irq
	537	*/
	538	hdev->irq = pci->irq;
	539	sdev->ipc_irq = pci->irq;
	540	sdev->msi_enabled = 0;
	541	} else {
	542	dev_info(sdev->dev, "use msi interrupt mode\n");
	543	hdev->irq = pci_irq_vector(pci, 0);
	544	/* ipc irq number is the same of hda irq */
	545	sdev->ipc_irq = hdev->irq;
	546	sdev->msi_enabled = 1;
	547	}
	548
	549	dev_dbg(sdev->dev, "using HDA IRQ %d\n", hdev->irq);
	550	ret = request_threaded_irq(hdev->irq, hda_dsp_stream_interrupt,
	551	hda_dsp_stream_threaded_handler,
	552	IRQF_SHARED, "AudioHDA", bus);
	553	if (ret < 0) {
	554	dev_err(sdev->dev, "error: failed to register HDA IRQ %d\n",
	555	hdev->irq);
	556	goto free_irq_vector;
	557	}
558
559	dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq);
560	ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_ipc_irq_handler,
561	sof_ops(sdev)->irq_thread, IRQF_SHARED,
562	"AudioDSP", sdev);
563	if (ret < 0) {
564	dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n",
565	sdev->ipc_irq);
566	goto free_hda_irq;
567	}
568
569	pci_set_master(pci);
570	synchronize_irq(pci->irq);
571
572	/*
573	* clear TCSEL to clear playback on some HD Audio
574	* codecs. PCI TCSEL is defined in the Intel manuals.
575	*/
576	snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
577
578	/* init HDA capabilities */
579	ret = hda_init_caps(sdev);
580	if (ret < 0)
581	goto free_ipc_irq;
582
1f5253b0 ZY	583	/* enable ppcap interrupt */
	584	hda_dsp_ctrl_ppcap_enable(sdev, true);
	585	hda_dsp_ctrl_ppcap_int_enable(sdev, true);
dd96daca LG	586
	587	/* initialize waitq for code loading */
	588	init_waitqueue_head(&sdev->waitq);
	589
	590	/* set default mailbox offset for FW ready message */
	591	sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET;
	592
	593	return 0;
	594
	595	free_ipc_irq:
	596	free_irq(sdev->ipc_irq, sdev);
	597	free_hda_irq:
	598	free_irq(hdev->irq, bus);
	599	free_irq_vector:
	600	if (sdev->msi_enabled)
	601	pci_free_irq_vectors(pci);
	602	free_streams:
	603	hda_dsp_stream_free(sdev);
	604	/* dsp_unmap: not currently used */
	605	iounmap(sdev->bar[HDA_DSP_BAR]);
	606	hdac_bus_unmap:
	607	iounmap(bus->remap_addr);
	608	err:
	609	return ret;
	610	}
	611
	612	int hda_dsp_remove(struct snd_sof_dev *sdev)
	613	{
	614	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
	615	struct hdac_bus *bus = sof_to_bus(sdev);
	616	struct pci_dev *pci = to_pci_dev(sdev->dev);
	617	const struct sof_intel_dsp_desc *chip = hda->desc;
	618
	619	#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
	620	/* codec removal, invoke bus_device_remove */
	621	snd_hdac_ext_bus_device_remove(bus);
	622	#endif
	623
	624	if (!IS_ERR_OR_NULL(hda->dmic_dev))
	625	platform_device_unregister(hda->dmic_dev);
	626
	627	/* disable DSP IRQ */
	628	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
	629	SOF_HDA_PPCTL_PIE, 0);
	630
	631	/* disable CIE and GIE interrupts */
	632	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
	633	SOF_HDA_INT_CTRL_EN \| SOF_HDA_INT_GLOBAL_EN, 0);
	634
	635	/* disable cores */
	636	if (chip)
	637	hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
	638
	639	/* disable DSP */
	640	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
	641	SOF_HDA_PPCTL_GPROCEN, 0);
	642
	643	free_irq(sdev->ipc_irq, sdev);
	644	free_irq(hda->irq, bus);
	645	if (sdev->msi_enabled)
	646	pci_free_irq_vectors(pci);
	647
	648	hda_dsp_stream_free(sdev);
	649	#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
650	snd_hdac_link_free_all(bus);
651	#endif
652
653	iounmap(sdev->bar[HDA_DSP_BAR]);
654	iounmap(bus->remap_addr);
655
656	#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
657	snd_hdac_ext_bus_exit(bus);
658	#endif
659	hda_codec_i915_exit(sdev);
660
661	return 0;
662	}
663
664	MODULE_LICENSE("Dual BSD/GPL");