[linux-2.6-block.git] / sound / soc / sof / intel / cnl.c

// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license.  When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
//	    Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
//	    Rander Wang <rander.wang@intel.com>
//          Keyon Jie <yang.jie@linux.intel.com>
//

/*
 * Hardware interface for audio DSP on Cannonlake.
 */

#include "../ops.h"
#include "hda.h"

static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = {
	{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
	{"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
	{"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
};

static void cnl_ipc_host_done(struct snd_sof_dev *sdev);
static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev);

static irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
{
	struct snd_sof_dev *sdev = context;
	u32 hipci;
	u32 hipcida;
	u32 hipctdr;
	u32 hipctdd;
	u32 msg;
	u32 msg_ext;
	bool ipc_irq = false;

	hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
	hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
	hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD);
	hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR);

	/* reply message from DSP */
	if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) {
		msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK;
		msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK;

		dev_vdbg(sdev->dev,
			 "ipc: firmware response, msg:0x%x, msg_ext:0x%x\n",
			 msg, msg_ext);

		/* mask Done interrupt */
		snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
					CNL_DSP_REG_HIPCCTL,
					CNL_DSP_REG_HIPCCTL_DONE, 0);

		spin_lock_irq(&sdev->ipc_lock);

		/* handle immediate reply from DSP core */
		hda_dsp_ipc_get_reply(sdev);
		snd_sof_ipc_reply(sdev, msg);

		if (sdev->code_loading)	{
			sdev->code_loading = 0;
			wake_up(&sdev->waitq);
		}

		cnl_ipc_dsp_done(sdev);

		spin_unlock_irq(&sdev->ipc_lock);

		ipc_irq = true;
	}

	/* new message from DSP */
	if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
		msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
		msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;

		dev_vdbg(sdev->dev,
			 "ipc: firmware initiated, msg:0x%x, msg_ext:0x%x\n",
			 msg, msg_ext);

		/* handle messages from DSP */
		if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) ==
		   SOF_IPC_PANIC_MAGIC) {
			snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext));
		} else {
			snd_sof_ipc_msgs_rx(sdev);
		}

		cnl_ipc_host_done(sdev);

		ipc_irq = true;
	}

	if (!ipc_irq) {
		/*
		 * This interrupt is not shared so no need to return IRQ_NONE.
		 */
		dev_err_ratelimited(sdev->dev,
				    "error: nothing to do in IRQ thread\n");
	}

	/* re-enable IPC interrupt */
	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
				HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);

	return IRQ_HANDLED;
}

static void cnl_ipc_host_done(struct snd_sof_dev *sdev)
{
	/*
	 * clear busy interrupt to tell dsp controller this
	 * interrupt has been accepted, not trigger it again
	 */
	snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
				       CNL_DSP_REG_HIPCTDR,
				       CNL_DSP_REG_HIPCTDR_BUSY,
				       CNL_DSP_REG_HIPCTDR_BUSY);
	/*
	 * set done bit to ack dsp the msg has been
	 * processed and send reply msg to dsp
	 */
	snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
				       CNL_DSP_REG_HIPCTDA,
				       CNL_DSP_REG_HIPCTDA_DONE,
				       CNL_DSP_REG_HIPCTDA_DONE);
}

static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev)
{
	/*
	 * set DONE bit - tell DSP we have received the reply msg
	 * from DSP, and processed it, don't send more reply to host
	 */
	snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
				       CNL_DSP_REG_HIPCIDA,
				       CNL_DSP_REG_HIPCIDA_DONE,
				       CNL_DSP_REG_HIPCIDA_DONE);

	/* unmask Done interrupt */
	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
				CNL_DSP_REG_HIPCCTL,
				CNL_DSP_REG_HIPCCTL_DONE,
				CNL_DSP_REG_HIPCCTL_DONE);
}

static int cnl_ipc_send_msg(struct snd_sof_dev *sdev,
			    struct snd_sof_ipc_msg *msg)
{
	/* send the message */
	sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
			  msg->msg_size);
	snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
			  CNL_DSP_REG_HIPCIDR_BUSY);

	return 0;
}

static void cnl_ipc_dump(struct snd_sof_dev *sdev)
{
	u32 hipcctl;
	u32 hipcida;
	u32 hipctdr;

	hda_ipc_irq_dump(sdev);

	/* read IPC status */
	hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
	hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
	hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);

	/* dump the IPC regs */
	/* TODO: parse the raw msg */
	dev_err(sdev->dev,
		"error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
		hipcida, hipctdr, hipcctl);
}

/* cannonlake ops */
const struct snd_sof_dsp_ops sof_cnl_ops = {
	/* probe and remove */
	.probe		= hda_dsp_probe,
	.remove		= hda_dsp_remove,

	/* Register IO */
	.write		= sof_io_write,
	.read		= sof_io_read,
	.write64	= sof_io_write64,
	.read64		= sof_io_read64,

	/* Block IO */
	.block_read	= sof_block_read,
	.block_write	= sof_block_write,

	/* doorbell */
	.irq_handler	= hda_dsp_ipc_irq_handler,
	.irq_thread	= cnl_ipc_irq_thread,

	/* ipc */
	.send_msg	= cnl_ipc_send_msg,
	.fw_ready	= hda_dsp_ipc_fw_ready,

	.ipc_msg_data	= hda_ipc_msg_data,
	.ipc_pcm_params	= hda_ipc_pcm_params,

	/* debug */
	.debug_map	= cnl_dsp_debugfs,
	.debug_map_count	= ARRAY_SIZE(cnl_dsp_debugfs),
	.dbg_dump	= hda_dsp_dump,
	.ipc_dump	= cnl_ipc_dump,

	/* stream callbacks */
	.pcm_open	= hda_dsp_pcm_open,
	.pcm_close	= hda_dsp_pcm_close,
	.pcm_hw_params	= hda_dsp_pcm_hw_params,
	.pcm_hw_free	= hda_dsp_stream_hw_free,
	.pcm_trigger	= hda_dsp_pcm_trigger,
	.pcm_pointer	= hda_dsp_pcm_pointer,

	/* firmware loading */
	.load_firmware = snd_sof_load_firmware_raw,

	/* pre/post fw run */
	.pre_fw_run = hda_dsp_pre_fw_run,
	.post_fw_run = hda_dsp_post_fw_run,

	/* dsp core power up/down */
	.core_power_up = hda_dsp_enable_core,
	.core_power_down = hda_dsp_core_reset_power_down,

	/* firmware run */
	.run = hda_dsp_cl_boot_firmware,

	/* trace callback */
	.trace_init = hda_dsp_trace_init,
	.trace_release = hda_dsp_trace_release,
	.trace_trigger = hda_dsp_trace_trigger,

	/* DAI drivers */
	.drv		= skl_dai,
	.num_drv	= SOF_SKL_NUM_DAIS,

	/* PM */
	.suspend		= hda_dsp_suspend,
	.resume			= hda_dsp_resume,
	.runtime_suspend	= hda_dsp_runtime_suspend,
	.runtime_resume		= hda_dsp_runtime_resume,
	.runtime_idle		= hda_dsp_runtime_idle,
	.set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
};
EXPORT_SYMBOL(sof_cnl_ops);

const struct sof_intel_dsp_desc cnl_chip_info = {
	/* Cannonlake */
	.cores_num = 4,
	.init_core_mask = 1,
	.cores_mask = HDA_DSP_CORE_MASK(0) |
				HDA_DSP_CORE_MASK(1) |
				HDA_DSP_CORE_MASK(2) |
				HDA_DSP_CORE_MASK(3),
	.ipc_req = CNL_DSP_REG_HIPCIDR,
	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	.rom_init_timeout	= 300,
	.ssp_count = CNL_SSP_COUNT,
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
};
EXPORT_SYMBOL(cnl_chip_info);

const struct sof_intel_dsp_desc icl_chip_info = {
	/* Icelake */
	.cores_num = 4,
	.init_core_mask = 1,
	.cores_mask = HDA_DSP_CORE_MASK(0) |
				HDA_DSP_CORE_MASK(1) |
				HDA_DSP_CORE_MASK(2) |
				HDA_DSP_CORE_MASK(3),
	.ipc_req = CNL_DSP_REG_HIPCIDR,
	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	.rom_init_timeout	= 300,
	.ssp_count = ICL_SSP_COUNT,
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
};
EXPORT_SYMBOL(icl_chip_info);
Commit	Line	Data
27302052 LG	1	// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
	2	//
	3	// This file is provided under a dual BSD/GPLv2 license. When using or
	4	// redistributing this file, you may do so under either license.
	5	//
	6	// Copyright(c) 2018 Intel Corporation. All rights reserved.
	7	//
	8	// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
	9	// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
	10	// Rander Wang <rander.wang@intel.com>
	11	// Keyon Jie <yang.jie@linux.intel.com>
	12	//
	13
	14	/*
	15	* Hardware interface for audio DSP on Cannonlake.
	16	*/
	17
	18	#include "../ops.h"
	19	#include "hda.h"
	20
	21	static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = {
	22	{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
	23	{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
	24	{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
	25	};
	26
	27	static void cnl_ipc_host_done(struct snd_sof_dev *sdev);
	28	static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev);
	29
	30	static irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
	31	{
	32	struct snd_sof_dev *sdev = context;
	33	u32 hipci;
27302052 LG	34	u32 hipcida;
	35	u32 hipctdr;
	36	u32 hipctdd;
	37	u32 msg;
	38	u32 msg_ext;
3f58521b	39	bool ipc_irq = false;
27302052	40
27302052	41	hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
27302052	42	hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
c24b1b72 PLB	43	hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD);
c24b1b72 PLB	44	hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR);
27302052	45
27302052	46	/* reply message from DSP */
09a173a6	47	if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) {
27302052 LG	48	msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK;
	49	msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK;
	50
	51	dev_vdbg(sdev->dev,
	52	"ipc: firmware response, msg:0x%x, msg_ext:0x%x\n",
	53	msg, msg_ext);
	54
	55	/* mask Done interrupt */
	56	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
	57	CNL_DSP_REG_HIPCCTL,
	58	CNL_DSP_REG_HIPCCTL_DONE, 0);
	59
1183e9a6 GL	60	spin_lock_irq(&sdev->ipc_lock);
1183e9a6 GL	61
27302052 LG	62	/* handle immediate reply from DSP core */
	63	hda_dsp_ipc_get_reply(sdev);
	64	snd_sof_ipc_reply(sdev, msg);
	65
	66	if (sdev->code_loading) {
	67	sdev->code_loading = 0;
	68	wake_up(&sdev->waitq);
	69	}
	70
	71	cnl_ipc_dsp_done(sdev);
	72
1183e9a6 GL	73	spin_unlock_irq(&sdev->ipc_lock);
1183e9a6 GL	74
3f58521b	75	ipc_irq = true;
27302052 LG	76	}
	77
	78	/* new message from DSP */
	79	if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
27302052 LG	80	msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
	81	msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;
	82
	83	dev_vdbg(sdev->dev,
	84	"ipc: firmware initiated, msg:0x%x, msg_ext:0x%x\n",
	85	msg, msg_ext);
	86
	87	/* handle messages from DSP */
	88	if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) ==
	89	SOF_IPC_PANIC_MAGIC) {
	90	snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext));
	91	} else {
	92	snd_sof_ipc_msgs_rx(sdev);
	93	}
	94
27302052 LG	95	cnl_ipc_host_done(sdev);
27302052 LG	96
3f58521b PLB	97	ipc_irq = true;
	98	}
	99
	100	if (!ipc_irq) {
	101	/*
	102	* This interrupt is not shared so no need to return IRQ_NONE.
	103	*/
	104	dev_err_ratelimited(sdev->dev,
	105	"error: nothing to do in IRQ thread\n");
27302052 LG	106	}
27302052 LG	107
3f58521b PLB	108	/* re-enable IPC interrupt */
	109	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
	110	HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
	111
	112	return IRQ_HANDLED;
27302052 LG	113	}
	114
	115	static void cnl_ipc_host_done(struct snd_sof_dev *sdev)
	116	{
ddbe9223 PLB	117	/*
	118	* clear busy interrupt to tell dsp controller this
	119	* interrupt has been accepted, not trigger it again
	120	*/
	121	snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
	122	CNL_DSP_REG_HIPCTDR,
	123	CNL_DSP_REG_HIPCTDR_BUSY,
	124	CNL_DSP_REG_HIPCTDR_BUSY);
27302052 LG	125	/*
	126	* set done bit to ack dsp the msg has been
	127	* processed and send reply msg to dsp
	128	*/
	129	snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
	130	CNL_DSP_REG_HIPCTDA,
	131	CNL_DSP_REG_HIPCTDA_DONE,
	132	CNL_DSP_REG_HIPCTDA_DONE);
	133	}
	134
	135	static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev)
	136	{
	137	/*
	138	* set DONE bit - tell DSP we have received the reply msg
	139	* from DSP, and processed it, don't send more reply to host
	140	*/
	141	snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
	142	CNL_DSP_REG_HIPCIDA,
	143	CNL_DSP_REG_HIPCIDA_DONE,
	144	CNL_DSP_REG_HIPCIDA_DONE);
	145
	146	/* unmask Done interrupt */
	147	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
	148	CNL_DSP_REG_HIPCCTL,
	149	CNL_DSP_REG_HIPCCTL_DONE,
	150	CNL_DSP_REG_HIPCCTL_DONE);
	151	}
	152
	153	static int cnl_ipc_send_msg(struct snd_sof_dev *sdev,
	154	struct snd_sof_ipc_msg *msg)
	155	{
27302052 LG	156	/* send the message */
	157	sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
	158	msg->msg_size);
	159	snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
6fbbc18e	160	CNL_DSP_REG_HIPCIDR_BUSY);
27302052 LG	161
	162	return 0;
	163	}
	164
dc20e5f3 PX	165	static void cnl_ipc_dump(struct snd_sof_dev *sdev)
	166	{
	167	u32 hipcctl;
	168	u32 hipcida;
	169	u32 hipctdr;
	170
f1fd9d0e KV	171	hda_ipc_irq_dump(sdev);
f1fd9d0e KV	172
dc20e5f3 PX	173	/* read IPC status */
	174	hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
	175	hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
	176	hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
	177
	178	/* dump the IPC regs */
	179	/* TODO: parse the raw msg */
	180	dev_err(sdev->dev,
	181	"error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
	182	hipcida, hipctdr, hipcctl);
	183	}
	184
27302052 LG	185	/* cannonlake ops */
	186	const struct snd_sof_dsp_ops sof_cnl_ops = {
	187	/* probe and remove */
	188	.probe = hda_dsp_probe,
	189	.remove = hda_dsp_remove,
	190
	191	/* Register IO */
	192	.write = sof_io_write,
	193	.read = sof_io_read,
	194	.write64 = sof_io_write64,
	195	.read64 = sof_io_read64,
	196
	197	/* Block IO */
	198	.block_read = sof_block_read,
	199	.block_write = sof_block_write,
	200
	201	/* doorbell */
	202	.irq_handler = hda_dsp_ipc_irq_handler,
	203	.irq_thread = cnl_ipc_irq_thread,
	204
	205	/* ipc */
	206	.send_msg = cnl_ipc_send_msg,
	207	.fw_ready = hda_dsp_ipc_fw_ready,
	208
	209	.ipc_msg_data = hda_ipc_msg_data,
	210	.ipc_pcm_params = hda_ipc_pcm_params,
	211
	212	/* debug */
	213	.debug_map = cnl_dsp_debugfs,
	214	.debug_map_count = ARRAY_SIZE(cnl_dsp_debugfs),
	215	.dbg_dump = hda_dsp_dump,
dc20e5f3	216	.ipc_dump = cnl_ipc_dump,
27302052 LG	217
	218	/* stream callbacks */
	219	.pcm_open = hda_dsp_pcm_open,
	220	.pcm_close = hda_dsp_pcm_close,
	221	.pcm_hw_params = hda_dsp_pcm_hw_params,
93146bc2	222	.pcm_hw_free = hda_dsp_stream_hw_free,
27302052	223	.pcm_trigger = hda_dsp_pcm_trigger,
acd1c188	224	.pcm_pointer = hda_dsp_pcm_pointer,
27302052 LG	225
	226	/* firmware loading */
	227	.load_firmware = snd_sof_load_firmware_raw,
	228
	229	/* pre/post fw run */
	230	.pre_fw_run = hda_dsp_pre_fw_run,
	231	.post_fw_run = hda_dsp_post_fw_run,
	232
	233	/* dsp core power up/down */
	234	.core_power_up = hda_dsp_enable_core,
	235	.core_power_down = hda_dsp_core_reset_power_down,
	236
	237	/* firmware run */
	238	.run = hda_dsp_cl_boot_firmware,
	239
	240	/* trace callback */
	241	.trace_init = hda_dsp_trace_init,
	242	.trace_release = hda_dsp_trace_release,
	243	.trace_trigger = hda_dsp_trace_trigger,
	244
	245	/* DAI drivers */
	246	.drv = skl_dai,
	247	.num_drv = SOF_SKL_NUM_DAIS,
	248
	249	/* PM */
	250	.suspend = hda_dsp_suspend,
	251	.resume = hda_dsp_resume,
	252	.runtime_suspend = hda_dsp_runtime_suspend,
	253	.runtime_resume = hda_dsp_runtime_resume,
87a6fe80	254	.runtime_idle = hda_dsp_runtime_idle,
ed3baacd	255	.set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
27302052 LG	256	};
	257	EXPORT_SYMBOL(sof_cnl_ops);
	258
	259	const struct sof_intel_dsp_desc cnl_chip_info = {
	260	/* Cannonlake */
	261	.cores_num = 4,
	262	.init_core_mask = 1,
	263	.cores_mask = HDA_DSP_CORE_MASK(0) \|
	264	HDA_DSP_CORE_MASK(1) \|
	265	HDA_DSP_CORE_MASK(2) \|
	266	HDA_DSP_CORE_MASK(3),
	267	.ipc_req = CNL_DSP_REG_HIPCIDR,
	268	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	269	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	270	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	271	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	272	.rom_init_timeout = 300,
b095fe47 ZY	273	.ssp_count = CNL_SSP_COUNT,
b095fe47 ZY	274	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
27302052 LG	275	};
27302052 LG	276	EXPORT_SYMBOL(cnl_chip_info);
630be964 ZY	277
	278	const struct sof_intel_dsp_desc icl_chip_info = {
	279	/* Icelake */
	280	.cores_num = 4,
	281	.init_core_mask = 1,
	282	.cores_mask = HDA_DSP_CORE_MASK(0) \|
	283	HDA_DSP_CORE_MASK(1) \|
	284	HDA_DSP_CORE_MASK(2) \|
	285	HDA_DSP_CORE_MASK(3),
	286	.ipc_req = CNL_DSP_REG_HIPCIDR,
	287	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
	288	.ipc_ack = CNL_DSP_REG_HIPCIDA,
	289	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
	290	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
	291	.rom_init_timeout = 300,
	292	.ssp_count = ICL_SSP_COUNT,
	293	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
	294	};
	295	EXPORT_SYMBOL(icl_chip_info);