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ASoC: SOF: control: correct the copy size for bytes kcontrol put
[linux-2.6-block.git] / sound / soc / sof / intel / cnl.c
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27302052
LG		 1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2//
3// This file is provided under a dual BSD/GPLv2 license. When using or
4// redistributing this file, you may do so under either license.
5//
6// Copyright(c) 2018 Intel Corporation. All rights reserved.
7//
8// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10// Rander Wang <rander.wang@intel.com>
11// Keyon Jie <yang.jie@linux.intel.com>
12//
13
14/*
15 * Hardware interface for audio DSP on Cannonlake.
16 */
17
18#include "../ops.h"
19#include "hda.h"
20
21static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = {
22 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
23 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
24 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
25};
26
27static void cnl_ipc_host_done(struct snd_sof_dev *sdev);
28static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev);
29
30static irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
31{
32 struct snd_sof_dev *sdev = context;
33 u32 hipci;
34 u32 hipcctl;
35 u32 hipcida;
36 u32 hipctdr;
37 u32 hipctdd;
38 u32 msg;
39 u32 msg_ext;
40 irqreturn_t ret = IRQ_NONE;
41
27302052
LG		 42 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
43 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
44 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
45
46 /* reenable IPC interrupt */
47 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
48 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
49
50 /* reply message from DSP */
51 if (hipcida & CNL_DSP_REG_HIPCIDA_DONE &&
52 hipcctl & CNL_DSP_REG_HIPCCTL_DONE) {
53 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
54 CNL_DSP_REG_HIPCIDR);
55 msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK;
56 msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK;
57
58 dev_vdbg(sdev->dev,
59 "ipc: firmware response, msg:0x%x, msg_ext:0x%x\n",
60 msg, msg_ext);
61
62 /* mask Done interrupt */
63 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
64 CNL_DSP_REG_HIPCCTL,
65 CNL_DSP_REG_HIPCCTL_DONE, 0);
66
67 /* handle immediate reply from DSP core */
68 hda_dsp_ipc_get_reply(sdev);
69 snd_sof_ipc_reply(sdev, msg);
70
71 if (sdev->code_loading) {
72 sdev->code_loading = 0;
73 wake_up(&sdev->waitq);
74 }
75
76 cnl_ipc_dsp_done(sdev);
77
78 ret = IRQ_HANDLED;
79 }
80
81 /* new message from DSP */
82 if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
83 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
84 CNL_DSP_REG_HIPCTDD);
85 msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
86 msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;
87
88 dev_vdbg(sdev->dev,
89 "ipc: firmware initiated, msg:0x%x, msg_ext:0x%x\n",
90 msg, msg_ext);
91
92 /* handle messages from DSP */
93 if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) ==
94 SOF_IPC_PANIC_MAGIC) {
95 snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext));
96 } else {
97 snd_sof_ipc_msgs_rx(sdev);
98 }
99
100 /*
101 * clear busy interrupt to tell dsp controller this
102 * interrupt has been accepted, not trigger it again
103 */
104 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
105 CNL_DSP_REG_HIPCTDR,
106 CNL_DSP_REG_HIPCTDR_BUSY,
107 CNL_DSP_REG_HIPCTDR_BUSY);
108
109 cnl_ipc_host_done(sdev);
110
111 ret = IRQ_HANDLED;
112 }
113
114 return ret;
115}
116
117static void cnl_ipc_host_done(struct snd_sof_dev *sdev)
118{
119 /*
120 * set done bit to ack dsp the msg has been
121 * processed and send reply msg to dsp
122 */
123 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
124 CNL_DSP_REG_HIPCTDA,
125 CNL_DSP_REG_HIPCTDA_DONE,
126 CNL_DSP_REG_HIPCTDA_DONE);
127}
128
129static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev)
130{
131 /*
132 * set DONE bit - tell DSP we have received the reply msg
133 * from DSP, and processed it, don't send more reply to host
134 */
135 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
136 CNL_DSP_REG_HIPCIDA,
137 CNL_DSP_REG_HIPCIDA_DONE,
138 CNL_DSP_REG_HIPCIDA_DONE);
139
140 /* unmask Done interrupt */
141 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
142 CNL_DSP_REG_HIPCCTL,
143 CNL_DSP_REG_HIPCCTL_DONE,
144 CNL_DSP_REG_HIPCCTL_DONE);
145}
146
147static int cnl_ipc_send_msg(struct snd_sof_dev *sdev,
148 struct snd_sof_ipc_msg *msg)
149{
150 u32 cmd = msg->header;
151
152 /* send the message */
153 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
154 msg->msg_size);
155 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
156 cmd | CNL_DSP_REG_HIPCIDR_BUSY);
157
158 return 0;
159}
160
dc20e5f3
PX		 161static void cnl_ipc_dump(struct snd_sof_dev *sdev)
162{
163 u32 hipcctl;
164 u32 hipcida;
165 u32 hipctdr;
166
167 /* read IPC status */
168 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
169 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
170 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
171
172 /* dump the IPC regs */
173 /* TODO: parse the raw msg */
174 dev_err(sdev->dev,
175 "error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
176 hipcida, hipctdr, hipcctl);
177}
178
27302052
LG		 179/* cannonlake ops */
180const struct snd_sof_dsp_ops sof_cnl_ops = {
181 /* probe and remove */
182 .probe = hda_dsp_probe,
183 .remove = hda_dsp_remove,
184
185 /* Register IO */
186 .write = sof_io_write,
187 .read = sof_io_read,
188 .write64 = sof_io_write64,
189 .read64 = sof_io_read64,
190
191 /* Block IO */
192 .block_read = sof_block_read,
193 .block_write = sof_block_write,
194
195 /* doorbell */
196 .irq_handler = hda_dsp_ipc_irq_handler,
197 .irq_thread = cnl_ipc_irq_thread,
198
199 /* ipc */
200 .send_msg = cnl_ipc_send_msg,
201 .fw_ready = hda_dsp_ipc_fw_ready,
202
203 .ipc_msg_data = hda_ipc_msg_data,
204 .ipc_pcm_params = hda_ipc_pcm_params,
205
206 /* debug */
207 .debug_map = cnl_dsp_debugfs,
208 .debug_map_count = ARRAY_SIZE(cnl_dsp_debugfs),
209 .dbg_dump = hda_dsp_dump,
dc20e5f3 210 .ipc_dump = cnl_ipc_dump,
27302052
LG		 211
212 /* stream callbacks */
213 .pcm_open = hda_dsp_pcm_open,
214 .pcm_close = hda_dsp_pcm_close,
215 .pcm_hw_params = hda_dsp_pcm_hw_params,
216 .pcm_trigger = hda_dsp_pcm_trigger,
acd1c188 217 .pcm_pointer = hda_dsp_pcm_pointer,
27302052
LG		 218
219 /* firmware loading */
220 .load_firmware = snd_sof_load_firmware_raw,
221
222 /* pre/post fw run */
223 .pre_fw_run = hda_dsp_pre_fw_run,
224 .post_fw_run = hda_dsp_post_fw_run,
225
226 /* dsp core power up/down */
227 .core_power_up = hda_dsp_enable_core,
228 .core_power_down = hda_dsp_core_reset_power_down,
229
230 /* firmware run */
231 .run = hda_dsp_cl_boot_firmware,
232
233 /* trace callback */
234 .trace_init = hda_dsp_trace_init,
235 .trace_release = hda_dsp_trace_release,
236 .trace_trigger = hda_dsp_trace_trigger,
237
238 /* DAI drivers */
239 .drv = skl_dai,
240 .num_drv = SOF_SKL_NUM_DAIS,
241
242 /* PM */
243 .suspend = hda_dsp_suspend,
244 .resume = hda_dsp_resume,
245 .runtime_suspend = hda_dsp_runtime_suspend,
246 .runtime_resume = hda_dsp_runtime_resume,
ed3baacd 247 .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
27302052
LG		 248};
249EXPORT_SYMBOL(sof_cnl_ops);
250
251const struct sof_intel_dsp_desc cnl_chip_info = {
252 /* Cannonlake */
253 .cores_num = 4,
254 .init_core_mask = 1,
255 .cores_mask = HDA_DSP_CORE_MASK(0) |
256 HDA_DSP_CORE_MASK(1) |
257 HDA_DSP_CORE_MASK(2) |
258 HDA_DSP_CORE_MASK(3),
259 .ipc_req = CNL_DSP_REG_HIPCIDR,
260 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
261 .ipc_ack = CNL_DSP_REG_HIPCIDA,
262 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
263 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
264 .rom_init_timeout = 300,
b095fe47
ZY		 265 .ssp_count = CNL_SSP_COUNT,
266 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
27302052
LG		 267};
268EXPORT_SYMBOL(cnl_chip_info);
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