[linux-2.6-block.git] / sound / soc / soc-cache.c

/*
 * soc-cache.c  --  ASoC register cache helpers
 *
 * Copyright 2009 Wolfson Microelectronics PLC.
 *
 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */

#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <sound/soc.h>

static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
				     unsigned int reg)
{
	u16 *cache = codec->reg_cache;

	if (reg >= codec->driver->reg_cache_size ||
		snd_soc_codec_volatile_register(codec, reg)) {
			if (codec->cache_only)
				return -1;

			BUG_ON(!codec->hw_read);
			return codec->hw_read(codec, reg);
	}

	return cache[reg];
}

static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
			     unsigned int value)
{
	u16 *cache = codec->reg_cache;
	u8 data[2];
	int ret;

	data[0] = (reg << 4) | ((value >> 8) & 0x000f);
	data[1] = value & 0x00ff;

	if (!snd_soc_codec_volatile_register(codec, reg) &&
		reg < codec->driver->reg_cache_size)
			cache[reg] = value;

	if (codec->cache_only) {
		codec->cache_sync = 1;
		return 0;
	}

	ret = codec->hw_write(codec->control_data, data, 2);
	if (ret == 2)
		return 0;
	if (ret < 0)
		return ret;
	else
		return -EIO;
}

#if defined(CONFIG_SPI_MASTER)
static int snd_soc_4_12_spi_write(void *control_data, const char *data,
				 int len)
{
	struct spi_device *spi = control_data;
	struct spi_transfer t;
	struct spi_message m;
	u8 msg[2];

	if (len <= 0)
		return 0;

	msg[0] = data[1];
	msg[1] = data[0];

	spi_message_init(&m);
	memset(&t, 0, (sizeof t));

	t.tx_buf = &msg[0];
	t.len = len;

	spi_message_add_tail(&t, &m);
	spi_sync(spi, &m);

	return len;
}
#else
#define snd_soc_4_12_spi_write NULL
#endif

static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
				     unsigned int reg)
{
	u16 *cache = codec->reg_cache;

	if (reg >= codec->driver->reg_cache_size ||
		snd_soc_codec_volatile_register(codec, reg)) {
			if (codec->cache_only)
				return -1;

			BUG_ON(!codec->hw_read);
			return codec->hw_read(codec, reg);
	}

	return cache[reg];
}

static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
			     unsigned int value)
{
	u16 *cache = codec->reg_cache;
	u8 data[2];
	int ret;

	data[0] = (reg << 1) | ((value >> 8) & 0x0001);
	data[1] = value & 0x00ff;

	if (!snd_soc_codec_volatile_register(codec, reg) &&
		reg < codec->driver->reg_cache_size)
			cache[reg] = value;

	if (codec->cache_only) {
		codec->cache_sync = 1;
		return 0;
	}

	ret = codec->hw_write(codec->control_data, data, 2);
	if (ret == 2)
		return 0;
	if (ret < 0)
		return ret;
	else
		return -EIO;
}

#if defined(CONFIG_SPI_MASTER)
static int snd_soc_7_9_spi_write(void *control_data, const char *data,
				 int len)
{
	struct spi_device *spi = control_data;
	struct spi_transfer t;
	struct spi_message m;
	u8 msg[2];

	if (len <= 0)
		return 0;

	msg[0] = data[0];
	msg[1] = data[1];

	spi_message_init(&m);
	memset(&t, 0, (sizeof t));

	t.tx_buf = &msg[0];
	t.len = len;

	spi_message_add_tail(&t, &m);
	spi_sync(spi, &m);

	return len;
}
#else
#define snd_soc_7_9_spi_write NULL
#endif

static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
			     unsigned int value)
{
	u8 *cache = codec->reg_cache;
	u8 data[2];

	reg &= 0xff;
	data[0] = reg;
	data[1] = value & 0xff;

	if (!snd_soc_codec_volatile_register(codec, reg) &&
		reg < codec->driver->reg_cache_size)
			cache[reg] = value;

	if (codec->cache_only) {
		codec->cache_sync = 1;
		return 0;
	}

	if (codec->hw_write(codec->control_data, data, 2) == 2)
		return 0;
	else
		return -EIO;
}

static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
				     unsigned int reg)
{
	u8 *cache = codec->reg_cache;

	reg &= 0xff;
	if (reg >= codec->driver->reg_cache_size ||
		snd_soc_codec_volatile_register(codec, reg)) {
			if (codec->cache_only)
				return -1;

			BUG_ON(!codec->hw_read);
			return codec->hw_read(codec, reg);
	}

	return cache[reg];
}

#if defined(CONFIG_SPI_MASTER)
static int snd_soc_8_8_spi_write(void *control_data, const char *data,
				 int len)
{
	struct spi_device *spi = control_data;
	struct spi_transfer t;
	struct spi_message m;
	u8 msg[2];

	if (len <= 0)
		return 0;

	msg[0] = data[0];
	msg[1] = data[1];

	spi_message_init(&m);
	memset(&t, 0, (sizeof t));

	t.tx_buf = &msg[0];
	t.len = len;

	spi_message_add_tail(&t, &m);
	spi_sync(spi, &m);

	return len;
}
#else
#define snd_soc_8_8_spi_write NULL
#endif

static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
			      unsigned int value)
{
	u16 *reg_cache = codec->reg_cache;
	u8 data[3];

	data[0] = reg;
	data[1] = (value >> 8) & 0xff;
	data[2] = value & 0xff;

	if (!snd_soc_codec_volatile_register(codec, reg) &&
	    reg < codec->driver->reg_cache_size)
		reg_cache[reg] = value;

	if (codec->cache_only) {
		codec->cache_sync = 1;
		return 0;
	}

	if (codec->hw_write(codec->control_data, data, 3) == 3)
		return 0;
	else
		return -EIO;
}

static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
				      unsigned int reg)
{
	u16 *cache = codec->reg_cache;

	if (reg >= codec->driver->reg_cache_size ||
	    snd_soc_codec_volatile_register(codec, reg)) {
		if (codec->cache_only)
			return -1;

		BUG_ON(!codec->hw_read);
		return codec->hw_read(codec, reg);
	} else {
		return cache[reg];
	}
}

#if defined(CONFIG_SPI_MASTER)
static int snd_soc_8_16_spi_write(void *control_data, const char *data,
				 int len)
{
	struct spi_device *spi = control_data;
	struct spi_transfer t;
	struct spi_message m;
	u8 msg[3];

	if (len <= 0)
		return 0;

	msg[0] = data[0];
	msg[1] = data[1];
	msg[2] = data[2];

	spi_message_init(&m);
	memset(&t, 0, (sizeof t));

	t.tx_buf = &msg[0];
	t.len = len;

	spi_message_add_tail(&t, &m);
	spi_sync(spi, &m);

	return len;
}
#else
#define snd_soc_8_16_spi_write NULL
#endif

#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
					  unsigned int r)
{
	struct i2c_msg xfer[2];
	u8 reg = r;
	u8 data;
	int ret;
	struct i2c_client *client = codec->control_data;

	/* Write register */
	xfer[0].addr = client->addr;
	xfer[0].flags = 0;
	xfer[0].len = 1;
	xfer[0].buf = &reg;

	/* Read data */
	xfer[1].addr = client->addr;
	xfer[1].flags = I2C_M_RD;
	xfer[1].len = 1;
	xfer[1].buf = &data;

	ret = i2c_transfer(client->adapter, xfer, 2);
	if (ret != 2) {
		dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
		return 0;
	}

	return data;
}
#else
#define snd_soc_8_8_read_i2c NULL
#endif

#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
					  unsigned int r)
{
	struct i2c_msg xfer[2];
	u8 reg = r;
	u16 data;
	int ret;
	struct i2c_client *client = codec->control_data;

	/* Write register */
	xfer[0].addr = client->addr;
	xfer[0].flags = 0;
	xfer[0].len = 1;
	xfer[0].buf = &reg;

	/* Read data */
	xfer[1].addr = client->addr;
	xfer[1].flags = I2C_M_RD;
	xfer[1].len = 2;
	xfer[1].buf = (u8 *)&data;

	ret = i2c_transfer(client->adapter, xfer, 2);
	if (ret != 2) {
		dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
		return 0;
	}

	return (data >> 8) | ((data & 0xff) << 8);
}
#else
#define snd_soc_8_16_read_i2c NULL
#endif

#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
					  unsigned int r)
{
	struct i2c_msg xfer[2];
	u16 reg = r;
	u8 data;
	int ret;
	struct i2c_client *client = codec->control_data;

	/* Write register */
	xfer[0].addr = client->addr;
	xfer[0].flags = 0;
	xfer[0].len = 2;
	xfer[0].buf = (u8 *)&reg;

	/* Read data */
	xfer[1].addr = client->addr;
	xfer[1].flags = I2C_M_RD;
	xfer[1].len = 1;
	xfer[1].buf = &data;

	ret = i2c_transfer(client->adapter, xfer, 2);
	if (ret != 2) {
		dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
		return 0;
	}

	return data;
}
#else
#define snd_soc_16_8_read_i2c NULL
#endif

static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
				     unsigned int reg)
{
	u8 *cache = codec->reg_cache;

	reg &= 0xff;
	if (reg >= codec->driver->reg_cache_size ||
		snd_soc_codec_volatile_register(codec, reg)) {
			if (codec->cache_only)
				return -1;

			BUG_ON(!codec->hw_read);
			return codec->hw_read(codec, reg);
	}

	return cache[reg];
}

static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
			     unsigned int value)
{
	u8 *cache = codec->reg_cache;
	u8 data[3];
	int ret;

	data[0] = (reg >> 8) & 0xff;
	data[1] = reg & 0xff;
	data[2] = value;

	reg &= 0xff;
	if (!snd_soc_codec_volatile_register(codec, reg) &&
		reg < codec->driver->reg_cache_size)
			cache[reg] = value;

	if (codec->cache_only) {
		codec->cache_sync = 1;
		return 0;
	}

	ret = codec->hw_write(codec->control_data, data, 3);
	if (ret == 3)
		return 0;
	if (ret < 0)
		return ret;
	else
		return -EIO;
}

#if defined(CONFIG_SPI_MASTER)
static int snd_soc_16_8_spi_write(void *control_data, const char *data,
				 int len)
{
	struct spi_device *spi = control_data;
	struct spi_transfer t;
	struct spi_message m;
	u8 msg[3];

	if (len <= 0)
		return 0;

	msg[0] = data[0];
	msg[1] = data[1];
	msg[2] = data[2];

	spi_message_init(&m);
	memset(&t, 0, (sizeof t));

	t.tx_buf = &msg[0];
	t.len = len;

	spi_message_add_tail(&t, &m);
	spi_sync(spi, &m);

	return len;
}
#else
#define snd_soc_16_8_spi_write NULL
#endif

#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
					   unsigned int r)
{
	struct i2c_msg xfer[2];
	u16 reg = cpu_to_be16(r);
	u16 data;
	int ret;
	struct i2c_client *client = codec->control_data;

	/* Write register */
	xfer[0].addr = client->addr;
	xfer[0].flags = 0;
	xfer[0].len = 2;
	xfer[0].buf = (u8 *)&reg;

	/* Read data */
	xfer[1].addr = client->addr;
	xfer[1].flags = I2C_M_RD;
	xfer[1].len = 2;
	xfer[1].buf = (u8 *)&data;

	ret = i2c_transfer(client->adapter, xfer, 2);
	if (ret != 2) {
		dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
		return 0;
	}

	return be16_to_cpu(data);
}
#else
#define snd_soc_16_16_read_i2c NULL
#endif

static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec,
				       unsigned int reg)
{
	u16 *cache = codec->reg_cache;

	if (reg >= codec->driver->reg_cache_size ||
	    snd_soc_codec_volatile_register(codec, reg)) {
		if (codec->cache_only)
			return -1;

		BUG_ON(!codec->hw_read);
		return codec->hw_read(codec, reg);
	}

	return cache[reg];
}

static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
			       unsigned int value)
{
	u16 *cache = codec->reg_cache;
	u8 data[4];
	int ret;

	data[0] = (reg >> 8) & 0xff;
	data[1] = reg & 0xff;
	data[2] = (value >> 8) & 0xff;
	data[3] = value & 0xff;

	if (!snd_soc_codec_volatile_register(codec, reg) &&
		reg < codec->driver->reg_cache_size)
			cache[reg] = value;

	if (codec->cache_only) {
		codec->cache_sync = 1;
		return 0;
	}

	ret = codec->hw_write(codec->control_data, data, 4);
	if (ret == 4)
		return 0;
	if (ret < 0)
		return ret;
	else
		return -EIO;
}

#if defined(CONFIG_SPI_MASTER)
static int snd_soc_16_16_spi_write(void *control_data, const char *data,
				 int len)
{
	struct spi_device *spi = control_data;
	struct spi_transfer t;
	struct spi_message m;
	u8 msg[4];

	if (len <= 0)
		return 0;

	msg[0] = data[0];
	msg[1] = data[1];
	msg[2] = data[2];
	msg[3] = data[3];

	spi_message_init(&m);
	memset(&t, 0, (sizeof t));

	t.tx_buf = &msg[0];
	t.len = len;

	spi_message_add_tail(&t, &m);
	spi_sync(spi, &m);

	return len;
}
#else
#define snd_soc_16_16_spi_write NULL
#endif

static struct {
	int addr_bits;
	int data_bits;
	int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
	int (*spi_write)(void *, const char *, int);
	unsigned int (*read)(struct snd_soc_codec *, unsigned int);
	unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
} io_types[] = {
	{
		.addr_bits = 4, .data_bits = 12,
		.write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
		.spi_write = snd_soc_4_12_spi_write,
	},
	{
		.addr_bits = 7, .data_bits = 9,
		.write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
		.spi_write = snd_soc_7_9_spi_write,
	},
	{
		.addr_bits = 8, .data_bits = 8,
		.write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
		.i2c_read = snd_soc_8_8_read_i2c,
		.spi_write = snd_soc_8_8_spi_write,
	},
	{
		.addr_bits = 8, .data_bits = 16,
		.write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
		.i2c_read = snd_soc_8_16_read_i2c,
		.spi_write = snd_soc_8_16_spi_write,
	},
	{
		.addr_bits = 16, .data_bits = 8,
		.write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
		.i2c_read = snd_soc_16_8_read_i2c,
		.spi_write = snd_soc_16_8_spi_write,
	},
	{
		.addr_bits = 16, .data_bits = 16,
		.write = snd_soc_16_16_write, .read = snd_soc_16_16_read,
		.i2c_read = snd_soc_16_16_read_i2c,
		.spi_write = snd_soc_16_16_spi_write,
	},
};

/**
 * snd_soc_codec_set_cache_io: Set up standard I/O functions.
 *
 * @codec: CODEC to configure.
 * @type: Type of cache.
 * @addr_bits: Number of bits of register address data.
 * @data_bits: Number of bits of data per register.
 * @control: Control bus used.
 *
 * Register formats are frequently shared between many I2C and SPI
 * devices.  In order to promote code reuse the ASoC core provides
 * some standard implementations of CODEC read and write operations
 * which can be set up using this function.
 *
 * The caller is responsible for allocating and initialising the
 * actual cache.
 *
 * Note that at present this code cannot be used by CODECs with
 * volatile registers.
 */
int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
			       int addr_bits, int data_bits,
			       enum snd_soc_control_type control)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(io_types); i++)
		if (io_types[i].addr_bits == addr_bits &&
		    io_types[i].data_bits == data_bits)
			break;
	if (i == ARRAY_SIZE(io_types)) {
		printk(KERN_ERR
		       "No I/O functions for %d bit address %d bit data\n",
		       addr_bits, data_bits);
		return -EINVAL;
	}

	codec->driver->write = io_types[i].write;
	codec->driver->read = io_types[i].read;

	switch (control) {
	case SND_SOC_CUSTOM:
		break;

	case SND_SOC_I2C:
#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
		codec->hw_write = (hw_write_t)i2c_master_send;
#endif
		if (io_types[i].i2c_read)
			codec->hw_read = io_types[i].i2c_read;

		codec->control_data = container_of(codec->dev,
						   struct i2c_client,
						   dev);
		break;

	case SND_SOC_SPI:
		if (io_types[i].spi_write)
			codec->hw_write = io_types[i].spi_write;

		codec->control_data = container_of(codec->dev,
						   struct spi_device,
						   dev);
		break;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
Commit	Line	Data
17a52fd6 MB	1	/*
	2	* soc-cache.c -- ASoC register cache helpers
	3	*
	4	* Copyright 2009 Wolfson Microelectronics PLC.
	5	*
	6	* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
7084a42b	14	#include <linux/i2c.h>
27ded041	15	#include <linux/spi/spi.h>
17a52fd6 MB	16	#include <sound/soc.h>
17a52fd6 MB	17
63b62ab0 BS	18	static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
	19	unsigned int reg)
	20	{
	21	u16 *cache = codec->reg_cache;
db49c146 DP	22
	23	if (reg >= codec->driver->reg_cache_size \|\|
	24	snd_soc_codec_volatile_register(codec, reg)) {
	25	if (codec->cache_only)
	26	return -1;
	27
5aaa062c	28	BUG_ON(!codec->hw_read);
db49c146 DP	29	return codec->hw_read(codec, reg);
	30	}
	31
63b62ab0 BS	32	return cache[reg];
	33	}
	34
	35	static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
	36	unsigned int value)
	37	{
	38	u16 *cache = codec->reg_cache;
	39	u8 data[2];
	40	int ret;
	41
63b62ab0 BS	42	data[0] = (reg << 4) \| ((value >> 8) & 0x000f);
	43	data[1] = value & 0x00ff;
	44
db49c146 DP	45	if (!snd_soc_codec_volatile_register(codec, reg) &&
	46	reg < codec->driver->reg_cache_size)
	47	cache[reg] = value;
8c961bcc	48
a3032b47 MB	49	if (codec->cache_only) {
a3032b47 MB	50	codec->cache_sync = 1;
8c961bcc	51	return 0;
a3032b47	52	}
8c961bcc	53
63b62ab0 BS	54	ret = codec->hw_write(codec->control_data, data, 2);
	55	if (ret == 2)
	56	return 0;
	57	if (ret < 0)
	58	return ret;
	59	else
	60	return -EIO;
	61	}
	62
	63	#if defined(CONFIG_SPI_MASTER)
	64	static int snd_soc_4_12_spi_write(void control_data, const char data,
	65	int len)
	66	{
	67	struct spi_device *spi = control_data;
	68	struct spi_transfer t;
	69	struct spi_message m;
	70	u8 msg[2];
	71
	72	if (len <= 0)
	73	return 0;
	74
	75	msg[0] = data[1];
	76	msg[1] = data[0];
	77
	78	spi_message_init(&m);
	79	memset(&t, 0, (sizeof t));
	80
	81	t.tx_buf = &msg[0];
	82	t.len = len;
	83
	84	spi_message_add_tail(&t, &m);
	85	spi_sync(spi, &m);
	86
	87	return len;
	88	}
	89	#else
	90	#define snd_soc_4_12_spi_write NULL
	91	#endif
	92
17a52fd6 MB	93	static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
	94	unsigned int reg)
	95	{
	96	u16 *cache = codec->reg_cache;
db49c146 DP	97
	98	if (reg >= codec->driver->reg_cache_size \|\|
	99	snd_soc_codec_volatile_register(codec, reg)) {
	100	if (codec->cache_only)
	101	return -1;
	102
5aaa062c	103	BUG_ON(!codec->hw_read);
db49c146 DP	104	return codec->hw_read(codec, reg);
	105	}
	106
17a52fd6 MB	107	return cache[reg];
	108	}
	109
	110	static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
	111	unsigned int value)
	112	{
	113	u16 *cache = codec->reg_cache;
	114	u8 data[2];
	115	int ret;
	116
17a52fd6 MB	117	data[0] = (reg << 1) \| ((value >> 8) & 0x0001);
	118	data[1] = value & 0x00ff;
	119
db49c146 DP	120	if (!snd_soc_codec_volatile_register(codec, reg) &&
	121	reg < codec->driver->reg_cache_size)
	122	cache[reg] = value;
8c961bcc	123
a3032b47 MB	124	if (codec->cache_only) {
a3032b47 MB	125	codec->cache_sync = 1;
8c961bcc	126	return 0;
a3032b47	127	}
8c961bcc	128
17a52fd6 MB	129	ret = codec->hw_write(codec->control_data, data, 2);
	130	if (ret == 2)
	131	return 0;
	132	if (ret < 0)
	133	return ret;
	134	else
	135	return -EIO;
	136	}
	137
27ded041 MB	138	#if defined(CONFIG_SPI_MASTER)
	139	static int snd_soc_7_9_spi_write(void control_data, const char data,
	140	int len)
	141	{
	142	struct spi_device *spi = control_data;
	143	struct spi_transfer t;
	144	struct spi_message m;
	145	u8 msg[2];
	146
	147	if (len <= 0)
	148	return 0;
	149
	150	msg[0] = data[0];
	151	msg[1] = data[1];
	152
	153	spi_message_init(&m);
	154	memset(&t, 0, (sizeof t));
	155
	156	t.tx_buf = &msg[0];
	157	t.len = len;
	158
	159	spi_message_add_tail(&t, &m);
	160	spi_sync(spi, &m);
	161
	162	return len;
	163	}
	164	#else
	165	#define snd_soc_7_9_spi_write NULL
	166	#endif
	167
341c9b84 JS	168	static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
	169	unsigned int value)
	170	{
	171	u8 *cache = codec->reg_cache;
	172	u8 data[2];
	173
f4bee1bb BS	174	reg &= 0xff;
f4bee1bb BS	175	data[0] = reg;
341c9b84 JS	176	data[1] = value & 0xff;
341c9b84 JS	177
005d65fb	178	if (!snd_soc_codec_volatile_register(codec, reg) &&
db49c146 DP	179	reg < codec->driver->reg_cache_size)
db49c146 DP	180	cache[reg] = value;
341c9b84	181
a3032b47 MB	182	if (codec->cache_only) {
a3032b47 MB	183	codec->cache_sync = 1;
8c961bcc	184	return 0;
a3032b47	185	}
8c961bcc	186
341c9b84 JS	187	if (codec->hw_write(codec->control_data, data, 2) == 2)
	188	return 0;
	189	else
	190	return -EIO;
	191	}
	192
	193	static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
	194	unsigned int reg)
	195	{
	196	u8 *cache = codec->reg_cache;
db49c146	197
f4bee1bb	198	reg &= 0xff;
db49c146 DP	199	if (reg >= codec->driver->reg_cache_size \|\|
	200	snd_soc_codec_volatile_register(codec, reg)) {
	201	if (codec->cache_only)
	202	return -1;
	203
5aaa062c	204	BUG_ON(!codec->hw_read);
db49c146 DP	205	return codec->hw_read(codec, reg);
	206	}
	207
341c9b84 JS	208	return cache[reg];
	209	}
	210
f479fd93 DP	211	#if defined(CONFIG_SPI_MASTER)
	212	static int snd_soc_8_8_spi_write(void control_data, const char data,
	213	int len)
	214	{
	215	struct spi_device *spi = control_data;
	216	struct spi_transfer t;
	217	struct spi_message m;
	218	u8 msg[2];
	219
	220	if (len <= 0)
	221	return 0;
	222
	223	msg[0] = data[0];
	224	msg[1] = data[1];
	225
	226	spi_message_init(&m);
	227	memset(&t, 0, (sizeof t));
	228
	229	t.tx_buf = &msg[0];
	230	t.len = len;
	231
	232	spi_message_add_tail(&t, &m);
	233	spi_sync(spi, &m);
	234
	235	return len;
	236	}
	237	#else
	238	#define snd_soc_8_8_spi_write NULL
	239	#endif
	240
afa2f106 MB	241	static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
	242	unsigned int value)
	243	{
	244	u16 *reg_cache = codec->reg_cache;
	245	u8 data[3];
	246
	247	data[0] = reg;
	248	data[1] = (value >> 8) & 0xff;
	249	data[2] = value & 0xff;
	250
3e13f65e TI	251	if (!snd_soc_codec_volatile_register(codec, reg) &&
	252	reg < codec->driver->reg_cache_size)
	253	reg_cache[reg] = value;
afa2f106	254
a3032b47 MB	255	if (codec->cache_only) {
a3032b47 MB	256	codec->cache_sync = 1;
8c961bcc	257	return 0;
a3032b47	258	}
8c961bcc	259
afa2f106 MB	260	if (codec->hw_write(codec->control_data, data, 3) == 3)
	261	return 0;
	262	else
	263	return -EIO;
	264	}
	265
	266	static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
	267	unsigned int reg)
	268	{
	269	u16 *cache = codec->reg_cache;
	270
f0fba2ad	271	if (reg >= codec->driver->reg_cache_size \|\|
8c961bcc MB	272	snd_soc_codec_volatile_register(codec, reg)) {
8c961bcc MB	273	if (codec->cache_only)
391d8a04	274	return -1;
8c961bcc	275
5aaa062c	276	BUG_ON(!codec->hw_read);
afa2f106	277	return codec->hw_read(codec, reg);
8c961bcc	278	} else {
afa2f106	279	return cache[reg];
8c961bcc	280	}
afa2f106 MB	281	}
afa2f106 MB	282
f479fd93 DP	283	#if defined(CONFIG_SPI_MASTER)
	284	static int snd_soc_8_16_spi_write(void control_data, const char data,
	285	int len)
	286	{
	287	struct spi_device *spi = control_data;
	288	struct spi_transfer t;
	289	struct spi_message m;
	290	u8 msg[3];
	291
	292	if (len <= 0)
	293	return 0;
	294
	295	msg[0] = data[0];
	296	msg[1] = data[1];
	297	msg[2] = data[2];
	298
	299	spi_message_init(&m);
	300	memset(&t, 0, (sizeof t));
	301
	302	t.tx_buf = &msg[0];
	303	t.len = len;
	304
	305	spi_message_add_tail(&t, &m);
	306	spi_sync(spi, &m);
	307
	308	return len;
	309	}
	310	#else
	311	#define snd_soc_8_16_spi_write NULL
	312	#endif
	313
85dfcdff CC	314	#if defined(CONFIG_I2C) \|\| (defined(CONFIG_I2C_MODULE) && defined(MODULE))
	315	static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
	316	unsigned int r)
	317	{
	318	struct i2c_msg xfer[2];
	319	u8 reg = r;
	320	u8 data;
	321	int ret;
	322	struct i2c_client *client = codec->control_data;
	323
	324	/* Write register */
	325	xfer[0].addr = client->addr;
	326	xfer[0].flags = 0;
	327	xfer[0].len = 1;
	328	xfer[0].buf = ®
	329
	330	/* Read data */
	331	xfer[1].addr = client->addr;
	332	xfer[1].flags = I2C_M_RD;
	333	xfer[1].len = 1;
	334	xfer[1].buf = &data;
	335
	336	ret = i2c_transfer(client->adapter, xfer, 2);
	337	if (ret != 2) {
	338	dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
	339	return 0;
	340	}
	341
	342	return data;
	343	}
	344	#else
	345	#define snd_soc_8_8_read_i2c NULL
	346	#endif
	347
17244c24	348	#if defined(CONFIG_I2C) \|\| (defined(CONFIG_I2C_MODULE) && defined(MODULE))
afa2f106 MB	349	static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
	350	unsigned int r)
	351	{
	352	struct i2c_msg xfer[2];
	353	u8 reg = r;
	354	u16 data;
	355	int ret;
	356	struct i2c_client *client = codec->control_data;
	357
	358	/* Write register */
	359	xfer[0].addr = client->addr;
	360	xfer[0].flags = 0;
	361	xfer[0].len = 1;
	362	xfer[0].buf = ®
	363
	364	/* Read data */
	365	xfer[1].addr = client->addr;
	366	xfer[1].flags = I2C_M_RD;
	367	xfer[1].len = 2;
	368	xfer[1].buf = (u8 *)&data;
	369
	370	ret = i2c_transfer(client->adapter, xfer, 2);
	371	if (ret != 2) {
	372	dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
	373	return 0;
	374	}
	375
	376	return (data >> 8) \| ((data & 0xff) << 8);
	377	}
	378	#else
	379	#define snd_soc_8_16_read_i2c NULL
	380	#endif
17a52fd6	381
994dc424 BS	382	#if defined(CONFIG_I2C) \|\| (defined(CONFIG_I2C_MODULE) && defined(MODULE))
	383	static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
	384	unsigned int r)
	385	{
	386	struct i2c_msg xfer[2];
	387	u16 reg = r;
	388	u8 data;
	389	int ret;
	390	struct i2c_client *client = codec->control_data;
	391
	392	/* Write register */
	393	xfer[0].addr = client->addr;
	394	xfer[0].flags = 0;
	395	xfer[0].len = 2;
	396	xfer[0].buf = (u8 *)®
	397
	398	/* Read data */
	399	xfer[1].addr = client->addr;
	400	xfer[1].flags = I2C_M_RD;
	401	xfer[1].len = 1;
	402	xfer[1].buf = &data;
	403
	404	ret = i2c_transfer(client->adapter, xfer, 2);
	405	if (ret != 2) {
	406	dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
	407	return 0;
	408	}
	409
	410	return data;
	411	}
	412	#else
	413	#define snd_soc_16_8_read_i2c NULL
	414	#endif
	415
	416	static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
	417	unsigned int reg)
	418	{
ac770267	419	u8 *cache = codec->reg_cache;
994dc424 BS	420
994dc424 BS	421	reg &= 0xff;
db49c146 DP	422	if (reg >= codec->driver->reg_cache_size \|\|
	423	snd_soc_codec_volatile_register(codec, reg)) {
	424	if (codec->cache_only)
	425	return -1;
	426
5aaa062c	427	BUG_ON(!codec->hw_read);
db49c146 DP	428	return codec->hw_read(codec, reg);
	429	}
	430
994dc424 BS	431	return cache[reg];
	432	}
	433
	434	static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
	435	unsigned int value)
	436	{
ac770267	437	u8 *cache = codec->reg_cache;
994dc424 BS	438	u8 data[3];
	439	int ret;
	440
994dc424 BS	441	data[0] = (reg >> 8) & 0xff;
	442	data[1] = reg & 0xff;
	443	data[2] = value;
	444
	445	reg &= 0xff;
db49c146 DP	446	if (!snd_soc_codec_volatile_register(codec, reg) &&
	447	reg < codec->driver->reg_cache_size)
	448	cache[reg] = value;
8c961bcc	449
a3032b47 MB	450	if (codec->cache_only) {
a3032b47 MB	451	codec->cache_sync = 1;
8c961bcc	452	return 0;
a3032b47	453	}
8c961bcc	454
994dc424 BS	455	ret = codec->hw_write(codec->control_data, data, 3);
	456	if (ret == 3)
	457	return 0;
	458	if (ret < 0)
	459	return ret;
	460	else
	461	return -EIO;
	462	}
	463
	464	#if defined(CONFIG_SPI_MASTER)
	465	static int snd_soc_16_8_spi_write(void control_data, const char data,
	466	int len)
	467	{
	468	struct spi_device *spi = control_data;
	469	struct spi_transfer t;
	470	struct spi_message m;
	471	u8 msg[3];
	472
	473	if (len <= 0)
	474	return 0;
	475
	476	msg[0] = data[0];
	477	msg[1] = data[1];
	478	msg[2] = data[2];
	479
	480	spi_message_init(&m);
	481	memset(&t, 0, (sizeof t));
	482
	483	t.tx_buf = &msg[0];
	484	t.len = len;
	485
	486	spi_message_add_tail(&t, &m);
	487	spi_sync(spi, &m);
	488
	489	return len;
	490	}
	491	#else
	492	#define snd_soc_16_8_spi_write NULL
	493	#endif
	494
bc6552f4 MB	495	#if defined(CONFIG_I2C) \|\| (defined(CONFIG_I2C_MODULE) && defined(MODULE))
	496	static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
	497	unsigned int r)
	498	{
	499	struct i2c_msg xfer[2];
	500	u16 reg = cpu_to_be16(r);
	501	u16 data;
	502	int ret;
	503	struct i2c_client *client = codec->control_data;
	504
	505	/* Write register */
	506	xfer[0].addr = client->addr;
	507	xfer[0].flags = 0;
	508	xfer[0].len = 2;
	509	xfer[0].buf = (u8 *)®
	510
	511	/* Read data */
	512	xfer[1].addr = client->addr;
	513	xfer[1].flags = I2C_M_RD;
	514	xfer[1].len = 2;
	515	xfer[1].buf = (u8 *)&data;
	516
	517	ret = i2c_transfer(client->adapter, xfer, 2);
	518	if (ret != 2) {
	519	dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
	520	return 0;
	521	}
	522
	523	return be16_to_cpu(data);
	524	}
	525	#else
	526	#define snd_soc_16_16_read_i2c NULL
	527	#endif
	528
	529	static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec,
	530	unsigned int reg)
	531	{
	532	u16 *cache = codec->reg_cache;
	533
f0fba2ad	534	if (reg >= codec->driver->reg_cache_size \|\|
bc6552f4 MB	535	snd_soc_codec_volatile_register(codec, reg)) {
bc6552f4 MB	536	if (codec->cache_only)
391d8a04	537	return -1;
bc6552f4	538
5aaa062c	539	BUG_ON(!codec->hw_read);
bc6552f4 MB	540	return codec->hw_read(codec, reg);
	541	}
	542
	543	return cache[reg];
	544	}
	545
	546	static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
	547	unsigned int value)
	548	{
	549	u16 *cache = codec->reg_cache;
	550	u8 data[4];
	551	int ret;
	552
	553	data[0] = (reg >> 8) & 0xff;
	554	data[1] = reg & 0xff;
	555	data[2] = (value >> 8) & 0xff;
	556	data[3] = value & 0xff;
	557
db49c146 DP	558	if (!snd_soc_codec_volatile_register(codec, reg) &&
	559	reg < codec->driver->reg_cache_size)
	560	cache[reg] = value;
bc6552f4 MB	561
	562	if (codec->cache_only) {
	563	codec->cache_sync = 1;
	564	return 0;
	565	}
	566
	567	ret = codec->hw_write(codec->control_data, data, 4);
	568	if (ret == 4)
	569	return 0;
	570	if (ret < 0)
	571	return ret;
	572	else
	573	return -EIO;
	574	}
994dc424	575
f479fd93 DP	576	#if defined(CONFIG_SPI_MASTER)
	577	static int snd_soc_16_16_spi_write(void control_data, const char data,
	578	int len)
	579	{
	580	struct spi_device *spi = control_data;
	581	struct spi_transfer t;
	582	struct spi_message m;
	583	u8 msg[4];
	584
	585	if (len <= 0)
	586	return 0;
	587
	588	msg[0] = data[0];
	589	msg[1] = data[1];
	590	msg[2] = data[2];
	591	msg[3] = data[3];
	592
	593	spi_message_init(&m);
	594	memset(&t, 0, (sizeof t));
	595
	596	t.tx_buf = &msg[0];
	597	t.len = len;
	598
	599	spi_message_add_tail(&t, &m);
	600	spi_sync(spi, &m);
	601
	602	return len;
	603	}
	604	#else
	605	#define snd_soc_16_16_spi_write NULL
	606	#endif
	607
17a52fd6 MB	608	static struct {
	609	int addr_bits;
	610	int data_bits;
afa2f106	611	int (write)(struct snd_soc_codec codec, unsigned int, unsigned int);
27ded041	612	int (spi_write)(void , const char *, int);
17a52fd6	613	unsigned int (read)(struct snd_soc_codec , unsigned int);
afa2f106	614	unsigned int (i2c_read)(struct snd_soc_codec , unsigned int);
17a52fd6	615	} io_types[] = {
63b62ab0 BS	616	{
	617	.addr_bits = 4, .data_bits = 12,
	618	.write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
	619	.spi_write = snd_soc_4_12_spi_write,
	620	},
d62ab358 MB	621	{
	622	.addr_bits = 7, .data_bits = 9,
	623	.write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
8998c899	624	.spi_write = snd_soc_7_9_spi_write,
d62ab358 MB	625	},
	626	{
	627	.addr_bits = 8, .data_bits = 8,
	628	.write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
85dfcdff	629	.i2c_read = snd_soc_8_8_read_i2c,
f479fd93	630	.spi_write = snd_soc_8_8_spi_write,
d62ab358 MB	631	},
	632	{
	633	.addr_bits = 8, .data_bits = 16,
	634	.write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
	635	.i2c_read = snd_soc_8_16_read_i2c,
f479fd93	636	.spi_write = snd_soc_8_16_spi_write,
d62ab358	637	},
994dc424 BS	638	{
	639	.addr_bits = 16, .data_bits = 8,
	640	.write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
	641	.i2c_read = snd_soc_16_8_read_i2c,
	642	.spi_write = snd_soc_16_8_spi_write,
	643	},
bc6552f4 MB	644	{
	645	.addr_bits = 16, .data_bits = 16,
	646	.write = snd_soc_16_16_write, .read = snd_soc_16_16_read,
	647	.i2c_read = snd_soc_16_16_read_i2c,
f479fd93	648	.spi_write = snd_soc_16_16_spi_write,
bc6552f4	649	},
17a52fd6 MB	650	};
	651
	652	/**
	653	* snd_soc_codec_set_cache_io: Set up standard I/O functions.
	654	*
	655	* @codec: CODEC to configure.
	656	* @type: Type of cache.
	657	* @addr_bits: Number of bits of register address data.
	658	* @data_bits: Number of bits of data per register.
7084a42b	659	* @control: Control bus used.
17a52fd6 MB	660	*
	661	* Register formats are frequently shared between many I2C and SPI
	662	* devices. In order to promote code reuse the ASoC core provides
	663	* some standard implementations of CODEC read and write operations
	664	* which can be set up using this function.
	665	*
	666	* The caller is responsible for allocating and initialising the
	667	* actual cache.
	668	*
	669	* Note that at present this code cannot be used by CODECs with
	670	* volatile registers.
	671	*/
	672	int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
7084a42b MB	673	int addr_bits, int data_bits,
7084a42b MB	674	enum snd_soc_control_type control)
17a52fd6 MB	675	{
	676	int i;
	677
17a52fd6 MB	678	for (i = 0; i < ARRAY_SIZE(io_types); i++)
	679	if (io_types[i].addr_bits == addr_bits &&
	680	io_types[i].data_bits == data_bits)
	681	break;
	682	if (i == ARRAY_SIZE(io_types)) {
	683	printk(KERN_ERR
	684	"No I/O functions for %d bit address %d bit data\n",
	685	addr_bits, data_bits);
	686	return -EINVAL;
	687	}
	688
f0fba2ad LG	689	codec->driver->write = io_types[i].write;
f0fba2ad LG	690	codec->driver->read = io_types[i].read;
17a52fd6	691
7084a42b MB	692	switch (control) {
	693	case SND_SOC_CUSTOM:
	694	break;
	695
	696	case SND_SOC_I2C:
17244c24	697	#if defined(CONFIG_I2C) \|\| (defined(CONFIG_I2C_MODULE) && defined(MODULE))
7084a42b MB	698	codec->hw_write = (hw_write_t)i2c_master_send;
7084a42b MB	699	#endif
afa2f106 MB	700	if (io_types[i].i2c_read)
afa2f106 MB	701	codec->hw_read = io_types[i].i2c_read;
a6d14342 MB	702
	703	codec->control_data = container_of(codec->dev,
	704	struct i2c_client,
	705	dev);
7084a42b MB	706	break;
	707
	708	case SND_SOC_SPI:
27ded041 MB	709	if (io_types[i].spi_write)
27ded041 MB	710	codec->hw_write = io_types[i].spi_write;
a6d14342 MB	711
	712	codec->control_data = container_of(codec->dev,
	713	struct spi_device,
	714	dev);
7084a42b MB	715	break;
	716	}
	717
17a52fd6 MB	718	return 0;
	719	}
	720	EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);