Commit | Line | Data |
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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
785d1c45 | 16 | #include <linux/pm_runtime.h> |
a4d7d550 | 17 | #include <linux/io.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
a4d7d550 | 19 | #include <sound/soc.h> |
a4d7d550 | 20 | #include <sound/sh_fsi.h> |
a4d7d550 | 21 | |
e8c8b631 KM |
22 | /* PortA/PortB register */ |
23 | #define REG_DO_FMT 0x0000 | |
24 | #define REG_DOFF_CTL 0x0004 | |
25 | #define REG_DOFF_ST 0x0008 | |
26 | #define REG_DI_FMT 0x000C | |
27 | #define REG_DIFF_CTL 0x0010 | |
28 | #define REG_DIFF_ST 0x0014 | |
29 | #define REG_CKG1 0x0018 | |
30 | #define REG_CKG2 0x001C | |
31 | #define REG_DIDT 0x0020 | |
32 | #define REG_DODT 0x0024 | |
33 | #define REG_MUTE_ST 0x0028 | |
34 | #define REG_OUT_SEL 0x0030 | |
cc780d38 | 35 | |
43fa95ca KM |
36 | /* master register */ |
37 | #define MST_CLK_RST 0x0210 | |
38 | #define MST_SOFT_RST 0x0214 | |
39 | #define MST_FIFO_SZ 0x0218 | |
40 | ||
41 | /* core register (depend on FSI version) */ | |
3bc28070 KM |
42 | #define A_MST_CTLR 0x0180 |
43 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
44 | #define CPU_INT_ST 0x01F4 |
45 | #define CPU_IEMSK 0x01F8 | |
46 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
47 | #define INT_ST 0x0200 |
48 | #define IEMSK 0x0204 | |
49 | #define IMSK 0x0208 | |
a4d7d550 KM |
50 | |
51 | /* DO_FMT */ | |
52 | /* DI_FMT */ | |
f7d711e3 KM |
53 | #define CR_BWS_24 (0x0 << 20) /* FSI2 */ |
54 | #define CR_BWS_16 (0x1 << 20) /* FSI2 */ | |
55 | #define CR_BWS_20 (0x2 << 20) /* FSI2 */ | |
56 | ||
57 | #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ | |
58 | #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ | |
59 | #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ | |
60 | ||
a7ffb52b KM |
61 | #define CR_MONO (0x0 << 4) |
62 | #define CR_MONO_D (0x1 << 4) | |
63 | #define CR_PCM (0x2 << 4) | |
64 | #define CR_I2S (0x3 << 4) | |
65 | #define CR_TDM (0x4 << 4) | |
66 | #define CR_TDM_D (0x5 << 4) | |
a4d7d550 KM |
67 | |
68 | /* DOFF_CTL */ | |
69 | /* DIFF_CTL */ | |
70 | #define IRQ_HALF 0x00100000 | |
71 | #define FIFO_CLR 0x00000001 | |
72 | ||
73 | /* DOFF_ST */ | |
74 | #define ERR_OVER 0x00000010 | |
75 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 76 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 77 | |
ccad7b44 KM |
78 | /* CKG1 */ |
79 | #define ACKMD_MASK 0x00007000 | |
80 | #define BPFMD_MASK 0x00000700 | |
81 | ||
3bc28070 KM |
82 | /* A/B MST_CTLR */ |
83 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
84 | #define SE (1 << 0) /* Fix the master clock */ | |
85 | ||
a4d7d550 KM |
86 | /* CLK_RST */ |
87 | #define B_CLK 0x00000010 | |
88 | #define A_CLK 0x00000001 | |
89 | ||
cf6edd00 KM |
90 | /* IO SHIFT / MACRO */ |
91 | #define BI_SHIFT 12 | |
92 | #define BO_SHIFT 8 | |
93 | #define AI_SHIFT 4 | |
94 | #define AO_SHIFT 0 | |
95 | #define AB_IO(param, shift) (param << shift) | |
a4d7d550 | 96 | |
feb58cff KM |
97 | /* SOFT_RST */ |
98 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
99 | #define PASR (1 << 8) /* Port A Software Reset */ | |
100 | #define IR (1 << 4) /* Interrupt Reset */ | |
101 | #define FSISR (1 << 0) /* Software Reset */ | |
102 | ||
f7d711e3 KM |
103 | /* OUT_SEL (FSI2) */ |
104 | #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ | |
105 | /* 1: Biphase and serial */ | |
106 | ||
4a942b45 | 107 | /* FIFO_SZ */ |
cf6edd00 | 108 | #define FIFO_SZ_MASK 0x7 |
4a942b45 | 109 | |
a4d7d550 KM |
110 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
111 | ||
112 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
113 | ||
5bfb9ad0 KM |
114 | /* |
115 | * FSI driver use below type name for variable | |
116 | * | |
117 | * xxx_len : data length | |
118 | * xxx_width : data width | |
119 | * xxx_offset : data offset | |
120 | * xxx_num : number of data | |
121 | */ | |
122 | ||
c8fe2574 KM |
123 | /* |
124 | * struct | |
125 | */ | |
a4d7d550 | 126 | |
93193c2b | 127 | struct fsi_stream { |
a4d7d550 KM |
128 | struct snd_pcm_substream *substream; |
129 | ||
5bfb9ad0 KM |
130 | int fifo_max_num; |
131 | int chan_num; | |
a4d7d550 | 132 | |
5bfb9ad0 KM |
133 | int buff_offset; |
134 | int buff_len; | |
a4d7d550 | 135 | int period_len; |
5bfb9ad0 | 136 | int period_num; |
93193c2b KM |
137 | }; |
138 | ||
139 | struct fsi_priv { | |
140 | void __iomem *base; | |
141 | struct fsi_master *master; | |
142 | ||
143 | struct fsi_stream playback; | |
144 | struct fsi_stream capture; | |
3bc28070 | 145 | |
d4bc99b9 | 146 | long rate; |
a4d7d550 KM |
147 | }; |
148 | ||
73b92c1f KM |
149 | struct fsi_core { |
150 | int ver; | |
151 | ||
cc780d38 KM |
152 | u32 int_st; |
153 | u32 iemsk; | |
154 | u32 imsk; | |
2b0e7302 KM |
155 | u32 a_mclk; |
156 | u32 b_mclk; | |
cc780d38 KM |
157 | }; |
158 | ||
a4d7d550 KM |
159 | struct fsi_master { |
160 | void __iomem *base; | |
161 | int irq; | |
a4d7d550 KM |
162 | struct fsi_priv fsia; |
163 | struct fsi_priv fsib; | |
73b92c1f | 164 | struct fsi_core *core; |
a4d7d550 | 165 | struct sh_fsi_platform_info *info; |
8fc176d5 | 166 | spinlock_t lock; |
a4d7d550 KM |
167 | }; |
168 | ||
c8fe2574 KM |
169 | /* |
170 | * basic read write function | |
171 | */ | |
a4d7d550 | 172 | |
0f69d978 | 173 | static void __fsi_reg_write(u32 reg, u32 data) |
a4d7d550 KM |
174 | { |
175 | /* valid data area is 24bit */ | |
176 | data &= 0x00ffffff; | |
177 | ||
0f69d978 | 178 | __raw_writel(data, reg); |
a4d7d550 KM |
179 | } |
180 | ||
181 | static u32 __fsi_reg_read(u32 reg) | |
182 | { | |
0f69d978 | 183 | return __raw_readl(reg); |
a4d7d550 KM |
184 | } |
185 | ||
0f69d978 | 186 | static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data) |
a4d7d550 KM |
187 | { |
188 | u32 val = __fsi_reg_read(reg); | |
189 | ||
190 | val &= ~mask; | |
191 | val |= data & mask; | |
192 | ||
0f69d978 | 193 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
194 | } |
195 | ||
e8c8b631 KM |
196 | #define fsi_reg_write(p, r, d)\ |
197 | __fsi_reg_write((u32)(p->base + REG_##r), d) | |
a4d7d550 | 198 | |
e8c8b631 KM |
199 | #define fsi_reg_read(p, r)\ |
200 | __fsi_reg_read((u32)(p->base + REG_##r)) | |
a4d7d550 | 201 | |
e8c8b631 KM |
202 | #define fsi_reg_mask_set(p, r, m, d)\ |
203 | __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d) | |
a4d7d550 | 204 | |
43fa95ca KM |
205 | #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) |
206 | #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) | |
207 | static u32 _fsi_master_read(struct fsi_master *master, u32 reg) | |
a4d7d550 | 208 | { |
8fc176d5 KM |
209 | u32 ret; |
210 | unsigned long flags; | |
211 | ||
8fc176d5 KM |
212 | spin_lock_irqsave(&master->lock, flags); |
213 | ret = __fsi_reg_read((u32)(master->base + reg)); | |
214 | spin_unlock_irqrestore(&master->lock, flags); | |
215 | ||
216 | return ret; | |
a4d7d550 KM |
217 | } |
218 | ||
43fa95ca KM |
219 | #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) |
220 | #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) | |
221 | static void _fsi_master_mask_set(struct fsi_master *master, | |
71f6e064 | 222 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 223 | { |
8fc176d5 KM |
224 | unsigned long flags; |
225 | ||
8fc176d5 | 226 | spin_lock_irqsave(&master->lock, flags); |
0f69d978 | 227 | __fsi_reg_mask_set((u32)(master->base + reg), mask, data); |
8fc176d5 | 228 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
229 | } |
230 | ||
c8fe2574 KM |
231 | /* |
232 | * basic function | |
233 | */ | |
a4d7d550 | 234 | |
71f6e064 | 235 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 236 | { |
71f6e064 | 237 | return fsi->master; |
a4d7d550 KM |
238 | } |
239 | ||
240 | static int fsi_is_port_a(struct fsi_priv *fsi) | |
241 | { | |
71f6e064 KM |
242 | return fsi->master->base == fsi->base; |
243 | } | |
a4d7d550 | 244 | |
142e8174 | 245 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
246 | { |
247 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 248 | |
f0fba2ad | 249 | return rtd->cpu_dai; |
142e8174 KM |
250 | } |
251 | ||
252 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) | |
253 | { | |
254 | struct snd_soc_dai *dai = fsi_get_dai(substream); | |
f0fba2ad | 255 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 256 | |
f0fba2ad LG |
257 | if (dai->id == 0) |
258 | return &master->fsia; | |
259 | else | |
260 | return &master->fsib; | |
a4d7d550 KM |
261 | } |
262 | ||
263 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) | |
264 | { | |
265 | int is_porta = fsi_is_port_a(fsi); | |
71f6e064 | 266 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
267 | |
268 | return is_porta ? master->info->porta_flags : | |
269 | master->info->portb_flags; | |
270 | } | |
271 | ||
93193c2b KM |
272 | static inline int fsi_stream_is_play(int stream) |
273 | { | |
274 | return stream == SNDRV_PCM_STREAM_PLAYBACK; | |
275 | } | |
276 | ||
00545785 KM |
277 | static inline int fsi_is_play(struct snd_pcm_substream *substream) |
278 | { | |
93193c2b KM |
279 | return fsi_stream_is_play(substream->stream); |
280 | } | |
281 | ||
282 | static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi, | |
283 | int is_play) | |
284 | { | |
285 | return is_play ? &fsi->playback : &fsi->capture; | |
00545785 KM |
286 | } |
287 | ||
a4d7d550 KM |
288 | static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play) |
289 | { | |
290 | u32 mode; | |
291 | u32 flags = fsi_get_info_flags(fsi); | |
292 | ||
293 | mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE; | |
294 | ||
295 | /* return | |
296 | * 1 : master mode | |
297 | * 0 : slave mode | |
298 | */ | |
299 | ||
300 | return (mode & flags) != mode; | |
301 | } | |
302 | ||
cf6edd00 | 303 | static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
304 | { |
305 | int is_porta = fsi_is_port_a(fsi); | |
cf6edd00 | 306 | u32 shift; |
a4d7d550 KM |
307 | |
308 | if (is_porta) | |
cf6edd00 | 309 | shift = is_play ? AO_SHIFT : AI_SHIFT; |
a4d7d550 | 310 | else |
cf6edd00 | 311 | shift = is_play ? BO_SHIFT : BI_SHIFT; |
a4d7d550 | 312 | |
cf6edd00 | 313 | return shift; |
a4d7d550 KM |
314 | } |
315 | ||
316 | static void fsi_stream_push(struct fsi_priv *fsi, | |
93193c2b | 317 | int is_play, |
a4d7d550 KM |
318 | struct snd_pcm_substream *substream, |
319 | u32 buffer_len, | |
320 | u32 period_len) | |
321 | { | |
93193c2b KM |
322 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
323 | ||
324 | io->substream = substream; | |
325 | io->buff_len = buffer_len; | |
326 | io->buff_offset = 0; | |
327 | io->period_len = period_len; | |
328 | io->period_num = 0; | |
a4d7d550 KM |
329 | } |
330 | ||
93193c2b | 331 | static void fsi_stream_pop(struct fsi_priv *fsi, int is_play) |
a4d7d550 | 332 | { |
93193c2b KM |
333 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
334 | ||
335 | io->substream = NULL; | |
336 | io->buff_len = 0; | |
337 | io->buff_offset = 0; | |
338 | io->period_len = 0; | |
339 | io->period_num = 0; | |
a4d7d550 KM |
340 | } |
341 | ||
5bfb9ad0 | 342 | static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
343 | { |
344 | u32 status; | |
93193c2b | 345 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
5bfb9ad0 | 346 | int data_num; |
a4d7d550 | 347 | |
e8c8b631 KM |
348 | status = is_play ? |
349 | fsi_reg_read(fsi, DOFF_ST) : | |
350 | fsi_reg_read(fsi, DIFF_ST); | |
351 | ||
5bfb9ad0 | 352 | data_num = 0x1ff & (status >> 8); |
93193c2b | 353 | data_num *= io->chan_num; |
5bfb9ad0 KM |
354 | |
355 | return data_num; | |
356 | } | |
a4d7d550 | 357 | |
5bfb9ad0 KM |
358 | static int fsi_len2num(int len, int width) |
359 | { | |
360 | return len / width; | |
361 | } | |
362 | ||
363 | #define fsi_num2offset(a, b) fsi_num2len(a, b) | |
364 | static int fsi_num2len(int num, int width) | |
365 | { | |
366 | return num * width; | |
a4d7d550 KM |
367 | } |
368 | ||
93193c2b | 369 | static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play) |
cca1b235 | 370 | { |
93193c2b KM |
371 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
372 | struct snd_pcm_substream *substream = io->substream; | |
cca1b235 KM |
373 | struct snd_pcm_runtime *runtime = substream->runtime; |
374 | ||
93193c2b | 375 | return frames_to_bytes(runtime, 1) / io->chan_num; |
cca1b235 KM |
376 | } |
377 | ||
b9fde18c KM |
378 | /* |
379 | * dma function | |
380 | */ | |
381 | ||
93193c2b | 382 | static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream) |
c79eab3e | 383 | { |
93193c2b KM |
384 | int is_play = fsi_stream_is_play(stream); |
385 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
386 | ||
387 | return io->substream->runtime->dma_area + io->buff_offset; | |
c79eab3e KM |
388 | } |
389 | ||
5bfb9ad0 | 390 | static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
391 | { |
392 | u16 *start; | |
393 | int i; | |
394 | ||
93193c2b | 395 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
b9fde18c | 396 | |
5bfb9ad0 | 397 | for (i = 0; i < num; i++) |
b9fde18c KM |
398 | fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8)); |
399 | } | |
400 | ||
5bfb9ad0 | 401 | static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
402 | { |
403 | u16 *start; | |
404 | int i; | |
405 | ||
93193c2b KM |
406 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
407 | ||
b9fde18c | 408 | |
5bfb9ad0 | 409 | for (i = 0; i < num; i++) |
b9fde18c KM |
410 | *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); |
411 | } | |
412 | ||
5bfb9ad0 | 413 | static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
414 | { |
415 | u32 *start; | |
416 | int i; | |
417 | ||
93193c2b KM |
418 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
419 | ||
b9fde18c | 420 | |
5bfb9ad0 | 421 | for (i = 0; i < num; i++) |
b9fde18c KM |
422 | fsi_reg_write(fsi, DODT, *(start + i)); |
423 | } | |
424 | ||
5bfb9ad0 | 425 | static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
426 | { |
427 | u32 *start; | |
428 | int i; | |
429 | ||
93193c2b | 430 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
b9fde18c | 431 | |
5bfb9ad0 | 432 | for (i = 0; i < num; i++) |
b9fde18c KM |
433 | *(start + i) = fsi_reg_read(fsi, DIDT); |
434 | } | |
435 | ||
c8fe2574 KM |
436 | /* |
437 | * irq function | |
438 | */ | |
a4d7d550 | 439 | |
a4d7d550 KM |
440 | static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) |
441 | { | |
cf6edd00 | 442 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 443 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 444 | |
43fa95ca KM |
445 | fsi_core_mask_set(master, imsk, data, data); |
446 | fsi_core_mask_set(master, iemsk, data, data); | |
a4d7d550 KM |
447 | } |
448 | ||
449 | static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | |
450 | { | |
cf6edd00 | 451 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 452 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 453 | |
43fa95ca KM |
454 | fsi_core_mask_set(master, imsk, data, 0); |
455 | fsi_core_mask_set(master, iemsk, data, 0); | |
a4d7d550 KM |
456 | } |
457 | ||
10ea76cc KM |
458 | static u32 fsi_irq_get_status(struct fsi_master *master) |
459 | { | |
43fa95ca | 460 | return fsi_core_read(master, int_st); |
10ea76cc KM |
461 | } |
462 | ||
10ea76cc KM |
463 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
464 | { | |
465 | u32 data = 0; | |
466 | struct fsi_master *master = fsi_get_master(fsi); | |
467 | ||
cf6edd00 KM |
468 | data |= AB_IO(1, fsi_get_port_shift(fsi, 0)); |
469 | data |= AB_IO(1, fsi_get_port_shift(fsi, 1)); | |
10ea76cc KM |
470 | |
471 | /* clear interrupt factor */ | |
43fa95ca | 472 | fsi_core_mask_set(master, int_st, data, 0); |
10ea76cc KM |
473 | } |
474 | ||
c8fe2574 KM |
475 | /* |
476 | * SPDIF master clock function | |
477 | * | |
478 | * These functions are used later FSI2 | |
479 | */ | |
3bc28070 KM |
480 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
481 | { | |
482 | struct fsi_master *master = fsi_get_master(fsi); | |
2b0e7302 | 483 | u32 mask, val; |
3bc28070 KM |
484 | |
485 | if (master->core->ver < 2) { | |
486 | pr_err("fsi: register access err (%s)\n", __func__); | |
487 | return; | |
488 | } | |
489 | ||
2b0e7302 KM |
490 | mask = BP | SE; |
491 | val = enable ? mask : 0; | |
492 | ||
493 | fsi_is_port_a(fsi) ? | |
43fa95ca KM |
494 | fsi_core_mask_set(master, a_mclk, mask, val) : |
495 | fsi_core_mask_set(master, b_mclk, mask, val); | |
3bc28070 KM |
496 | } |
497 | ||
c8fe2574 KM |
498 | /* |
499 | * ctrl function | |
500 | */ | |
10ea76cc | 501 | |
a4d7d550 KM |
502 | static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable) |
503 | { | |
504 | u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4); | |
71f6e064 | 505 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
506 | |
507 | if (enable) | |
71f6e064 | 508 | fsi_master_mask_set(master, CLK_RST, val, val); |
a4d7d550 | 509 | else |
71f6e064 | 510 | fsi_master_mask_set(master, CLK_RST, val, 0); |
a4d7d550 KM |
511 | } |
512 | ||
4a942b45 KM |
513 | static void fsi_fifo_init(struct fsi_priv *fsi, |
514 | int is_play, | |
515 | struct snd_soc_dai *dai) | |
a4d7d550 | 516 | { |
4a942b45 | 517 | struct fsi_master *master = fsi_get_master(fsi); |
93193c2b | 518 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
e8c8b631 | 519 | u32 shift, i; |
a4d7d550 | 520 | |
4a942b45 KM |
521 | /* get on-chip RAM capacity */ |
522 | shift = fsi_master_read(master, FIFO_SZ); | |
cf6edd00 KM |
523 | shift >>= fsi_get_port_shift(fsi, is_play); |
524 | shift &= FIFO_SZ_MASK; | |
93193c2b KM |
525 | io->fifo_max_num = 256 << shift; |
526 | dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num); | |
a4d7d550 | 527 | |
4a942b45 KM |
528 | /* |
529 | * The maximum number of sample data varies depending | |
530 | * on the number of channels selected for the format. | |
531 | * | |
532 | * FIFOs are used in 4-channel units in 3-channel mode | |
533 | * and in 8-channel units in 5- to 7-channel mode | |
534 | * meaning that more FIFOs than the required size of DPRAM | |
535 | * are used. | |
536 | * | |
537 | * ex) if 256 words of DP-RAM is connected | |
538 | * 1 channel: 256 (256 x 1 = 256) | |
539 | * 2 channels: 128 (128 x 2 = 256) | |
540 | * 3 channels: 64 ( 64 x 3 = 192) | |
541 | * 4 channels: 64 ( 64 x 4 = 256) | |
542 | * 5 channels: 32 ( 32 x 5 = 160) | |
543 | * 6 channels: 32 ( 32 x 6 = 192) | |
544 | * 7 channels: 32 ( 32 x 7 = 224) | |
545 | * 8 channels: 32 ( 32 x 8 = 256) | |
546 | */ | |
93193c2b KM |
547 | for (i = 1; i < io->chan_num; i <<= 1) |
548 | io->fifo_max_num >>= 1; | |
5bfb9ad0 | 549 | dev_dbg(dai->dev, "%d channel %d store\n", |
93193c2b | 550 | io->chan_num, io->fifo_max_num); |
a4d7d550 | 551 | |
e8c8b631 KM |
552 | /* |
553 | * set interrupt generation factor | |
554 | * clear FIFO | |
555 | */ | |
556 | if (is_play) { | |
557 | fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); | |
558 | fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); | |
559 | } else { | |
560 | fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); | |
561 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
562 | } | |
a4d7d550 KM |
563 | } |
564 | ||
71f6e064 | 565 | static void fsi_soft_all_reset(struct fsi_master *master) |
a4d7d550 | 566 | { |
a4d7d550 | 567 | /* port AB reset */ |
feb58cff | 568 | fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0); |
a4d7d550 KM |
569 | mdelay(10); |
570 | ||
571 | /* soft reset */ | |
feb58cff KM |
572 | fsi_master_mask_set(master, SOFT_RST, FSISR, 0); |
573 | fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR); | |
a4d7d550 KM |
574 | mdelay(10); |
575 | } | |
576 | ||
93193c2b | 577 | static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int startup, int stream) |
a4d7d550 KM |
578 | { |
579 | struct snd_pcm_runtime *runtime; | |
580 | struct snd_pcm_substream *substream = NULL; | |
93193c2b KM |
581 | int is_play = fsi_stream_is_play(stream); |
582 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
d8b33534 KM |
583 | int data_residue_num; |
584 | int data_num; | |
585 | int data_num_max; | |
5bfb9ad0 | 586 | int ch_width; |
b9fde18c | 587 | int over_period; |
d8b33534 | 588 | void (*fn)(struct fsi_priv *fsi, int size); |
a4d7d550 KM |
589 | |
590 | if (!fsi || | |
93193c2b KM |
591 | !io->substream || |
592 | !io->substream->runtime) | |
a4d7d550 KM |
593 | return -EINVAL; |
594 | ||
1c418d1f | 595 | over_period = 0; |
93193c2b | 596 | substream = io->substream; |
1c418d1f | 597 | runtime = substream->runtime; |
a4d7d550 KM |
598 | |
599 | /* FSI FIFO has limit. | |
600 | * So, this driver can not send periods data at a time | |
601 | */ | |
93193c2b KM |
602 | if (io->buff_offset >= |
603 | fsi_num2offset(io->period_num + 1, io->period_len)) { | |
a4d7d550 | 604 | |
1c418d1f | 605 | over_period = 1; |
93193c2b | 606 | io->period_num = (io->period_num + 1) % runtime->periods; |
a4d7d550 | 607 | |
93193c2b KM |
608 | if (0 == io->period_num) |
609 | io->buff_offset = 0; | |
a4d7d550 KM |
610 | } |
611 | ||
612 | /* get 1 channel data width */ | |
93193c2b | 613 | ch_width = fsi_get_frame_width(fsi, is_play); |
a4d7d550 | 614 | |
d8b33534 | 615 | /* get residue data number of alsa */ |
93193c2b | 616 | data_residue_num = fsi_len2num(io->buff_len - io->buff_offset, |
d8b33534 KM |
617 | ch_width); |
618 | ||
619 | if (is_play) { | |
620 | /* | |
621 | * for play-back | |
622 | * | |
623 | * data_num_max : number of FSI fifo free space | |
624 | * data_num : number of ALSA residue data | |
625 | */ | |
93193c2b | 626 | data_num_max = io->fifo_max_num * io->chan_num; |
d8b33534 KM |
627 | data_num_max -= fsi_get_fifo_data_num(fsi, is_play); |
628 | ||
629 | data_num = data_residue_num; | |
630 | ||
631 | switch (ch_width) { | |
632 | case 2: | |
633 | fn = fsi_dma_soft_push16; | |
634 | break; | |
635 | case 4: | |
636 | fn = fsi_dma_soft_push32; | |
637 | break; | |
638 | default: | |
639 | return -EINVAL; | |
640 | } | |
641 | } else { | |
642 | /* | |
643 | * for capture | |
644 | * | |
645 | * data_num_max : number of ALSA free space | |
646 | * data_num : number of data in FSI fifo | |
647 | */ | |
648 | data_num_max = data_residue_num; | |
649 | data_num = fsi_get_fifo_data_num(fsi, is_play); | |
650 | ||
651 | switch (ch_width) { | |
652 | case 2: | |
653 | fn = fsi_dma_soft_pop16; | |
654 | break; | |
655 | case 4: | |
656 | fn = fsi_dma_soft_pop32; | |
657 | break; | |
658 | default: | |
659 | return -EINVAL; | |
660 | } | |
661 | } | |
a4d7d550 | 662 | |
d8b33534 | 663 | data_num = min(data_num, data_num_max); |
a4d7d550 | 664 | |
d8b33534 | 665 | fn(fsi, data_num); |
a4d7d550 | 666 | |
d8b33534 | 667 | /* update buff_offset */ |
93193c2b | 668 | io->buff_offset += fsi_num2offset(data_num, ch_width); |
a4d7d550 | 669 | |
d8b33534 | 670 | /* check fifo status */ |
47fc9a0a | 671 | if (!startup) { |
59c3b003 | 672 | struct snd_soc_dai *dai = fsi_get_dai(substream); |
e8c8b631 KM |
673 | u32 status = is_play ? |
674 | fsi_reg_read(fsi, DOFF_ST) : | |
675 | fsi_reg_read(fsi, DIFF_ST); | |
47fc9a0a KM |
676 | |
677 | if (status & ERR_OVER) | |
678 | dev_err(dai->dev, "over run\n"); | |
679 | if (status & ERR_UNDER) | |
680 | dev_err(dai->dev, "under run\n"); | |
59c3b003 | 681 | } |
e8c8b631 KM |
682 | |
683 | is_play ? | |
684 | fsi_reg_write(fsi, DOFF_ST, 0) : | |
685 | fsi_reg_write(fsi, DIFF_ST, 0); | |
59c3b003 | 686 | |
1c418d1f | 687 | if (over_period) |
a4d7d550 KM |
688 | snd_pcm_period_elapsed(substream); |
689 | ||
47fc9a0a | 690 | return 0; |
a4d7d550 KM |
691 | } |
692 | ||
47fc9a0a | 693 | static int fsi_data_pop(struct fsi_priv *fsi, int startup) |
07102f3c | 694 | { |
93193c2b | 695 | return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_CAPTURE); |
d8b33534 | 696 | } |
07102f3c | 697 | |
d8b33534 KM |
698 | static int fsi_data_push(struct fsi_priv *fsi, int startup) |
699 | { | |
93193c2b | 700 | return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_PLAYBACK); |
07102f3c KM |
701 | } |
702 | ||
a4d7d550 KM |
703 | static irqreturn_t fsi_interrupt(int irq, void *data) |
704 | { | |
71f6e064 | 705 | struct fsi_master *master = data; |
10ea76cc | 706 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
707 | |
708 | /* clear irq status */ | |
feb58cff KM |
709 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
710 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 | 711 | |
cf6edd00 | 712 | if (int_st & AB_IO(1, AO_SHIFT)) |
47fc9a0a | 713 | fsi_data_push(&master->fsia, 0); |
cf6edd00 | 714 | if (int_st & AB_IO(1, BO_SHIFT)) |
47fc9a0a | 715 | fsi_data_push(&master->fsib, 0); |
cf6edd00 | 716 | if (int_st & AB_IO(1, AI_SHIFT)) |
47fc9a0a | 717 | fsi_data_pop(&master->fsia, 0); |
cf6edd00 | 718 | if (int_st & AB_IO(1, BI_SHIFT)) |
47fc9a0a | 719 | fsi_data_pop(&master->fsib, 0); |
a4d7d550 | 720 | |
48d78e58 KM |
721 | fsi_irq_clear_status(&master->fsia); |
722 | fsi_irq_clear_status(&master->fsib); | |
a4d7d550 KM |
723 | |
724 | return IRQ_HANDLED; | |
725 | } | |
726 | ||
c8fe2574 KM |
727 | /* |
728 | * dai ops | |
729 | */ | |
a4d7d550 | 730 | |
a4d7d550 KM |
731 | static int fsi_dai_startup(struct snd_pcm_substream *substream, |
732 | struct snd_soc_dai *dai) | |
733 | { | |
71f6e064 | 734 | struct fsi_priv *fsi = fsi_get_priv(substream); |
3bc28070 | 735 | struct fsi_master *master = fsi_get_master(fsi); |
93193c2b KM |
736 | struct fsi_stream *io; |
737 | u32 flags = fsi_get_info_flags(fsi); | |
a4d7d550 | 738 | u32 fmt; |
a4d7d550 | 739 | u32 data; |
00545785 | 740 | int is_play = fsi_is_play(substream); |
a4d7d550 | 741 | int is_master; |
a4d7d550 | 742 | |
93193c2b KM |
743 | io = fsi_get_stream(fsi, is_play); |
744 | ||
785d1c45 | 745 | pm_runtime_get_sync(dai->dev); |
a4d7d550 KM |
746 | |
747 | /* CKG1 */ | |
748 | data = is_play ? (1 << 0) : (1 << 4); | |
749 | is_master = fsi_is_master_mode(fsi, is_play); | |
750 | if (is_master) | |
751 | fsi_reg_mask_set(fsi, CKG1, data, data); | |
752 | else | |
753 | fsi_reg_mask_set(fsi, CKG1, data, 0); | |
754 | ||
755 | /* clock inversion (CKG2) */ | |
756 | data = 0; | |
b427b44c KM |
757 | if (SH_FSI_LRM_INV & flags) |
758 | data |= 1 << 12; | |
759 | if (SH_FSI_BRM_INV & flags) | |
760 | data |= 1 << 8; | |
761 | if (SH_FSI_LRS_INV & flags) | |
762 | data |= 1 << 4; | |
763 | if (SH_FSI_BRS_INV & flags) | |
764 | data |= 1 << 0; | |
765 | ||
a4d7d550 KM |
766 | fsi_reg_write(fsi, CKG2, data); |
767 | ||
768 | /* do fmt, di fmt */ | |
769 | data = 0; | |
a4d7d550 KM |
770 | fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags); |
771 | switch (fmt) { | |
772 | case SH_FSI_FMT_MONO: | |
a7ffb52b | 773 | data = CR_MONO; |
93193c2b | 774 | io->chan_num = 1; |
a4d7d550 KM |
775 | break; |
776 | case SH_FSI_FMT_MONO_DELAY: | |
a7ffb52b | 777 | data = CR_MONO_D; |
93193c2b | 778 | io->chan_num = 1; |
a4d7d550 KM |
779 | break; |
780 | case SH_FSI_FMT_PCM: | |
a7ffb52b | 781 | data = CR_PCM; |
93193c2b | 782 | io->chan_num = 2; |
a4d7d550 KM |
783 | break; |
784 | case SH_FSI_FMT_I2S: | |
a7ffb52b | 785 | data = CR_I2S; |
93193c2b | 786 | io->chan_num = 2; |
a4d7d550 KM |
787 | break; |
788 | case SH_FSI_FMT_TDM: | |
93193c2b | 789 | io->chan_num = is_play ? |
a4d7d550 | 790 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); |
93193c2b | 791 | data = CR_TDM | (io->chan_num - 1); |
a4d7d550 KM |
792 | break; |
793 | case SH_FSI_FMT_TDM_DELAY: | |
93193c2b | 794 | io->chan_num = is_play ? |
a4d7d550 | 795 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); |
93193c2b | 796 | data = CR_TDM_D | (io->chan_num - 1); |
a4d7d550 | 797 | break; |
3bc28070 KM |
798 | case SH_FSI_FMT_SPDIF: |
799 | if (master->core->ver < 2) { | |
800 | dev_err(dai->dev, "This FSI can not use SPDIF\n"); | |
801 | return -EINVAL; | |
802 | } | |
f7d711e3 | 803 | data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM; |
93193c2b | 804 | io->chan_num = 2; |
3bc28070 | 805 | fsi_spdif_clk_ctrl(fsi, 1); |
f7d711e3 | 806 | fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); |
3bc28070 | 807 | break; |
a4d7d550 KM |
808 | default: |
809 | dev_err(dai->dev, "unknown format.\n"); | |
810 | return -EINVAL; | |
811 | } | |
e8c8b631 KM |
812 | is_play ? |
813 | fsi_reg_write(fsi, DO_FMT, data) : | |
814 | fsi_reg_write(fsi, DI_FMT, data); | |
a4d7d550 | 815 | |
10ea76cc KM |
816 | /* irq clear */ |
817 | fsi_irq_disable(fsi, is_play); | |
818 | fsi_irq_clear_status(fsi); | |
819 | ||
820 | /* fifo init */ | |
4a942b45 | 821 | fsi_fifo_init(fsi, is_play, dai); |
a4d7d550 | 822 | |
a68a3b4e | 823 | return 0; |
a4d7d550 KM |
824 | } |
825 | ||
826 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, | |
827 | struct snd_soc_dai *dai) | |
828 | { | |
71f6e064 | 829 | struct fsi_priv *fsi = fsi_get_priv(substream); |
00545785 | 830 | int is_play = fsi_is_play(substream); |
d4bc99b9 KM |
831 | struct fsi_master *master = fsi_get_master(fsi); |
832 | int (*set_rate)(struct device *dev, int is_porta, int rate, int enable); | |
a4d7d550 KM |
833 | |
834 | fsi_irq_disable(fsi, is_play); | |
835 | fsi_clk_ctrl(fsi, 0); | |
836 | ||
d4bc99b9 KM |
837 | set_rate = master->info->set_rate; |
838 | if (set_rate && fsi->rate) | |
839 | set_rate(dai->dev, fsi_is_port_a(fsi), fsi->rate, 0); | |
840 | fsi->rate = 0; | |
841 | ||
785d1c45 | 842 | pm_runtime_put_sync(dai->dev); |
a4d7d550 KM |
843 | } |
844 | ||
845 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
846 | struct snd_soc_dai *dai) | |
847 | { | |
71f6e064 | 848 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 | 849 | struct snd_pcm_runtime *runtime = substream->runtime; |
00545785 | 850 | int is_play = fsi_is_play(substream); |
a4d7d550 KM |
851 | int ret = 0; |
852 | ||
a4d7d550 KM |
853 | switch (cmd) { |
854 | case SNDRV_PCM_TRIGGER_START: | |
93193c2b | 855 | fsi_stream_push(fsi, is_play, substream, |
a4d7d550 KM |
856 | frames_to_bytes(runtime, runtime->buffer_size), |
857 | frames_to_bytes(runtime, runtime->period_size)); | |
47fc9a0a | 858 | ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1); |
9e261bbc | 859 | fsi_irq_enable(fsi, is_play); |
a4d7d550 KM |
860 | break; |
861 | case SNDRV_PCM_TRIGGER_STOP: | |
862 | fsi_irq_disable(fsi, is_play); | |
93193c2b | 863 | fsi_stream_pop(fsi, is_play); |
a4d7d550 KM |
864 | break; |
865 | } | |
866 | ||
867 | return ret; | |
868 | } | |
869 | ||
ccad7b44 KM |
870 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
871 | struct snd_pcm_hw_params *params, | |
872 | struct snd_soc_dai *dai) | |
873 | { | |
874 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
875 | struct fsi_master *master = fsi_get_master(fsi); | |
d4bc99b9 | 876 | int (*set_rate)(struct device *dev, int is_porta, int rate, int enable); |
ccad7b44 | 877 | int fsi_ver = master->core->ver; |
d4bc99b9 | 878 | long rate = params_rate(params); |
ccad7b44 KM |
879 | int ret; |
880 | ||
d4bc99b9 | 881 | set_rate = master->info->set_rate; |
ccad7b44 | 882 | if (!set_rate) |
ccad7b44 KM |
883 | return 0; |
884 | ||
d4bc99b9 KM |
885 | ret = set_rate(dai->dev, fsi_is_port_a(fsi), rate, 1); |
886 | if (ret < 0) /* error */ | |
887 | return ret; | |
ccad7b44 | 888 | |
d4bc99b9 | 889 | fsi->rate = rate; |
ccad7b44 KM |
890 | if (ret > 0) { |
891 | u32 data = 0; | |
892 | ||
893 | switch (ret & SH_FSI_ACKMD_MASK) { | |
894 | default: | |
895 | /* FALL THROUGH */ | |
896 | case SH_FSI_ACKMD_512: | |
897 | data |= (0x0 << 12); | |
898 | break; | |
899 | case SH_FSI_ACKMD_256: | |
900 | data |= (0x1 << 12); | |
901 | break; | |
902 | case SH_FSI_ACKMD_128: | |
903 | data |= (0x2 << 12); | |
904 | break; | |
905 | case SH_FSI_ACKMD_64: | |
906 | data |= (0x3 << 12); | |
907 | break; | |
908 | case SH_FSI_ACKMD_32: | |
909 | if (fsi_ver < 2) | |
910 | dev_err(dai->dev, "unsupported ACKMD\n"); | |
911 | else | |
912 | data |= (0x4 << 12); | |
913 | break; | |
914 | } | |
915 | ||
916 | switch (ret & SH_FSI_BPFMD_MASK) { | |
917 | default: | |
918 | /* FALL THROUGH */ | |
919 | case SH_FSI_BPFMD_32: | |
920 | data |= (0x0 << 8); | |
921 | break; | |
922 | case SH_FSI_BPFMD_64: | |
923 | data |= (0x1 << 8); | |
924 | break; | |
925 | case SH_FSI_BPFMD_128: | |
926 | data |= (0x2 << 8); | |
927 | break; | |
928 | case SH_FSI_BPFMD_256: | |
929 | data |= (0x3 << 8); | |
930 | break; | |
931 | case SH_FSI_BPFMD_512: | |
932 | data |= (0x4 << 8); | |
933 | break; | |
934 | case SH_FSI_BPFMD_16: | |
935 | if (fsi_ver < 2) | |
936 | dev_err(dai->dev, "unsupported ACKMD\n"); | |
937 | else | |
938 | data |= (0x7 << 8); | |
939 | break; | |
940 | } | |
941 | ||
942 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
943 | udelay(10); | |
944 | fsi_clk_ctrl(fsi, 1); | |
945 | ret = 0; | |
946 | } | |
ccad7b44 KM |
947 | |
948 | return ret; | |
949 | ||
950 | } | |
951 | ||
a4d7d550 KM |
952 | static struct snd_soc_dai_ops fsi_dai_ops = { |
953 | .startup = fsi_dai_startup, | |
954 | .shutdown = fsi_dai_shutdown, | |
955 | .trigger = fsi_dai_trigger, | |
ccad7b44 | 956 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
957 | }; |
958 | ||
c8fe2574 KM |
959 | /* |
960 | * pcm ops | |
961 | */ | |
a4d7d550 | 962 | |
a4d7d550 KM |
963 | static struct snd_pcm_hardware fsi_pcm_hardware = { |
964 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
965 | SNDRV_PCM_INFO_MMAP | | |
966 | SNDRV_PCM_INFO_MMAP_VALID | | |
967 | SNDRV_PCM_INFO_PAUSE, | |
968 | .formats = FSI_FMTS, | |
969 | .rates = FSI_RATES, | |
970 | .rate_min = 8000, | |
971 | .rate_max = 192000, | |
972 | .channels_min = 1, | |
973 | .channels_max = 2, | |
974 | .buffer_bytes_max = 64 * 1024, | |
975 | .period_bytes_min = 32, | |
976 | .period_bytes_max = 8192, | |
977 | .periods_min = 1, | |
978 | .periods_max = 32, | |
979 | .fifo_size = 256, | |
980 | }; | |
981 | ||
982 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
983 | { | |
984 | struct snd_pcm_runtime *runtime = substream->runtime; | |
985 | int ret = 0; | |
986 | ||
987 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
988 | ||
989 | ret = snd_pcm_hw_constraint_integer(runtime, | |
990 | SNDRV_PCM_HW_PARAM_PERIODS); | |
991 | ||
992 | return ret; | |
993 | } | |
994 | ||
995 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
996 | struct snd_pcm_hw_params *hw_params) | |
997 | { | |
998 | return snd_pcm_lib_malloc_pages(substream, | |
999 | params_buffer_bytes(hw_params)); | |
1000 | } | |
1001 | ||
1002 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
1003 | { | |
1004 | return snd_pcm_lib_free_pages(substream); | |
1005 | } | |
1006 | ||
1007 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
1008 | { | |
1009 | struct snd_pcm_runtime *runtime = substream->runtime; | |
71f6e064 | 1010 | struct fsi_priv *fsi = fsi_get_priv(substream); |
93193c2b | 1011 | struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream)); |
a4d7d550 KM |
1012 | long location; |
1013 | ||
93193c2b | 1014 | location = (io->buff_offset - 1); |
a4d7d550 KM |
1015 | if (location < 0) |
1016 | location = 0; | |
1017 | ||
1018 | return bytes_to_frames(runtime, location); | |
1019 | } | |
1020 | ||
1021 | static struct snd_pcm_ops fsi_pcm_ops = { | |
1022 | .open = fsi_pcm_open, | |
1023 | .ioctl = snd_pcm_lib_ioctl, | |
1024 | .hw_params = fsi_hw_params, | |
1025 | .hw_free = fsi_hw_free, | |
1026 | .pointer = fsi_pointer, | |
1027 | }; | |
1028 | ||
c8fe2574 KM |
1029 | /* |
1030 | * snd_soc_platform | |
1031 | */ | |
a4d7d550 | 1032 | |
a4d7d550 KM |
1033 | #define PREALLOC_BUFFER (32 * 1024) |
1034 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1035 | ||
1036 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1037 | { | |
1038 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1039 | } | |
1040 | ||
1041 | static int fsi_pcm_new(struct snd_card *card, | |
1042 | struct snd_soc_dai *dai, | |
1043 | struct snd_pcm *pcm) | |
1044 | { | |
1045 | /* | |
1046 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1047 | * in MMAP mode (i.e. aplay -M) | |
1048 | */ | |
1049 | return snd_pcm_lib_preallocate_pages_for_all( | |
1050 | pcm, | |
1051 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1052 | snd_dma_continuous_data(GFP_KERNEL), | |
1053 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1054 | } | |
1055 | ||
c8fe2574 KM |
1056 | /* |
1057 | * alsa struct | |
1058 | */ | |
a4d7d550 | 1059 | |
f0fba2ad | 1060 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1061 | { |
f0fba2ad | 1062 | .name = "fsia-dai", |
a4d7d550 KM |
1063 | .playback = { |
1064 | .rates = FSI_RATES, | |
1065 | .formats = FSI_FMTS, | |
1066 | .channels_min = 1, | |
1067 | .channels_max = 8, | |
1068 | }, | |
07102f3c KM |
1069 | .capture = { |
1070 | .rates = FSI_RATES, | |
1071 | .formats = FSI_FMTS, | |
1072 | .channels_min = 1, | |
1073 | .channels_max = 8, | |
1074 | }, | |
a4d7d550 KM |
1075 | .ops = &fsi_dai_ops, |
1076 | }, | |
1077 | { | |
f0fba2ad | 1078 | .name = "fsib-dai", |
a4d7d550 KM |
1079 | .playback = { |
1080 | .rates = FSI_RATES, | |
1081 | .formats = FSI_FMTS, | |
1082 | .channels_min = 1, | |
1083 | .channels_max = 8, | |
1084 | }, | |
07102f3c KM |
1085 | .capture = { |
1086 | .rates = FSI_RATES, | |
1087 | .formats = FSI_FMTS, | |
1088 | .channels_min = 1, | |
1089 | .channels_max = 8, | |
1090 | }, | |
a4d7d550 KM |
1091 | .ops = &fsi_dai_ops, |
1092 | }, | |
1093 | }; | |
a4d7d550 | 1094 | |
f0fba2ad LG |
1095 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1096 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1097 | .pcm_new = fsi_pcm_new, |
1098 | .pcm_free = fsi_pcm_free, | |
1099 | }; | |
a4d7d550 | 1100 | |
c8fe2574 KM |
1101 | /* |
1102 | * platform function | |
1103 | */ | |
a4d7d550 | 1104 | |
a4d7d550 KM |
1105 | static int fsi_probe(struct platform_device *pdev) |
1106 | { | |
71f6e064 | 1107 | struct fsi_master *master; |
cc780d38 | 1108 | const struct platform_device_id *id_entry; |
a4d7d550 | 1109 | struct resource *res; |
a4d7d550 KM |
1110 | unsigned int irq; |
1111 | int ret; | |
1112 | ||
cc780d38 KM |
1113 | id_entry = pdev->id_entry; |
1114 | if (!id_entry) { | |
1115 | dev_err(&pdev->dev, "unknown fsi device\n"); | |
1116 | return -ENODEV; | |
1117 | } | |
1118 | ||
a4d7d550 KM |
1119 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1120 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 1121 | if (!res || (int)irq <= 0) { |
a4d7d550 KM |
1122 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
1123 | ret = -ENODEV; | |
1124 | goto exit; | |
1125 | } | |
1126 | ||
1127 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
1128 | if (!master) { | |
1129 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
1130 | ret = -ENOMEM; | |
1131 | goto exit; | |
1132 | } | |
1133 | ||
1134 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
1135 | if (!master->base) { | |
1136 | ret = -ENXIO; | |
1137 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
1138 | goto exit_kfree; | |
1139 | } | |
1140 | ||
3bc28070 | 1141 | /* master setting */ |
a4d7d550 KM |
1142 | master->irq = irq; |
1143 | master->info = pdev->dev.platform_data; | |
3bc28070 KM |
1144 | master->core = (struct fsi_core *)id_entry->driver_data; |
1145 | spin_lock_init(&master->lock); | |
1146 | ||
1147 | /* FSI A setting */ | |
a4d7d550 | 1148 | master->fsia.base = master->base; |
71f6e064 | 1149 | master->fsia.master = master; |
3bc28070 KM |
1150 | |
1151 | /* FSI B setting */ | |
a4d7d550 | 1152 | master->fsib.base = master->base + 0x40; |
71f6e064 | 1153 | master->fsib.master = master; |
a4d7d550 | 1154 | |
785d1c45 KM |
1155 | pm_runtime_enable(&pdev->dev); |
1156 | pm_runtime_resume(&pdev->dev); | |
f0fba2ad | 1157 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 1158 | |
71f6e064 | 1159 | fsi_soft_all_reset(master); |
a4d7d550 | 1160 | |
cc780d38 KM |
1161 | ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, |
1162 | id_entry->name, master); | |
a4d7d550 KM |
1163 | if (ret) { |
1164 | dev_err(&pdev->dev, "irq request err\n"); | |
9ddc9aa9 | 1165 | goto exit_iounmap; |
a4d7d550 KM |
1166 | } |
1167 | ||
f0fba2ad | 1168 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
1169 | if (ret < 0) { |
1170 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1171 | goto exit_free_irq; | |
1172 | } | |
1173 | ||
f0fba2ad | 1174 | return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); |
a4d7d550 KM |
1175 | |
1176 | exit_free_irq: | |
1177 | free_irq(irq, master); | |
a4d7d550 KM |
1178 | exit_iounmap: |
1179 | iounmap(master->base); | |
785d1c45 | 1180 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
1181 | exit_kfree: |
1182 | kfree(master); | |
1183 | master = NULL; | |
1184 | exit: | |
1185 | return ret; | |
1186 | } | |
1187 | ||
1188 | static int fsi_remove(struct platform_device *pdev) | |
1189 | { | |
71f6e064 KM |
1190 | struct fsi_master *master; |
1191 | ||
f0fba2ad | 1192 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 1193 | |
f0fba2ad LG |
1194 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); |
1195 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 | 1196 | |
785d1c45 | 1197 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 1198 | |
a4d7d550 KM |
1199 | free_irq(master->irq, master); |
1200 | ||
1201 | iounmap(master->base); | |
1202 | kfree(master); | |
71f6e064 | 1203 | |
a4d7d550 KM |
1204 | return 0; |
1205 | } | |
1206 | ||
785d1c45 KM |
1207 | static int fsi_runtime_nop(struct device *dev) |
1208 | { | |
1209 | /* Runtime PM callback shared between ->runtime_suspend() | |
1210 | * and ->runtime_resume(). Simply returns success. | |
1211 | * | |
1212 | * This driver re-initializes all registers after | |
1213 | * pm_runtime_get_sync() anyway so there is no need | |
1214 | * to save and restore registers here. | |
1215 | */ | |
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | static struct dev_pm_ops fsi_pm_ops = { | |
1220 | .runtime_suspend = fsi_runtime_nop, | |
1221 | .runtime_resume = fsi_runtime_nop, | |
1222 | }; | |
1223 | ||
73b92c1f KM |
1224 | static struct fsi_core fsi1_core = { |
1225 | .ver = 1, | |
1226 | ||
1227 | /* Interrupt */ | |
cc780d38 KM |
1228 | .int_st = INT_ST, |
1229 | .iemsk = IEMSK, | |
1230 | .imsk = IMSK, | |
1231 | }; | |
1232 | ||
73b92c1f KM |
1233 | static struct fsi_core fsi2_core = { |
1234 | .ver = 2, | |
1235 | ||
1236 | /* Interrupt */ | |
cc780d38 KM |
1237 | .int_st = CPU_INT_ST, |
1238 | .iemsk = CPU_IEMSK, | |
1239 | .imsk = CPU_IMSK, | |
2b0e7302 KM |
1240 | .a_mclk = A_MST_CTLR, |
1241 | .b_mclk = B_MST_CTLR, | |
cc780d38 KM |
1242 | }; |
1243 | ||
1244 | static struct platform_device_id fsi_id_table[] = { | |
73b92c1f KM |
1245 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
1246 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
05c69450 | 1247 | {}, |
cc780d38 | 1248 | }; |
d85a6d7b | 1249 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 1250 | |
a4d7d550 KM |
1251 | static struct platform_driver fsi_driver = { |
1252 | .driver = { | |
f0fba2ad | 1253 | .name = "fsi-pcm-audio", |
785d1c45 | 1254 | .pm = &fsi_pm_ops, |
a4d7d550 KM |
1255 | }, |
1256 | .probe = fsi_probe, | |
1257 | .remove = fsi_remove, | |
cc780d38 | 1258 | .id_table = fsi_id_table, |
a4d7d550 KM |
1259 | }; |
1260 | ||
1261 | static int __init fsi_mobile_init(void) | |
1262 | { | |
1263 | return platform_driver_register(&fsi_driver); | |
1264 | } | |
1265 | ||
1266 | static void __exit fsi_mobile_exit(void) | |
1267 | { | |
1268 | platform_driver_unregister(&fsi_driver); | |
1269 | } | |
d85a6d7b | 1270 | |
a4d7d550 KM |
1271 | module_init(fsi_mobile_init); |
1272 | module_exit(fsi_mobile_exit); | |
1273 | ||
1274 | MODULE_LICENSE("GPL"); | |
1275 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1276 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); |