[linux-2.6-block.git] / sound / soc / rockchip / rockchip_i2s.c

// SPDX-License-Identifier: GPL-2.0-only
/* sound/soc/rockchip/rockchip_i2s.c
 *
 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
 *
 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
 * Author: Jianqun <jay.xu@rock-chips.com>
 */

#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/delay.h>
#include <linux/of_gpio.h>
#include <linux/of_device.h>
#include <linux/clk.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include <sound/dmaengine_pcm.h>

#include "rockchip_i2s.h"
#include "rockchip_pcm.h"

#define DRV_NAME "rockchip-i2s"

struct rk_i2s_pins {
	u32 reg_offset;
	u32 shift;
};

struct rk_i2s_dev {
	struct device *dev;

	struct clk *hclk;
	struct clk *mclk;

	struct snd_dmaengine_dai_dma_data capture_dma_data;
	struct snd_dmaengine_dai_dma_data playback_dma_data;

	struct regmap *regmap;
	struct regmap *grf;

/*
 * Used to indicate the tx/rx status.
 * I2S controller hopes to start the tx and rx together,
 * also to stop them when they are both try to stop.
*/
	bool tx_start;
	bool rx_start;
	bool is_master_mode;
	const struct rk_i2s_pins *pins;
};

static int i2s_runtime_suspend(struct device *dev)
{
	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);

	regcache_cache_only(i2s->regmap, true);
	clk_disable_unprepare(i2s->mclk);

	return 0;
}

static int i2s_runtime_resume(struct device *dev)
{
	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(i2s->mclk);
	if (ret) {
		dev_err(i2s->dev, "clock enable failed %d\n", ret);
		return ret;
	}

	regcache_cache_only(i2s->regmap, false);
	regcache_mark_dirty(i2s->regmap);

	ret = regcache_sync(i2s->regmap);
	if (ret)
		clk_disable_unprepare(i2s->mclk);

	return ret;
}

static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
{
	return snd_soc_dai_get_drvdata(dai);
}

static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
{
	unsigned int val = 0;
	int retry = 10;

	if (on) {
		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);

		regmap_update_bits(i2s->regmap, I2S_XFER,
				   I2S_XFER_TXS_START | I2S_XFER_RXS_START,
				   I2S_XFER_TXS_START | I2S_XFER_RXS_START);

		i2s->tx_start = true;
	} else {
		i2s->tx_start = false;

		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);

		if (!i2s->rx_start) {
			regmap_update_bits(i2s->regmap, I2S_XFER,
					   I2S_XFER_TXS_START |
					   I2S_XFER_RXS_START,
					   I2S_XFER_TXS_STOP |
					   I2S_XFER_RXS_STOP);

			udelay(150);
			regmap_update_bits(i2s->regmap, I2S_CLR,
					   I2S_CLR_TXC | I2S_CLR_RXC,
					   I2S_CLR_TXC | I2S_CLR_RXC);

			regmap_read(i2s->regmap, I2S_CLR, &val);

			/* Should wait for clear operation to finish */
			while (val) {
				regmap_read(i2s->regmap, I2S_CLR, &val);
				retry--;
				if (!retry) {
					dev_warn(i2s->dev, "fail to clear\n");
					break;
				}
			}
		}
	}
}

static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
{
	unsigned int val = 0;
	int retry = 10;

	if (on) {
		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);

		regmap_update_bits(i2s->regmap, I2S_XFER,
				   I2S_XFER_TXS_START | I2S_XFER_RXS_START,
				   I2S_XFER_TXS_START | I2S_XFER_RXS_START);

		i2s->rx_start = true;
	} else {
		i2s->rx_start = false;

		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);

		if (!i2s->tx_start) {
			regmap_update_bits(i2s->regmap, I2S_XFER,
					   I2S_XFER_TXS_START |
					   I2S_XFER_RXS_START,
					   I2S_XFER_TXS_STOP |
					   I2S_XFER_RXS_STOP);

			udelay(150);
			regmap_update_bits(i2s->regmap, I2S_CLR,
					   I2S_CLR_TXC | I2S_CLR_RXC,
					   I2S_CLR_TXC | I2S_CLR_RXC);

			regmap_read(i2s->regmap, I2S_CLR, &val);

			/* Should wait for clear operation to finish */
			while (val) {
				regmap_read(i2s->regmap, I2S_CLR, &val);
				retry--;
				if (!retry) {
					dev_warn(i2s->dev, "fail to clear\n");
					break;
				}
			}
		}
	}
}

static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
				unsigned int fmt)
{
	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	unsigned int mask = 0, val = 0;

	mask = I2S_CKR_MSS_MASK;
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* Set source clock in Master mode */
		val = I2S_CKR_MSS_MASTER;
		i2s->is_master_mode = true;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		val = I2S_CKR_MSS_SLAVE;
		i2s->is_master_mode = false;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);

	mask = I2S_CKR_CKP_MASK;
	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		val = I2S_CKR_CKP_NEG;
		break;
	case SND_SOC_DAIFMT_IB_NF:
		val = I2S_CKR_CKP_POS;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);

	mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		val = I2S_TXCR_IBM_RSJM;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		val = I2S_TXCR_IBM_LSJM;
		break;
	case SND_SOC_DAIFMT_I2S:
		val = I2S_TXCR_IBM_NORMAL;
		break;
	case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
		val = I2S_TXCR_TFS_PCM;
		break;
	case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
		val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);

	mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		val = I2S_RXCR_IBM_RSJM;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		val = I2S_RXCR_IBM_LSJM;
		break;
	case SND_SOC_DAIFMT_I2S:
		val = I2S_RXCR_IBM_NORMAL;
		break;
	case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
		val = I2S_RXCR_TFS_PCM;
		break;
	case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
		val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);

	return 0;
}

static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
				  struct snd_pcm_hw_params *params,
				  struct snd_soc_dai *dai)
{
	struct rk_i2s_dev *i2s = to_info(dai);
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	unsigned int val = 0;
	unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;

	if (i2s->is_master_mode) {
		mclk_rate = clk_get_rate(i2s->mclk);
		bclk_rate = 2 * 32 * params_rate(params);
		if (bclk_rate && mclk_rate % bclk_rate)
			return -EINVAL;

		div_bclk = mclk_rate / bclk_rate;
		div_lrck = bclk_rate / params_rate(params);
		regmap_update_bits(i2s->regmap, I2S_CKR,
				   I2S_CKR_MDIV_MASK,
				   I2S_CKR_MDIV(div_bclk));

		regmap_update_bits(i2s->regmap, I2S_CKR,
				   I2S_CKR_TSD_MASK |
				   I2S_CKR_RSD_MASK,
				   I2S_CKR_TSD(div_lrck) |
				   I2S_CKR_RSD(div_lrck));
	}

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		val |= I2S_TXCR_VDW(8);
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		val |= I2S_TXCR_VDW(16);
		break;
	case SNDRV_PCM_FORMAT_S20_3LE:
		val |= I2S_TXCR_VDW(20);
		break;
	case SNDRV_PCM_FORMAT_S24_LE:
		val |= I2S_TXCR_VDW(24);
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		val |= I2S_TXCR_VDW(32);
		break;
	default:
		return -EINVAL;
	}

	switch (params_channels(params)) {
	case 8:
		val |= I2S_CHN_8;
		break;
	case 6:
		val |= I2S_CHN_6;
		break;
	case 4:
		val |= I2S_CHN_4;
		break;
	case 2:
		val |= I2S_CHN_2;
		break;
	default:
		dev_err(i2s->dev, "invalid channel: %d\n",
			params_channels(params));
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
		regmap_update_bits(i2s->regmap, I2S_RXCR,
				   I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
				   val);
	else
		regmap_update_bits(i2s->regmap, I2S_TXCR,
				   I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
				   val);

	if (!IS_ERR(i2s->grf) && i2s->pins) {
		regmap_read(i2s->regmap, I2S_TXCR, &val);
		val &= I2S_TXCR_CSR_MASK;

		switch (val) {
		case I2S_CHN_4:
			val = I2S_IO_4CH_OUT_6CH_IN;
			break;
		case I2S_CHN_6:
			val = I2S_IO_6CH_OUT_4CH_IN;
			break;
		case I2S_CHN_8:
			val = I2S_IO_8CH_OUT_2CH_IN;
			break;
		default:
			val = I2S_IO_2CH_OUT_8CH_IN;
			break;
		}

		val <<= i2s->pins->shift;
		val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
		regmap_write(i2s->grf, i2s->pins->reg_offset, val);
	}

	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
			   I2S_DMACR_TDL(16));
	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
			   I2S_DMACR_RDL(16));

	val = I2S_CKR_TRCM_TXRX;
	if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates)
		val = I2S_CKR_TRCM_TXONLY;

	regmap_update_bits(i2s->regmap, I2S_CKR,
			   I2S_CKR_TRCM_MASK,
			   val);
	return 0;
}

static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
				int cmd, struct snd_soc_dai *dai)
{
	struct rk_i2s_dev *i2s = to_info(dai);
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			rockchip_snd_rxctrl(i2s, 1);
		else
			rockchip_snd_txctrl(i2s, 1);
		break;
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			rockchip_snd_rxctrl(i2s, 0);
		else
			rockchip_snd_txctrl(i2s, 0);
		break;
	default:
		ret = -EINVAL;
		break;
	}

	return ret;
}

static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
				   unsigned int freq, int dir)
{
	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	int ret;

	ret = clk_set_rate(i2s->mclk, freq);
	if (ret)
		dev_err(i2s->dev, "Fail to set mclk %d\n", ret);

	return ret;
}

static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
{
	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);

	dai->capture_dma_data = &i2s->capture_dma_data;
	dai->playback_dma_data = &i2s->playback_dma_data;

	return 0;
}

static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
	.hw_params = rockchip_i2s_hw_params,
	.set_sysclk = rockchip_i2s_set_sysclk,
	.set_fmt = rockchip_i2s_set_fmt,
	.trigger = rockchip_i2s_trigger,
};

static struct snd_soc_dai_driver rockchip_i2s_dai = {
	.probe = rockchip_i2s_dai_probe,
	.playback = {
		.stream_name = "Playback",
		.channels_min = 2,
		.channels_max = 8,
		.rates = SNDRV_PCM_RATE_8000_192000,
		.formats = (SNDRV_PCM_FMTBIT_S8 |
			    SNDRV_PCM_FMTBIT_S16_LE |
			    SNDRV_PCM_FMTBIT_S20_3LE |
			    SNDRV_PCM_FMTBIT_S24_LE |
			    SNDRV_PCM_FMTBIT_S32_LE),
	},
	.capture = {
		.stream_name = "Capture",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_192000,
		.formats = (SNDRV_PCM_FMTBIT_S8 |
			    SNDRV_PCM_FMTBIT_S16_LE |
			    SNDRV_PCM_FMTBIT_S20_3LE |
			    SNDRV_PCM_FMTBIT_S24_LE |
			    SNDRV_PCM_FMTBIT_S32_LE),
	},
	.ops = &rockchip_i2s_dai_ops,
	.symmetric_rates = 1,
};

static const struct snd_soc_component_driver rockchip_i2s_component = {
	.name = DRV_NAME,
};

static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_TXCR:
	case I2S_RXCR:
	case I2S_CKR:
	case I2S_DMACR:
	case I2S_INTCR:
	case I2S_XFER:
	case I2S_CLR:
	case I2S_TXDR:
		return true;
	default:
		return false;
	}
}

static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_TXCR:
	case I2S_RXCR:
	case I2S_CKR:
	case I2S_DMACR:
	case I2S_INTCR:
	case I2S_XFER:
	case I2S_CLR:
	case I2S_TXDR:
	case I2S_RXDR:
	case I2S_FIFOLR:
	case I2S_INTSR:
		return true;
	default:
		return false;
	}
}

static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_INTSR:
	case I2S_CLR:
	case I2S_FIFOLR:
	case I2S_TXDR:
	case I2S_RXDR:
		return true;
	default:
		return false;
	}
}

static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_RXDR:
		return true;
	default:
		return false;
	}
}

static const struct reg_default rockchip_i2s_reg_defaults[] = {
	{0x00, 0x0000000f},
	{0x04, 0x0000000f},
	{0x08, 0x00071f1f},
	{0x10, 0x001f0000},
	{0x14, 0x01f00000},
};

static const struct regmap_config rockchip_i2s_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = I2S_RXDR,
	.reg_defaults = rockchip_i2s_reg_defaults,
	.num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
	.writeable_reg = rockchip_i2s_wr_reg,
	.readable_reg = rockchip_i2s_rd_reg,
	.volatile_reg = rockchip_i2s_volatile_reg,
	.precious_reg = rockchip_i2s_precious_reg,
	.cache_type = REGCACHE_FLAT,
};

static const struct rk_i2s_pins rk3399_i2s_pins = {
	.reg_offset = 0xe220,
	.shift = 11,
};

static const struct of_device_id rockchip_i2s_match[] = {
	{ .compatible = "rockchip,rk3066-i2s", },
	{ .compatible = "rockchip,rk3188-i2s", },
	{ .compatible = "rockchip,rk3288-i2s", },
	{ .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
	{},
};

static int rockchip_i2s_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	const struct of_device_id *of_id;
	struct rk_i2s_dev *i2s;
	struct snd_soc_dai_driver *soc_dai;
	struct resource *res;
	void __iomem *regs;
	int ret;
	int val;

	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
	if (!i2s)
		return -ENOMEM;

	i2s->dev = &pdev->dev;

	i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
	if (!IS_ERR(i2s->grf)) {
		of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
		if (!of_id || !of_id->data)
			return -EINVAL;

		i2s->pins = of_id->data;
	}

	/* try to prepare related clocks */
	i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
	if (IS_ERR(i2s->hclk)) {
		dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
		return PTR_ERR(i2s->hclk);
	}
	ret = clk_prepare_enable(i2s->hclk);
	if (ret) {
		dev_err(i2s->dev, "hclock enable failed %d\n", ret);
		return ret;
	}

	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
	if (IS_ERR(i2s->mclk)) {
		dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
		return PTR_ERR(i2s->mclk);
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
					    &rockchip_i2s_regmap_config);
	if (IS_ERR(i2s->regmap)) {
		dev_err(&pdev->dev,
			"Failed to initialise managed register map\n");
		return PTR_ERR(i2s->regmap);
	}

	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	i2s->playback_dma_data.maxburst = 4;

	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	i2s->capture_dma_data.maxburst = 4;

	dev_set_drvdata(&pdev->dev, i2s);

	pm_runtime_enable(&pdev->dev);
	if (!pm_runtime_enabled(&pdev->dev)) {
		ret = i2s_runtime_resume(&pdev->dev);
		if (ret)
			goto err_pm_disable;
	}

	soc_dai = devm_kmemdup(&pdev->dev, &rockchip_i2s_dai,
			       sizeof(*soc_dai), GFP_KERNEL);
	if (!soc_dai) {
		ret = -ENOMEM;
		goto err_pm_disable;
	}

	if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
		if (val >= 2 && val <= 8)
			soc_dai->playback.channels_max = val;
	}

	if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
		if (val >= 2 && val <= 8)
			soc_dai->capture.channels_max = val;
	}

	ret = devm_snd_soc_register_component(&pdev->dev,
					      &rockchip_i2s_component,
					      soc_dai, 1);

	if (ret) {
		dev_err(&pdev->dev, "Could not register DAI\n");
		goto err_suspend;
	}

	ret = rockchip_pcm_platform_register(&pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "Could not register PCM\n");
		return ret;
	}

	return 0;

err_suspend:
	if (!pm_runtime_status_suspended(&pdev->dev))
		i2s_runtime_suspend(&pdev->dev);
err_pm_disable:
	pm_runtime_disable(&pdev->dev);

	return ret;
}

static int rockchip_i2s_remove(struct platform_device *pdev)
{
	struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		i2s_runtime_suspend(&pdev->dev);

	clk_disable_unprepare(i2s->hclk);

	return 0;
}

static const struct dev_pm_ops rockchip_i2s_pm_ops = {
	SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
			   NULL)
};

static struct platform_driver rockchip_i2s_driver = {
	.probe = rockchip_i2s_probe,
	.remove = rockchip_i2s_remove,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = of_match_ptr(rockchip_i2s_match),
		.pm = &rockchip_i2s_pm_ops,
	},
};
module_platform_driver(rockchip_i2s_driver);

MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
4495c89f JX	2	/* sound/soc/rockchip/rockchip_i2s.c
	3	*
	4	* ALSA SoC Audio Layer - Rockchip I2S Controller driver
	5	*
	6	* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
	7	* Author: Jianqun <jay.xu@rock-chips.com>
4495c89f JX	8	*/
4495c89f JX	9
1b21572f	10	#include <linux/module.h>
170abcaa	11	#include <linux/mfd/syscon.h>
4495c89f JX	12	#include <linux/delay.h>
4495c89f JX	13	#include <linux/of_gpio.h>
170abcaa	14	#include <linux/of_device.h>
4495c89f JX	15	#include <linux/clk.h>
	16	#include <linux/pm_runtime.h>
	17	#include <linux/regmap.h>
	18	#include <sound/pcm_params.h>
	19	#include <sound/dmaengine_pcm.h>
	20
	21	#include "rockchip_i2s.h"
75b31192	22	#include "rockchip_pcm.h"
4495c89f JX	23
	24	#define DRV_NAME "rockchip-i2s"
	25
170abcaa SZ	26	struct rk_i2s_pins {
	27	u32 reg_offset;
	28	u32 shift;
	29	};
	30
4495c89f JX	31	struct rk_i2s_dev {
	32	struct device *dev;
	33
	34	struct clk *hclk;
	35	struct clk *mclk;
	36
	37	struct snd_dmaengine_dai_dma_data capture_dma_data;
	38	struct snd_dmaengine_dai_dma_data playback_dma_data;
	39
	40	struct regmap *regmap;
170abcaa	41	struct regmap *grf;
4495c89f	42
a6e806c4 JK	43	/*
	44	* Used to indicate the tx/rx status.
	45	* I2S controller hopes to start the tx and rx together,
	46	* also to stop them when they are both try to stop.
	47	*/
	48	bool tx_start;
	49	bool rx_start;
2458c377	50	bool is_master_mode;
170abcaa	51	const struct rk_i2s_pins *pins;
4495c89f JX	52	};
	53
	54	static int i2s_runtime_suspend(struct device *dev)
	55	{
	56	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
	57
f0447f6c	58	regcache_cache_only(i2s->regmap, true);
4495c89f JX	59	clk_disable_unprepare(i2s->mclk);
	60
	61	return 0;
	62	}
	63
	64	static int i2s_runtime_resume(struct device *dev)
	65	{
	66	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
	67	int ret;
	68
	69	ret = clk_prepare_enable(i2s->mclk);
	70	if (ret) {
	71	dev_err(i2s->dev, "clock enable failed %d\n", ret);
	72	return ret;
	73	}
	74
f0447f6c SZ	75	regcache_cache_only(i2s->regmap, false);
	76	regcache_mark_dirty(i2s->regmap);
	77
	78	ret = regcache_sync(i2s->regmap);
	79	if (ret)
	80	clk_disable_unprepare(i2s->mclk);
	81
	82	return ret;
4495c89f JX	83	}
	84
	85	static inline struct rk_i2s_dev to_info(struct snd_soc_dai dai)
	86	{
	87	return snd_soc_dai_get_drvdata(dai);
	88	}
	89
	90	static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
	91	{
	92	unsigned int val = 0;
	93	int retry = 10;
	94
	95	if (on) {
	96	regmap_update_bits(i2s->regmap, I2S_DMACR,
	97	I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
	98
	99	regmap_update_bits(i2s->regmap, I2S_XFER,
7e885d21 JK	100	I2S_XFER_TXS_START \| I2S_XFER_RXS_START,
7e885d21 JK	101	I2S_XFER_TXS_START \| I2S_XFER_RXS_START);
a6e806c4 JK	102
a6e806c4 JK	103	i2s->tx_start = true;
4495c89f	104	} else {
a6e806c4 JK	105	i2s->tx_start = false;
a6e806c4 JK	106
4495c89f	107	regmap_update_bits(i2s->regmap, I2S_DMACR,
4c5258ac	108	I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
4495c89f	109
7e885d21 JK	110	if (!i2s->rx_start) {
	111	regmap_update_bits(i2s->regmap, I2S_XFER,
	112	I2S_XFER_TXS_START \|
	113	I2S_XFER_RXS_START,
	114	I2S_XFER_TXS_STOP \|
	115	I2S_XFER_RXS_STOP);
4495c89f	116
5894b91d	117	udelay(150);
7e885d21 JK	118	regmap_update_bits(i2s->regmap, I2S_CLR,
	119	I2S_CLR_TXC \| I2S_CLR_RXC,
	120	I2S_CLR_TXC \| I2S_CLR_RXC);
4495c89f	121
eba65d17	122	regmap_read(i2s->regmap, I2S_CLR, &val);
7e885d21 JK	123
	124	/* Should wait for clear operation to finish */
	125	while (val) {
	126	regmap_read(i2s->regmap, I2S_CLR, &val);
	127	retry--;
	128	if (!retry) {
	129	dev_warn(i2s->dev, "fail to clear\n");
	130	break;
	131	}
4495c89f JX	132	}
	133	}
	134	}
	135	}
	136
	137	static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
	138	{
	139	unsigned int val = 0;
	140	int retry = 10;
	141
	142	if (on) {
	143	regmap_update_bits(i2s->regmap, I2S_DMACR,
	144	I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
	145
	146	regmap_update_bits(i2s->regmap, I2S_XFER,
7e885d21 JK	147	I2S_XFER_TXS_START \| I2S_XFER_RXS_START,
7e885d21 JK	148	I2S_XFER_TXS_START \| I2S_XFER_RXS_START);
a6e806c4 JK	149
a6e806c4 JK	150	i2s->rx_start = true;
4495c89f	151	} else {
a6e806c4 JK	152	i2s->rx_start = false;
a6e806c4 JK	153
4495c89f JX	154	regmap_update_bits(i2s->regmap, I2S_DMACR,
	155	I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
	156
7e885d21 JK	157	if (!i2s->tx_start) {
	158	regmap_update_bits(i2s->regmap, I2S_XFER,
	159	I2S_XFER_TXS_START \|
	160	I2S_XFER_RXS_START,
	161	I2S_XFER_TXS_STOP \|
	162	I2S_XFER_RXS_STOP);
4495c89f	163
5894b91d	164	udelay(150);
7e885d21 JK	165	regmap_update_bits(i2s->regmap, I2S_CLR,
	166	I2S_CLR_TXC \| I2S_CLR_RXC,
	167	I2S_CLR_TXC \| I2S_CLR_RXC);
4495c89f	168
eba65d17	169	regmap_read(i2s->regmap, I2S_CLR, &val);
7e885d21 JK	170
	171	/* Should wait for clear operation to finish */
	172	while (val) {
	173	regmap_read(i2s->regmap, I2S_CLR, &val);
	174	retry--;
	175	if (!retry) {
	176	dev_warn(i2s->dev, "fail to clear\n");
	177	break;
	178	}
4495c89f JX	179	}
	180	}
	181	}
	182	}
	183
	184	static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
	185	unsigned int fmt)
	186	{
	187	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	188	unsigned int mask = 0, val = 0;
	189
07833d88	190	mask = I2S_CKR_MSS_MASK;
4495c89f JX	191	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4495c89f JX	192	case SND_SOC_DAIFMT_CBS_CFS:
07833d88 J	193	/* Set source clock in Master mode */
07833d88 J	194	val = I2S_CKR_MSS_MASTER;
2458c377	195	i2s->is_master_mode = true;
4495c89f JX	196	break;
4495c89f JX	197	case SND_SOC_DAIFMT_CBM_CFM:
07833d88	198	val = I2S_CKR_MSS_SLAVE;
2458c377	199	i2s->is_master_mode = false;
4495c89f JX	200	break;
	201	default:
	202	return -EINVAL;
	203	}
	204
	205	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
	206
ec2212c4	207	mask = I2S_CKR_CKP_MASK;
	208	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	209	case SND_SOC_DAIFMT_NB_NF:
	210	val = I2S_CKR_CKP_NEG;
	211	break;
	212	case SND_SOC_DAIFMT_IB_NF:
	213	val = I2S_CKR_CKP_POS;
	214	break;
	215	default:
	216	return -EINVAL;
	217	}
	218
	219	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
	220
	221	mask = I2S_TXCR_IBM_MASK \| I2S_TXCR_TFS_MASK \| I2S_TXCR_PBM_MASK;
4495c89f JX	222	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	223	case SND_SOC_DAIFMT_RIGHT_J:
	224	val = I2S_TXCR_IBM_RSJM;
	225	break;
	226	case SND_SOC_DAIFMT_LEFT_J:
	227	val = I2S_TXCR_IBM_LSJM;
	228	break;
	229	case SND_SOC_DAIFMT_I2S:
	230	val = I2S_TXCR_IBM_NORMAL;
	231	break;
ec2212c4	232	case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
	233	val = I2S_TXCR_TFS_PCM;
	234	break;
	235	case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
	236	val = I2S_TXCR_TFS_PCM \| I2S_TXCR_PBM_MODE(1);
	237	break;
4495c89f JX	238	default:
	239	return -EINVAL;
	240	}
	241
	242	regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
	243
ec2212c4	244	mask = I2S_RXCR_IBM_MASK \| I2S_RXCR_TFS_MASK \| I2S_RXCR_PBM_MASK;
4495c89f JX	245	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	246	case SND_SOC_DAIFMT_RIGHT_J:
	247	val = I2S_RXCR_IBM_RSJM;
	248	break;
	249	case SND_SOC_DAIFMT_LEFT_J:
	250	val = I2S_RXCR_IBM_LSJM;
	251	break;
	252	case SND_SOC_DAIFMT_I2S:
	253	val = I2S_RXCR_IBM_NORMAL;
	254	break;
ec2212c4	255	case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
	256	val = I2S_RXCR_TFS_PCM;
	257	break;
	258	case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
	259	val = I2S_RXCR_TFS_PCM \| I2S_RXCR_PBM_MODE(1);
	260	break;
4495c89f JX	261	default:
	262	return -EINVAL;
	263	}
	264
	265	regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
	266
	267	return 0;
	268	}
	269
	270	static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
	271	struct snd_pcm_hw_params *params,
	272	struct snd_soc_dai *dai)
	273	{
	274	struct rk_i2s_dev *i2s = to_info(dai);
b3f2dcdd	275	struct snd_soc_pcm_runtime *rtd = substream->private_data;
4495c89f	276	unsigned int val = 0;
2458c377 CW	277	unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
	278
	279	if (i2s->is_master_mode) {
	280	mclk_rate = clk_get_rate(i2s->mclk);
	281	bclk_rate = 2 * 32 * params_rate(params);
	282	if (bclk_rate && mclk_rate % bclk_rate)
	283	return -EINVAL;
	284
	285	div_bclk = mclk_rate / bclk_rate;
	286	div_lrck = bclk_rate / params_rate(params);
	287	regmap_update_bits(i2s->regmap, I2S_CKR,
	288	I2S_CKR_MDIV_MASK,
	289	I2S_CKR_MDIV(div_bclk));
	290
	291	regmap_update_bits(i2s->regmap, I2S_CKR,
	292	I2S_CKR_TSD_MASK \|
	293	I2S_CKR_RSD_MASK,
	294	I2S_CKR_TSD(div_lrck) \|
	295	I2S_CKR_RSD(div_lrck));
	296	}
4495c89f JX	297
	298	switch (params_format(params)) {
	299	case SNDRV_PCM_FORMAT_S8:
	300	val \|= I2S_TXCR_VDW(8);
	301	break;
	302	case SNDRV_PCM_FORMAT_S16_LE:
	303	val \|= I2S_TXCR_VDW(16);
	304	break;
	305	case SNDRV_PCM_FORMAT_S20_3LE:
	306	val \|= I2S_TXCR_VDW(20);
	307	break;
	308	case SNDRV_PCM_FORMAT_S24_LE:
	309	val \|= I2S_TXCR_VDW(24);
	310	break;
4ab936d1 MT	311	case SNDRV_PCM_FORMAT_S32_LE:
	312	val \|= I2S_TXCR_VDW(32);
	313	break;
4495c89f JX	314	default:
	315	return -EINVAL;
	316	}
	317
4c9c018b SZ	318	switch (params_channels(params)) {
	319	case 8:
	320	val \|= I2S_CHN_8;
	321	break;
	322	case 6:
	323	val \|= I2S_CHN_6;
	324	break;
	325	case 4:
	326	val \|= I2S_CHN_4;
	327	break;
	328	case 2:
	329	val \|= I2S_CHN_2;
	330	break;
	331	default:
	332	dev_err(i2s->dev, "invalid channel: %d\n",
	333	params_channels(params));
	334	return -EINVAL;
	335	}
	336
	337	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	338	regmap_update_bits(i2s->regmap, I2S_RXCR,
	339	I2S_RXCR_VDW_MASK \| I2S_RXCR_CSR_MASK,
	340	val);
	341	else
	342	regmap_update_bits(i2s->regmap, I2S_TXCR,
	343	I2S_TXCR_VDW_MASK \| I2S_TXCR_CSR_MASK,
	344	val);
	345
170abcaa SZ	346	if (!IS_ERR(i2s->grf) && i2s->pins) {
	347	regmap_read(i2s->regmap, I2S_TXCR, &val);
	348	val &= I2S_TXCR_CSR_MASK;
	349
	350	switch (val) {
	351	case I2S_CHN_4:
	352	val = I2S_IO_4CH_OUT_6CH_IN;
	353	break;
	354	case I2S_CHN_6:
	355	val = I2S_IO_6CH_OUT_4CH_IN;
	356	break;
	357	case I2S_CHN_8:
	358	val = I2S_IO_8CH_OUT_2CH_IN;
	359	break;
	360	default:
	361	val = I2S_IO_2CH_OUT_8CH_IN;
	362	break;
	363	}
	364
	365	val <<= i2s->pins->shift;
	366	val \|= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
	367	regmap_write(i2s->grf, i2s->pins->reg_offset, val);
	368	}
	369
bba14312 JX	370	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
	371	I2S_DMACR_TDL(16));
	372	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
	373	I2S_DMACR_RDL(16));
4495c89f	374
b3f2dcdd	375	val = I2S_CKR_TRCM_TXRX;
359d9abd SZ	376	if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates)
359d9abd SZ	377	val = I2S_CKR_TRCM_TXONLY;
b3f2dcdd SZ	378
	379	regmap_update_bits(i2s->regmap, I2S_CKR,
	380	I2S_CKR_TRCM_MASK,
	381	val);
4495c89f JX	382	return 0;
	383	}
	384
	385	static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
	386	int cmd, struct snd_soc_dai *dai)
	387	{
	388	struct rk_i2s_dev *i2s = to_info(dai);
	389	int ret = 0;
	390
	391	switch (cmd) {
	392	case SNDRV_PCM_TRIGGER_START:
	393	case SNDRV_PCM_TRIGGER_RESUME:
	394	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	395	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	396	rockchip_snd_rxctrl(i2s, 1);
	397	else
	398	rockchip_snd_txctrl(i2s, 1);
	399	break;
	400	case SNDRV_PCM_TRIGGER_SUSPEND:
	401	case SNDRV_PCM_TRIGGER_STOP:
	402	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	403	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	404	rockchip_snd_rxctrl(i2s, 0);
	405	else
	406	rockchip_snd_txctrl(i2s, 0);
	407	break;
	408	default:
	409	ret = -EINVAL;
	410	break;
	411	}
	412
	413	return ret;
	414	}
	415
	416	static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
	417	unsigned int freq, int dir)
	418	{
	419	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	420	int ret;
	421
	422	ret = clk_set_rate(i2s->mclk, freq);
	423	if (ret)
	424	dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
	425
	426	return ret;
	427	}
	428
3b40a802 J	429	static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
	430	{
	431	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
	432
	433	dai->capture_dma_data = &i2s->capture_dma_data;
	434	dai->playback_dma_data = &i2s->playback_dma_data;
	435
	436	return 0;
	437	}
	438
4495c89f JX	439	static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
	440	.hw_params = rockchip_i2s_hw_params,
	441	.set_sysclk = rockchip_i2s_set_sysclk,
	442	.set_fmt = rockchip_i2s_set_fmt,
	443	.trigger = rockchip_i2s_trigger,
	444	};
	445
	446	static struct snd_soc_dai_driver rockchip_i2s_dai = {
3b40a802	447	.probe = rockchip_i2s_dai_probe,
4495c89f	448	.playback = {
3b40a802	449	.stream_name = "Playback",
4495c89f JX	450	.channels_min = 2,
	451	.channels_max = 8,
	452	.rates = SNDRV_PCM_RATE_8000_192000,
	453	.formats = (SNDRV_PCM_FMTBIT_S8 \|
	454	SNDRV_PCM_FMTBIT_S16_LE \|
	455	SNDRV_PCM_FMTBIT_S20_3LE \|
4ab936d1 MT	456	SNDRV_PCM_FMTBIT_S24_LE \|
4ab936d1 MT	457	SNDRV_PCM_FMTBIT_S32_LE),
4495c89f JX	458	},
4495c89f JX	459	.capture = {
3b40a802	460	.stream_name = "Capture",
789e162a	461	.channels_min = 2,
4495c89f JX	462	.channels_max = 2,
	463	.rates = SNDRV_PCM_RATE_8000_192000,
	464	.formats = (SNDRV_PCM_FMTBIT_S8 \|
	465	SNDRV_PCM_FMTBIT_S16_LE \|
	466	SNDRV_PCM_FMTBIT_S20_3LE \|
4ab936d1 MT	467	SNDRV_PCM_FMTBIT_S24_LE \|
4ab936d1 MT	468	SNDRV_PCM_FMTBIT_S32_LE),
4495c89f JX	469	},
4495c89f JX	470	.ops = &rockchip_i2s_dai_ops,
a12d159d	471	.symmetric_rates = 1,
4495c89f JX	472	};
	473
	474	static const struct snd_soc_component_driver rockchip_i2s_component = {
	475	.name = DRV_NAME,
	476	};
	477
	478	static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
	479	{
	480	switch (reg) {
	481	case I2S_TXCR:
	482	case I2S_RXCR:
	483	case I2S_CKR:
	484	case I2S_DMACR:
	485	case I2S_INTCR:
	486	case I2S_XFER:
	487	case I2S_CLR:
	488	case I2S_TXDR:
	489	return true;
	490	default:
	491	return false;
	492	}
	493	}
	494
	495	static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
	496	{
	497	switch (reg) {
	498	case I2S_TXCR:
	499	case I2S_RXCR:
	500	case I2S_CKR:
	501	case I2S_DMACR:
	502	case I2S_INTCR:
	503	case I2S_XFER:
	504	case I2S_CLR:
c66234cf	505	case I2S_TXDR:
4495c89f	506	case I2S_RXDR:
2f1e93f8 J	507	case I2S_FIFOLR:
2f1e93f8 J	508	case I2S_INTSR:
4495c89f JX	509	return true;
	510	default:
	511	return false;
	512	}
	513	}
	514
	515	static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
	516	{
	517	switch (reg) {
4495c89f	518	case I2S_INTSR:
2f1e93f8	519	case I2S_CLR:
c66234cf JK	520	case I2S_FIFOLR:
	521	case I2S_TXDR:
	522	case I2S_RXDR:
4495c89f JX	523	return true;
	524	default:
	525	return false;
	526	}
	527	}
	528
	529	static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
	530	{
	531	switch (reg) {
c66234cf JK	532	case I2S_RXDR:
c66234cf JK	533	return true;
4495c89f JX	534	default:
	535	return false;
	536	}
	537	}
	538
ea2e5b96 SZ	539	static const struct reg_default rockchip_i2s_reg_defaults[] = {
	540	{0x00, 0x0000000f},
	541	{0x04, 0x0000000f},
	542	{0x08, 0x00071f1f},
	543	{0x10, 0x001f0000},
	544	{0x14, 0x01f00000},
	545	};
	546
4495c89f JX	547	static const struct regmap_config rockchip_i2s_regmap_config = {
	548	.reg_bits = 32,
	549	.reg_stride = 4,
	550	.val_bits = 32,
	551	.max_register = I2S_RXDR,
ea2e5b96 SZ	552	.reg_defaults = rockchip_i2s_reg_defaults,
ea2e5b96 SZ	553	.num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
4495c89f JX	554	.writeable_reg = rockchip_i2s_wr_reg,
	555	.readable_reg = rockchip_i2s_rd_reg,
	556	.volatile_reg = rockchip_i2s_volatile_reg,
	557	.precious_reg = rockchip_i2s_precious_reg,
	558	.cache_type = REGCACHE_FLAT,
	559	};
	560
170abcaa SZ	561	static const struct rk_i2s_pins rk3399_i2s_pins = {
	562	.reg_offset = 0xe220,
	563	.shift = 11,
	564	};
	565
	566	static const struct of_device_id rockchip_i2s_match[] = {
	567	{ .compatible = "rockchip,rk3066-i2s", },
	568	{ .compatible = "rockchip,rk3188-i2s", },
	569	{ .compatible = "rockchip,rk3288-i2s", },
	570	{ .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
	571	{},
	572	};
	573
4495c89f JX	574	static int rockchip_i2s_probe(struct platform_device *pdev)
4495c89f JX	575	{
4c9c018b	576	struct device_node *node = pdev->dev.of_node;
170abcaa	577	const struct of_device_id *of_id;
4495c89f	578	struct rk_i2s_dev *i2s;
c4f9374d	579	struct snd_soc_dai_driver *soc_dai;
4495c89f JX	580	struct resource *res;
	581	void __iomem *regs;
	582	int ret;
4c9c018b	583	int val;
4495c89f JX	584
4495c89f JX	585	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
b48b2710	586	if (!i2s)
4495c89f	587	return -ENOMEM;
4495c89f	588
170abcaa SZ	589	i2s->dev = &pdev->dev;
	590
	591	i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
	592	if (!IS_ERR(i2s->grf)) {
	593	of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
	594	if (!of_id \|\| !of_id->data)
	595	return -EINVAL;
	596
	597	i2s->pins = of_id->data;
	598	}
	599
4495c89f JX	600	/* try to prepare related clocks */
	601	i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
	602	if (IS_ERR(i2s->hclk)) {
	603	dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
	604	return PTR_ERR(i2s->hclk);
	605	}
01605ad1 J	606	ret = clk_prepare_enable(i2s->hclk);
	607	if (ret) {
	608	dev_err(i2s->dev, "hclock enable failed %d\n", ret);
	609	return ret;
	610	}
4495c89f JX	611
	612	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
	613	if (IS_ERR(i2s->mclk)) {
	614	dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
	615	return PTR_ERR(i2s->mclk);
	616	}
	617
	618	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	619	regs = devm_ioremap_resource(&pdev->dev, res);
55b21944	620	if (IS_ERR(regs))
4495c89f	621	return PTR_ERR(regs);
4495c89f JX	622
	623	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
	624	&rockchip_i2s_regmap_config);
	625	if (IS_ERR(i2s->regmap)) {
	626	dev_err(&pdev->dev,
	627	"Failed to initialise managed register map\n");
	628	return PTR_ERR(i2s->regmap);
	629	}
	630
	631	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
	632	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
27fd36ab	633	i2s->playback_dma_data.maxburst = 4;
4495c89f JX	634
	635	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
	636	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
27fd36ab	637	i2s->capture_dma_data.maxburst = 4;
4495c89f	638
4495c89f JX	639	dev_set_drvdata(&pdev->dev, i2s);
	640
	641	pm_runtime_enable(&pdev->dev);
	642	if (!pm_runtime_enabled(&pdev->dev)) {
	643	ret = i2s_runtime_resume(&pdev->dev);
	644	if (ret)
	645	goto err_pm_disable;
	646	}
	647
33c0f552	648	soc_dai = devm_kmemdup(&pdev->dev, &rockchip_i2s_dai,
c4f9374d	649	sizeof(*soc_dai), GFP_KERNEL);
c3a3d3c4	650	if (!soc_dai) {
33c0f552	651	ret = -ENOMEM;
c3a3d3c4 CJ	652	goto err_pm_disable;
c3a3d3c4 CJ	653	}
c4f9374d	654
c4f9374d SZ	655	if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
	656	if (val >= 2 && val <= 8)
	657	soc_dai->playback.channels_max = val;
	658	}
	659
4c9c018b	660	if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
789e162a	661	if (val >= 2 && val <= 8)
c4f9374d	662	soc_dai->capture.channels_max = val;
4c9c018b SZ	663	}
4c9c018b SZ	664
4495c89f JX	665	ret = devm_snd_soc_register_component(&pdev->dev,
4495c89f JX	666	&rockchip_i2s_component,
c4f9374d SZ	667	soc_dai, 1);
c4f9374d SZ	668
4495c89f JX	669	if (ret) {
	670	dev_err(&pdev->dev, "Could not register DAI\n");
	671	goto err_suspend;
	672	}
	673
75b31192	674	ret = rockchip_pcm_platform_register(&pdev->dev);
4495c89f JX	675	if (ret) {
4495c89f JX	676	dev_err(&pdev->dev, "Could not register PCM\n");
ebb75c0b	677	return ret;
4495c89f JX	678	}
	679
	680	return 0;
	681
4495c89f JX	682	err_suspend:
	683	if (!pm_runtime_status_suspended(&pdev->dev))
	684	i2s_runtime_suspend(&pdev->dev);
	685	err_pm_disable:
	686	pm_runtime_disable(&pdev->dev);
	687
	688	return ret;
	689	}
	690
	691	static int rockchip_i2s_remove(struct platform_device *pdev)
	692	{
	693	struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
	694
	695	pm_runtime_disable(&pdev->dev);
	696	if (!pm_runtime_status_suspended(&pdev->dev))
	697	i2s_runtime_suspend(&pdev->dev);
	698
4495c89f	699	clk_disable_unprepare(i2s->hclk);
4495c89f JX	700
	701	return 0;
	702	}
	703
4495c89f JX	704	static const struct dev_pm_ops rockchip_i2s_pm_ops = {
	705	SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
	706	NULL)
	707	};
	708
	709	static struct platform_driver rockchip_i2s_driver = {
	710	.probe = rockchip_i2s_probe,
	711	.remove = rockchip_i2s_remove,
	712	.driver = {
	713	.name = DRV_NAME,
4495c89f JX	714	.of_match_table = of_match_ptr(rockchip_i2s_match),
	715	.pm = &rockchip_i2s_pm_ops,
	716	},
	717	};
	718	module_platform_driver(rockchip_i2s_driver);
	719
	720	MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
	721	MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
	722	MODULE_LICENSE("GPL v2");
	723	MODULE_ALIAS("platform:" DRV_NAME);
	724	MODULE_DEVICE_TABLE(of, rockchip_i2s_match);