[linux-2.6-block.git] / sound / soc / qcom / lpass-cpu.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
 *
 * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS
 */

#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"

static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
		unsigned int freq, int dir)
{
	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
	int ret;

	ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq);
	if (ret)
		dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n",
			freq, ret);

	return ret;
}

static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
		struct snd_soc_dai *dai)
{
	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
	int ret;

	ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]);
	if (ret) {
		dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
		return ret;
	}

	ret = clk_prepare_enable(drvdata->mi2s_bit_clk[dai->driver->id]);
	if (ret) {
		dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
		clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
		return ret;
	}

	return 0;
}

static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
		struct snd_soc_dai *dai)
{
	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);

	clk_disable_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);

	clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
}

static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
	snd_pcm_format_t format = params_format(params);
	unsigned int channels = params_channels(params);
	unsigned int rate = params_rate(params);
	unsigned int regval;
	int bitwidth, ret;

	bitwidth = snd_pcm_format_width(format);
	if (bitwidth < 0) {
		dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth);
		return bitwidth;
	}

	regval = LPAIF_I2SCTL_LOOPBACK_DISABLE |
			LPAIF_I2SCTL_WSSRC_INTERNAL;

	switch (bitwidth) {
	case 16:
		regval |= LPAIF_I2SCTL_BITWIDTH_16;
		break;
	case 24:
		regval |= LPAIF_I2SCTL_BITWIDTH_24;
		break;
	case 32:
		regval |= LPAIF_I2SCTL_BITWIDTH_32;
		break;
	default:
		dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth);
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		switch (channels) {
		case 1:
			regval |= LPAIF_I2SCTL_SPKMODE_SD0;
			regval |= LPAIF_I2SCTL_SPKMONO_MONO;
			break;
		case 2:
			regval |= LPAIF_I2SCTL_SPKMODE_SD0;
			regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
			break;
		case 4:
			regval |= LPAIF_I2SCTL_SPKMODE_QUAD01;
			regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
			break;
		case 6:
			regval |= LPAIF_I2SCTL_SPKMODE_6CH;
			regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
			break;
		case 8:
			regval |= LPAIF_I2SCTL_SPKMODE_8CH;
			regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
			break;
		default:
			dev_err(dai->dev, "invalid channels given: %u\n",
				channels);
			return -EINVAL;
		}
	} else {
		switch (channels) {
		case 1:
			regval |= LPAIF_I2SCTL_MICMODE_SD0;
			regval |= LPAIF_I2SCTL_MICMONO_MONO;
			break;
		case 2:
			regval |= LPAIF_I2SCTL_MICMODE_SD0;
			regval |= LPAIF_I2SCTL_MICMONO_STEREO;
			break;
		case 4:
			regval |= LPAIF_I2SCTL_MICMODE_QUAD01;
			regval |= LPAIF_I2SCTL_MICMONO_STEREO;
			break;
		case 6:
			regval |= LPAIF_I2SCTL_MICMODE_6CH;
			regval |= LPAIF_I2SCTL_MICMONO_STEREO;
			break;
		case 8:
			regval |= LPAIF_I2SCTL_MICMODE_8CH;
			regval |= LPAIF_I2SCTL_MICMONO_STEREO;
			break;
		default:
			dev_err(dai->dev, "invalid channels given: %u\n",
				channels);
			return -EINVAL;
		}
	}

	ret = regmap_write(drvdata->lpaif_map,
			   LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id),
			   regval);
	if (ret) {
		dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
		return ret;
	}

	ret = clk_set_rate(drvdata->mi2s_bit_clk[dai->driver->id],
			   rate * bitwidth * 2);
	if (ret) {
		dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n",
			rate * bitwidth * 2, ret);
		return ret;
	}

	return 0;
}

static int lpass_cpu_daiops_hw_free(struct snd_pcm_substream *substream,
		struct snd_soc_dai *dai)
{
	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
	int ret;

	ret = regmap_write(drvdata->lpaif_map,
			   LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id),
			   0);
	if (ret)
		dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);

	return ret;
}

static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream,
		struct snd_soc_dai *dai)
{
	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
	int ret;
	unsigned int val, mask;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		val = LPAIF_I2SCTL_SPKEN_ENABLE;
		mask = LPAIF_I2SCTL_SPKEN_MASK;
	} else  {
		val = LPAIF_I2SCTL_MICEN_ENABLE;
		mask = LPAIF_I2SCTL_MICEN_MASK;
	}

	ret = regmap_update_bits(drvdata->lpaif_map,
			LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id),
			mask, val);
	if (ret)
		dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);

	return ret;
}

static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
		int cmd, struct snd_soc_dai *dai)
{
	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
	int ret = -EINVAL;
	unsigned int val, mask;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
			val = LPAIF_I2SCTL_SPKEN_ENABLE;
			mask = LPAIF_I2SCTL_SPKEN_MASK;
		} else  {
			val = LPAIF_I2SCTL_MICEN_ENABLE;
			mask = LPAIF_I2SCTL_MICEN_MASK;
		}

		ret = regmap_update_bits(drvdata->lpaif_map,
				LPAIF_I2SCTL_REG(drvdata->variant,
						dai->driver->id),
				mask, val);
		if (ret)
			dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
				ret);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
			val = LPAIF_I2SCTL_SPKEN_DISABLE;
			mask = LPAIF_I2SCTL_SPKEN_MASK;
		} else  {
			val = LPAIF_I2SCTL_MICEN_DISABLE;
			mask = LPAIF_I2SCTL_MICEN_MASK;
		}

		ret = regmap_update_bits(drvdata->lpaif_map,
				LPAIF_I2SCTL_REG(drvdata->variant,
						dai->driver->id),
				mask, val);
		if (ret)
			dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
				ret);
		break;
	}

	return ret;
}

const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = {
	.set_sysclk	= lpass_cpu_daiops_set_sysclk,
	.startup	= lpass_cpu_daiops_startup,
	.shutdown	= lpass_cpu_daiops_shutdown,
	.hw_params	= lpass_cpu_daiops_hw_params,
	.hw_free	= lpass_cpu_daiops_hw_free,
	.prepare	= lpass_cpu_daiops_prepare,
	.trigger	= lpass_cpu_daiops_trigger,
};
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops);

int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai)
{
	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
	int ret;

	/* ensure audio hardware is disabled */
	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0);
	if (ret)
		dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);

	return ret;
}
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe);

static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
	.name = "lpass-cpu",
};

static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
{
	struct lpass_data *drvdata = dev_get_drvdata(dev);
	struct lpass_variant *v = drvdata->variant;
	int i;

	for (i = 0; i < v->i2s_ports; ++i)
		if (reg == LPAIF_I2SCTL_REG(v, i))
			return true;

	for (i = 0; i < v->irq_ports; ++i) {
		if (reg == LPAIF_IRQEN_REG(v, i))
			return true;
		if (reg == LPAIF_IRQCLEAR_REG(v, i))
			return true;
	}

	for (i = 0; i < v->rdma_channels; ++i) {
		if (reg == LPAIF_RDMACTL_REG(v, i))
			return true;
		if (reg == LPAIF_RDMABASE_REG(v, i))
			return true;
		if (reg == LPAIF_RDMABUFF_REG(v, i))
			return true;
		if (reg == LPAIF_RDMAPER_REG(v, i))
			return true;
	}

	for (i = 0; i < v->wrdma_channels; ++i) {
		if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
			return true;
		if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
			return true;
		if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
			return true;
		if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
			return true;
	}

	return false;
}

static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
{
	struct lpass_data *drvdata = dev_get_drvdata(dev);
	struct lpass_variant *v = drvdata->variant;
	int i;

	for (i = 0; i < v->i2s_ports; ++i)
		if (reg == LPAIF_I2SCTL_REG(v, i))
			return true;

	for (i = 0; i < v->irq_ports; ++i) {
		if (reg == LPAIF_IRQEN_REG(v, i))
			return true;
		if (reg == LPAIF_IRQSTAT_REG(v, i))
			return true;
	}

	for (i = 0; i < v->rdma_channels; ++i) {
		if (reg == LPAIF_RDMACTL_REG(v, i))
			return true;
		if (reg == LPAIF_RDMABASE_REG(v, i))
			return true;
		if (reg == LPAIF_RDMABUFF_REG(v, i))
			return true;
		if (reg == LPAIF_RDMACURR_REG(v, i))
			return true;
		if (reg == LPAIF_RDMAPER_REG(v, i))
			return true;
	}

	for (i = 0; i < v->wrdma_channels; ++i) {
		if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
			return true;
		if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
			return true;
		if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
			return true;
		if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
			return true;
		if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
			return true;
	}

	return false;
}

static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
{
	struct lpass_data *drvdata = dev_get_drvdata(dev);
	struct lpass_variant *v = drvdata->variant;
	int i;

	for (i = 0; i < v->irq_ports; ++i)
		if (reg == LPAIF_IRQSTAT_REG(v, i))
			return true;

	for (i = 0; i < v->rdma_channels; ++i)
		if (reg == LPAIF_RDMACURR_REG(v, i))
			return true;

	for (i = 0; i < v->wrdma_channels; ++i)
		if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
			return true;

	return false;
}

static struct regmap_config lpass_cpu_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.writeable_reg = lpass_cpu_regmap_writeable,
	.readable_reg = lpass_cpu_regmap_readable,
	.volatile_reg = lpass_cpu_regmap_volatile,
	.cache_type = REGCACHE_FLAT,
};

int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
{
	struct lpass_data *drvdata;
	struct device_node *dsp_of_node;
	struct resource *res;
	struct lpass_variant *variant;
	struct device *dev = &pdev->dev;
	const struct of_device_id *match;
	int ret, i, dai_id;

	dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0);
	if (dsp_of_node) {
		dev_err(&pdev->dev, "DSP exists and holds audio resources\n");
		return -EBUSY;
	}

	drvdata = devm_kzalloc(&pdev->dev, sizeof(struct lpass_data),
			GFP_KERNEL);
	if (!drvdata)
		return -ENOMEM;
	platform_set_drvdata(pdev, drvdata);

	match = of_match_device(dev->driver->of_match_table, dev);
	if (!match || !match->data)
		return -EINVAL;

	drvdata->variant = (struct lpass_variant *)match->data;
	variant = drvdata->variant;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif");

	drvdata->lpaif = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR((void const __force *)drvdata->lpaif)) {
		dev_err(&pdev->dev, "error mapping reg resource: %ld\n",
				PTR_ERR((void const __force *)drvdata->lpaif));
		return PTR_ERR((void const __force *)drvdata->lpaif);
	}

	lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant,
						variant->wrdma_channels +
						variant->wrdma_channel_start);

	drvdata->lpaif_map = devm_regmap_init_mmio(&pdev->dev, drvdata->lpaif,
			&lpass_cpu_regmap_config);
	if (IS_ERR(drvdata->lpaif_map)) {
		dev_err(&pdev->dev, "error initializing regmap: %ld\n",
			PTR_ERR(drvdata->lpaif_map));
		return PTR_ERR(drvdata->lpaif_map);
	}

	if (variant->init)
		variant->init(pdev);

	for (i = 0; i < variant->num_dai; i++) {
		dai_id = variant->dai_driver[i].id;
		drvdata->mi2s_osr_clk[dai_id] = devm_clk_get(&pdev->dev,
					     variant->dai_osr_clk_names[i]);
		if (IS_ERR(drvdata->mi2s_osr_clk[dai_id])) {
			dev_warn(&pdev->dev,
				"%s() error getting optional %s: %ld\n",
				__func__,
				variant->dai_osr_clk_names[i],
				PTR_ERR(drvdata->mi2s_osr_clk[dai_id]));

			drvdata->mi2s_osr_clk[dai_id] = NULL;
		}

		drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(&pdev->dev,
						variant->dai_bit_clk_names[i]);
		if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) {
			dev_err(&pdev->dev,
				"error getting %s: %ld\n",
				variant->dai_bit_clk_names[i],
				PTR_ERR(drvdata->mi2s_bit_clk[dai_id]));
			return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]);
		}
	}

	drvdata->ahbix_clk = devm_clk_get(&pdev->dev, "ahbix-clk");
	if (IS_ERR(drvdata->ahbix_clk)) {
		dev_err(&pdev->dev, "error getting ahbix-clk: %ld\n",
			PTR_ERR(drvdata->ahbix_clk));
		return PTR_ERR(drvdata->ahbix_clk);
	}

	ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY);
	if (ret) {
		dev_err(&pdev->dev, "error setting rate on ahbix_clk: %d\n",
			ret);
		return ret;
	}
	dev_dbg(&pdev->dev, "set ahbix_clk rate to %lu\n",
		clk_get_rate(drvdata->ahbix_clk));

	ret = clk_prepare_enable(drvdata->ahbix_clk);
	if (ret) {
		dev_err(&pdev->dev, "error enabling ahbix_clk: %d\n", ret);
		return ret;
	}

	ret = devm_snd_soc_register_component(&pdev->dev,
					      &lpass_cpu_comp_driver,
					      variant->dai_driver,
					      variant->num_dai);
	if (ret) {
		dev_err(&pdev->dev, "error registering cpu driver: %d\n", ret);
		goto err_clk;
	}

	ret = asoc_qcom_lpass_platform_register(pdev);
	if (ret) {
		dev_err(&pdev->dev, "error registering platform driver: %d\n",
			ret);
		goto err_clk;
	}

	return 0;

err_clk:
	clk_disable_unprepare(drvdata->ahbix_clk);
	return ret;
}
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe);

int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev)
{
	struct lpass_data *drvdata = platform_get_drvdata(pdev);

	if (drvdata->variant->exit)
		drvdata->variant->exit(pdev);

	clk_disable_unprepare(drvdata->ahbix_clk);

	return 0;
}
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove);

MODULE_DESCRIPTION("QTi LPASS CPU Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
97fb5e8d	1	// SPDX-License-Identifier: GPL-2.0-only
80beab8e KW	2	/*
	3	* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
	4	*
80beab8e KW	5	* lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS
	6	*/
	7
	8	#include <linux/clk.h>
80beab8e	9	#include <linux/kernel.h>
80beab8e KW	10	#include <linux/module.h>
80beab8e KW	11	#include <linux/of.h>
9bae4880	12	#include <linux/of_device.h>
80beab8e KW	13	#include <linux/platform_device.h>
	14	#include <sound/pcm.h>
	15	#include <sound/pcm_params.h>
	16	#include <linux/regmap.h>
	17	#include <sound/soc.h>
	18	#include <sound/soc-dai.h>
9bae4880	19	#include "lpass-lpaif-reg.h"
80beab8e KW	20	#include "lpass.h"
	21
	22	static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
	23	unsigned int freq, int dir)
	24	{
	25	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
	26	int ret;
	27
9a127cff	28	ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq);
80beab8e	29	if (ret)
b6e643ad BA	30	dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n",
b6e643ad BA	31	freq, ret);
80beab8e KW	32
	33	return ret;
	34	}
	35
	36	static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
	37	struct snd_soc_dai *dai)
	38	{
	39	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
	40	int ret;
	41
46dccc35 BA	42	ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]);
46dccc35 BA	43	if (ret) {
b6e643ad	44	dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
46dccc35	45	return ret;
80beab8e KW	46	}
80beab8e KW	47
9a127cff	48	ret = clk_prepare_enable(drvdata->mi2s_bit_clk[dai->driver->id]);
80beab8e	49	if (ret) {
b6e643ad	50	dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
46dccc35	51	clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
80beab8e KW	52	return ret;
	53	}
	54
	55	return 0;
	56	}
	57
	58	static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
	59	struct snd_soc_dai *dai)
	60	{
	61	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
	62
9a127cff	63	clk_disable_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
3e53ac82	64
46dccc35	65	clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
80beab8e KW	66	}
	67
	68	static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
	69	struct snd_pcm_hw_params params, struct snd_soc_dai dai)
	70	{
	71	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
	72	snd_pcm_format_t format = params_format(params);
	73	unsigned int channels = params_channels(params);
	74	unsigned int rate = params_rate(params);
	75	unsigned int regval;
	76	int bitwidth, ret;
	77
	78	bitwidth = snd_pcm_format_width(format);
	79	if (bitwidth < 0) {
b6e643ad	80	dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth);
80beab8e KW	81	return bitwidth;
	82	}
	83
	84	regval = LPAIF_I2SCTL_LOOPBACK_DISABLE \|
	85	LPAIF_I2SCTL_WSSRC_INTERNAL;
	86
	87	switch (bitwidth) {
	88	case 16:
	89	regval \|= LPAIF_I2SCTL_BITWIDTH_16;
	90	break;
	91	case 24:
	92	regval \|= LPAIF_I2SCTL_BITWIDTH_24;
	93	break;
	94	case 32:
	95	regval \|= LPAIF_I2SCTL_BITWIDTH_32;
	96	break;
	97	default:
b6e643ad	98	dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth);
80beab8e KW	99	return -EINVAL;
	100	}
	101
fb5d1152 SK	102	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	103	switch (channels) {
	104	case 1:
	105	regval \|= LPAIF_I2SCTL_SPKMODE_SD0;
	106	regval \|= LPAIF_I2SCTL_SPKMONO_MONO;
	107	break;
	108	case 2:
	109	regval \|= LPAIF_I2SCTL_SPKMODE_SD0;
	110	regval \|= LPAIF_I2SCTL_SPKMONO_STEREO;
	111	break;
	112	case 4:
	113	regval \|= LPAIF_I2SCTL_SPKMODE_QUAD01;
	114	regval \|= LPAIF_I2SCTL_SPKMONO_STEREO;
	115	break;
	116	case 6:
	117	regval \|= LPAIF_I2SCTL_SPKMODE_6CH;
	118	regval \|= LPAIF_I2SCTL_SPKMONO_STEREO;
	119	break;
	120	case 8:
	121	regval \|= LPAIF_I2SCTL_SPKMODE_8CH;
	122	regval \|= LPAIF_I2SCTL_SPKMONO_STEREO;
	123	break;
	124	default:
b6e643ad BA	125	dev_err(dai->dev, "invalid channels given: %u\n",
b6e643ad BA	126	channels);
fb5d1152 SK	127	return -EINVAL;
	128	}
	129	} else {
	130	switch (channels) {
	131	case 1:
	132	regval \|= LPAIF_I2SCTL_MICMODE_SD0;
	133	regval \|= LPAIF_I2SCTL_MICMONO_MONO;
	134	break;
	135	case 2:
	136	regval \|= LPAIF_I2SCTL_MICMODE_SD0;
	137	regval \|= LPAIF_I2SCTL_MICMONO_STEREO;
	138	break;
	139	case 4:
	140	regval \|= LPAIF_I2SCTL_MICMODE_QUAD01;
	141	regval \|= LPAIF_I2SCTL_MICMONO_STEREO;
	142	break;
	143	case 6:
	144	regval \|= LPAIF_I2SCTL_MICMODE_6CH;
	145	regval \|= LPAIF_I2SCTL_MICMONO_STEREO;
	146	break;
	147	case 8:
	148	regval \|= LPAIF_I2SCTL_MICMODE_8CH;
	149	regval \|= LPAIF_I2SCTL_MICMONO_STEREO;
	150	break;
	151	default:
b6e643ad BA	152	dev_err(dai->dev, "invalid channels given: %u\n",
b6e643ad BA	153	channels);
fb5d1152 SK	154	return -EINVAL;
fb5d1152 SK	155	}
80beab8e KW	156	}
	157
	158	ret = regmap_write(drvdata->lpaif_map,
0ae9fd3b	159	LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id),
9bae4880	160	regval);
80beab8e	161	if (ret) {
b6e643ad	162	dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
80beab8e KW	163	return ret;
	164	}
	165
9a127cff SK	166	ret = clk_set_rate(drvdata->mi2s_bit_clk[dai->driver->id],
9a127cff SK	167	rate * bitwidth * 2);
80beab8e	168	if (ret) {
b6e643ad BA	169	dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n",
b6e643ad BA	170	rate * bitwidth * 2, ret);
80beab8e KW	171	return ret;
	172	}
	173
	174	return 0;
	175	}
	176
	177	static int lpass_cpu_daiops_hw_free(struct snd_pcm_substream *substream,
	178	struct snd_soc_dai *dai)
	179	{
	180	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
	181	int ret;
	182
	183	ret = regmap_write(drvdata->lpaif_map,
0ae9fd3b SK	184	LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id),
0ae9fd3b SK	185	0);
80beab8e	186	if (ret)
b6e643ad	187	dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
80beab8e KW	188
	189	return ret;
	190	}
	191
	192	static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream,
	193	struct snd_soc_dai *dai)
	194	{
	195	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
	196	int ret;
fb5d1152 SK	197	unsigned int val, mask;
	198
	199	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	200	val = LPAIF_I2SCTL_SPKEN_ENABLE;
	201	mask = LPAIF_I2SCTL_SPKEN_MASK;
	202	} else {
	203	val = LPAIF_I2SCTL_MICEN_ENABLE;
	204	mask = LPAIF_I2SCTL_MICEN_MASK;
	205	}
80beab8e KW	206
80beab8e KW	207	ret = regmap_update_bits(drvdata->lpaif_map,
0ae9fd3b	208	LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id),
fb5d1152	209	mask, val);
80beab8e	210	if (ret)
b6e643ad	211	dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
80beab8e KW	212
	213	return ret;
	214	}
	215
	216	static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
	217	int cmd, struct snd_soc_dai *dai)
	218	{
	219	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
96f05be3	220	int ret = -EINVAL;
fb5d1152	221	unsigned int val, mask;
80beab8e KW	222
	223	switch (cmd) {
	224	case SNDRV_PCM_TRIGGER_START:
	225	case SNDRV_PCM_TRIGGER_RESUME:
	226	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
fb5d1152 SK	227	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	228	val = LPAIF_I2SCTL_SPKEN_ENABLE;
	229	mask = LPAIF_I2SCTL_SPKEN_MASK;
	230	} else {
	231	val = LPAIF_I2SCTL_MICEN_ENABLE;
	232	mask = LPAIF_I2SCTL_MICEN_MASK;
	233	}
	234
80beab8e	235	ret = regmap_update_bits(drvdata->lpaif_map,
9bae4880	236	LPAIF_I2SCTL_REG(drvdata->variant,
0ae9fd3b	237	dai->driver->id),
fb5d1152	238	mask, val);
80beab8e	239	if (ret)
b6e643ad BA	240	dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
b6e643ad BA	241	ret);
80beab8e KW	242	break;
	243	case SNDRV_PCM_TRIGGER_STOP:
	244	case SNDRV_PCM_TRIGGER_SUSPEND:
	245	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
fb5d1152 SK	246	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	247	val = LPAIF_I2SCTL_SPKEN_DISABLE;
	248	mask = LPAIF_I2SCTL_SPKEN_MASK;
	249	} else {
	250	val = LPAIF_I2SCTL_MICEN_DISABLE;
	251	mask = LPAIF_I2SCTL_MICEN_MASK;
	252	}
	253
80beab8e	254	ret = regmap_update_bits(drvdata->lpaif_map,
9bae4880	255	LPAIF_I2SCTL_REG(drvdata->variant,
0ae9fd3b	256	dai->driver->id),
fb5d1152	257	mask, val);
80beab8e	258	if (ret)
b6e643ad BA	259	dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
b6e643ad BA	260	ret);
80beab8e KW	261	break;
	262	}
	263
	264	return ret;
	265	}
	266
618718dc	267	const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = {
80beab8e KW	268	.set_sysclk = lpass_cpu_daiops_set_sysclk,
	269	.startup = lpass_cpu_daiops_startup,
	270	.shutdown = lpass_cpu_daiops_shutdown,
	271	.hw_params = lpass_cpu_daiops_hw_params,
	272	.hw_free = lpass_cpu_daiops_hw_free,
	273	.prepare = lpass_cpu_daiops_prepare,
	274	.trigger = lpass_cpu_daiops_trigger,
	275	};
9bae4880	276	EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops);
80beab8e	277
9bae4880	278	int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai)
80beab8e KW	279	{
	280	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
	281	int ret;
	282
	283	/* ensure audio hardware is disabled */
	284	ret = regmap_write(drvdata->lpaif_map,
0ae9fd3b	285	LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0);
80beab8e	286	if (ret)
b6e643ad	287	dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
80beab8e KW	288
	289	return ret;
	290	}
9bae4880	291	EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe);
80beab8e KW	292
	293	static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
	294	.name = "lpass-cpu",
	295	};
	296
	297	static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
	298	{
9bae4880 SK	299	struct lpass_data *drvdata = dev_get_drvdata(dev);
9bae4880 SK	300	struct lpass_variant *v = drvdata->variant;
80beab8e KW	301	int i;
80beab8e KW	302
9bae4880 SK	303	for (i = 0; i < v->i2s_ports; ++i)
9bae4880 SK	304	if (reg == LPAIF_I2SCTL_REG(v, i))
80beab8e KW	305	return true;
80beab8e KW	306
9bae4880 SK	307	for (i = 0; i < v->irq_ports; ++i) {
9bae4880 SK	308	if (reg == LPAIF_IRQEN_REG(v, i))
80beab8e	309	return true;
9bae4880	310	if (reg == LPAIF_IRQCLEAR_REG(v, i))
80beab8e KW	311	return true;
	312	}
	313
9bae4880 SK	314	for (i = 0; i < v->rdma_channels; ++i) {
9bae4880 SK	315	if (reg == LPAIF_RDMACTL_REG(v, i))
80beab8e	316	return true;
9bae4880	317	if (reg == LPAIF_RDMABASE_REG(v, i))
80beab8e	318	return true;
9bae4880	319	if (reg == LPAIF_RDMABUFF_REG(v, i))
80beab8e	320	return true;
9bae4880	321	if (reg == LPAIF_RDMAPER_REG(v, i))
80beab8e KW	322	return true;
	323	}
	324
dad80614 SK	325	for (i = 0; i < v->wrdma_channels; ++i) {
	326	if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
	327	return true;
	328	if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
	329	return true;
	330	if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
	331	return true;
	332	if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
	333	return true;
	334	}
	335
80beab8e KW	336	return false;
	337	}
	338
	339	static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
	340	{
9bae4880 SK	341	struct lpass_data *drvdata = dev_get_drvdata(dev);
9bae4880 SK	342	struct lpass_variant *v = drvdata->variant;
80beab8e KW	343	int i;
80beab8e KW	344
9bae4880 SK	345	for (i = 0; i < v->i2s_ports; ++i)
9bae4880 SK	346	if (reg == LPAIF_I2SCTL_REG(v, i))
80beab8e KW	347	return true;
80beab8e KW	348
9bae4880 SK	349	for (i = 0; i < v->irq_ports; ++i) {
9bae4880 SK	350	if (reg == LPAIF_IRQEN_REG(v, i))
80beab8e	351	return true;
9bae4880	352	if (reg == LPAIF_IRQSTAT_REG(v, i))
80beab8e KW	353	return true;
	354	}
	355
9bae4880 SK	356	for (i = 0; i < v->rdma_channels; ++i) {
9bae4880 SK	357	if (reg == LPAIF_RDMACTL_REG(v, i))
80beab8e	358	return true;
9bae4880	359	if (reg == LPAIF_RDMABASE_REG(v, i))
80beab8e	360	return true;
9bae4880	361	if (reg == LPAIF_RDMABUFF_REG(v, i))
80beab8e	362	return true;
9bae4880	363	if (reg == LPAIF_RDMACURR_REG(v, i))
80beab8e	364	return true;
9bae4880	365	if (reg == LPAIF_RDMAPER_REG(v, i))
80beab8e KW	366	return true;
	367	}
	368
dad80614 SK	369	for (i = 0; i < v->wrdma_channels; ++i) {
	370	if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
	371	return true;
	372	if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
	373	return true;
	374	if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
	375	return true;
	376	if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
	377	return true;
	378	if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
	379	return true;
	380	}
	381
80beab8e KW	382	return false;
	383	}
	384
	385	static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
	386	{
9bae4880 SK	387	struct lpass_data *drvdata = dev_get_drvdata(dev);
9bae4880 SK	388	struct lpass_variant *v = drvdata->variant;
80beab8e KW	389	int i;
80beab8e KW	390
9bae4880 SK	391	for (i = 0; i < v->irq_ports; ++i)
9bae4880 SK	392	if (reg == LPAIF_IRQSTAT_REG(v, i))
80beab8e KW	393	return true;
80beab8e KW	394
9bae4880 SK	395	for (i = 0; i < v->rdma_channels; ++i)
9bae4880 SK	396	if (reg == LPAIF_RDMACURR_REG(v, i))
80beab8e KW	397	return true;
80beab8e KW	398
dad80614 SK	399	for (i = 0; i < v->wrdma_channels; ++i)
	400	if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
	401	return true;
	402
80beab8e KW	403	return false;
	404	}
	405
9bae4880	406	static struct regmap_config lpass_cpu_regmap_config = {
80beab8e KW	407	.reg_bits = 32,
	408	.reg_stride = 4,
	409	.val_bits = 32,
80beab8e KW	410	.writeable_reg = lpass_cpu_regmap_writeable,
	411	.readable_reg = lpass_cpu_regmap_readable,
	412	.volatile_reg = lpass_cpu_regmap_volatile,
	413	.cache_type = REGCACHE_FLAT,
	414	};
	415
9bae4880	416	int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
80beab8e	417	{
8ebe148b	418	struct lpass_data *drvdata;
80beab8e	419	struct device_node *dsp_of_node;
8ebe148b	420	struct resource *res;
9bae4880 SK	421	struct lpass_variant *variant;
	422	struct device *dev = &pdev->dev;
	423	const struct of_device_id *match;
9a127cff	424	int ret, i, dai_id;
80beab8e	425
8ebe148b KW	426	dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0);
8ebe148b KW	427	if (dsp_of_node) {
b6e643ad	428	dev_err(&pdev->dev, "DSP exists and holds audio resources\n");
80beab8e KW	429	return -EBUSY;
	430	}
	431
80beab8e KW	432	drvdata = devm_kzalloc(&pdev->dev, sizeof(struct lpass_data),
	433	GFP_KERNEL);
	434	if (!drvdata)
	435	return -ENOMEM;
	436	platform_set_drvdata(pdev, drvdata);
	437
9bae4880 SK	438	match = of_match_device(dev->driver->of_match_table, dev);
	439	if (!match \|\| !match->data)
	440	return -EINVAL;
	441
	442	drvdata->variant = (struct lpass_variant *)match->data;
	443	variant = drvdata->variant;
	444
80beab8e	445	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif");
80beab8e KW	446
	447	drvdata->lpaif = devm_ioremap_resource(&pdev->dev, res);
	448	if (IS_ERR((void const __force *)drvdata->lpaif)) {
b6e643ad	449	dev_err(&pdev->dev, "error mapping reg resource: %ld\n",
80beab8e KW	450	PTR_ERR((void const __force *)drvdata->lpaif));
	451	return PTR_ERR((void const __force *)drvdata->lpaif);
	452	}
	453
dad80614 SK	454	lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant,
	455	variant->wrdma_channels +
	456	variant->wrdma_channel_start);
9bae4880	457
80beab8e KW	458	drvdata->lpaif_map = devm_regmap_init_mmio(&pdev->dev, drvdata->lpaif,
	459	&lpass_cpu_regmap_config);
	460	if (IS_ERR(drvdata->lpaif_map)) {
b6e643ad BA	461	dev_err(&pdev->dev, "error initializing regmap: %ld\n",
b6e643ad BA	462	PTR_ERR(drvdata->lpaif_map));
80beab8e KW	463	return PTR_ERR(drvdata->lpaif_map);
	464	}
	465
9bae4880 SK	466	if (variant->init)
	467	variant->init(pdev);
	468
9a127cff SK	469	for (i = 0; i < variant->num_dai; i++) {
9a127cff SK	470	dai_id = variant->dai_driver[i].id;
9a127cff	471	drvdata->mi2s_osr_clk[dai_id] = devm_clk_get(&pdev->dev,
97c52eb9	472	variant->dai_osr_clk_names[i]);
9a127cff	473	if (IS_ERR(drvdata->mi2s_osr_clk[dai_id])) {
3e53ac82	474	dev_warn(&pdev->dev,
97c52eb9 LW	475	"%s() error getting optional %s: %ld\n",
	476	__func__,
	477	variant->dai_osr_clk_names[i],
9a127cff	478	PTR_ERR(drvdata->mi2s_osr_clk[dai_id]));
46dccc35 BA	479
46dccc35 BA	480	drvdata->mi2s_osr_clk[dai_id] = NULL;
9a127cff SK	481	}
9a127cff SK	482
9a127cff	483	drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(&pdev->dev,
97c52eb9	484	variant->dai_bit_clk_names[i]);
9a127cff SK	485	if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) {
9a127cff SK	486	dev_err(&pdev->dev,
97c52eb9 LW	487	"error getting %s: %ld\n",
97c52eb9 LW	488	variant->dai_bit_clk_names[i],
89857295	489	PTR_ERR(drvdata->mi2s_bit_clk[dai_id]));
9a127cff SK	490	return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]);
9a127cff SK	491	}
80beab8e KW	492	}
	493
	494	drvdata->ahbix_clk = devm_clk_get(&pdev->dev, "ahbix-clk");
	495	if (IS_ERR(drvdata->ahbix_clk)) {
b6e643ad BA	496	dev_err(&pdev->dev, "error getting ahbix-clk: %ld\n",
b6e643ad BA	497	PTR_ERR(drvdata->ahbix_clk));
80beab8e KW	498	return PTR_ERR(drvdata->ahbix_clk);
	499	}
	500
	501	ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY);
	502	if (ret) {
b6e643ad BA	503	dev_err(&pdev->dev, "error setting rate on ahbix_clk: %d\n",
b6e643ad BA	504	ret);
80beab8e KW	505	return ret;
80beab8e KW	506	}
b6e643ad BA	507	dev_dbg(&pdev->dev, "set ahbix_clk rate to %lu\n",
b6e643ad BA	508	clk_get_rate(drvdata->ahbix_clk));
80beab8e KW	509
	510	ret = clk_prepare_enable(drvdata->ahbix_clk);
	511	if (ret) {
b6e643ad	512	dev_err(&pdev->dev, "error enabling ahbix_clk: %d\n", ret);
80beab8e KW	513	return ret;
	514	}
	515
	516	ret = devm_snd_soc_register_component(&pdev->dev,
9bae4880 SK	517	&lpass_cpu_comp_driver,
	518	variant->dai_driver,
	519	variant->num_dai);
80beab8e	520	if (ret) {
b6e643ad	521	dev_err(&pdev->dev, "error registering cpu driver: %d\n", ret);
80beab8e KW	522	goto err_clk;
	523	}
	524
	525	ret = asoc_qcom_lpass_platform_register(pdev);
	526	if (ret) {
b6e643ad BA	527	dev_err(&pdev->dev, "error registering platform driver: %d\n",
b6e643ad BA	528	ret);
80beab8e KW	529	goto err_clk;
	530	}
	531
	532	return 0;
	533
	534	err_clk:
	535	clk_disable_unprepare(drvdata->ahbix_clk);
	536	return ret;
	537	}
9bae4880	538	EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe);
80beab8e	539
9bae4880	540	int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev)
80beab8e KW	541	{
	542	struct lpass_data *drvdata = platform_get_drvdata(pdev);
	543
9bae4880 SK	544	if (drvdata->variant->exit)
	545	drvdata->variant->exit(pdev);
	546
80beab8e KW	547	clk_disable_unprepare(drvdata->ahbix_clk);
	548
	549	return 0;
	550	}
9bae4880	551	EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove);
94201798 SK	552
	553	MODULE_DESCRIPTION("QTi LPASS CPU Driver");
	554	MODULE_LICENSE("GPL v2");