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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
75b41027 LG |
2 | /* |
3 | * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip. | |
4 | * | |
5 | * Author: Nicolas Pitre | |
6 | * Created: Dec 02, 2004 | |
7 | * Copyright: MontaVista Software Inc. | |
75b41027 LG |
8 | */ |
9 | ||
10 | #include <linux/init.h> | |
23019a73 | 11 | #include <linux/io.h> |
75b41027 LG |
12 | #include <linux/module.h> |
13 | #include <linux/platform_device.h> | |
d65a1458 | 14 | #include <linux/dmaengine.h> |
58ceb57e | 15 | #include <linux/dma/pxa-dma.h> |
75b41027 | 16 | |
1c8bc7b3 | 17 | #include <sound/ac97/controller.h> |
75b41027 | 18 | #include <sound/core.h> |
75b41027 | 19 | #include <sound/ac97_codec.h> |
75b41027 | 20 | #include <sound/soc.h> |
9c636342 | 21 | #include <sound/pxa2xx-lib.h> |
d65a1458 | 22 | #include <sound/dmaengine_pcm.h> |
75b41027 | 23 | |
22f08665 | 24 | #include <linux/platform_data/asoc-pxa.h> |
75b41027 | 25 | |
4d2dba6b AB |
26 | #define PCDR 0x0040 /* PCM FIFO Data Register */ |
27 | #define MODR 0x0140 /* Modem FIFO Data Register */ | |
28 | #define MCDR 0x0060 /* Mic-in FIFO Data Register */ | |
29 | ||
1c8bc7b3 | 30 | static void pxa2xx_ac97_warm_reset(struct ac97_controller *adrv) |
75b41027 | 31 | { |
6f8acad6 | 32 | pxa2xx_ac97_try_warm_reset(); |
75b41027 | 33 | |
6f8acad6 | 34 | pxa2xx_ac97_finish_reset(); |
75b41027 LG |
35 | } |
36 | ||
1c8bc7b3 | 37 | static void pxa2xx_ac97_cold_reset(struct ac97_controller *adrv) |
75b41027 | 38 | { |
6f8acad6 | 39 | pxa2xx_ac97_try_cold_reset(); |
7a22323b | 40 | |
6f8acad6 RJ |
41 | pxa2xx_ac97_finish_reset(); |
42 | } | |
43 | ||
1c8bc7b3 RJ |
44 | static int pxa2xx_ac97_read_actrl(struct ac97_controller *adrv, int slot, |
45 | unsigned short reg) | |
6f8acad6 | 46 | { |
1c8bc7b3 | 47 | return pxa2xx_ac97_read(slot, reg); |
6f8acad6 RJ |
48 | } |
49 | ||
1c8bc7b3 RJ |
50 | static int pxa2xx_ac97_write_actrl(struct ac97_controller *adrv, int slot, |
51 | unsigned short reg, unsigned short val) | |
6f8acad6 | 52 | { |
1c8bc7b3 | 53 | return pxa2xx_ac97_write(slot, reg, val); |
75b41027 LG |
54 | } |
55 | ||
1c8bc7b3 RJ |
56 | static struct ac97_controller_ops pxa2xx_ac97_ops = { |
57 | .read = pxa2xx_ac97_read_actrl, | |
58 | .write = pxa2xx_ac97_write_actrl, | |
75b41027 LG |
59 | .warm_reset = pxa2xx_ac97_warm_reset, |
60 | .reset = pxa2xx_ac97_cold_reset, | |
61 | }; | |
62 | ||
d65a1458 | 63 | static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_stereo_in = { |
d65a1458 | 64 | .addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
8f54061d | 65 | .chan_name = "pcm_pcm_stereo_in", |
d65a1458 | 66 | .maxburst = 32, |
58ceb57e DM |
67 | }; |
68 | ||
d65a1458 | 69 | static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_stereo_out = { |
d65a1458 | 70 | .addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
8f54061d | 71 | .chan_name = "pcm_pcm_stereo_out", |
d65a1458 | 72 | .maxburst = 32, |
75b41027 LG |
73 | }; |
74 | ||
d65a1458 | 75 | static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_aux_mono_out = { |
d65a1458 | 76 | .addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES, |
8f54061d | 77 | .chan_name = "pcm_aux_mono_out", |
d65a1458 | 78 | .maxburst = 16, |
75b41027 LG |
79 | }; |
80 | ||
d65a1458 | 81 | static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_aux_mono_in = { |
d65a1458 | 82 | .addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES, |
8f54061d | 83 | .chan_name = "pcm_aux_mono_in", |
d65a1458 | 84 | .maxburst = 16, |
75b41027 LG |
85 | }; |
86 | ||
d65a1458 | 87 | static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_mic_mono_in = { |
d65a1458 | 88 | .addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES, |
8f54061d | 89 | .chan_name = "pcm_aux_mic_mono", |
d65a1458 | 90 | .maxburst = 16, |
75b41027 LG |
91 | }; |
92 | ||
58ceb57e DM |
93 | static int pxa2xx_ac97_hifi_startup(struct snd_pcm_substream *substream, |
94 | struct snd_soc_dai *cpu_dai) | |
75b41027 | 95 | { |
d65a1458 | 96 | struct snd_dmaengine_dai_dma_data *dma_data; |
75b41027 LG |
97 | |
98 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
5f712b2b | 99 | dma_data = &pxa2xx_ac97_pcm_stereo_out; |
75b41027 | 100 | else |
5f712b2b DM |
101 | dma_data = &pxa2xx_ac97_pcm_stereo_in; |
102 | ||
103 | snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data); | |
75b41027 LG |
104 | |
105 | return 0; | |
106 | } | |
107 | ||
58ceb57e DM |
108 | static int pxa2xx_ac97_aux_startup(struct snd_pcm_substream *substream, |
109 | struct snd_soc_dai *cpu_dai) | |
75b41027 | 110 | { |
d65a1458 | 111 | struct snd_dmaengine_dai_dma_data *dma_data; |
75b41027 LG |
112 | |
113 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
5f712b2b | 114 | dma_data = &pxa2xx_ac97_pcm_aux_mono_out; |
75b41027 | 115 | else |
5f712b2b DM |
116 | dma_data = &pxa2xx_ac97_pcm_aux_mono_in; |
117 | ||
118 | snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data); | |
75b41027 LG |
119 | |
120 | return 0; | |
121 | } | |
122 | ||
58ceb57e DM |
123 | static int pxa2xx_ac97_mic_startup(struct snd_pcm_substream *substream, |
124 | struct snd_soc_dai *cpu_dai) | |
75b41027 | 125 | { |
75b41027 LG |
126 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
127 | return -ENODEV; | |
291aaff0 CG |
128 | snd_soc_dai_set_dma_data(cpu_dai, substream, |
129 | &pxa2xx_ac97_pcm_mic_mono_in); | |
75b41027 LG |
130 | |
131 | return 0; | |
132 | } | |
133 | ||
596ce32b LG |
134 | #define PXA2XX_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ |
135 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ | |
136 | SNDRV_PCM_RATE_48000) | |
137 | ||
85e7652d | 138 | static const struct snd_soc_dai_ops pxa_ac97_hifi_dai_ops = { |
58ceb57e | 139 | .startup = pxa2xx_ac97_hifi_startup, |
6335d055 EM |
140 | }; |
141 | ||
85e7652d | 142 | static const struct snd_soc_dai_ops pxa_ac97_aux_dai_ops = { |
58ceb57e | 143 | .startup = pxa2xx_ac97_aux_startup, |
852fd9e5 MB |
144 | }; |
145 | ||
85e7652d | 146 | static const struct snd_soc_dai_ops pxa_ac97_mic_dai_ops = { |
58ceb57e | 147 | .startup = pxa2xx_ac97_mic_startup, |
852fd9e5 MB |
148 | }; |
149 | ||
75b41027 LG |
150 | /* |
151 | * There is only 1 physical AC97 interface for pxa2xx, but it | |
152 | * has extra fifo's that can be used for aux DACs and ADCs. | |
153 | */ | |
a3874196 | 154 | static struct snd_soc_dai_driver pxa_ac97_dai_driver[] = { |
75b41027 LG |
155 | { |
156 | .name = "pxa2xx-ac97", | |
75b41027 LG |
157 | .playback = { |
158 | .stream_name = "AC97 Playback", | |
159 | .channels_min = 2, | |
596ce32b LG |
160 | .channels_max = 2, |
161 | .rates = PXA2XX_AC97_RATES, | |
162 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
75b41027 LG |
163 | .capture = { |
164 | .stream_name = "AC97 Capture", | |
165 | .channels_min = 2, | |
596ce32b LG |
166 | .channels_max = 2, |
167 | .rates = PXA2XX_AC97_RATES, | |
168 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
852fd9e5 | 169 | .ops = &pxa_ac97_hifi_dai_ops, |
75b41027 LG |
170 | }, |
171 | { | |
172 | .name = "pxa2xx-ac97-aux", | |
75b41027 LG |
173 | .playback = { |
174 | .stream_name = "AC97 Aux Playback", | |
175 | .channels_min = 1, | |
596ce32b LG |
176 | .channels_max = 1, |
177 | .rates = PXA2XX_AC97_RATES, | |
178 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
75b41027 LG |
179 | .capture = { |
180 | .stream_name = "AC97 Aux Capture", | |
181 | .channels_min = 1, | |
596ce32b LG |
182 | .channels_max = 1, |
183 | .rates = PXA2XX_AC97_RATES, | |
184 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
852fd9e5 | 185 | .ops = &pxa_ac97_aux_dai_ops, |
75b41027 LG |
186 | }, |
187 | { | |
188 | .name = "pxa2xx-ac97-mic", | |
75b41027 LG |
189 | .capture = { |
190 | .stream_name = "AC97 Mic Capture", | |
191 | .channels_min = 1, | |
596ce32b LG |
192 | .channels_max = 1, |
193 | .rates = PXA2XX_AC97_RATES, | |
194 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
852fd9e5 | 195 | .ops = &pxa_ac97_mic_dai_ops, |
596ce32b | 196 | }, |
75b41027 LG |
197 | }; |
198 | ||
ad53232c KM |
199 | static const struct snd_soc_component_driver pxa_ac97_component = { |
200 | .name = "pxa-ac97", | |
f8772e17 | 201 | .pcm_construct = pxa2xx_soc_pcm_new, |
f8772e17 KM |
202 | .open = pxa2xx_soc_pcm_open, |
203 | .close = pxa2xx_soc_pcm_close, | |
f8772e17 | 204 | .hw_params = pxa2xx_soc_pcm_hw_params, |
f8772e17 KM |
205 | .prepare = pxa2xx_soc_pcm_prepare, |
206 | .trigger = pxa2xx_soc_pcm_trigger, | |
207 | .pointer = pxa2xx_soc_pcm_pointer, | |
ad53232c KM |
208 | }; |
209 | ||
a4519526 RJ |
210 | #ifdef CONFIG_OF |
211 | static const struct of_device_id pxa2xx_ac97_dt_ids[] = { | |
212 | { .compatible = "marvell,pxa250-ac97", }, | |
213 | { .compatible = "marvell,pxa270-ac97", }, | |
214 | { .compatible = "marvell,pxa300-ac97", }, | |
215 | { } | |
216 | }; | |
217 | MODULE_DEVICE_TABLE(of, pxa2xx_ac97_dt_ids); | |
218 | ||
219 | #endif | |
220 | ||
570f6fe1 | 221 | static int pxa2xx_ac97_dev_probe(struct platform_device *pdev) |
3f4b783c | 222 | { |
7685e016 | 223 | int ret; |
1c8bc7b3 RJ |
224 | struct ac97_controller *ctrl; |
225 | pxa2xx_audio_ops_t *pdata = pdev->dev.platform_data; | |
4d2dba6b | 226 | struct resource *regs; |
1c8bc7b3 | 227 | void **codecs_pdata; |
7685e016 | 228 | |
f0fba2ad | 229 | if (pdev->id != -1) { |
4ac0478f MV |
230 | dev_err(&pdev->dev, "PXA2xx has only one AC97 port.\n"); |
231 | return -ENXIO; | |
232 | } | |
233 | ||
4d2dba6b AB |
234 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
235 | if (!regs) | |
236 | return -ENXIO; | |
237 | ||
238 | pxa2xx_ac97_pcm_stereo_in.addr = regs->start + PCDR; | |
239 | pxa2xx_ac97_pcm_stereo_out.addr = regs->start + PCDR; | |
240 | pxa2xx_ac97_pcm_aux_mono_out.addr = regs->start + MODR; | |
241 | pxa2xx_ac97_pcm_aux_mono_in.addr = regs->start + MODR; | |
242 | pxa2xx_ac97_pcm_mic_mono_in.addr = regs->start + MCDR; | |
243 | ||
f62aa9b6 DES |
244 | ret = pxa2xx_ac97_hw_probe(pdev); |
245 | if (ret) { | |
246 | dev_err(&pdev->dev, "PXA2xx AC97 hw probe error (%d)\n", ret); | |
247 | return ret; | |
248 | } | |
249 | ||
1c8bc7b3 RJ |
250 | codecs_pdata = pdata ? pdata->codec_pdata : NULL; |
251 | ctrl = snd_ac97_controller_register(&pxa2xx_ac97_ops, &pdev->dev, | |
252 | AC97_SLOTS_AVAILABLE_ALL, | |
253 | codecs_pdata); | |
254 | if (IS_ERR(ctrl)) | |
255 | return PTR_ERR(ctrl); | |
b047e1cc | 256 | |
1c8bc7b3 | 257 | platform_set_drvdata(pdev, ctrl); |
6b849bcf MB |
258 | /* Punt most of the init to the SoC probe; we may need the machine |
259 | * driver to do interesting things with the clocking to get us up | |
260 | * and running. | |
261 | */ | |
4b9b73b8 | 262 | return devm_snd_soc_register_component(&pdev->dev, &pxa_ac97_component, |
ad53232c | 263 | pxa_ac97_dai_driver, ARRAY_SIZE(pxa_ac97_dai_driver)); |
3f4b783c | 264 | } |
6b849bcf | 265 | |
acb6a698 | 266 | static void pxa2xx_ac97_dev_remove(struct platform_device *pdev) |
6b849bcf | 267 | { |
1c8bc7b3 RJ |
268 | struct ac97_controller *ctrl = platform_get_drvdata(pdev); |
269 | ||
1c8bc7b3 | 270 | snd_ac97_controller_unregister(ctrl); |
f62aa9b6 | 271 | pxa2xx_ac97_hw_remove(pdev); |
6b849bcf MB |
272 | } |
273 | ||
f62aa9b6 DES |
274 | static int pxa2xx_ac97_dev_suspend(struct device *dev) |
275 | { | |
276 | return pxa2xx_ac97_hw_suspend(); | |
277 | } | |
278 | ||
279 | static int pxa2xx_ac97_dev_resume(struct device *dev) | |
280 | { | |
281 | return pxa2xx_ac97_hw_resume(); | |
282 | } | |
283 | ||
8e5ffd76 | 284 | static DEFINE_SIMPLE_DEV_PM_OPS(pxa2xx_ac97_pm_ops, |
f62aa9b6 | 285 | pxa2xx_ac97_dev_suspend, pxa2xx_ac97_dev_resume); |
f62aa9b6 | 286 | |
6b849bcf MB |
287 | static struct platform_driver pxa2xx_ac97_driver = { |
288 | .probe = pxa2xx_ac97_dev_probe, | |
acb6a698 | 289 | .remove_new = pxa2xx_ac97_dev_remove, |
6b849bcf MB |
290 | .driver = { |
291 | .name = "pxa2xx-ac97", | |
f62aa9b6 | 292 | .pm = &pxa2xx_ac97_pm_ops, |
a4519526 | 293 | .of_match_table = of_match_ptr(pxa2xx_ac97_dt_ids), |
6b849bcf MB |
294 | }, |
295 | }; | |
296 | ||
2f702a19 | 297 | module_platform_driver(pxa2xx_ac97_driver); |
3f4b783c | 298 | |
75b41027 LG |
299 | MODULE_AUTHOR("Nicolas Pitre"); |
300 | MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip"); | |
301 | MODULE_LICENSE("GPL"); | |
e5b7d71a | 302 | MODULE_ALIAS("platform:pxa2xx-ac97"); |