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ASoC: pxa-ssp: allow more flexible setup order
[linux-2.6-block.git] / sound / soc / pxa / pxa-ssp.c
CommitLineData
1b340bd7
MB		 1/*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
5a0e3ad6 19#include <linux/slab.h>
1b340bd7
MB		 20#include <linux/platform_device.h>
21#include <linux/clk.h>
22#include <linux/io.h>
8348c259 23#include <linux/pxa2xx_ssp.h>
2023c90c 24#include <linux/of.h>
d65a1458 25#include <linux/dmaengine.h>
1b340bd7 26
0664678a
PZ		 27#include <asm/irq.h>
28
1b340bd7
MB		 29#include <sound/core.h>
30#include <sound/pcm.h>
31#include <sound/initval.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/pxa2xx-lib.h>
d65a1458 35#include <sound/dmaengine_pcm.h>
1b340bd7 36
dd99a452 37#include "../../arm/pxa2xx-pcm.h"
1b340bd7
MB		 38#include "pxa-ssp.h"
39
40/*
41 * SSP audio private data
42 */
43struct ssp_priv {
f9efc9df 44 struct ssp_device *ssp;
1b340bd7 45 unsigned int sysclk;
737e370a
DM		 46 unsigned int dai_fmt;
47 unsigned int configured_dai_fmt;
1b340bd7 48#ifdef CONFIG_PM
f9efc9df
EM		 49 uint32_t cr0;
50 uint32_t cr1;
51 uint32_t to;
52 uint32_t psp;
1b340bd7
MB		 53#endif
54};
55
1b340bd7
MB		 56static void dump_registers(struct ssp_device *ssp)
57{
58 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
baffe169
HZ		 59 pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
60 pxa_ssp_read_reg(ssp, SSTO));
1b340bd7
MB		 61
62 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
baffe169
HZ		 63 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
64 pxa_ssp_read_reg(ssp, SSACD));
1b340bd7
MB		 65}
66
baffe169 67static void pxa_ssp_enable(struct ssp_device *ssp)
f9efc9df
EM		 68{
69 uint32_t sscr0;
70
71 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
72 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
73}
74
baffe169 75static void pxa_ssp_disable(struct ssp_device *ssp)
f9efc9df
EM		 76{
77 uint32_t sscr0;
78
79 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
80 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
81}
82
d93ca1ae 83static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
d65a1458 84 int out, struct snd_dmaengine_dai_dma_data *dma)
2d7e71fa 85{
d65a1458
DM		 86 dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES :
87 DMA_SLAVE_BUSWIDTH_2_BYTES;
88 dma->maxburst = 16;
89 dma->addr = ssp->phys_base + SSDR;
2d7e71fa
EM		 90}
91
dee89c4d 92static int pxa_ssp_startup(struct snd_pcm_substream *substream,
f0fba2ad 93 struct snd_soc_dai *cpu_dai)
1b340bd7 94{
f0fba2ad 95 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 96 struct ssp_device *ssp = priv->ssp;
d65a1458 97 struct snd_dmaengine_dai_dma_data *dma;
1b340bd7
MB		 98 int ret = 0;
99
100 if (!cpu_dai->active) {
6d3efa40 101 clk_prepare_enable(ssp->clk);
baffe169 102 pxa_ssp_disable(ssp);
1b340bd7 103 }
2d7e71fa 104
d65a1458 105 dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL);
d93ca1ae 106 if (!dma)
107 return -ENOMEM;
a671468d
DM		 108
109 dma->filter_data = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
110 &ssp->drcmr_tx : &ssp->drcmr_rx;
111
d65a1458 112 snd_soc_dai_set_dma_data(cpu_dai, substream, dma);
5f712b2b 113
1b340bd7
MB		 114 return ret;
115}
116
dee89c4d 117static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
f0fba2ad 118 struct snd_soc_dai *cpu_dai)
1b340bd7 119{
f0fba2ad 120 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 121 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 122
123 if (!cpu_dai->active) {
baffe169 124 pxa_ssp_disable(ssp);
6d3efa40 125 clk_disable_unprepare(ssp->clk);
1b340bd7 126 }
2d7e71fa 127
5f712b2b
DM		 128 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
129 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
1b340bd7
MB		 130}
131
132#ifdef CONFIG_PM
133
dc7d7b83 134static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
1b340bd7 135{
f0fba2ad 136 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 137 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 138
139 if (!cpu_dai->active)
6d3efa40 140 clk_prepare_enable(ssp->clk);
1b340bd7 141
f9efc9df
EM		 142 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
143 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
144 priv->to = __raw_readl(ssp->mmio_base + SSTO);
145 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
146
baffe169 147 pxa_ssp_disable(ssp);
6d3efa40 148 clk_disable_unprepare(ssp->clk);
1b340bd7
MB		 149 return 0;
150}
151
dc7d7b83 152static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
1b340bd7 153{
f0fba2ad 154 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df
EM		 155 struct ssp_device *ssp = priv->ssp;
156 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
1b340bd7 157
6d3efa40 158 clk_prepare_enable(ssp->clk);
f9efc9df
EM		 159
160 __raw_writel(sssr, ssp->mmio_base + SSSR);
f9efc9df
EM		 161 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
162 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
163 __raw_writel(priv->to, ssp->mmio_base + SSTO);
164 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
026384d6
DM		 165
166 if (cpu_dai->active)
baffe169 167 pxa_ssp_enable(ssp);
026384d6 168 else
6d3efa40 169 clk_disable_unprepare(ssp->clk);
1b340bd7
MB		 170
171 return 0;
172}
173
174#else
175#define pxa_ssp_suspend NULL
176#define pxa_ssp_resume NULL
177#endif
178
179/**
180 * ssp_set_clkdiv - set SSP clock divider
181 * @div: serial clock rate divider
182 */
baffe169 183static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
1b340bd7 184{
baffe169 185 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
1a297286 186
972a55b6 187 if (ssp->type == PXA25x_SSP) {
1a297286
PZ		 188 sscr0 &= ~0x0000ff00;
189 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
190 } else {
191 sscr0 &= ~0x000fff00;
192 sscr0 |= (div - 1) << 8; /* 1..4096 */
193 }
baffe169 194 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
1a297286
PZ		 195}
196
197/**
baffe169 198 * pxa_ssp_get_clkdiv - get SSP clock divider
1a297286 199 */
baffe169 200static u32 pxa_ssp_get_scr(struct ssp_device *ssp)
1a297286 201{
baffe169 202 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
1a297286 203 u32 div;
1b340bd7 204
972a55b6 205 if (ssp->type == PXA25x_SSP)
1a297286
PZ		 206 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
207 else
208 div = ((sscr0 >> 8) & 0xfff) + 1;
209 return div;
1b340bd7
MB		 210}
211
212/*
213 * Set the SSP ports SYSCLK.
214 */
215static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
216 int clk_id, unsigned int freq, int dir)
217{
f0fba2ad 218 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 219 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 220 int val;
221
baffe169 222 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
20a41eac 223 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 224
225 dev_dbg(&ssp->pdev->dev,
449bd54d 226 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
1b340bd7
MB		 227 cpu_dai->id, clk_id, freq);
228
229 switch (clk_id) {
230 case PXA_SSP_CLK_NET_PLL:
231 sscr0 |= SSCR0_MOD;
232 break;
233 case PXA_SSP_CLK_PLL:
234 /* Internal PLL is fixed */
972a55b6 235 if (ssp->type == PXA25x_SSP)
1b340bd7
MB		 236 priv->sysclk = 1843200;
237 else
238 priv->sysclk = 13000000;
239 break;
240 case PXA_SSP_CLK_EXT:
241 priv->sysclk = freq;
242 sscr0 |= SSCR0_ECS;
243 break;
244 case PXA_SSP_CLK_NET:
245 priv->sysclk = freq;
246 sscr0 |= SSCR0_NCS | SSCR0_MOD;
247 break;
248 case PXA_SSP_CLK_AUDIO:
249 priv->sysclk = 0;
baffe169 250 pxa_ssp_set_scr(ssp, 1);
20a41eac 251 sscr0 |= SSCR0_ACS;
1b340bd7
MB		 252 break;
253 default:
254 return -ENODEV;
255 }
256
257 /* The SSP clock must be disabled when changing SSP clock mode
258 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
972a55b6 259 if (ssp->type != PXA3xx_SSP)
6d3efa40 260 clk_disable_unprepare(ssp->clk);
baffe169
HZ		 261 val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0;
262 pxa_ssp_write_reg(ssp, SSCR0, val);
972a55b6 263 if (ssp->type != PXA3xx_SSP)
6d3efa40 264 clk_prepare_enable(ssp->clk);
1b340bd7
MB		 265
266 return 0;
267}
268
269/*
270 * Set the SSP clock dividers.
271 */
272static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
273 int div_id, int div)
274{
f0fba2ad 275 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 276 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 277 int val;
278
279 switch (div_id) {
280 case PXA_SSP_AUDIO_DIV_ACDS:
baffe169
HZ		 281 val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
282 pxa_ssp_write_reg(ssp, SSACD, val);
1b340bd7
MB		 283 break;
284 case PXA_SSP_AUDIO_DIV_SCDB:
baffe169 285 val = pxa_ssp_read_reg(ssp, SSACD);
1b340bd7 286 val &= ~SSACD_SCDB;
972a55b6 287 if (ssp->type == PXA3xx_SSP)
1b340bd7 288 val &= ~SSACD_SCDX8;
1b340bd7
MB		 289 switch (div) {
290 case PXA_SSP_CLK_SCDB_1:
291 val |= SSACD_SCDB;
292 break;
293 case PXA_SSP_CLK_SCDB_4:
294 break;
1b340bd7 295 case PXA_SSP_CLK_SCDB_8:
972a55b6 296 if (ssp->type == PXA3xx_SSP)
1b340bd7
MB		 297 val |= SSACD_SCDX8;
298 else
299 return -EINVAL;
300 break;
1b340bd7
MB		 301 default:
302 return -EINVAL;
303 }
baffe169 304 pxa_ssp_write_reg(ssp, SSACD, val);
1b340bd7
MB		 305 break;
306 case PXA_SSP_DIV_SCR:
baffe169 307 pxa_ssp_set_scr(ssp, div);
1b340bd7
MB		 308 break;
309 default:
310 return -ENODEV;
311 }
312
313 return 0;
314}
315
316/*
317 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
318 */
85488037
MB		 319static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
320 int source, unsigned int freq_in, unsigned int freq_out)
1b340bd7 321{
f0fba2ad 322 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 323 struct ssp_device *ssp = priv->ssp;
baffe169 324 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
1b340bd7 325
972a55b6 326 if (ssp->type == PXA3xx_SSP)
baffe169 327 pxa_ssp_write_reg(ssp, SSACDD, 0);
1b340bd7
MB		 328
329 switch (freq_out) {
330 case 5622000:
331 break;
332 case 11345000:
333 ssacd |= (0x1 << 4);
334 break;
335 case 12235000:
336 ssacd |= (0x2 << 4);
337 break;
338 case 14857000:
339 ssacd |= (0x3 << 4);
340 break;
341 case 32842000:
342 ssacd |= (0x4 << 4);
343 break;
344 case 48000000:
345 ssacd |= (0x5 << 4);
346 break;
347 case 0:
348 /* Disable */
349 break;
350
351 default:
1b340bd7
MB		 352 /* PXA3xx has a clock ditherer which can be used to generate
353 * a wider range of frequencies - calculate a value for it.
354 */
972a55b6 355 if (ssp->type == PXA3xx_SSP) {
1b340bd7
MB		 356 u32 val;
357 u64 tmp = 19968;
1dbe6923 358
1b340bd7
MB		 359 tmp *= 1000000;
360 do_div(tmp, freq_out);
361 val = tmp;
362
a419aef8 363 val = (val << 16) | 64;
baffe169 364 pxa_ssp_write_reg(ssp, SSACDD, val);
1b340bd7
MB		 365
366 ssacd |= (0x6 << 4);
367
368 dev_dbg(&ssp->pdev->dev,
449bd54d 369 "Using SSACDD %x to supply %uHz\n",
1b340bd7
MB		 370 val, freq_out);
371 break;
372 }
1b340bd7
MB		 373
374 return -EINVAL;
375 }
376
baffe169 377 pxa_ssp_write_reg(ssp, SSACD, ssacd);
1b340bd7
MB		 378
379 return 0;
380}
381
382/*
383 * Set the active slots in TDM/Network mode
384 */
385static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
a5479e38 386 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1b340bd7 387{
f0fba2ad 388 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 389 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 390 u32 sscr0;
391
baffe169 392 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
a5479e38 393 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
1b340bd7 394
a5479e38
DR		 395 /* set slot width */
396 if (slot_width > 16)
397 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
398 else
399 sscr0 |= SSCR0_DataSize(slot_width);
400
401 if (slots > 1) {
402 /* enable network mode */
403 sscr0 |= SSCR0_MOD;
404
405 /* set number of active slots */
406 sscr0 |= SSCR0_SlotsPerFrm(slots);
407
408 /* set active slot mask */
baffe169
HZ		 409 pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
410 pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
a5479e38 411 }
baffe169 412 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
1b340bd7 413
1b340bd7
MB		 414 return 0;
415}
416
417/*
418 * Tristate the SSP DAI lines
419 */
420static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
421 int tristate)
422{
f0fba2ad 423 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 424 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 425 u32 sscr1;
426
baffe169 427 sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
1b340bd7
MB		 428 if (tristate)
429 sscr1 &= ~SSCR1_TTE;
430 else
431 sscr1 |= SSCR1_TTE;
baffe169 432 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
1b340bd7
MB		 433
434 return 0;
435}
436
737e370a
DM		 437static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
438 unsigned int fmt)
439{
440 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
441
442 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
443 case SND_SOC_DAIFMT_CBM_CFM:
444 case SND_SOC_DAIFMT_CBM_CFS:
445 case SND_SOC_DAIFMT_CBS_CFS:
446 break;
447 default:
448 return -EINVAL;
449 }
450
451 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
452 case SND_SOC_DAIFMT_NB_NF:
453 case SND_SOC_DAIFMT_NB_IF:
454 case SND_SOC_DAIFMT_IB_IF:
455 case SND_SOC_DAIFMT_IB_NF:
456 break;
457 default:
458 return -EINVAL;
459 }
460
461 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
462 case SND_SOC_DAIFMT_I2S:
463 case SND_SOC_DAIFMT_DSP_A:
464 case SND_SOC_DAIFMT_DSP_B:
465 break;
466
467 default:
468 return -EINVAL;
469 }
470
471 /* Settings will be applied in hw_params() */
472 priv->dai_fmt = fmt;
473
474 return 0;
475}
476
1b340bd7
MB		 477/*
478 * Set up the SSP DAI format.
479 * The SSP Port must be inactive before calling this function as the
480 * physical interface format is changed.
481 */
737e370a 482static int pxa_ssp_configure_dai_fmt(struct ssp_priv *priv)
1b340bd7 483{
f9efc9df 484 struct ssp_device *ssp = priv->ssp;
f5d1e5ed 485 u32 sscr0, sscr1, sspsp, scfr;
1b340bd7 486
cbf1146d 487 /* check if we need to change anything at all */
737e370a 488 if (priv->configured_dai_fmt == priv->dai_fmt)
cbf1146d
DM		 489 return 0;
490
1b340bd7 491 /* reset port settings */
baffe169 492 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
737e370a
DM		 493 ~(SSCR0_PSP | SSCR0_MOD);
494 sscr1 = pxa_ssp_read_reg(ssp, SSCR1) &
495 ~(SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR |
496 SSCR1_RWOT | SSCR1_TRAIL | SSCR1_TFT | SSCR1_RFT);
497 sspsp = pxa_ssp_read_reg(ssp, SSPSP) &
498 ~(SSPSP_SFRMP | SSPSP_SCMODE(3));
1b340bd7 499
737e370a
DM		 500 sscr1 |= SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
501
502 switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1b340bd7 503 case SND_SOC_DAIFMT_CBM_CFM:
f5d1e5ed 504 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
1b340bd7
MB		 505 break;
506 case SND_SOC_DAIFMT_CBM_CFS:
f5d1e5ed 507 sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
1b340bd7
MB		 508 break;
509 case SND_SOC_DAIFMT_CBS_CFS:
510 break;
511 default:
512 return -EINVAL;
513 }
514
737e370a 515 switch (priv->dai_fmt & SND_SOC_DAIFMT_INV_MASK) {
fa44c077
DR		 516 case SND_SOC_DAIFMT_NB_NF:
517 sspsp |= SSPSP_SFRMP;
518 break;
519 case SND_SOC_DAIFMT_NB_IF:
520 break;
521 case SND_SOC_DAIFMT_IB_IF:
522 sspsp |= SSPSP_SCMODE(2);
523 break;
524 case SND_SOC_DAIFMT_IB_NF:
525 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
526 break;
527 default:
528 return -EINVAL;
529 }
1b340bd7 530
737e370a 531 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1b340bd7 532 case SND_SOC_DAIFMT_I2S:
72d74664 533 sscr0 |= SSCR0_PSP;
1b340bd7 534 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
0ce36c5f 535 /* See hw_params() */
1b340bd7
MB		 536 break;
537
538 case SND_SOC_DAIFMT_DSP_A:
539 sspsp |= SSPSP_FSRT;
540 case SND_SOC_DAIFMT_DSP_B:
541 sscr0 |= SSCR0_MOD | SSCR0_PSP;
542 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
1b340bd7
MB		 543 break;
544
545 default:
546 return -EINVAL;
547 }
548
baffe169
HZ		 549 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
550 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
551 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
1b340bd7 552
737e370a 553 switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
f5d1e5ed
HZ		 554 case SND_SOC_DAIFMT_CBM_CFM:
555 case SND_SOC_DAIFMT_CBM_CFS:
556 scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
557 pxa_ssp_write_reg(ssp, SSCR1, scfr);
558
559 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
560 cpu_relax();
561 break;
562 }
563
1b340bd7
MB		 564 dump_registers(ssp);
565
566 /* Since we are configuring the timings for the format by hand
567 * we have to defer some things until hw_params() where we
568 * know parameters like the sample size.
569 */
737e370a 570 priv->configured_dai_fmt = priv->dai_fmt;
1b340bd7
MB		 571
572 return 0;
573}
574
575/*
576 * Set the SSP audio DMA parameters and sample size.
577 * Can be called multiple times by oss emulation.
578 */
579static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
dee89c4d 580 struct snd_pcm_hw_params *params,
f0fba2ad 581 struct snd_soc_dai *cpu_dai)
1b340bd7 582{
f0fba2ad 583 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 584 struct ssp_device *ssp = priv->ssp;
2d7e71fa 585 int chn = params_channels(params);
1b340bd7
MB		 586 u32 sscr0;
587 u32 sspsp;
588 int width = snd_pcm_format_physical_width(params_format(params));
baffe169 589 int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
d65a1458 590 struct snd_dmaengine_dai_dma_data *dma_data;
737e370a 591 int ret;
5f712b2b 592
f0fba2ad 593 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
1b340bd7 594
92429069
PZ		 595 /* Network mode with one active slot (ttsa == 1) can be used
596 * to force 16-bit frame width on the wire (for S16_LE), even
597 * with two channels. Use 16-bit DMA transfers for this case.
598 */
d93ca1ae 599 pxa_ssp_set_dma_params(ssp,
600 ((chn == 2) && (ttsa != 1)) || (width == 32),
601 substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
5f712b2b 602
1b340bd7 603 /* we can only change the settings if the port is not in use */
baffe169 604 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
1b340bd7
MB		 605 return 0;
606
737e370a
DM		 607 ret = pxa_ssp_configure_dai_fmt(priv);
608 if (ret < 0)
609 return ret;
610
1b340bd7 611 /* clear selected SSP bits */
baffe169 612 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
1b340bd7
MB		 613
614 /* bit size */
1b340bd7
MB		 615 switch (params_format(params)) {
616 case SNDRV_PCM_FORMAT_S16_LE:
972a55b6 617 if (ssp->type == PXA3xx_SSP)
1b340bd7 618 sscr0 |= SSCR0_FPCKE;
1b340bd7 619 sscr0 |= SSCR0_DataSize(16);
1b340bd7
MB		 620 break;
621 case SNDRV_PCM_FORMAT_S24_LE:
622 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
1b340bd7
MB		 623 break;
624 case SNDRV_PCM_FORMAT_S32_LE:
625 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
1b340bd7
MB		 626 break;
627 }
baffe169 628 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
1b340bd7
MB		 629
630 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
631 case SND_SOC_DAIFMT_I2S:
baffe169 632 sspsp = pxa_ssp_read_reg(ssp, SSPSP);
72d74664 633
baffe169 634 if ((pxa_ssp_get_scr(ssp) == 4) && (width == 16)) {
72d74664 635 /* This is a special case where the bitclk is 64fs
34e82433
CG		 636 * and we're not dealing with 2*32 bits of audio
637 * samples.
638 *
639 * The SSP values used for that are all found out by
640 * trying and failing a lot; some of the registers
641 * needed for that mode are only available on PXA3xx.
642 */
972a55b6 643 if (ssp->type != PXA3xx_SSP)
72d74664
DM		 644 return -EINVAL;
645
646 sspsp |= SSPSP_SFRMWDTH(width * 2);
647 sspsp |= SSPSP_SFRMDLY(width * 4);
648 sspsp |= SSPSP_EDMYSTOP(3);
649 sspsp |= SSPSP_DMYSTOP(3);
650 sspsp |= SSPSP_DMYSTRT(1);
0ce36c5f
MB		 651 } else {
652 /* The frame width is the width the LRCLK is
653 * asserted for; the delay is expressed in
654 * half cycle units. We need the extra cycle
655 * because the data starts clocking out one BCLK
656 * after LRCLK changes polarity.
657 */
658 sspsp |= SSPSP_SFRMWDTH(width + 1);
659 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
660 sspsp |= SSPSP_DMYSTRT(1);
661 }
72d74664 662
baffe169 663 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
1b340bd7
MB		 664 break;
665 default:
666 break;
667 }
668
72d74664 669 /* When we use a network mode, we always require TDM slots
1b340bd7
MB		 670 * - complain loudly and fail if they've not been set up yet.
671 */
92429069 672 if ((sscr0 & SSCR0_MOD) && !ttsa) {
1b340bd7
MB		 673 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
674 return -EINVAL;
675 }
676
677 dump_registers(ssp);
678
679 return 0;
680}
681
273b72c8
DM		 682static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
683 struct ssp_device *ssp, int value)
684{
685 uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
686 uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
687 uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
688 uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
689
690 if (value && (sscr0 & SSCR0_SSE))
691 pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
692
693 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
694 if (value)
695 sscr1 |= SSCR1_TSRE;
696 else
697 sscr1 &= ~SSCR1_TSRE;
698 } else {
699 if (value)
700 sscr1 |= SSCR1_RSRE;
701 else
702 sscr1 &= ~SSCR1_RSRE;
703 }
704
705 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
706
707 if (value) {
708 pxa_ssp_write_reg(ssp, SSSR, sssr);
709 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
710 pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
711 }
712}
713
dee89c4d 714static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
f0fba2ad 715 struct snd_soc_dai *cpu_dai)
1b340bd7 716{
1b340bd7 717 int ret = 0;
f0fba2ad 718 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 719 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 720 int val;
721
722 switch (cmd) {
723 case SNDRV_PCM_TRIGGER_RESUME:
baffe169 724 pxa_ssp_enable(ssp);
1b340bd7
MB		 725 break;
726 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
273b72c8 727 pxa_ssp_set_running_bit(substream, ssp, 1);
baffe169
HZ		 728 val = pxa_ssp_read_reg(ssp, SSSR);
729 pxa_ssp_write_reg(ssp, SSSR, val);
1b340bd7
MB		 730 break;
731 case SNDRV_PCM_TRIGGER_START:
273b72c8 732 pxa_ssp_set_running_bit(substream, ssp, 1);
1b340bd7
MB		 733 break;
734 case SNDRV_PCM_TRIGGER_STOP:
273b72c8 735 pxa_ssp_set_running_bit(substream, ssp, 0);
1b340bd7
MB		 736 break;
737 case SNDRV_PCM_TRIGGER_SUSPEND:
baffe169 738 pxa_ssp_disable(ssp);
1b340bd7
MB		 739 break;
740 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
273b72c8 741 pxa_ssp_set_running_bit(substream, ssp, 0);
1b340bd7
MB		 742 break;
743
744 default:
745 ret = -EINVAL;
746 }
747
748 dump_registers(ssp);
749
750 return ret;
751}
752
f0fba2ad 753static int pxa_ssp_probe(struct snd_soc_dai *dai)
1b340bd7 754{
2023c90c 755 struct device *dev = dai->dev;
1b340bd7
MB		 756 struct ssp_priv *priv;
757 int ret;
758
759 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
760 if (!priv)
761 return -ENOMEM;
762
2023c90c
DM		 763 if (dev->of_node) {
764 struct device_node *ssp_handle;
765
766 ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
767 if (!ssp_handle) {
768 dev_err(dev, "unable to get 'port' phandle\n");
45487289
DC		 769 ret = -ENODEV;
770 goto err_priv;
2023c90c
DM		 771 }
772
773 priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
774 if (priv->ssp == NULL) {
775 ret = -ENODEV;
776 goto err_priv;
777 }
778 } else {
779 priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
780 if (priv->ssp == NULL) {
781 ret = -ENODEV;
782 goto err_priv;
783 }
1b340bd7
MB		 784 }
785
a5735b7e 786 priv->dai_fmt = (unsigned int) -1;
f0fba2ad 787 snd_soc_dai_set_drvdata(dai, priv);
1b340bd7
MB		 788
789 return 0;
790
791err_priv:
792 kfree(priv);
793 return ret;
794}
795
f0fba2ad 796static int pxa_ssp_remove(struct snd_soc_dai *dai)
1b340bd7 797{
f0fba2ad
LG		 798 struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
799
baffe169 800 pxa_ssp_free(priv->ssp);
014a2755 801 kfree(priv);
f0fba2ad 802 return 0;
1b340bd7
MB		 803}
804
805#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
806 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
8d8bf58b
QZ		 807 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
808 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
1b340bd7
MB		 809 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
810
9301503a 811#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1b340bd7 812
85e7652d 813static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
6335d055
EM		 814 .startup = pxa_ssp_startup,
815 .shutdown = pxa_ssp_shutdown,
816 .trigger = pxa_ssp_trigger,
817 .hw_params = pxa_ssp_hw_params,
818 .set_sysclk = pxa_ssp_set_dai_sysclk,
819 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
820 .set_pll = pxa_ssp_set_dai_pll,
821 .set_fmt = pxa_ssp_set_dai_fmt,
822 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
823 .set_tristate = pxa_ssp_set_dai_tristate,
824};
825
f0fba2ad 826static struct snd_soc_dai_driver pxa_ssp_dai = {
1b340bd7
MB		 827 .probe = pxa_ssp_probe,
828 .remove = pxa_ssp_remove,
829 .suspend = pxa_ssp_suspend,
830 .resume = pxa_ssp_resume,
831 .playback = {
832 .channels_min = 1,
f34762b6 833 .channels_max = 8,
1b340bd7
MB		 834 .rates = PXA_SSP_RATES,
835 .formats = PXA_SSP_FORMATS,
836 },
837 .capture = {
838 .channels_min = 1,
f34762b6 839 .channels_max = 8,
1b340bd7
MB		 840 .rates = PXA_SSP_RATES,
841 .formats = PXA_SSP_FORMATS,
842 },
6335d055 843 .ops = &pxa_ssp_dai_ops,
f0fba2ad
LG		 844};
845
e580f1ce
KM		 846static const struct snd_soc_component_driver pxa_ssp_component = {
847 .name = "pxa-ssp",
848};
849
2023c90c
DM		 850#ifdef CONFIG_OF
851static const struct of_device_id pxa_ssp_of_ids[] = {
852 { .compatible = "mrvl,pxa-ssp-dai" },
4c715c75 853 {}
2023c90c 854};
baafd373 855MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);
2023c90c
DM		 856#endif
857
570f6fe1 858static int asoc_ssp_probe(struct platform_device *pdev)
f0fba2ad 859{
637ce53a
AL		 860 return devm_snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
861 &pxa_ssp_dai, 1);
f0fba2ad
LG		 862}
863
864static struct platform_driver asoc_ssp_driver = {
865 .driver = {
2023c90c 866 .name = "pxa-ssp-dai",
2023c90c 867 .of_match_table = of_match_ptr(pxa_ssp_of_ids),
1b340bd7 868 },
f0fba2ad
LG		 869
870 .probe = asoc_ssp_probe,
1b340bd7 871};
1b340bd7 872
2f702a19 873module_platform_driver(asoc_ssp_driver);
3f4b783c 874
1b340bd7
MB		 875/* Module information */
876MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
877MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
878MODULE_LICENSE("GPL");
e5b7d71a 879MODULE_ALIAS("platform:pxa-ssp-dai");
Linux 6.x block layer and io_uring tree(s)