[linux-block.git] / sound / soc / pxa / mmp-sspa.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * linux/sound/soc/pxa/mmp-sspa.c
 * Base on pxa2xx-ssp.c
 *
 * Copyright (C) 2011 Marvell International Ltd.
 */
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/dmaengine.h>
#include <linux/pm_runtime.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/pxa2xx-lib.h>
#include <sound/dmaengine_pcm.h>
#include "mmp-sspa.h"

/*
 * SSPA audio private data
 */
struct sspa_priv {
	void __iomem *tx_base;
	void __iomem *rx_base;

	struct snd_dmaengine_dai_dma_data playback_dma_data;
	struct snd_dmaengine_dai_dma_data capture_dma_data;
	struct clk *clk;
	struct clk *audio_clk;
	struct clk *sysclk;

	int running_cnt;
	u32 sp;
	u32 ctrl;
};

static void mmp_sspa_tx_enable(struct sspa_priv *sspa)
{
	unsigned int sspa_sp = sspa->sp;

	sspa_sp &= ~SSPA_SP_MSL;
	sspa_sp |= SSPA_SP_S_EN;
	sspa_sp |= SSPA_SP_WEN;
	__raw_writel(sspa_sp, sspa->tx_base + SSPA_SP);
}

static void mmp_sspa_tx_disable(struct sspa_priv *sspa)
{
	unsigned int sspa_sp = sspa->sp;

	sspa_sp &= ~SSPA_SP_MSL;
	sspa_sp &= ~SSPA_SP_S_EN;
	sspa_sp |= SSPA_SP_WEN;
	__raw_writel(sspa_sp, sspa->tx_base + SSPA_SP);
}

static void mmp_sspa_rx_enable(struct sspa_priv *sspa)
{
	unsigned int sspa_sp = sspa->sp;

	sspa_sp |= SSPA_SP_S_EN;
	sspa_sp |= SSPA_SP_WEN;
	__raw_writel(sspa_sp, sspa->rx_base + SSPA_SP);
}

static void mmp_sspa_rx_disable(struct sspa_priv *sspa)
{
	unsigned int sspa_sp = sspa->sp;

	sspa_sp &= ~SSPA_SP_S_EN;
	sspa_sp |= SSPA_SP_WEN;
	__raw_writel(sspa_sp, sspa->rx_base + SSPA_SP);
}

static int mmp_sspa_startup(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);

	clk_prepare_enable(sspa->sysclk);
	clk_prepare_enable(sspa->clk);

	return 0;
}

static void mmp_sspa_shutdown(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);

	clk_disable_unprepare(sspa->clk);
	clk_disable_unprepare(sspa->sysclk);
}

/*
 * Set the SSP ports SYSCLK.
 */
static int mmp_sspa_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
				    int clk_id, unsigned int freq, int dir)
{
	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(cpu_dai);
	struct device *dev = cpu_dai->component->dev;
	int ret = 0;

	if (dev->of_node)
		return -ENOTSUPP;

	switch (clk_id) {
	case MMP_SSPA_CLK_AUDIO:
		ret = clk_set_rate(sspa->audio_clk, freq);
		if (ret)
			return ret;
		break;
	case MMP_SSPA_CLK_PLL:
	case MMP_SSPA_CLK_VCXO:
		/* not support yet */
		return -EINVAL;
	default:
		return -EINVAL;
	}

	return 0;
}

static int mmp_sspa_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
				 int source, unsigned int freq_in,
				 unsigned int freq_out)
{
	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(cpu_dai);
	struct device *dev = cpu_dai->component->dev;
	int ret = 0;

	if (dev->of_node)
		return -ENOTSUPP;

	switch (pll_id) {
	case MMP_SYSCLK:
		ret = clk_set_rate(sspa->sysclk, freq_out);
		if (ret)
			return ret;
		break;
	case MMP_SSPA_CLK:
		ret = clk_set_rate(sspa->clk, freq_out);
		if (ret)
			return ret;
		break;
	default:
		return -ENODEV;
	}

	return 0;
}

/*
 * Set up the sspa dai format.
 */
static int mmp_sspa_set_dai_fmt(struct snd_soc_dai *cpu_dai,
				 unsigned int fmt)
{
	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(cpu_dai);

	/* reset port settings */
	sspa->sp   = SSPA_SP_WEN | SSPA_SP_S_RST | SSPA_SP_FFLUSH;
	sspa->ctrl = 0;

	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
	case SND_SOC_DAIFMT_BP_FP:
		sspa->sp |= SSPA_SP_MSL;
		break;
	case SND_SOC_DAIFMT_BC_FC:
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		sspa->sp |= SSPA_SP_FSP;
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		sspa->ctrl |= SSPA_CTL_XDATDLY(1);
		break;
	default:
		return -EINVAL;
	}

	/* Since we are configuring the timings for the format by hand
	 * we have to defer some things until hw_params() where we
	 * know parameters like the sample size.
	 */
	return 0;
}

/*
 * Set the SSPA audio DMA parameters and sample size.
 * Can be called multiple times by oss emulation.
 */
static int mmp_sspa_hw_params(struct snd_pcm_substream *substream,
			       struct snd_pcm_hw_params *params,
			       struct snd_soc_dai *dai)
{
	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
	struct device *dev = dai->component->dev;
	u32 sspa_ctrl = sspa->ctrl;
	int bits;
	int bitval;

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		bits = 8;
		bitval = SSPA_CTL_8_BITS;
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		bits = 16;
		bitval = SSPA_CTL_16_BITS;
		break;
	case SNDRV_PCM_FORMAT_S24_3LE:
		bits = 24;
		bitval = SSPA_CTL_24_BITS;
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		bits = 32;
		bitval = SSPA_CTL_32_BITS;
		break;
	default:
		return -EINVAL;
	}

	sspa_ctrl &= ~SSPA_CTL_XPH;
	if (dev->of_node || params_channels(params) == 2)
		sspa_ctrl |= SSPA_CTL_XPH;

	sspa_ctrl &= ~SSPA_CTL_XWDLEN1_MASK;
	sspa_ctrl |= SSPA_CTL_XWDLEN1(bitval);

	sspa_ctrl &= ~SSPA_CTL_XWDLEN2_MASK;
	sspa_ctrl |= SSPA_CTL_XWDLEN2(bitval);

	sspa_ctrl &= ~SSPA_CTL_XSSZ1_MASK;
	sspa_ctrl |= SSPA_CTL_XSSZ1(bitval);

	sspa_ctrl &= ~SSPA_CTL_XSSZ2_MASK;
	sspa_ctrl |= SSPA_CTL_XSSZ2(bitval);

	sspa->sp &= ~SSPA_SP_FWID_MASK;
	sspa->sp |= SSPA_SP_FWID(bits - 1);

	sspa->sp &= ~SSPA_TXSP_FPER_MASK;
	sspa->sp |= SSPA_TXSP_FPER(bits * 2 - 1);

	if (dev->of_node) {
		clk_set_rate(sspa->clk, params_rate(params) *
					params_channels(params) * bits);
	}

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		__raw_writel(sspa_ctrl, sspa->tx_base + SSPA_CTL);
		__raw_writel(0x1, sspa->tx_base + SSPA_FIFO_UL);
	} else {
		__raw_writel(sspa_ctrl, sspa->rx_base + SSPA_CTL);
		__raw_writel(0x0, sspa->rx_base + SSPA_FIFO_UL);
	}

	return 0;
}

static int mmp_sspa_trigger(struct snd_pcm_substream *substream, int cmd,
			     struct snd_soc_dai *dai)
{
	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		/*
		 * whatever playback or capture, must enable rx.
		 * this is a hw issue, so need check if rx has been
		 * enabled or not; if has been enabled by another
		 * stream, do not enable again.
		 */
		if (!sspa->running_cnt)
			mmp_sspa_rx_enable(sspa);

		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			mmp_sspa_tx_enable(sspa);

		sspa->running_cnt++;
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		sspa->running_cnt--;

		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			mmp_sspa_tx_disable(sspa);

		/* have no capture stream, disable rx port */
		if (!sspa->running_cnt)
			mmp_sspa_rx_disable(sspa);
		break;

	default:
		ret = -EINVAL;
	}

	return ret;
}

static int mmp_sspa_probe(struct snd_soc_dai *dai)
{
	struct sspa_priv *sspa = dev_get_drvdata(dai->dev);

	snd_soc_dai_init_dma_data(dai,
				&sspa->playback_dma_data,
				&sspa->capture_dma_data);

	return 0;
}

#define MMP_SSPA_RATES SNDRV_PCM_RATE_8000_192000
#define MMP_SSPA_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
		SNDRV_PCM_FMTBIT_S16_LE | \
		SNDRV_PCM_FMTBIT_S24_3LE | \
		SNDRV_PCM_FMTBIT_S32_LE)

static const struct snd_soc_dai_ops mmp_sspa_dai_ops = {
	.startup	= mmp_sspa_startup,
	.shutdown	= mmp_sspa_shutdown,
	.trigger	= mmp_sspa_trigger,
	.hw_params	= mmp_sspa_hw_params,
	.set_sysclk	= mmp_sspa_set_dai_sysclk,
	.set_pll	= mmp_sspa_set_dai_pll,
	.set_fmt	= mmp_sspa_set_dai_fmt,
};

static struct snd_soc_dai_driver mmp_sspa_dai = {
	.probe = mmp_sspa_probe,
	.playback = {
		.channels_min = 1,
		.channels_max = 128,
		.rates = MMP_SSPA_RATES,
		.formats = MMP_SSPA_FORMATS,
	},
	.capture = {
		.channels_min = 1,
		.channels_max = 2,
		.rates = MMP_SSPA_RATES,
		.formats = MMP_SSPA_FORMATS,
	},
	.ops = &mmp_sspa_dai_ops,
};

#define MMP_PCM_INFO (SNDRV_PCM_INFO_MMAP |	\
		SNDRV_PCM_INFO_MMAP_VALID |	\
		SNDRV_PCM_INFO_INTERLEAVED |	\
		SNDRV_PCM_INFO_PAUSE |		\
		SNDRV_PCM_INFO_RESUME |		\
		SNDRV_PCM_INFO_NO_PERIOD_WAKEUP)

static const struct snd_pcm_hardware mmp_pcm_hardware[] = {
	{
		.info			= MMP_PCM_INFO,
		.period_bytes_min	= 1024,
		.period_bytes_max	= 2048,
		.periods_min		= 2,
		.periods_max		= 32,
		.buffer_bytes_max	= 4096,
		.fifo_size		= 32,
	},
	{
		.info			= MMP_PCM_INFO,
		.period_bytes_min	= 1024,
		.period_bytes_max	= 2048,
		.periods_min		= 2,
		.periods_max		= 32,
		.buffer_bytes_max	= 4096,
		.fifo_size		= 32,
	},
};

static const struct snd_dmaengine_pcm_config mmp_pcm_config = {
	.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
	.pcm_hardware = mmp_pcm_hardware,
	.prealloc_buffer_size = 4096,
};

static int mmp_pcm_mmap(struct snd_soc_component *component,
			struct snd_pcm_substream *substream,
			struct vm_area_struct *vma)
{
	vm_flags_set(vma, VM_DONTEXPAND | VM_DONTDUMP);
	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
	return remap_pfn_range(vma, vma->vm_start,
		substream->dma_buffer.addr >> PAGE_SHIFT,
		vma->vm_end - vma->vm_start, vma->vm_page_prot);
}

static int mmp_sspa_open(struct snd_soc_component *component,
			 struct snd_pcm_substream *substream)
{
	struct sspa_priv *sspa = snd_soc_component_get_drvdata(component);

	pm_runtime_get_sync(component->dev);

	/* we can only change the settings if the port is not in use */
	if ((__raw_readl(sspa->tx_base + SSPA_SP) & SSPA_SP_S_EN) ||
	    (__raw_readl(sspa->rx_base + SSPA_SP) & SSPA_SP_S_EN)) {
		dev_err(component->dev,
			"can't change hardware dai format: stream is in use\n");
		return -EBUSY;
	}

	__raw_writel(sspa->sp, sspa->tx_base + SSPA_SP);
	__raw_writel(sspa->sp, sspa->rx_base + SSPA_SP);

	sspa->sp &= ~(SSPA_SP_S_RST | SSPA_SP_FFLUSH);
	__raw_writel(sspa->sp, sspa->tx_base + SSPA_SP);
	__raw_writel(sspa->sp, sspa->rx_base + SSPA_SP);

	/*
	 * FIXME: hw issue, for the tx serial port,
	 * can not config the master/slave mode;
	 * so must clean this bit.
	 * The master/slave mode has been set in the
	 * rx port.
	 */
	__raw_writel(sspa->sp & ~SSPA_SP_MSL, sspa->tx_base + SSPA_SP);

	__raw_writel(sspa->ctrl, sspa->tx_base + SSPA_CTL);
	__raw_writel(sspa->ctrl, sspa->rx_base + SSPA_CTL);

	return 0;
}

static int mmp_sspa_close(struct snd_soc_component *component,
			  struct snd_pcm_substream *substream)
{
	pm_runtime_put_sync(component->dev);
	return 0;
}

static const struct snd_soc_component_driver mmp_sspa_component = {
	.name			= "mmp-sspa",
	.mmap			= mmp_pcm_mmap,
	.open			= mmp_sspa_open,
	.close			= mmp_sspa_close,
	.legacy_dai_naming	= 1,
};

static int asoc_mmp_sspa_probe(struct platform_device *pdev)
{
	struct sspa_priv *sspa;
	int ret;

	sspa = devm_kzalloc(&pdev->dev,
				sizeof(struct sspa_priv), GFP_KERNEL);
	if (!sspa)
		return -ENOMEM;

	if (pdev->dev.of_node) {
		sspa->rx_base = devm_platform_ioremap_resource(pdev, 0);
		if (IS_ERR(sspa->rx_base))
			return PTR_ERR(sspa->rx_base);

		sspa->tx_base = devm_platform_ioremap_resource(pdev, 1);
		if (IS_ERR(sspa->tx_base))
			return PTR_ERR(sspa->tx_base);

		sspa->clk = devm_clk_get(&pdev->dev, "bitclk");
		if (IS_ERR(sspa->clk))
			return PTR_ERR(sspa->clk);

		sspa->audio_clk = devm_clk_get(&pdev->dev, "audio");
		if (IS_ERR(sspa->audio_clk))
			return PTR_ERR(sspa->audio_clk);
	} else {
		struct resource *res;

		res = platform_get_resource(pdev, IORESOURCE_IO, 0);
		if (res == NULL)
			return -ENODEV;

		sspa->rx_base = devm_ioremap(&pdev->dev, res->start, 0x30);
		if (!sspa->rx_base)
			return -ENOMEM;

		sspa->tx_base = devm_ioremap(&pdev->dev,
					     res->start + 0x80, 0x30);
		if (!sspa->tx_base)
			return -ENOMEM;

		sspa->clk = devm_clk_get(&pdev->dev, NULL);
		if (IS_ERR(sspa->clk))
			return PTR_ERR(sspa->clk);

		sspa->audio_clk = clk_get(NULL, "mmp-audio");
		if (IS_ERR(sspa->audio_clk))
			return PTR_ERR(sspa->audio_clk);

		sspa->sysclk = clk_get(NULL, "mmp-sysclk");
		if (IS_ERR(sspa->sysclk)) {
			clk_put(sspa->audio_clk);
			return PTR_ERR(sspa->sysclk);
		}
	}
	platform_set_drvdata(pdev, sspa);

	sspa->playback_dma_data.maxburst = 4;
	sspa->capture_dma_data.maxburst = 4;
	/* You know, these addresses are actually ignored. */
	sspa->capture_dma_data.addr = SSPA_D;
	sspa->playback_dma_data.addr = 0x80 + SSPA_D;

	if (pdev->dev.of_node) {
		ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
						      &mmp_pcm_config, 0);
		if (ret)
			return ret;
	}

	ret = devm_snd_soc_register_component(&pdev->dev, &mmp_sspa_component,
					      &mmp_sspa_dai, 1);
	if (ret)
		return ret;

	pm_runtime_enable(&pdev->dev);
	clk_prepare_enable(sspa->audio_clk);

	return 0;
}

static int asoc_mmp_sspa_remove(struct platform_device *pdev)
{
	struct sspa_priv *sspa = platform_get_drvdata(pdev);

	clk_disable_unprepare(sspa->audio_clk);
	pm_runtime_disable(&pdev->dev);

	if (pdev->dev.of_node)
		return 0;

	clk_put(sspa->audio_clk);
	clk_put(sspa->sysclk);
	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id mmp_sspa_of_match[] = {
	{ .compatible = "marvell,mmp-sspa" },
	{},
};

MODULE_DEVICE_TABLE(of, mmp_sspa_of_match);
#endif

static struct platform_driver asoc_mmp_sspa_driver = {
	.driver = {
		.name = "mmp-sspa-dai",
		.of_match_table = of_match_ptr(mmp_sspa_of_match),
	},
	.probe = asoc_mmp_sspa_probe,
	.remove = asoc_mmp_sspa_remove,
};

module_platform_driver(asoc_mmp_sspa_driver);

MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
MODULE_DESCRIPTION("MMP SSPA SoC Interface");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mmp-sspa-dai");
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
fa375d42 ZG	2	/*
	3	* linux/sound/soc/pxa/mmp-sspa.c
	4	* Base on pxa2xx-ssp.c
	5	*
	6	* Copyright (C) 2011 Marvell International Ltd.
fa375d42 ZG	7	*/
	8	#include <linux/init.h>
	9	#include <linux/module.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/delay.h>
	12	#include <linux/clk.h>
	13	#include <linux/slab.h>
fa375d42	14	#include <linux/io.h>
d65a1458	15	#include <linux/dmaengine.h>
7d98cc64	16	#include <linux/pm_runtime.h>
d65a1458	17
fa375d42 ZG	18	#include <sound/core.h>
	19	#include <sound/pcm.h>
	20	#include <sound/initval.h>
	21	#include <sound/pcm_params.h>
	22	#include <sound/soc.h>
	23	#include <sound/pxa2xx-lib.h>
d65a1458	24	#include <sound/dmaengine_pcm.h>
fa375d42 ZG	25	#include "mmp-sspa.h"
	26
	27	/*
	28	* SSPA audio private data
	29	*/
	30	struct sspa_priv {
a97e384b LR	31	void __iomem *tx_base;
	32	void __iomem *rx_base;
	33
c9aeda1c LR	34	struct snd_dmaengine_dai_dma_data playback_dma_data;
c9aeda1c LR	35	struct snd_dmaengine_dai_dma_data capture_dma_data;
3c4e89df	36	struct clk *clk;
fa375d42 ZG	37	struct clk *audio_clk;
fa375d42 ZG	38	struct clk *sysclk;
a97e384b	39
fa375d42	40	int running_cnt;
7d98cc64 LR	41	u32 sp;
7d98cc64 LR	42	u32 ctrl;
fa375d42 ZG	43	};
fa375d42 ZG	44
3c4e89df	45	static void mmp_sspa_tx_enable(struct sspa_priv *sspa)
fa375d42	46	{
7d98cc64	47	unsigned int sspa_sp = sspa->sp;
fa375d42	48
7d98cc64	49	sspa_sp &= ~SSPA_SP_MSL;
fa375d42 ZG	50	sspa_sp \|= SSPA_SP_S_EN;
fa375d42 ZG	51	sspa_sp \|= SSPA_SP_WEN;
a97e384b	52	__raw_writel(sspa_sp, sspa->tx_base + SSPA_SP);
fa375d42 ZG	53	}
fa375d42 ZG	54
3c4e89df	55	static void mmp_sspa_tx_disable(struct sspa_priv *sspa)
fa375d42	56	{
7d98cc64	57	unsigned int sspa_sp = sspa->sp;
fa375d42	58
7d98cc64	59	sspa_sp &= ~SSPA_SP_MSL;
fa375d42 ZG	60	sspa_sp &= ~SSPA_SP_S_EN;
fa375d42 ZG	61	sspa_sp \|= SSPA_SP_WEN;
a97e384b	62	__raw_writel(sspa_sp, sspa->tx_base + SSPA_SP);
fa375d42 ZG	63	}
fa375d42 ZG	64
3c4e89df	65	static void mmp_sspa_rx_enable(struct sspa_priv *sspa)
fa375d42	66	{
7d98cc64	67	unsigned int sspa_sp = sspa->sp;
fa375d42	68
fa375d42 ZG	69	sspa_sp \|= SSPA_SP_S_EN;
fa375d42 ZG	70	sspa_sp \|= SSPA_SP_WEN;
a97e384b	71	__raw_writel(sspa_sp, sspa->rx_base + SSPA_SP);
fa375d42 ZG	72	}
fa375d42 ZG	73
3c4e89df	74	static void mmp_sspa_rx_disable(struct sspa_priv *sspa)
fa375d42	75	{
7d98cc64	76	unsigned int sspa_sp = sspa->sp;
fa375d42	77
fa375d42 ZG	78	sspa_sp &= ~SSPA_SP_S_EN;
fa375d42 ZG	79	sspa_sp \|= SSPA_SP_WEN;
a97e384b	80	__raw_writel(sspa_sp, sspa->rx_base + SSPA_SP);
fa375d42 ZG	81	}
	82
	83	static int mmp_sspa_startup(struct snd_pcm_substream *substream,
	84	struct snd_soc_dai *dai)
	85	{
3c4e89df	86	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
fa375d42	87
8ecdcac8 LR	88	clk_prepare_enable(sspa->sysclk);
8ecdcac8 LR	89	clk_prepare_enable(sspa->clk);
fa375d42 ZG	90
	91	return 0;
	92	}
	93
	94	static void mmp_sspa_shutdown(struct snd_pcm_substream *substream,
	95	struct snd_soc_dai *dai)
	96	{
3c4e89df	97	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
fa375d42	98
8ecdcac8 LR	99	clk_disable_unprepare(sspa->clk);
8ecdcac8 LR	100	clk_disable_unprepare(sspa->sysclk);
fa375d42 ZG	101	}
	102
	103	/*
	104	* Set the SSP ports SYSCLK.
	105	*/
	106	static int mmp_sspa_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
	107	int clk_id, unsigned int freq, int dir)
	108	{
3c4e89df	109	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(cpu_dai);
a97e384b	110	struct device *dev = cpu_dai->component->dev;
fa375d42 ZG	111	int ret = 0;
fa375d42 ZG	112
a97e384b LR	113	if (dev->of_node)
	114	return -ENOTSUPP;
	115
fa375d42 ZG	116	switch (clk_id) {
fa375d42 ZG	117	case MMP_SSPA_CLK_AUDIO:
3c4e89df	118	ret = clk_set_rate(sspa->audio_clk, freq);
fa375d42 ZG	119	if (ret)
	120	return ret;
	121	break;
	122	case MMP_SSPA_CLK_PLL:
	123	case MMP_SSPA_CLK_VCXO:
	124	/* not support yet */
	125	return -EINVAL;
	126	default:
	127	return -EINVAL;
	128	}
	129
	130	return 0;
	131	}
	132
	133	static int mmp_sspa_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
	134	int source, unsigned int freq_in,
	135	unsigned int freq_out)
	136	{
3c4e89df	137	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(cpu_dai);
a97e384b	138	struct device *dev = cpu_dai->component->dev;
fa375d42 ZG	139	int ret = 0;
fa375d42 ZG	140
a97e384b LR	141	if (dev->of_node)
	142	return -ENOTSUPP;
	143
fa375d42 ZG	144	switch (pll_id) {
fa375d42 ZG	145	case MMP_SYSCLK:
3c4e89df	146	ret = clk_set_rate(sspa->sysclk, freq_out);
fa375d42 ZG	147	if (ret)
	148	return ret;
	149	break;
	150	case MMP_SSPA_CLK:
3c4e89df	151	ret = clk_set_rate(sspa->clk, freq_out);
fa375d42 ZG	152	if (ret)
	153	return ret;
	154	break;
	155	default:
	156	return -ENODEV;
	157	}
	158
	159	return 0;
	160	}
	161
	162	/*
7d98cc64	163	* Set up the sspa dai format.
fa375d42 ZG	164	*/
	165	static int mmp_sspa_set_dai_fmt(struct snd_soc_dai *cpu_dai,
	166	unsigned int fmt)
	167	{
3c4e89df	168	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(cpu_dai);
fa375d42 ZG	169
fa375d42 ZG	170	/* reset port settings */
7d98cc64 LR	171	sspa->sp = SSPA_SP_WEN \| SSPA_SP_S_RST \| SSPA_SP_FFLUSH;
7d98cc64 LR	172	sspa->ctrl = 0;
fa375d42	173
84c5b47c CK	174	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
84c5b47c CK	175	case SND_SOC_DAIFMT_BP_FP:
7d98cc64	176	sspa->sp \|= SSPA_SP_MSL;
fa375d42	177	break;
84c5b47c	178	case SND_SOC_DAIFMT_BC_FC:
fa375d42 ZG	179	break;
	180	default:
	181	return -EINVAL;
	182	}
	183
	184	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	185	case SND_SOC_DAIFMT_NB_NF:
7d98cc64	186	sspa->sp \|= SSPA_SP_FSP;
fa375d42 ZG	187	break;
	188	default:
	189	return -EINVAL;
	190	}
	191
	192	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	193	case SND_SOC_DAIFMT_I2S:
7d98cc64	194	sspa->ctrl \|= SSPA_CTL_XDATDLY(1);
fa375d42 ZG	195	break;
	196	default:
	197	return -EINVAL;
	198	}
	199
fa375d42 ZG	200	/* Since we are configuring the timings for the format by hand
	201	* we have to defer some things until hw_params() where we
	202	* know parameters like the sample size.
	203	*/
fa375d42 ZG	204	return 0;
	205	}
	206
	207	/*
	208	* Set the SSPA audio DMA parameters and sample size.
	209	* Can be called multiple times by oss emulation.
	210	*/
	211	static int mmp_sspa_hw_params(struct snd_pcm_substream *substream,
	212	struct snd_pcm_hw_params *params,
	213	struct snd_soc_dai *dai)
	214	{
3c4e89df	215	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
a97e384b	216	struct device *dev = dai->component->dev;
7d98cc64	217	u32 sspa_ctrl = sspa->ctrl;
39ec7e9b LR	218	int bits;
39ec7e9b LR	219	int bitval;
fa375d42 ZG	220
	221	switch (params_format(params)) {
	222	case SNDRV_PCM_FORMAT_S8:
39ec7e9b LR	223	bits = 8;
39ec7e9b LR	224	bitval = SSPA_CTL_8_BITS;
fa375d42 ZG	225	break;
fa375d42 ZG	226	case SNDRV_PCM_FORMAT_S16_LE:
39ec7e9b LR	227	bits = 16;
39ec7e9b LR	228	bitval = SSPA_CTL_16_BITS;
fa375d42	229	break;
fa375d42	230	case SNDRV_PCM_FORMAT_S24_3LE:
39ec7e9b LR	231	bits = 24;
39ec7e9b LR	232	bitval = SSPA_CTL_24_BITS;
fa375d42 ZG	233	break;
fa375d42 ZG	234	case SNDRV_PCM_FORMAT_S32_LE:
39ec7e9b LR	235	bits = 32;
39ec7e9b LR	236	bitval = SSPA_CTL_32_BITS;
fa375d42 ZG	237	break;
	238	default:
	239	return -EINVAL;
	240	}
	241
b88b31f4	242	sspa_ctrl &= ~SSPA_CTL_XPH;
a97e384b	243	if (dev->of_node \|\| params_channels(params) == 2)
39ec7e9b LR	244	sspa_ctrl \|= SSPA_CTL_XPH;
	245
	246	sspa_ctrl &= ~SSPA_CTL_XWDLEN1_MASK;
	247	sspa_ctrl \|= SSPA_CTL_XWDLEN1(bitval);
	248
82d1aeb8 KR	249	sspa_ctrl &= ~SSPA_CTL_XWDLEN2_MASK;
	250	sspa_ctrl \|= SSPA_CTL_XWDLEN2(bitval);
	251
39ec7e9b LR	252	sspa_ctrl &= ~SSPA_CTL_XSSZ1_MASK;
	253	sspa_ctrl \|= SSPA_CTL_XSSZ1(bitval);
	254
	255	sspa_ctrl &= ~SSPA_CTL_XSSZ2_MASK;
	256	sspa_ctrl \|= SSPA_CTL_XSSZ2(bitval);
	257
	258	sspa->sp &= ~SSPA_SP_FWID_MASK;
	259	sspa->sp \|= SSPA_SP_FWID(bits - 1);
	260
	261	sspa->sp &= ~SSPA_TXSP_FPER_MASK;
	262	sspa->sp \|= SSPA_TXSP_FPER(bits * 2 - 1);
	263
a97e384b LR	264	if (dev->of_node) {
	265	clk_set_rate(sspa->clk, params_rate(params) *
	266	params_channels(params) * bits);
	267	}
	268
fa375d42	269	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
a97e384b LR	270	__raw_writel(sspa_ctrl, sspa->tx_base + SSPA_CTL);
a97e384b LR	271	__raw_writel(0x1, sspa->tx_base + SSPA_FIFO_UL);
fa375d42	272	} else {
a97e384b LR	273	__raw_writel(sspa_ctrl, sspa->rx_base + SSPA_CTL);
a97e384b LR	274	__raw_writel(0x0, sspa->rx_base + SSPA_FIFO_UL);
fa375d42 ZG	275	}
fa375d42 ZG	276
fa375d42 ZG	277	return 0;
	278	}
	279
	280	static int mmp_sspa_trigger(struct snd_pcm_substream *substream, int cmd,
	281	struct snd_soc_dai *dai)
	282	{
3c4e89df	283	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
fa375d42 ZG	284	int ret = 0;
	285
	286	switch (cmd) {
	287	case SNDRV_PCM_TRIGGER_START:
	288	case SNDRV_PCM_TRIGGER_RESUME:
	289	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	290	/*
	291	* whatever playback or capture, must enable rx.
	292	* this is a hw issue, so need check if rx has been
	293	* enabled or not; if has been enabled by another
	294	* stream, do not enable again.
	295	*/
3c4e89df	296	if (!sspa->running_cnt)
fa375d42 ZG	297	mmp_sspa_rx_enable(sspa);
	298
	299	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	300	mmp_sspa_tx_enable(sspa);
	301
3c4e89df	302	sspa->running_cnt++;
fa375d42 ZG	303	break;
	304
	305	case SNDRV_PCM_TRIGGER_STOP:
	306	case SNDRV_PCM_TRIGGER_SUSPEND:
	307	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
3c4e89df	308	sspa->running_cnt--;
fa375d42 ZG	309
	310	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	311	mmp_sspa_tx_disable(sspa);
	312
	313	/* have no capture stream, disable rx port */
3c4e89df	314	if (!sspa->running_cnt)
fa375d42 ZG	315	mmp_sspa_rx_disable(sspa);
	316	break;
	317
	318	default:
	319	ret = -EINVAL;
	320	}
	321
	322	return ret;
	323	}
	324
	325	static int mmp_sspa_probe(struct snd_soc_dai *dai)
	326	{
3c4e89df	327	struct sspa_priv *sspa = dev_get_drvdata(dai->dev);
fa375d42	328
c9aeda1c	329	snd_soc_dai_init_dma_data(dai,
3c4e89df LR	330	&sspa->playback_dma_data,
3c4e89df LR	331	&sspa->capture_dma_data);
c9aeda1c	332
fa375d42	333	return 0;
fa375d42 ZG	334	}
	335
	336	#define MMP_SSPA_RATES SNDRV_PCM_RATE_8000_192000
	337	#define MMP_SSPA_FORMATS (SNDRV_PCM_FMTBIT_S8 \| \
	338	SNDRV_PCM_FMTBIT_S16_LE \| \
00a1aca2	339	SNDRV_PCM_FMTBIT_S24_3LE \| \
fa375d42 ZG	340	SNDRV_PCM_FMTBIT_S32_LE)
fa375d42 ZG	341
cb753443	342	static const struct snd_soc_dai_ops mmp_sspa_dai_ops = {
fa375d42 ZG	343	.startup = mmp_sspa_startup,
	344	.shutdown = mmp_sspa_shutdown,
	345	.trigger = mmp_sspa_trigger,
	346	.hw_params = mmp_sspa_hw_params,
	347	.set_sysclk = mmp_sspa_set_dai_sysclk,
	348	.set_pll = mmp_sspa_set_dai_pll,
8e2cc2b2	349	.set_fmt = mmp_sspa_set_dai_fmt,
fa375d42 ZG	350	};
fa375d42 ZG	351
5d9ff402	352	static struct snd_soc_dai_driver mmp_sspa_dai = {
fa375d42 ZG	353	.probe = mmp_sspa_probe,
	354	.playback = {
	355	.channels_min = 1,
	356	.channels_max = 128,
	357	.rates = MMP_SSPA_RATES,
	358	.formats = MMP_SSPA_FORMATS,
	359	},
	360	.capture = {
	361	.channels_min = 1,
	362	.channels_max = 2,
	363	.rates = MMP_SSPA_RATES,
	364	.formats = MMP_SSPA_FORMATS,
	365	},
	366	.ops = &mmp_sspa_dai_ops,
	367	};
	368
724da053 LR	369	#define MMP_PCM_INFO (SNDRV_PCM_INFO_MMAP \| \
	370	SNDRV_PCM_INFO_MMAP_VALID \| \
	371	SNDRV_PCM_INFO_INTERLEAVED \| \
	372	SNDRV_PCM_INFO_PAUSE \| \
	373	SNDRV_PCM_INFO_RESUME \| \
	374	SNDRV_PCM_INFO_NO_PERIOD_WAKEUP)
	375
	376	static const struct snd_pcm_hardware mmp_pcm_hardware[] = {
	377	{
	378	.info = MMP_PCM_INFO,
	379	.period_bytes_min = 1024,
	380	.period_bytes_max = 2048,
	381	.periods_min = 2,
	382	.periods_max = 32,
	383	.buffer_bytes_max = 4096,
	384	.fifo_size = 32,
	385	},
	386	{
	387	.info = MMP_PCM_INFO,
	388	.period_bytes_min = 1024,
	389	.period_bytes_max = 2048,
	390	.periods_min = 2,
	391	.periods_max = 32,
	392	.buffer_bytes_max = 4096,
	393	.fifo_size = 32,
	394	},
	395	};
	396
	397	static const struct snd_dmaengine_pcm_config mmp_pcm_config = {
	398	.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
	399	.pcm_hardware = mmp_pcm_hardware,
	400	.prealloc_buffer_size = 4096,
	401	};
	402
	403	static int mmp_pcm_mmap(struct snd_soc_component *component,
	404	struct snd_pcm_substream *substream,
	405	struct vm_area_struct *vma)
	406	{
1c71222e	407	vm_flags_set(vma, VM_DONTEXPAND \| VM_DONTDUMP);
724da053 LR	408	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
	409	return remap_pfn_range(vma, vma->vm_start,
	410	substream->dma_buffer.addr >> PAGE_SHIFT,
	411	vma->vm_end - vma->vm_start, vma->vm_page_prot);
	412	}
	413
7d98cc64 LR	414	static int mmp_sspa_open(struct snd_soc_component *component,
	415	struct snd_pcm_substream *substream)
	416	{
	417	struct sspa_priv *sspa = snd_soc_component_get_drvdata(component);
	418
	419	pm_runtime_get_sync(component->dev);
	420
	421	/* we can only change the settings if the port is not in use */
a97e384b LR	422	if ((__raw_readl(sspa->tx_base + SSPA_SP) & SSPA_SP_S_EN) \|\|
a97e384b LR	423	(__raw_readl(sspa->rx_base + SSPA_SP) & SSPA_SP_S_EN)) {
7d98cc64 LR	424	dev_err(component->dev,
	425	"can't change hardware dai format: stream is in use\n");
	426	return -EBUSY;
	427	}
	428
a97e384b LR	429	__raw_writel(sspa->sp, sspa->tx_base + SSPA_SP);
a97e384b LR	430	__raw_writel(sspa->sp, sspa->rx_base + SSPA_SP);
7d98cc64 LR	431
7d98cc64 LR	432	sspa->sp &= ~(SSPA_SP_S_RST \| SSPA_SP_FFLUSH);
a97e384b LR	433	__raw_writel(sspa->sp, sspa->tx_base + SSPA_SP);
a97e384b LR	434	__raw_writel(sspa->sp, sspa->rx_base + SSPA_SP);
7d98cc64 LR	435
	436	/*
	437	* FIXME: hw issue, for the tx serial port,
	438	* can not config the master/slave mode;
	439	* so must clean this bit.
	440	* The master/slave mode has been set in the
	441	* rx port.
	442	*/
a97e384b	443	__raw_writel(sspa->sp & ~SSPA_SP_MSL, sspa->tx_base + SSPA_SP);
7d98cc64	444
a97e384b LR	445	__raw_writel(sspa->ctrl, sspa->tx_base + SSPA_CTL);
a97e384b LR	446	__raw_writel(sspa->ctrl, sspa->rx_base + SSPA_CTL);
7d98cc64 LR	447
	448	return 0;
	449	}
	450
	451	static int mmp_sspa_close(struct snd_soc_component *component,
	452	struct snd_pcm_substream *substream)
	453	{
	454	pm_runtime_put_sync(component->dev);
	455	return 0;
	456	}
	457
425f3708	458	static const struct snd_soc_component_driver mmp_sspa_component = {
05603f15 CK	459	.name = "mmp-sspa",
	460	.mmap = mmp_pcm_mmap,
	461	.open = mmp_sspa_open,
	462	.close = mmp_sspa_close,
	463	.legacy_dai_naming = 1,
425f3708 KM	464	};
425f3708 KM	465
570f6fe1	466	static int asoc_mmp_sspa_probe(struct platform_device *pdev)
fa375d42	467	{
3c4e89df	468	struct sspa_priv *sspa;
6ea460d5	469	int ret;
fa375d42	470
3c4e89df	471	sspa = devm_kzalloc(&pdev->dev,
fa375d42	472	sizeof(struct sspa_priv), GFP_KERNEL);
3c4e89df	473	if (!sspa)
fa375d42 ZG	474	return -ENOMEM;
fa375d42 ZG	475
a97e384b LR	476	if (pdev->dev.of_node) {
	477	sspa->rx_base = devm_platform_ioremap_resource(pdev, 0);
	478	if (IS_ERR(sspa->rx_base))
	479	return PTR_ERR(sspa->rx_base);
fa375d42	480
a97e384b LR	481	sspa->tx_base = devm_platform_ioremap_resource(pdev, 1);
	482	if (IS_ERR(sspa->tx_base))
	483	return PTR_ERR(sspa->tx_base);
fa375d42	484
a97e384b LR	485	sspa->clk = devm_clk_get(&pdev->dev, "bitclk");
	486	if (IS_ERR(sspa->clk))
	487	return PTR_ERR(sspa->clk);
fa375d42	488
a97e384b LR	489	sspa->audio_clk = devm_clk_get(&pdev->dev, "audio");
	490	if (IS_ERR(sspa->audio_clk))
	491	return PTR_ERR(sspa->audio_clk);
	492	} else {
	493	struct resource *res;
	494
	495	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
	496	if (res == NULL)
	497	return -ENODEV;
	498
	499	sspa->rx_base = devm_ioremap(&pdev->dev, res->start, 0x30);
18545763 WY	500	if (!sspa->rx_base)
18545763 WY	501	return -ENOMEM;
a97e384b LR	502
	503	sspa->tx_base = devm_ioremap(&pdev->dev,
	504	res->start + 0x80, 0x30);
18545763 WY	505	if (!sspa->tx_base)
18545763 WY	506	return -ENOMEM;
a97e384b LR	507
	508	sspa->clk = devm_clk_get(&pdev->dev, NULL);
	509	if (IS_ERR(sspa->clk))
	510	return PTR_ERR(sspa->clk);
	511
	512	sspa->audio_clk = clk_get(NULL, "mmp-audio");
	513	if (IS_ERR(sspa->audio_clk))
	514	return PTR_ERR(sspa->audio_clk);
	515
	516	sspa->sysclk = clk_get(NULL, "mmp-sysclk");
	517	if (IS_ERR(sspa->sysclk)) {
	518	clk_put(sspa->audio_clk);
	519	return PTR_ERR(sspa->sysclk);
	520	}
fa375d42	521	}
3c4e89df	522	platform_set_drvdata(pdev, sspa);
fa375d42	523
3c4e89df LR	524	sspa->playback_dma_data.maxburst = 4;
3c4e89df LR	525	sspa->capture_dma_data.maxburst = 4;
c9aeda1c	526	/* You know, these addresses are actually ignored. */
a97e384b LR	527	sspa->capture_dma_data.addr = SSPA_D;
a97e384b LR	528	sspa->playback_dma_data.addr = 0x80 + SSPA_D;
c9aeda1c	529
724da053	530	if (pdev->dev.of_node) {
724da053 LR	531	ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
	532	&mmp_pcm_config, 0);
	533	if (ret)
	534	return ret;
	535	}
	536
6ea460d5 LR	537	ret = devm_snd_soc_register_component(&pdev->dev, &mmp_sspa_component,
	538	&mmp_sspa_dai, 1);
	539	if (ret)
	540	return ret;
	541
	542	pm_runtime_enable(&pdev->dev);
	543	clk_prepare_enable(sspa->audio_clk);
	544
	545	return 0;
fa375d42 ZG	546	}
fa375d42 ZG	547
570f6fe1	548	static int asoc_mmp_sspa_remove(struct platform_device *pdev)
fa375d42	549	{
3c4e89df	550	struct sspa_priv *sspa = platform_get_drvdata(pdev);
fa375d42	551
8ecdcac8	552	clk_disable_unprepare(sspa->audio_clk);
7d98cc64	553	pm_runtime_disable(&pdev->dev);
a97e384b LR	554
	555	if (pdev->dev.of_node)
	556	return 0;
	557
3c4e89df LR	558	clk_put(sspa->audio_clk);
3c4e89df LR	559	clk_put(sspa->sysclk);
fa375d42 ZG	560	return 0;
	561	}
	562
a97e384b LR	563	#ifdef CONFIG_OF
	564	static const struct of_device_id mmp_sspa_of_match[] = {
	565	{ .compatible = "marvell,mmp-sspa" },
	566	{},
	567	};
	568
	569	MODULE_DEVICE_TABLE(of, mmp_sspa_of_match);
	570	#endif
	571
fa375d42 ZG	572	static struct platform_driver asoc_mmp_sspa_driver = {
	573	.driver = {
	574	.name = "mmp-sspa-dai",
a97e384b	575	.of_match_table = of_match_ptr(mmp_sspa_of_match),
fa375d42 ZG	576	},
fa375d42 ZG	577	.probe = asoc_mmp_sspa_probe,
570f6fe1	578	.remove = asoc_mmp_sspa_remove,
fa375d42 ZG	579	};
	580
	581	module_platform_driver(asoc_mmp_sspa_driver);
	582
	583	MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
	584	MODULE_DESCRIPTION("MMP SSPA SoC Interface");
	585	MODULE_LICENSE("GPL");
e5b7d71a	586	MODULE_ALIAS("platform:mmp-sspa-dai");