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2e74796a JN |
1 | /* |
2 | * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port | |
3 | * | |
4 | * Copyright (C) 2008 Nokia Corporation | |
5 | * | |
b08f7a62 JN |
6 | * Contact: Jarkko Nikula <jhnikula@gmail.com> |
7 | * Peter Ujfalusi <peter.ujfalusi@nokia.com> | |
2e74796a JN |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <linux/init.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/device.h> | |
28 | #include <sound/core.h> | |
29 | #include <sound/pcm.h> | |
30 | #include <sound/pcm_params.h> | |
31 | #include <sound/initval.h> | |
32 | #include <sound/soc.h> | |
33 | ||
ce491cf8 TL |
34 | #include <plat/control.h> |
35 | #include <plat/dma.h> | |
36 | #include <plat/mcbsp.h> | |
2e74796a JN |
37 | #include "omap-mcbsp.h" |
38 | #include "omap-pcm.h" | |
39 | ||
0b604856 | 40 | #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000) |
2e74796a | 41 | |
83905c13 IK |
42 | #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \ |
43 | xhandler_get, xhandler_put) \ | |
44 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
45 | .info = omap_mcbsp_st_info_volsw, \ | |
46 | .get = xhandler_get, .put = xhandler_put, \ | |
47 | .private_value = (unsigned long) &(struct soc_mixer_control) \ | |
48 | {.min = xmin, .max = xmax} } | |
49 | ||
2e74796a JN |
50 | struct omap_mcbsp_data { |
51 | unsigned int bus_id; | |
52 | struct omap_mcbsp_reg_cfg regs; | |
ba9d0fd0 | 53 | unsigned int fmt; |
2e74796a JN |
54 | /* |
55 | * Flags indicating is the bus already activated and configured by | |
56 | * another substream | |
57 | */ | |
58 | int active; | |
59 | int configured; | |
5f63ef99 GG |
60 | unsigned int in_freq; |
61 | int clk_div; | |
2e74796a JN |
62 | }; |
63 | ||
64 | #define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id) | |
65 | ||
66 | static struct omap_mcbsp_data mcbsp_data[NUM_LINKS]; | |
67 | ||
68 | /* | |
69 | * Stream DMA parameters. DMA request line and port address are set runtime | |
70 | * since they are different between OMAP1 and later OMAPs | |
71 | */ | |
2e89713a | 72 | static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2]; |
2e74796a JN |
73 | |
74 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) | |
75 | static const int omap1_dma_reqs[][2] = { | |
76 | { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX }, | |
77 | { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX }, | |
78 | { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX }, | |
79 | }; | |
80 | static const unsigned long omap1_mcbsp_port[][2] = { | |
81 | { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1, | |
82 | OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 }, | |
83 | { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1, | |
84 | OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 }, | |
85 | { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1, | |
86 | OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 }, | |
87 | }; | |
88 | #else | |
89 | static const int omap1_dma_reqs[][2] = {}; | |
90 | static const unsigned long omap1_mcbsp_port[][2] = {}; | |
91 | #endif | |
406e2c48 | 92 | |
a8eb7ca0 | 93 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
406e2c48 | 94 | static const int omap24xx_dma_reqs[][2] = { |
2e74796a JN |
95 | { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX }, |
96 | { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX }, | |
a8eb7ca0 | 97 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) |
406e2c48 JN |
98 | { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX }, |
99 | { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX }, | |
100 | { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX }, | |
101 | #endif | |
2e74796a | 102 | }; |
406e2c48 JN |
103 | #else |
104 | static const int omap24xx_dma_reqs[][2] = {}; | |
105 | #endif | |
106 | ||
107 | #if defined(CONFIG_ARCH_OMAP2420) | |
2e74796a JN |
108 | static const unsigned long omap2420_mcbsp_port[][2] = { |
109 | { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1, | |
110 | OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 }, | |
111 | { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1, | |
112 | OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 }, | |
113 | }; | |
114 | #else | |
2e74796a JN |
115 | static const unsigned long omap2420_mcbsp_port[][2] = {}; |
116 | #endif | |
117 | ||
406e2c48 JN |
118 | #if defined(CONFIG_ARCH_OMAP2430) |
119 | static const unsigned long omap2430_mcbsp_port[][2] = { | |
120 | { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR, | |
121 | OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR }, | |
122 | { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR, | |
123 | OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR }, | |
124 | { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR, | |
125 | OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR }, | |
126 | { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR, | |
127 | OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR }, | |
128 | { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR, | |
129 | OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR }, | |
130 | }; | |
131 | #else | |
132 | static const unsigned long omap2430_mcbsp_port[][2] = {}; | |
133 | #endif | |
134 | ||
a8eb7ca0 | 135 | #if defined(CONFIG_ARCH_OMAP3) |
406e2c48 JN |
136 | static const unsigned long omap34xx_mcbsp_port[][2] = { |
137 | { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR, | |
138 | OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR }, | |
139 | { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR, | |
140 | OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR }, | |
141 | { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR, | |
142 | OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR }, | |
143 | { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR, | |
144 | OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR }, | |
145 | { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR, | |
146 | OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR }, | |
147 | }; | |
148 | #else | |
149 | static const unsigned long omap34xx_mcbsp_port[][2] = {}; | |
150 | #endif | |
151 | ||
caebc0cb EV |
152 | static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream) |
153 | { | |
154 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
155 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; | |
156 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); | |
a0a499c5 EV |
157 | int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id); |
158 | int samples; | |
159 | ||
160 | /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */ | |
161 | if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) | |
162 | samples = snd_pcm_lib_period_bytes(substream) >> 1; | |
163 | else | |
164 | samples = 1; | |
caebc0cb EV |
165 | |
166 | /* Configure McBSP internal buffer usage */ | |
167 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
168 | omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, samples - 1); | |
169 | else | |
170 | omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, samples - 1); | |
171 | } | |
172 | ||
dee89c4d MB |
173 | static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream, |
174 | struct snd_soc_dai *dai) | |
2e74796a JN |
175 | { |
176 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
8687eb8b | 177 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
2e74796a | 178 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); |
caebc0cb | 179 | int bus_id = mcbsp_data->bus_id; |
2e74796a JN |
180 | int err = 0; |
181 | ||
caebc0cb EV |
182 | if (!cpu_dai->active) |
183 | err = omap_mcbsp_request(bus_id); | |
184 | ||
185 | if (cpu_is_omap343x()) { | |
a0a499c5 | 186 | int dma_op_mode = omap_mcbsp_get_dma_op_mode(bus_id); |
caebc0cb EV |
187 | int max_period; |
188 | ||
6984992b JN |
189 | /* |
190 | * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer. | |
191 | * Set constraint for minimum buffer size to the same than FIFO | |
192 | * size in order to avoid underruns in playback startup because | |
193 | * HW is keeping the DMA request active until FIFO is filled. | |
194 | */ | |
caebc0cb EV |
195 | if (bus_id == 1) |
196 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
197 | SNDRV_PCM_HW_PARAM_BUFFER_BYTES, | |
198 | 4096, UINT_MAX); | |
199 | ||
200 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
201 | max_period = omap_mcbsp_get_max_tx_threshold(bus_id); | |
202 | else | |
203 | max_period = omap_mcbsp_get_max_rx_threshold(bus_id); | |
204 | ||
205 | max_period++; | |
206 | max_period <<= 1; | |
207 | ||
a0a499c5 EV |
208 | if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) |
209 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
caebc0cb EV |
210 | SNDRV_PCM_HW_PARAM_PERIOD_BYTES, |
211 | 32, max_period); | |
6984992b JN |
212 | } |
213 | ||
2e74796a JN |
214 | return err; |
215 | } | |
216 | ||
dee89c4d MB |
217 | static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream, |
218 | struct snd_soc_dai *dai) | |
2e74796a JN |
219 | { |
220 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
8687eb8b | 221 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
2e74796a JN |
222 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); |
223 | ||
224 | if (!cpu_dai->active) { | |
225 | omap_mcbsp_free(mcbsp_data->bus_id); | |
226 | mcbsp_data->configured = 0; | |
227 | } | |
228 | } | |
229 | ||
dee89c4d MB |
230 | static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd, |
231 | struct snd_soc_dai *dai) | |
2e74796a JN |
232 | { |
233 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
8687eb8b | 234 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
2e74796a | 235 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); |
c12abc01 | 236 | int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
2e74796a JN |
237 | |
238 | switch (cmd) { | |
239 | case SNDRV_PCM_TRIGGER_START: | |
240 | case SNDRV_PCM_TRIGGER_RESUME: | |
241 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
c12abc01 JN |
242 | mcbsp_data->active++; |
243 | omap_mcbsp_start(mcbsp_data->bus_id, play, !play); | |
2e74796a JN |
244 | break; |
245 | ||
246 | case SNDRV_PCM_TRIGGER_STOP: | |
247 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
248 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
c12abc01 JN |
249 | omap_mcbsp_stop(mcbsp_data->bus_id, play, !play); |
250 | mcbsp_data->active--; | |
2e74796a JN |
251 | break; |
252 | default: | |
253 | err = -EINVAL; | |
254 | } | |
255 | ||
256 | return err; | |
257 | } | |
258 | ||
259 | static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
260 | struct snd_pcm_hw_params *params, |
261 | struct snd_soc_dai *dai) | |
2e74796a JN |
262 | { |
263 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
8687eb8b | 264 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
2e74796a JN |
265 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); |
266 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; | |
267 | int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id; | |
caebc0cb | 268 | int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT; |
2e74796a | 269 | unsigned long port; |
5f63ef99 | 270 | unsigned int format, div, framesize, master; |
2e74796a JN |
271 | |
272 | if (cpu_class_is_omap1()) { | |
273 | dma = omap1_dma_reqs[bus_id][substream->stream]; | |
274 | port = omap1_mcbsp_port[bus_id][substream->stream]; | |
275 | } else if (cpu_is_omap2420()) { | |
406e2c48 | 276 | dma = omap24xx_dma_reqs[bus_id][substream->stream]; |
2e74796a | 277 | port = omap2420_mcbsp_port[bus_id][substream->stream]; |
406e2c48 JN |
278 | } else if (cpu_is_omap2430()) { |
279 | dma = omap24xx_dma_reqs[bus_id][substream->stream]; | |
280 | port = omap2430_mcbsp_port[bus_id][substream->stream]; | |
281 | } else if (cpu_is_omap343x()) { | |
282 | dma = omap24xx_dma_reqs[bus_id][substream->stream]; | |
283 | port = omap34xx_mcbsp_port[bus_id][substream->stream]; | |
caebc0cb EV |
284 | omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold = |
285 | omap_mcbsp_set_threshold; | |
a0a499c5 EV |
286 | /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */ |
287 | if (omap_mcbsp_get_dma_op_mode(bus_id) == | |
288 | MCBSP_DMA_MODE_THRESHOLD) | |
289 | sync_mode = OMAP_DMA_SYNC_FRAME; | |
2e74796a | 290 | } else { |
2e74796a JN |
291 | return -ENODEV; |
292 | } | |
2e89713a JN |
293 | omap_mcbsp_dai_dma_params[id][substream->stream].name = |
294 | substream->stream ? "Audio Capture" : "Audio Playback"; | |
2e74796a JN |
295 | omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma; |
296 | omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port; | |
caebc0cb | 297 | omap_mcbsp_dai_dma_params[id][substream->stream].sync_mode = sync_mode; |
e17dd32f MLC |
298 | omap_mcbsp_dai_dma_params[id][substream->stream].data_type = |
299 | OMAP_DMA_DATA_TYPE_S16; | |
5f712b2b DM |
300 | |
301 | snd_soc_dai_set_dma_data(cpu_dai, substream, | |
302 | &omap_mcbsp_dai_dma_params[id][substream->stream]); | |
2e74796a JN |
303 | |
304 | if (mcbsp_data->configured) { | |
305 | /* McBSP already configured by another stream */ | |
306 | return 0; | |
307 | } | |
308 | ||
c29b206f PU |
309 | format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK; |
310 | wpf = channels = params_channels(params); | |
5f63ef99 GG |
311 | if (channels == 2 && format == SND_SOC_DAIFMT_I2S) { |
312 | /* Use dual-phase frames */ | |
313 | regs->rcr2 |= RPHASE; | |
314 | regs->xcr2 |= XPHASE; | |
315 | /* Set 1 word per (McBSP) frame for phase1 and phase2 */ | |
316 | wpf--; | |
317 | regs->rcr2 |= RFRLEN2(wpf - 1); | |
318 | regs->xcr2 |= XFRLEN2(wpf - 1); | |
2e74796a JN |
319 | } |
320 | ||
5f63ef99 GG |
321 | regs->rcr1 |= RFRLEN1(wpf - 1); |
322 | regs->xcr1 |= XFRLEN1(wpf - 1); | |
323 | ||
2e74796a JN |
324 | switch (params_format(params)) { |
325 | case SNDRV_PCM_FORMAT_S16_LE: | |
326 | /* Set word lengths */ | |
ba9d0fd0 | 327 | wlen = 16; |
2e74796a JN |
328 | regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16); |
329 | regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16); | |
330 | regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16); | |
331 | regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16); | |
2e74796a JN |
332 | break; |
333 | default: | |
334 | /* Unsupported PCM format */ | |
335 | return -EINVAL; | |
336 | } | |
337 | ||
5f63ef99 GG |
338 | /* In McBSP master modes, FRAME (i.e. sample rate) is generated |
339 | * by _counting_ BCLKs. Calculate frame size in BCLKs */ | |
340 | master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK; | |
341 | if (master == SND_SOC_DAIFMT_CBS_CFS) { | |
342 | div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1; | |
343 | framesize = (mcbsp_data->in_freq / div) / params_rate(params); | |
344 | ||
345 | if (framesize < wlen * channels) { | |
346 | printk(KERN_ERR "%s: not enough bandwidth for desired rate and " | |
347 | "channels\n", __func__); | |
348 | return -EINVAL; | |
349 | } | |
350 | } else | |
351 | framesize = wlen * channels; | |
352 | ||
ba9d0fd0 | 353 | /* Set FS period and length in terms of bit clock periods */ |
c29b206f | 354 | switch (format) { |
ba9d0fd0 | 355 | case SND_SOC_DAIFMT_I2S: |
5f63ef99 GG |
356 | regs->srgr2 |= FPER(framesize - 1); |
357 | regs->srgr1 |= FWID((framesize >> 1) - 1); | |
ba9d0fd0 | 358 | break; |
3ba191ce | 359 | case SND_SOC_DAIFMT_DSP_A: |
bd25867a | 360 | case SND_SOC_DAIFMT_DSP_B: |
5f63ef99 | 361 | regs->srgr2 |= FPER(framesize - 1); |
36ce8582 | 362 | regs->srgr1 |= FWID(0); |
ba9d0fd0 JN |
363 | break; |
364 | } | |
365 | ||
2e74796a JN |
366 | omap_mcbsp_config(bus_id, &mcbsp_data->regs); |
367 | mcbsp_data->configured = 1; | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | /* | |
373 | * This must be called before _set_clkdiv and _set_sysclk since McBSP register | |
374 | * cache is initialized here | |
375 | */ | |
8687eb8b | 376 | static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
2e74796a JN |
377 | unsigned int fmt) |
378 | { | |
379 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); | |
380 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; | |
36ce8582 | 381 | unsigned int temp_fmt = fmt; |
2e74796a JN |
382 | |
383 | if (mcbsp_data->configured) | |
384 | return 0; | |
385 | ||
ba9d0fd0 | 386 | mcbsp_data->fmt = fmt; |
2e74796a JN |
387 | memset(regs, 0, sizeof(*regs)); |
388 | /* Generic McBSP register settings */ | |
389 | regs->spcr2 |= XINTM(3) | FREE; | |
390 | regs->spcr1 |= RINTM(3); | |
c721bbda EN |
391 | /* RFIG and XFIG are not defined in 34xx */ |
392 | if (!cpu_is_omap34xx()) { | |
393 | regs->rcr2 |= RFIG; | |
394 | regs->xcr2 |= XFIG; | |
395 | } | |
ef390c0b | 396 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { |
32080af7 JN |
397 | regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE; |
398 | regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE; | |
ef390c0b | 399 | } |
2e74796a JN |
400 | |
401 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
402 | case SND_SOC_DAIFMT_I2S: | |
403 | /* 1-bit data delay */ | |
404 | regs->rcr2 |= RDATDLY(1); | |
405 | regs->xcr2 |= XDATDLY(1); | |
406 | break; | |
3ba191ce PU |
407 | case SND_SOC_DAIFMT_DSP_A: |
408 | /* 1-bit data delay */ | |
409 | regs->rcr2 |= RDATDLY(1); | |
410 | regs->xcr2 |= XDATDLY(1); | |
411 | /* Invert FS polarity configuration */ | |
412 | temp_fmt ^= SND_SOC_DAIFMT_NB_IF; | |
413 | break; | |
bd25867a | 414 | case SND_SOC_DAIFMT_DSP_B: |
3336c5b5 AK |
415 | /* 0-bit data delay */ |
416 | regs->rcr2 |= RDATDLY(0); | |
417 | regs->xcr2 |= XDATDLY(0); | |
36ce8582 JN |
418 | /* Invert FS polarity configuration */ |
419 | temp_fmt ^= SND_SOC_DAIFMT_NB_IF; | |
3336c5b5 | 420 | break; |
2e74796a JN |
421 | default: |
422 | /* Unsupported data format */ | |
423 | return -EINVAL; | |
424 | } | |
425 | ||
426 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
427 | case SND_SOC_DAIFMT_CBS_CFS: | |
428 | /* McBSP master. Set FS and bit clocks as outputs */ | |
429 | regs->pcr0 |= FSXM | FSRM | | |
430 | CLKXM | CLKRM; | |
431 | /* Sample rate generator drives the FS */ | |
432 | regs->srgr2 |= FSGM; | |
433 | break; | |
434 | case SND_SOC_DAIFMT_CBM_CFM: | |
435 | /* McBSP slave */ | |
436 | break; | |
437 | default: | |
438 | /* Unsupported master/slave configuration */ | |
439 | return -EINVAL; | |
440 | } | |
441 | ||
442 | /* Set bit clock (CLKX/CLKR) and FS polarities */ | |
36ce8582 | 443 | switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) { |
2e74796a JN |
444 | case SND_SOC_DAIFMT_NB_NF: |
445 | /* | |
446 | * Normal BCLK + FS. | |
447 | * FS active low. TX data driven on falling edge of bit clock | |
448 | * and RX data sampled on rising edge of bit clock. | |
449 | */ | |
450 | regs->pcr0 |= FSXP | FSRP | | |
451 | CLKXP | CLKRP; | |
452 | break; | |
453 | case SND_SOC_DAIFMT_NB_IF: | |
454 | regs->pcr0 |= CLKXP | CLKRP; | |
455 | break; | |
456 | case SND_SOC_DAIFMT_IB_NF: | |
457 | regs->pcr0 |= FSXP | FSRP; | |
458 | break; | |
459 | case SND_SOC_DAIFMT_IB_IF: | |
460 | break; | |
461 | default: | |
462 | return -EINVAL; | |
463 | } | |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
8687eb8b | 468 | static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, |
2e74796a JN |
469 | int div_id, int div) |
470 | { | |
471 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); | |
472 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; | |
473 | ||
474 | if (div_id != OMAP_MCBSP_CLKGDV) | |
475 | return -ENODEV; | |
476 | ||
5f63ef99 | 477 | mcbsp_data->clk_div = div; |
2e74796a JN |
478 | regs->srgr1 |= CLKGDV(div - 1); |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
483 | static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data, | |
484 | int clk_id) | |
485 | { | |
486 | int sel_bit; | |
406e2c48 | 487 | u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1; |
2e74796a JN |
488 | |
489 | if (cpu_class_is_omap1()) { | |
490 | /* OMAP1's can use only external source clock */ | |
491 | if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)) | |
492 | return -EINVAL; | |
493 | else | |
494 | return 0; | |
495 | } | |
496 | ||
406e2c48 JN |
497 | if (cpu_is_omap2420() && mcbsp_data->bus_id > 1) |
498 | return -EINVAL; | |
499 | ||
500 | if (cpu_is_omap343x()) | |
501 | reg_devconf1 = OMAP343X_CONTROL_DEVCONF1; | |
502 | ||
2e74796a JN |
503 | switch (mcbsp_data->bus_id) { |
504 | case 0: | |
505 | reg = OMAP2_CONTROL_DEVCONF0; | |
506 | sel_bit = 2; | |
507 | break; | |
508 | case 1: | |
509 | reg = OMAP2_CONTROL_DEVCONF0; | |
510 | sel_bit = 6; | |
511 | break; | |
406e2c48 JN |
512 | case 2: |
513 | reg = reg_devconf1; | |
514 | sel_bit = 0; | |
515 | break; | |
516 | case 3: | |
517 | reg = reg_devconf1; | |
518 | sel_bit = 2; | |
519 | break; | |
520 | case 4: | |
521 | reg = reg_devconf1; | |
522 | sel_bit = 4; | |
523 | break; | |
2e74796a JN |
524 | default: |
525 | return -EINVAL; | |
526 | } | |
527 | ||
406e2c48 JN |
528 | if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK) |
529 | omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg); | |
530 | else | |
531 | omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg); | |
2e74796a JN |
532 | |
533 | return 0; | |
534 | } | |
535 | ||
d2c0bdaa JN |
536 | static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data, |
537 | int clk_id) | |
538 | { | |
539 | int sel_bit, set = 0; | |
540 | u16 reg = OMAP2_CONTROL_DEVCONF0; | |
541 | ||
542 | if (cpu_class_is_omap1()) | |
543 | return -EINVAL; /* TODO: Can this be implemented for OMAP1? */ | |
544 | if (mcbsp_data->bus_id != 0) | |
545 | return -EINVAL; | |
546 | ||
547 | switch (clk_id) { | |
548 | case OMAP_MCBSP_CLKR_SRC_CLKX: | |
549 | set = 1; | |
550 | case OMAP_MCBSP_CLKR_SRC_CLKR: | |
551 | sel_bit = 3; | |
552 | break; | |
553 | case OMAP_MCBSP_FSR_SRC_FSX: | |
554 | set = 1; | |
555 | case OMAP_MCBSP_FSR_SRC_FSR: | |
556 | sel_bit = 4; | |
557 | break; | |
558 | default: | |
559 | return -EINVAL; | |
560 | } | |
561 | ||
562 | if (set) | |
563 | omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg); | |
564 | else | |
565 | omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg); | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
8687eb8b | 570 | static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
2e74796a JN |
571 | int clk_id, unsigned int freq, |
572 | int dir) | |
573 | { | |
574 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); | |
575 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; | |
576 | int err = 0; | |
577 | ||
5f63ef99 GG |
578 | mcbsp_data->in_freq = freq; |
579 | ||
2e74796a JN |
580 | switch (clk_id) { |
581 | case OMAP_MCBSP_SYSCLK_CLK: | |
582 | regs->srgr2 |= CLKSM; | |
583 | break; | |
584 | case OMAP_MCBSP_SYSCLK_CLKS_FCLK: | |
585 | case OMAP_MCBSP_SYSCLK_CLKS_EXT: | |
586 | err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id); | |
587 | break; | |
588 | ||
589 | case OMAP_MCBSP_SYSCLK_CLKX_EXT: | |
590 | regs->srgr2 |= CLKSM; | |
591 | case OMAP_MCBSP_SYSCLK_CLKR_EXT: | |
592 | regs->pcr0 |= SCLKME; | |
593 | break; | |
d2c0bdaa JN |
594 | |
595 | case OMAP_MCBSP_CLKR_SRC_CLKR: | |
596 | case OMAP_MCBSP_CLKR_SRC_CLKX: | |
597 | case OMAP_MCBSP_FSR_SRC_FSR: | |
598 | case OMAP_MCBSP_FSR_SRC_FSX: | |
599 | err = omap_mcbsp_dai_set_rcvr_src(mcbsp_data, clk_id); | |
600 | break; | |
2e74796a JN |
601 | default: |
602 | err = -ENODEV; | |
603 | } | |
604 | ||
605 | return err; | |
606 | } | |
607 | ||
6335d055 EM |
608 | static struct snd_soc_dai_ops omap_mcbsp_dai_ops = { |
609 | .startup = omap_mcbsp_dai_startup, | |
610 | .shutdown = omap_mcbsp_dai_shutdown, | |
611 | .trigger = omap_mcbsp_dai_trigger, | |
612 | .hw_params = omap_mcbsp_dai_hw_params, | |
613 | .set_fmt = omap_mcbsp_dai_set_dai_fmt, | |
614 | .set_clkdiv = omap_mcbsp_dai_set_clkdiv, | |
615 | .set_sysclk = omap_mcbsp_dai_set_dai_sysclk, | |
616 | }; | |
617 | ||
8def464d JN |
618 | #define OMAP_MCBSP_DAI_BUILDER(link_id) \ |
619 | { \ | |
0c758bdd | 620 | .name = "omap-mcbsp-dai-"#link_id, \ |
8def464d | 621 | .id = (link_id), \ |
8def464d | 622 | .playback = { \ |
375e8a7c | 623 | .channels_min = 1, \ |
5f63ef99 | 624 | .channels_max = 16, \ |
8def464d JN |
625 | .rates = OMAP_MCBSP_RATES, \ |
626 | .formats = SNDRV_PCM_FMTBIT_S16_LE, \ | |
627 | }, \ | |
628 | .capture = { \ | |
375e8a7c | 629 | .channels_min = 1, \ |
5f63ef99 | 630 | .channels_max = 16, \ |
8def464d JN |
631 | .rates = OMAP_MCBSP_RATES, \ |
632 | .formats = SNDRV_PCM_FMTBIT_S16_LE, \ | |
633 | }, \ | |
6335d055 | 634 | .ops = &omap_mcbsp_dai_ops, \ |
8def464d JN |
635 | .private_data = &mcbsp_data[(link_id)].bus_id, \ |
636 | } | |
637 | ||
638 | struct snd_soc_dai omap_mcbsp_dai[] = { | |
639 | OMAP_MCBSP_DAI_BUILDER(0), | |
640 | OMAP_MCBSP_DAI_BUILDER(1), | |
641 | #if NUM_LINKS >= 3 | |
642 | OMAP_MCBSP_DAI_BUILDER(2), | |
643 | #endif | |
644 | #if NUM_LINKS == 5 | |
645 | OMAP_MCBSP_DAI_BUILDER(3), | |
646 | OMAP_MCBSP_DAI_BUILDER(4), | |
647 | #endif | |
2e74796a | 648 | }; |
8def464d | 649 | |
2e74796a JN |
650 | EXPORT_SYMBOL_GPL(omap_mcbsp_dai); |
651 | ||
83905c13 IK |
652 | int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol, |
653 | struct snd_ctl_elem_info *uinfo) | |
654 | { | |
655 | struct soc_mixer_control *mc = | |
656 | (struct soc_mixer_control *)kcontrol->private_value; | |
657 | int max = mc->max; | |
658 | int min = mc->min; | |
659 | ||
660 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
661 | uinfo->count = 1; | |
662 | uinfo->value.integer.min = min; | |
663 | uinfo->value.integer.max = max; | |
664 | return 0; | |
665 | } | |
666 | ||
667 | #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel) \ | |
668 | static int \ | |
669 | omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \ | |
670 | struct snd_ctl_elem_value *uc) \ | |
671 | { \ | |
672 | struct soc_mixer_control *mc = \ | |
673 | (struct soc_mixer_control *)kc->private_value; \ | |
674 | int max = mc->max; \ | |
675 | int min = mc->min; \ | |
676 | int val = uc->value.integer.value[0]; \ | |
677 | \ | |
678 | if (val < min || val > max) \ | |
679 | return -EINVAL; \ | |
680 | \ | |
681 | /* OMAP McBSP implementation uses index values 0..4 */ \ | |
682 | return omap_st_set_chgain((id)-1, channel, val); \ | |
683 | } | |
684 | ||
685 | #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel) \ | |
686 | static int \ | |
687 | omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \ | |
688 | struct snd_ctl_elem_value *uc) \ | |
689 | { \ | |
690 | s16 chgain; \ | |
691 | \ | |
692 | if (omap_st_get_chgain((id)-1, channel, &chgain)) \ | |
693 | return -EAGAIN; \ | |
694 | \ | |
695 | uc->value.integer.value[0] = chgain; \ | |
696 | return 0; \ | |
697 | } | |
698 | ||
699 | OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0) | |
700 | OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1) | |
701 | OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0) | |
702 | OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1) | |
703 | OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0) | |
704 | OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1) | |
705 | OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0) | |
706 | OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1) | |
707 | ||
708 | static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol, | |
709 | struct snd_ctl_elem_value *ucontrol) | |
710 | { | |
711 | struct soc_mixer_control *mc = | |
712 | (struct soc_mixer_control *)kcontrol->private_value; | |
713 | u8 value = ucontrol->value.integer.value[0]; | |
714 | ||
715 | if (value == omap_st_is_enabled(mc->reg)) | |
716 | return 0; | |
717 | ||
718 | if (value) | |
719 | omap_st_enable(mc->reg); | |
720 | else | |
721 | omap_st_disable(mc->reg); | |
722 | ||
723 | return 1; | |
724 | } | |
725 | ||
726 | static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol, | |
727 | struct snd_ctl_elem_value *ucontrol) | |
728 | { | |
729 | struct soc_mixer_control *mc = | |
730 | (struct soc_mixer_control *)kcontrol->private_value; | |
731 | ||
732 | ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg); | |
733 | return 0; | |
734 | } | |
735 | ||
736 | static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = { | |
737 | SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0, | |
738 | omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode), | |
739 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume", | |
740 | -32768, 32767, | |
741 | omap_mcbsp2_get_st_ch0_volume, | |
742 | omap_mcbsp2_set_st_ch0_volume), | |
743 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume", | |
744 | -32768, 32767, | |
745 | omap_mcbsp2_get_st_ch1_volume, | |
746 | omap_mcbsp2_set_st_ch1_volume), | |
747 | }; | |
748 | ||
749 | static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = { | |
750 | SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0, | |
751 | omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode), | |
752 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume", | |
753 | -32768, 32767, | |
754 | omap_mcbsp3_get_st_ch0_volume, | |
755 | omap_mcbsp3_set_st_ch0_volume), | |
756 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume", | |
757 | -32768, 32767, | |
758 | omap_mcbsp3_get_st_ch1_volume, | |
759 | omap_mcbsp3_set_st_ch1_volume), | |
760 | }; | |
761 | ||
762 | int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id) | |
763 | { | |
764 | if (!cpu_is_omap34xx()) | |
765 | return -ENODEV; | |
766 | ||
767 | switch (mcbsp_id) { | |
768 | case 1: /* McBSP 2 */ | |
769 | return snd_soc_add_controls(codec, omap_mcbsp2_st_controls, | |
770 | ARRAY_SIZE(omap_mcbsp2_st_controls)); | |
771 | case 2: /* McBSP 3 */ | |
772 | return snd_soc_add_controls(codec, omap_mcbsp3_st_controls, | |
773 | ARRAY_SIZE(omap_mcbsp3_st_controls)); | |
774 | default: | |
775 | break; | |
776 | } | |
777 | ||
778 | return -EINVAL; | |
779 | } | |
780 | EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls); | |
781 | ||
f73f2a6a | 782 | static int __init snd_omap_mcbsp_init(void) |
3f4b783c MB |
783 | { |
784 | return snd_soc_register_dais(omap_mcbsp_dai, | |
785 | ARRAY_SIZE(omap_mcbsp_dai)); | |
786 | } | |
f73f2a6a | 787 | module_init(snd_omap_mcbsp_init); |
3f4b783c | 788 | |
f73f2a6a | 789 | static void __exit snd_omap_mcbsp_exit(void) |
3f4b783c MB |
790 | { |
791 | snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai)); | |
792 | } | |
f73f2a6a | 793 | module_exit(snd_omap_mcbsp_exit); |
3f4b783c | 794 | |
b08f7a62 | 795 | MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>"); |
2e74796a JN |
796 | MODULE_DESCRIPTION("OMAP I2S SoC Interface"); |
797 | MODULE_LICENSE("GPL"); |