projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: mediatek: add some core clocks for MT2701 AFE
[linux-2.6-block.git] / sound / soc / mediatek / mt2701 / mt2701-afe-pcm.c
CommitLineData
43a6a7e7
GT		 1/*
2 * Mediatek ALSA SoC AFE platform driver for 2701
3 *
4 * Copyright (c) 2016 MediaTek Inc.
5 * Author: Garlic Tseng <garlic.tseng@mediatek.com>
6 * Ir Lian <ir.lian@mediatek.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 and
10 * only version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/delay.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/pm_runtime.h>
43a6a7e7
GT		 23
24#include "mt2701-afe-common.h"
43a6a7e7
GT		 25#include "mt2701-afe-clock-ctrl.h"
26#include "../common/mtk-afe-platform-driver.h"
27#include "../common/mtk-afe-fe-dai.h"
28
43a6a7e7
GT		 29static const struct snd_pcm_hardware mt2701_afe_hardware = {
30 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED
31 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID,
32 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE
33 | SNDRV_PCM_FMTBIT_S32_LE,
34 .period_bytes_min = 1024,
35 .period_bytes_max = 1024 * 256,
36 .periods_min = 4,
37 .periods_max = 1024,
38 .buffer_bytes_max = 1024 * 1024 * 16,
39 .fifo_size = 0,
40};
41
42struct mt2701_afe_rate {
43 unsigned int rate;
44 unsigned int regvalue;
45};
46
47static const struct mt2701_afe_rate mt2701_afe_i2s_rates[] = {
48 { .rate = 8000, .regvalue = 0 },
49 { .rate = 12000, .regvalue = 1 },
50 { .rate = 16000, .regvalue = 2 },
51 { .rate = 24000, .regvalue = 3 },
52 { .rate = 32000, .regvalue = 4 },
53 { .rate = 48000, .regvalue = 5 },
54 { .rate = 96000, .regvalue = 6 },
55 { .rate = 192000, .regvalue = 7 },
56 { .rate = 384000, .regvalue = 8 },
57 { .rate = 7350, .regvalue = 16 },
58 { .rate = 11025, .regvalue = 17 },
59 { .rate = 14700, .regvalue = 18 },
60 { .rate = 22050, .regvalue = 19 },
61 { .rate = 29400, .regvalue = 20 },
62 { .rate = 44100, .regvalue = 21 },
63 { .rate = 88200, .regvalue = 22 },
64 { .rate = 176400, .regvalue = 23 },
65 { .rate = 352800, .regvalue = 24 },
66};
67
25d01dc6 68static int mt2701_dai_num_to_i2s(struct mtk_base_afe *afe, int num)
43a6a7e7
GT		 69{
70 int val = num - MT2701_IO_I2S;
71
72 if (val < 0 || val >= MT2701_I2S_NUM) {
73 dev_err(afe->dev, "%s, num not available, num %d, val %d\n",
74 __func__, num, val);
75 return -EINVAL;
76 }
77 return val;
78}
79
80static int mt2701_afe_i2s_fs(unsigned int sample_rate)
81{
82 int i;
83
84 for (i = 0; i < ARRAY_SIZE(mt2701_afe_i2s_rates); i++)
85 if (mt2701_afe_i2s_rates[i].rate == sample_rate)
86 return mt2701_afe_i2s_rates[i].regvalue;
87
88 return -EINVAL;
89}
90
91static int mt2701_afe_i2s_startup(struct snd_pcm_substream *substream,
92 struct snd_soc_dai *dai)
93{
94 struct snd_soc_pcm_runtime *rtd = substream->private_data;
95 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
43a6a7e7 96 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
43a6a7e7
GT		 97
98 if (i2s_num < 0)
99 return i2s_num;
100
d8d99d8e 101 return mt2701_afe_enable_mclk(afe, i2s_num);
43a6a7e7
GT		 102}
103
104static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream,
105 struct snd_soc_dai *dai,
600b2fd4 106 int i2s_num,
43a6a7e7
GT		 107 int dir_invert)
108{
109 struct snd_soc_pcm_runtime *rtd = substream->private_data;
110 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
111 struct mt2701_afe_private *afe_priv = afe->platform_priv;
600b2fd4 112 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
43a6a7e7
GT		 113 const struct mt2701_i2s_data *i2s_data;
114 int stream_dir = substream->stream;
115
43a6a7e7
GT		 116 if (dir_invert) {
117 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
118 stream_dir = SNDRV_PCM_STREAM_CAPTURE;
119 else
120 stream_dir = SNDRV_PCM_STREAM_PLAYBACK;
121 }
122 i2s_data = i2s_path->i2s_data[stream_dir];
123
124 i2s_path->on[stream_dir]--;
125 if (i2s_path->on[stream_dir] < 0) {
126 dev_warn(afe->dev, "i2s_path->on: %d, dir: %d\n",
127 i2s_path->on[stream_dir], stream_dir);
128 i2s_path->on[stream_dir] = 0;
129 }
130 if (i2s_path->on[stream_dir])
131 return 0;
132
133 /* disable i2s */
134 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
135 ASYS_I2S_CON_I2S_EN, 0);
d8d99d8e
RL		 136
137 mt2701_afe_disable_i2s(afe, i2s_num, stream_dir);
138
43a6a7e7
GT		 139 return 0;
140}
141
142static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
143 struct snd_soc_dai *dai)
144{
145 struct snd_soc_pcm_runtime *rtd = substream->private_data;
146 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
147 struct mt2701_afe_private *afe_priv = afe->platform_priv;
148 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
149 struct mt2701_i2s_path *i2s_path;
43a6a7e7
GT		 150
151 if (i2s_num < 0)
152 return;
153
154 i2s_path = &afe_priv->i2s_path[i2s_num];
155
156 if (i2s_path->occupied[substream->stream])
157 i2s_path->occupied[substream->stream] = 0;
158 else
159 goto I2S_UNSTART;
160
600b2fd4 161 mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 0);
43a6a7e7
GT		 162
163 /* need to disable i2s-out path when disable i2s-in */
164 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
600b2fd4 165 mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 1);
43a6a7e7
GT		 166
167I2S_UNSTART:
168 /* disable mclk */
d8d99d8e 169 mt2701_afe_disable_mclk(afe, i2s_num);
43a6a7e7
GT		 170}
171
172static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream,
173 struct snd_soc_dai *dai,
600b2fd4 174 int i2s_num,
43a6a7e7
GT		 175 int dir_invert)
176{
177 struct snd_soc_pcm_runtime *rtd = substream->private_data;
178 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
179 struct mt2701_afe_private *afe_priv = afe->platform_priv;
600b2fd4 180 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
43a6a7e7
GT		 181 const struct mt2701_i2s_data *i2s_data;
182 struct snd_pcm_runtime * const runtime = substream->runtime;
183 int reg, fs, w_len = 1; /* now we support bck 64bits only */
184 int stream_dir = substream->stream;
185 unsigned int mask = 0, val = 0;
186
43a6a7e7
GT		 187 if (dir_invert) {
188 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
189 stream_dir = SNDRV_PCM_STREAM_CAPTURE;
190 else
191 stream_dir = SNDRV_PCM_STREAM_PLAYBACK;
192 }
193 i2s_data = i2s_path->i2s_data[stream_dir];
194
195 /* no need to enable if already done */
196 i2s_path->on[stream_dir]++;
197
198 if (i2s_path->on[stream_dir] != 1)
199 return 0;
200
201 fs = mt2701_afe_i2s_fs(runtime->rate);
202
203 mask = ASYS_I2S_CON_FS |
204 ASYS_I2S_CON_I2S_COUPLE_MODE | /* 0 */
205 ASYS_I2S_CON_I2S_MODE |
206 ASYS_I2S_CON_WIDE_MODE;
207
208 val = ASYS_I2S_CON_FS_SET(fs) |
209 ASYS_I2S_CON_I2S_MODE |
210 ASYS_I2S_CON_WIDE_MODE_SET(w_len);
211
212 if (stream_dir == SNDRV_PCM_STREAM_CAPTURE) {
213 mask |= ASYS_I2S_IN_PHASE_FIX;
214 val |= ASYS_I2S_IN_PHASE_FIX;
215 }
216
217 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, mask, val);
218
219 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
220 reg = ASMO_TIMING_CON1;
221 else
222 reg = ASMI_TIMING_CON1;
223
224 regmap_update_bits(afe->regmap, reg,
225 i2s_data->i2s_asrc_fs_mask
226 << i2s_data->i2s_asrc_fs_shift,
227 fs << i2s_data->i2s_asrc_fs_shift);
228
229 /* enable i2s */
d8d99d8e 230 mt2701_afe_enable_i2s(afe, i2s_num, stream_dir);
43a6a7e7
GT		 231
232 /* reset i2s hw status before enable */
233 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
234 ASYS_I2S_CON_RESET, ASYS_I2S_CON_RESET);
235 udelay(1);
236 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
237 ASYS_I2S_CON_RESET, 0);
238 udelay(1);
239 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
240 ASYS_I2S_CON_I2S_EN, ASYS_I2S_CON_I2S_EN);
241 return 0;
242}
243
244static int mt2701_afe_i2s_prepare(struct snd_pcm_substream *substream,
245 struct snd_soc_dai *dai)
246{
247 int clk_domain;
248 struct snd_soc_pcm_runtime *rtd = substream->private_data;
249 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
250 struct mt2701_afe_private *afe_priv = afe->platform_priv;
251 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
252 struct mt2701_i2s_path *i2s_path;
253 int mclk_rate;
254
255 if (i2s_num < 0)
256 return i2s_num;
257
258 i2s_path = &afe_priv->i2s_path[i2s_num];
259 mclk_rate = i2s_path->mclk_rate;
260
261 if (i2s_path->occupied[substream->stream])
262 return -EBUSY;
263 i2s_path->occupied[substream->stream] = 1;
264
265 if (MT2701_PLL_DOMAIN_0_RATE % mclk_rate == 0) {
266 clk_domain = 0;
267 } else if (MT2701_PLL_DOMAIN_1_RATE % mclk_rate == 0) {
268 clk_domain = 1;
269 } else {
270 dev_err(dai->dev, "%s() bad mclk rate %d\n",
271 __func__, mclk_rate);
272 return -EINVAL;
273 }
274 mt2701_mclk_configuration(afe, i2s_num, clk_domain, mclk_rate);
275
276 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
600b2fd4 277 mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
43a6a7e7
GT		 278 } else {
279 /* need to enable i2s-out path when enable i2s-in */
280 /* prepare for another direction "out" */
600b2fd4 281 mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 1);
43a6a7e7 282 /* prepare for "in" */
600b2fd4 283 mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
43a6a7e7
GT		 284 }
285
286 return 0;
287}
288
289static int mt2701_afe_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
290 unsigned int freq, int dir)
291{
292 struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
293 struct mt2701_afe_private *afe_priv = afe->platform_priv;
294 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
295
296 if (i2s_num < 0)
297 return i2s_num;
298
299 /* mclk */
300 if (dir == SND_SOC_CLOCK_IN) {
301 dev_warn(dai->dev,
302 "%s() warning: mt2701 doesn't support mclk input\n",
303 __func__);
304 return -EINVAL;
305 }
306 afe_priv->i2s_path[i2s_num].mclk_rate = freq;
307 return 0;
308}
309
4bdc8d45
GT		 310static int mt2701_btmrg_startup(struct snd_pcm_substream *substream,
311 struct snd_soc_dai *dai)
312{
313 struct snd_soc_pcm_runtime *rtd = substream->private_data;
314 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
315 struct mt2701_afe_private *afe_priv = afe->platform_priv;
d8d99d8e 316 int ret;
4bdc8d45 317
d8d99d8e
RL		 318 ret = mt2701_enable_btmrg_clk(afe);
319 if (ret)
320 return ret;
4bdc8d45
GT		 321
322 afe_priv->mrg_enable[substream->stream] = 1;
323 return 0;
324}
325
326static int mt2701_btmrg_hw_params(struct snd_pcm_substream *substream,
327 struct snd_pcm_hw_params *params,
328 struct snd_soc_dai *dai)
329{
330 struct snd_soc_pcm_runtime *rtd = substream->private_data;
331 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
332 int stream_fs;
333 u32 val, msk;
334
335 stream_fs = params_rate(params);
336
337 if ((stream_fs != 8000) && (stream_fs != 16000)) {
338 dev_err(afe->dev, "%s() btmgr not supprt this stream_fs %d\n",
339 __func__, stream_fs);
340 return -EINVAL;
341 }
342
343 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
344 AFE_MRGIF_CON_I2S_MODE_MASK,
345 AFE_MRGIF_CON_I2S_MODE_32K);
346
347 val = AFE_DAIBT_CON0_BT_FUNC_EN | AFE_DAIBT_CON0_BT_FUNC_RDY
348 | AFE_DAIBT_CON0_MRG_USE;
349 msk = val;
350
351 if (stream_fs == 16000)
352 val |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
353
354 msk |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
355
356 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0, msk, val);
357
358 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
359 AFE_DAIBT_CON0_DAIBT_EN,
360 AFE_DAIBT_CON0_DAIBT_EN);
361 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
362 AFE_MRGIF_CON_MRG_I2S_EN,
363 AFE_MRGIF_CON_MRG_I2S_EN);
364 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
365 AFE_MRGIF_CON_MRG_EN,
366 AFE_MRGIF_CON_MRG_EN);
367 return 0;
368}
369
370static void mt2701_btmrg_shutdown(struct snd_pcm_substream *substream,
371 struct snd_soc_dai *dai)
372{
373 struct snd_soc_pcm_runtime *rtd = substream->private_data;
374 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
375 struct mt2701_afe_private *afe_priv = afe->platform_priv;
376
377 /* if the other direction stream is not occupied */
378 if (!afe_priv->mrg_enable[!substream->stream]) {
379 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
380 AFE_DAIBT_CON0_DAIBT_EN, 0);
381 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
382 AFE_MRGIF_CON_MRG_EN, 0);
383 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
384 AFE_MRGIF_CON_MRG_I2S_EN, 0);
d8d99d8e 385 mt2701_disable_btmrg_clk(afe);
4bdc8d45
GT		 386 }
387 afe_priv->mrg_enable[substream->stream] = 0;
388}
389
43a6a7e7
GT		 390static int mt2701_simple_fe_startup(struct snd_pcm_substream *substream,
391 struct snd_soc_dai *dai)
392{
393 struct snd_soc_pcm_runtime *rtd = substream->private_data;
394 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
395 int stream_dir = substream->stream;
396 int memif_num = rtd->cpu_dai->id;
397 struct mtk_base_afe_memif *memif_tmp;
398
399 /* can't run single DL & DLM at the same time */
400 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) {
401 memif_tmp = &afe->memif[MT2701_MEMIF_DLM];
402 if (memif_tmp->substream) {
403 dev_warn(afe->dev, "%s memif is not available, stream_dir %d, memif_num %d\n",
404 __func__, stream_dir, memif_num);
405 return -EBUSY;
406 }
407 }
408 return mtk_afe_fe_startup(substream, dai);
409}
410
411static int mt2701_simple_fe_hw_params(struct snd_pcm_substream *substream,
412 struct snd_pcm_hw_params *params,
413 struct snd_soc_dai *dai)
414{
415 struct snd_soc_pcm_runtime *rtd = substream->private_data;
416 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
417 int stream_dir = substream->stream;
418
419 /* single DL use PAIR_INTERLEAVE */
420 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) {
421 regmap_update_bits(afe->regmap,
422 AFE_MEMIF_PBUF_SIZE,
423 AFE_MEMIF_PBUF_SIZE_DLM_MASK,
424 AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE);
425 }
426 return mtk_afe_fe_hw_params(substream, params, dai);
427}
428
429static int mt2701_dlm_fe_startup(struct snd_pcm_substream *substream,
430 struct snd_soc_dai *dai)
431{
432 struct snd_soc_pcm_runtime *rtd = substream->private_data;
433 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
434 struct mtk_base_afe_memif *memif_tmp;
435 const struct mtk_base_memif_data *memif_data;
436 int i;
437
438 for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
439 memif_tmp = &afe->memif[i];
440 if (memif_tmp->substream)
441 return -EBUSY;
442 }
443
444 /* enable agent for all signal DL (due to hw design) */
445 for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
446 memif_data = afe->memif[i].data;
447 regmap_update_bits(afe->regmap,
448 memif_data->agent_disable_reg,
449 1 << memif_data->agent_disable_shift,
450 0 << memif_data->agent_disable_shift);
451 }
452
453 return mtk_afe_fe_startup(substream, dai);
454}
455
456static void mt2701_dlm_fe_shutdown(struct snd_pcm_substream *substream,
457 struct snd_soc_dai *dai)
458{
459 struct snd_soc_pcm_runtime *rtd = substream->private_data;
460 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
461 const struct mtk_base_memif_data *memif_data;
462 int i;
463
464 for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
465 memif_data = afe->memif[i].data;
466 regmap_update_bits(afe->regmap,
467 memif_data->agent_disable_reg,
468 1 << memif_data->agent_disable_shift,
469 1 << memif_data->agent_disable_shift);
470 }
471 return mtk_afe_fe_shutdown(substream, dai);
472}
473
474static int mt2701_dlm_fe_hw_params(struct snd_pcm_substream *substream,
475 struct snd_pcm_hw_params *params,
476 struct snd_soc_dai *dai)
477{
478 struct snd_soc_pcm_runtime *rtd = substream->private_data;
479 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
480 int channels = params_channels(params);
481
482 regmap_update_bits(afe->regmap,
483 AFE_MEMIF_PBUF_SIZE,
484 AFE_MEMIF_PBUF_SIZE_DLM_MASK,
485 AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE);
486 regmap_update_bits(afe->regmap,
487 AFE_MEMIF_PBUF_SIZE,
488 AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK,
489 AFE_MEMIF_PBUF_SIZE_DLM_32BYTES);
490 regmap_update_bits(afe->regmap,
491 AFE_MEMIF_PBUF_SIZE,
492 AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK,
493 AFE_MEMIF_PBUF_SIZE_DLM_CH(channels));
494
495 return mtk_afe_fe_hw_params(substream, params, dai);
496}
497
498static int mt2701_dlm_fe_trigger(struct snd_pcm_substream *substream,
499 int cmd, struct snd_soc_dai *dai)
500{
501 struct snd_soc_pcm_runtime *rtd = substream->private_data;
502 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
503 struct mtk_base_afe_memif *memif_tmp = &afe->memif[MT2701_MEMIF_DL1];
504
505 switch (cmd) {
506 case SNDRV_PCM_TRIGGER_START:
507 case SNDRV_PCM_TRIGGER_RESUME:
508 regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
509 1 << memif_tmp->data->enable_shift,
510 1 << memif_tmp->data->enable_shift);
511 mtk_afe_fe_trigger(substream, cmd, dai);
512 return 0;
513 case SNDRV_PCM_TRIGGER_STOP:
514 case SNDRV_PCM_TRIGGER_SUSPEND:
515 mtk_afe_fe_trigger(substream, cmd, dai);
516 regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
517 1 << memif_tmp->data->enable_shift, 0);
518
519 return 0;
520 default:
521 return -EINVAL;
522 }
523}
524
525static int mt2701_memif_fs(struct snd_pcm_substream *substream,
526 unsigned int rate)
527{
528 struct snd_soc_pcm_runtime *rtd = substream->private_data;
529 int fs;
530
531 if (rtd->cpu_dai->id != MT2701_MEMIF_ULBT)
532 fs = mt2701_afe_i2s_fs(rate);
533 else
534 fs = (rate == 16000 ? 1 : 0);
535 return fs;
536}
537
538static int mt2701_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
539{
540 return mt2701_afe_i2s_fs(rate);
541}
542
543/* FE DAIs */
544static const struct snd_soc_dai_ops mt2701_single_memif_dai_ops = {
545 .startup = mt2701_simple_fe_startup,
546 .shutdown = mtk_afe_fe_shutdown,
547 .hw_params = mt2701_simple_fe_hw_params,
548 .hw_free = mtk_afe_fe_hw_free,
549 .prepare = mtk_afe_fe_prepare,
550 .trigger = mtk_afe_fe_trigger,
43a6a7e7
GT		 551};
552
553static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = {
554 .startup = mt2701_dlm_fe_startup,
555 .shutdown = mt2701_dlm_fe_shutdown,
556 .hw_params = mt2701_dlm_fe_hw_params,
557 .hw_free = mtk_afe_fe_hw_free,
558 .prepare = mtk_afe_fe_prepare,
559 .trigger = mt2701_dlm_fe_trigger,
560};
561
562/* I2S BE DAIs */
563static const struct snd_soc_dai_ops mt2701_afe_i2s_ops = {
564 .startup = mt2701_afe_i2s_startup,
565 .shutdown = mt2701_afe_i2s_shutdown,
566 .prepare = mt2701_afe_i2s_prepare,
567 .set_sysclk = mt2701_afe_i2s_set_sysclk,
568};
569
4bdc8d45 570/* MRG BE DAIs */
549acff9 571static const struct snd_soc_dai_ops mt2701_btmrg_ops = {
4bdc8d45
GT		 572 .startup = mt2701_btmrg_startup,
573 .shutdown = mt2701_btmrg_shutdown,
574 .hw_params = mt2701_btmrg_hw_params,
575};
576
43a6a7e7
GT		 577static struct snd_soc_dai_driver mt2701_afe_pcm_dais[] = {
578 /* FE DAIs: memory intefaces to CPU */
8625c1db
RL		 579 {
580 .name = "PCMO0",
581 .id = MT2701_MEMIF_DL1,
582 .suspend = mtk_afe_dai_suspend,
583 .resume = mtk_afe_dai_resume,
584 .playback = {
585 .stream_name = "DL1",
586 .channels_min = 1,
587 .channels_max = 2,
588 .rates = SNDRV_PCM_RATE_8000_192000,
589 .formats = (SNDRV_PCM_FMTBIT_S16_LE
590 | SNDRV_PCM_FMTBIT_S24_LE
591 | SNDRV_PCM_FMTBIT_S32_LE)
592 },
593 .ops = &mt2701_single_memif_dai_ops,
594 },
43a6a7e7
GT		 595 {
596 .name = "PCM_multi",
597 .id = MT2701_MEMIF_DLM,
598 .suspend = mtk_afe_dai_suspend,
599 .resume = mtk_afe_dai_resume,
600 .playback = {
601 .stream_name = "DLM",
602 .channels_min = 1,
603 .channels_max = 8,
604 .rates = SNDRV_PCM_RATE_8000_192000,
605 .formats = (SNDRV_PCM_FMTBIT_S16_LE
606 | SNDRV_PCM_FMTBIT_S24_LE
607 | SNDRV_PCM_FMTBIT_S32_LE)
608
609 },
610 .ops = &mt2701_dlm_memif_dai_ops,
611 },
612 {
613 .name = "PCM0",
614 .id = MT2701_MEMIF_UL1,
615 .suspend = mtk_afe_dai_suspend,
616 .resume = mtk_afe_dai_resume,
617 .capture = {
618 .stream_name = "UL1",
619 .channels_min = 1,
620 .channels_max = 2,
621 .rates = SNDRV_PCM_RATE_8000_48000,
622 .formats = (SNDRV_PCM_FMTBIT_S16_LE
623 | SNDRV_PCM_FMTBIT_S24_LE
624 | SNDRV_PCM_FMTBIT_S32_LE)
625 },
626 .ops = &mt2701_single_memif_dai_ops,
627 },
628 {
629 .name = "PCM1",
630 .id = MT2701_MEMIF_UL2,
631 .suspend = mtk_afe_dai_suspend,
632 .resume = mtk_afe_dai_resume,
633 .capture = {
634 .stream_name = "UL2",
635 .channels_min = 1,
636 .channels_max = 2,
637 .rates = SNDRV_PCM_RATE_8000_192000,
638 .formats = (SNDRV_PCM_FMTBIT_S16_LE
639 | SNDRV_PCM_FMTBIT_S24_LE
640 | SNDRV_PCM_FMTBIT_S32_LE)
641
642 },
643 .ops = &mt2701_single_memif_dai_ops,
644 },
4bdc8d45
GT		 645 {
646 .name = "PCM_BT_DL",
647 .id = MT2701_MEMIF_DLBT,
648 .suspend = mtk_afe_dai_suspend,
649 .resume = mtk_afe_dai_resume,
650 .playback = {
651 .stream_name = "DLBT",
652 .channels_min = 1,
653 .channels_max = 1,
654 .rates = (SNDRV_PCM_RATE_8000
655 | SNDRV_PCM_RATE_16000),
656 .formats = SNDRV_PCM_FMTBIT_S16_LE,
657 },
658 .ops = &mt2701_single_memif_dai_ops,
659 },
660 {
661 .name = "PCM_BT_UL",
662 .id = MT2701_MEMIF_ULBT,
663 .suspend = mtk_afe_dai_suspend,
664 .resume = mtk_afe_dai_resume,
665 .capture = {
666 .stream_name = "ULBT",
667 .channels_min = 1,
668 .channels_max = 1,
669 .rates = (SNDRV_PCM_RATE_8000
670 | SNDRV_PCM_RATE_16000),
671 .formats = SNDRV_PCM_FMTBIT_S16_LE,
672 },
673 .ops = &mt2701_single_memif_dai_ops,
674 },
43a6a7e7
GT		 675 /* BE DAIs */
676 {
677 .name = "I2S0",
678 .id = MT2701_IO_I2S,
679 .playback = {
680 .stream_name = "I2S0 Playback",
681 .channels_min = 1,
682 .channels_max = 2,
683 .rates = SNDRV_PCM_RATE_8000_192000,
684 .formats = (SNDRV_PCM_FMTBIT_S16_LE
685 | SNDRV_PCM_FMTBIT_S24_LE
686 | SNDRV_PCM_FMTBIT_S32_LE)
687
688 },
689 .capture = {
690 .stream_name = "I2S0 Capture",
691 .channels_min = 1,
692 .channels_max = 2,
693 .rates = SNDRV_PCM_RATE_8000_192000,
694 .formats = (SNDRV_PCM_FMTBIT_S16_LE
695 | SNDRV_PCM_FMTBIT_S24_LE
696 | SNDRV_PCM_FMTBIT_S32_LE)
697
698 },
699 .ops = &mt2701_afe_i2s_ops,
700 .symmetric_rates = 1,
701 },
702 {
703 .name = "I2S1",
704 .id = MT2701_IO_2ND_I2S,
705 .playback = {
706 .stream_name = "I2S1 Playback",
707 .channels_min = 1,
708 .channels_max = 2,
709 .rates = SNDRV_PCM_RATE_8000_192000,
710 .formats = (SNDRV_PCM_FMTBIT_S16_LE
711 | SNDRV_PCM_FMTBIT_S24_LE
712 | SNDRV_PCM_FMTBIT_S32_LE)
713 },
714 .capture = {
715 .stream_name = "I2S1 Capture",
716 .channels_min = 1,
717 .channels_max = 2,
718 .rates = SNDRV_PCM_RATE_8000_192000,
719 .formats = (SNDRV_PCM_FMTBIT_S16_LE
720 | SNDRV_PCM_FMTBIT_S24_LE
721 | SNDRV_PCM_FMTBIT_S32_LE)
722 },
723 .ops = &mt2701_afe_i2s_ops,
724 .symmetric_rates = 1,
725 },
726 {
727 .name = "I2S2",
728 .id = MT2701_IO_3RD_I2S,
729 .playback = {
730 .stream_name = "I2S2 Playback",
731 .channels_min = 1,
732 .channels_max = 2,
733 .rates = SNDRV_PCM_RATE_8000_192000,
734 .formats = (SNDRV_PCM_FMTBIT_S16_LE
735 | SNDRV_PCM_FMTBIT_S24_LE
736 | SNDRV_PCM_FMTBIT_S32_LE)
737 },
738 .capture = {
739 .stream_name = "I2S2 Capture",
740 .channels_min = 1,
741 .channels_max = 2,
742 .rates = SNDRV_PCM_RATE_8000_192000,
743 .formats = (SNDRV_PCM_FMTBIT_S16_LE
744 | SNDRV_PCM_FMTBIT_S24_LE
745 | SNDRV_PCM_FMTBIT_S32_LE)
746 },
747 .ops = &mt2701_afe_i2s_ops,
748 .symmetric_rates = 1,
749 },
750 {
751 .name = "I2S3",
752 .id = MT2701_IO_4TH_I2S,
753 .playback = {
754 .stream_name = "I2S3 Playback",
755 .channels_min = 1,
756 .channels_max = 2,
757 .rates = SNDRV_PCM_RATE_8000_192000,
758 .formats = (SNDRV_PCM_FMTBIT_S16_LE
759 | SNDRV_PCM_FMTBIT_S24_LE
760 | SNDRV_PCM_FMTBIT_S32_LE)
761 },
762 .capture = {
763 .stream_name = "I2S3 Capture",
764 .channels_min = 1,
765 .channels_max = 2,
766 .rates = SNDRV_PCM_RATE_8000_192000,
767 .formats = (SNDRV_PCM_FMTBIT_S16_LE
768 | SNDRV_PCM_FMTBIT_S24_LE
769 | SNDRV_PCM_FMTBIT_S32_LE)
770 },
771 .ops = &mt2701_afe_i2s_ops,
772 .symmetric_rates = 1,
773 },
4bdc8d45
GT		 774 {
775 .name = "MRG BT",
776 .id = MT2701_IO_MRG,
777 .playback = {
778 .stream_name = "BT Playback",
779 .channels_min = 1,
780 .channels_max = 1,
781 .rates = (SNDRV_PCM_RATE_8000
782 | SNDRV_PCM_RATE_16000),
783 .formats = SNDRV_PCM_FMTBIT_S16_LE,
784 },
785 .capture = {
786 .stream_name = "BT Capture",
787 .channels_min = 1,
788 .channels_max = 1,
789 .rates = (SNDRV_PCM_RATE_8000
790 | SNDRV_PCM_RATE_16000),
791 .formats = SNDRV_PCM_FMTBIT_S16_LE,
792 },
793 .ops = &mt2701_btmrg_ops,
794 .symmetric_rates = 1,
795 }
43a6a7e7
GT		 796};
797
798static const struct snd_kcontrol_new mt2701_afe_o00_mix[] = {
799 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN0, 0, 1, 0),
800};
801
802static const struct snd_kcontrol_new mt2701_afe_o01_mix[] = {
803 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN1, 1, 1, 0),
804};
805
806static const struct snd_kcontrol_new mt2701_afe_o02_mix[] = {
807 SOC_DAPM_SINGLE_AUTODISABLE("I02 Switch", AFE_CONN2, 2, 1, 0),
808};
809
810static const struct snd_kcontrol_new mt2701_afe_o03_mix[] = {
811 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 3, 1, 0),
812};
813
814static const struct snd_kcontrol_new mt2701_afe_o14_mix[] = {
815 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN14, 26, 1, 0),
816};
817
818static const struct snd_kcontrol_new mt2701_afe_o15_mix[] = {
819 SOC_DAPM_SINGLE_AUTODISABLE("I12 Switch", AFE_CONN15, 12, 1, 0),
820};
821
822static const struct snd_kcontrol_new mt2701_afe_o16_mix[] = {
823 SOC_DAPM_SINGLE_AUTODISABLE("I13 Switch", AFE_CONN16, 13, 1, 0),
824};
825
826static const struct snd_kcontrol_new mt2701_afe_o17_mix[] = {
827 SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN17, 14, 1, 0),
828};
829
830static const struct snd_kcontrol_new mt2701_afe_o18_mix[] = {
831 SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN18, 15, 1, 0),
832};
833
834static const struct snd_kcontrol_new mt2701_afe_o19_mix[] = {
835 SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN19, 16, 1, 0),
836};
837
838static const struct snd_kcontrol_new mt2701_afe_o20_mix[] = {
839 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN20, 17, 1, 0),
840};
841
842static const struct snd_kcontrol_new mt2701_afe_o21_mix[] = {
843 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN21, 18, 1, 0),
844};
845
846static const struct snd_kcontrol_new mt2701_afe_o22_mix[] = {
847 SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN22, 19, 1, 0),
848};
849
850static const struct snd_kcontrol_new mt2701_afe_o23_mix[] = {
851 SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN23, 20, 1, 0),
852};
853
854static const struct snd_kcontrol_new mt2701_afe_o24_mix[] = {
855 SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN24, 21, 1, 0),
856};
857
858static const struct snd_kcontrol_new mt2701_afe_o31_mix[] = {
859 SOC_DAPM_SINGLE_AUTODISABLE("I35 Switch", AFE_CONN41, 9, 1, 0),
860};
861
862static const struct snd_kcontrol_new mt2701_afe_i02_mix[] = {
863 SOC_DAPM_SINGLE("I2S0 Switch", SND_SOC_NOPM, 0, 1, 0),
864};
865
866static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s0[] = {
867 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S0 Out Switch",
868 ASYS_I2SO1_CON, 26, 1, 0),
869};
870
871static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s1[] = {
872 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S1 Out Switch",
873 ASYS_I2SO2_CON, 26, 1, 0),
874};
875
876static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s2[] = {
877 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S2 Out Switch",
878 PWR2_TOP_CON, 17, 1, 0),
879};
880
881static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s3[] = {
882 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S3 Out Switch",
883 PWR2_TOP_CON, 18, 1, 0),
884};
885
886static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s4[] = {
887 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S4 Out Switch",
888 PWR2_TOP_CON, 19, 1, 0),
889};
890
43a6a7e7
GT		 891static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
892 /* inter-connections */
893 SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
894 SND_SOC_DAPM_MIXER("I01", SND_SOC_NOPM, 0, 0, NULL, 0),
895 SND_SOC_DAPM_MIXER("I02", SND_SOC_NOPM, 0, 0, mt2701_afe_i02_mix,
896 ARRAY_SIZE(mt2701_afe_i02_mix)),
897 SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
898 SND_SOC_DAPM_MIXER("I12", SND_SOC_NOPM, 0, 0, NULL, 0),
899 SND_SOC_DAPM_MIXER("I13", SND_SOC_NOPM, 0, 0, NULL, 0),
900 SND_SOC_DAPM_MIXER("I14", SND_SOC_NOPM, 0, 0, NULL, 0),
901 SND_SOC_DAPM_MIXER("I15", SND_SOC_NOPM, 0, 0, NULL, 0),
902 SND_SOC_DAPM_MIXER("I16", SND_SOC_NOPM, 0, 0, NULL, 0),
903 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
904 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
905 SND_SOC_DAPM_MIXER("I19", SND_SOC_NOPM, 0, 0, NULL, 0),
906 SND_SOC_DAPM_MIXER("I26", SND_SOC_NOPM, 0, 0, NULL, 0),
907 SND_SOC_DAPM_MIXER("I35", SND_SOC_NOPM, 0, 0, NULL, 0),
908
909 SND_SOC_DAPM_MIXER("O00", SND_SOC_NOPM, 0, 0, mt2701_afe_o00_mix,
910 ARRAY_SIZE(mt2701_afe_o00_mix)),
911 SND_SOC_DAPM_MIXER("O01", SND_SOC_NOPM, 0, 0, mt2701_afe_o01_mix,
912 ARRAY_SIZE(mt2701_afe_o01_mix)),
913 SND_SOC_DAPM_MIXER("O02", SND_SOC_NOPM, 0, 0, mt2701_afe_o02_mix,
914 ARRAY_SIZE(mt2701_afe_o02_mix)),
915 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0, mt2701_afe_o03_mix,
916 ARRAY_SIZE(mt2701_afe_o03_mix)),
917 SND_SOC_DAPM_MIXER("O14", SND_SOC_NOPM, 0, 0, mt2701_afe_o14_mix,
918 ARRAY_SIZE(mt2701_afe_o14_mix)),
919 SND_SOC_DAPM_MIXER("O15", SND_SOC_NOPM, 0, 0, mt2701_afe_o15_mix,
920 ARRAY_SIZE(mt2701_afe_o15_mix)),
921 SND_SOC_DAPM_MIXER("O16", SND_SOC_NOPM, 0, 0, mt2701_afe_o16_mix,
922 ARRAY_SIZE(mt2701_afe_o16_mix)),
923 SND_SOC_DAPM_MIXER("O17", SND_SOC_NOPM, 0, 0, mt2701_afe_o17_mix,
924 ARRAY_SIZE(mt2701_afe_o17_mix)),
925 SND_SOC_DAPM_MIXER("O18", SND_SOC_NOPM, 0, 0, mt2701_afe_o18_mix,
926 ARRAY_SIZE(mt2701_afe_o18_mix)),
927 SND_SOC_DAPM_MIXER("O19", SND_SOC_NOPM, 0, 0, mt2701_afe_o19_mix,
928 ARRAY_SIZE(mt2701_afe_o19_mix)),
929 SND_SOC_DAPM_MIXER("O20", SND_SOC_NOPM, 0, 0, mt2701_afe_o20_mix,
930 ARRAY_SIZE(mt2701_afe_o20_mix)),
931 SND_SOC_DAPM_MIXER("O21", SND_SOC_NOPM, 0, 0, mt2701_afe_o21_mix,
932 ARRAY_SIZE(mt2701_afe_o21_mix)),
933 SND_SOC_DAPM_MIXER("O22", SND_SOC_NOPM, 0, 0, mt2701_afe_o22_mix,
934 ARRAY_SIZE(mt2701_afe_o22_mix)),
935 SND_SOC_DAPM_MIXER("O31", SND_SOC_NOPM, 0, 0, mt2701_afe_o31_mix,
936 ARRAY_SIZE(mt2701_afe_o31_mix)),
937
938 SND_SOC_DAPM_MIXER("I12I13", SND_SOC_NOPM, 0, 0,
939 mt2701_afe_multi_ch_out_i2s0,
940 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s0)),
941 SND_SOC_DAPM_MIXER("I14I15", SND_SOC_NOPM, 0, 0,
942 mt2701_afe_multi_ch_out_i2s1,
943 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s1)),
944 SND_SOC_DAPM_MIXER("I16I17", SND_SOC_NOPM, 0, 0,
945 mt2701_afe_multi_ch_out_i2s2,
946 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s2)),
947 SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0,
948 mt2701_afe_multi_ch_out_i2s3,
949 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)),
43a6a7e7
GT		 950};
951
952static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
953 {"I12", NULL, "DL1"},
954 {"I13", NULL, "DL1"},
955 {"I35", NULL, "DLBT"},
956
957 {"I2S0 Playback", NULL, "O15"},
958 {"I2S0 Playback", NULL, "O16"},
43a6a7e7
GT		 959 {"I2S1 Playback", NULL, "O17"},
960 {"I2S1 Playback", NULL, "O18"},
961 {"I2S2 Playback", NULL, "O19"},
962 {"I2S2 Playback", NULL, "O20"},
963 {"I2S3 Playback", NULL, "O21"},
964 {"I2S3 Playback", NULL, "O22"},
965 {"BT Playback", NULL, "O31"},
966
967 {"UL1", NULL, "O00"},
968 {"UL1", NULL, "O01"},
969 {"UL2", NULL, "O02"},
970 {"UL2", NULL, "O03"},
971 {"ULBT", NULL, "O14"},
972
973 {"I00", NULL, "I2S0 Capture"},
974 {"I01", NULL, "I2S0 Capture"},
43a6a7e7
GT		 975 {"I02", NULL, "I2S1 Capture"},
976 {"I03", NULL, "I2S1 Capture"},
977 /* I02,03 link to UL2, also need to open I2S0 */
978 {"I02", "I2S0 Switch", "I2S0 Capture"},
979
980 {"I26", NULL, "BT Capture"},
981
600b2fd4
RL		 982 {"I12I13", "Multich I2S0 Out Switch", "DLM"},
983 {"I14I15", "Multich I2S1 Out Switch", "DLM"},
984 {"I16I17", "Multich I2S2 Out Switch", "DLM"},
985 {"I18I19", "Multich I2S3 Out Switch", "DLM"},
43a6a7e7
GT		 986
987 { "I12", NULL, "I12I13" },
988 { "I13", NULL, "I12I13" },
989 { "I14", NULL, "I14I15" },
990 { "I15", NULL, "I14I15" },
991 { "I16", NULL, "I16I17" },
992 { "I17", NULL, "I16I17" },
993 { "I18", NULL, "I18I19" },
994 { "I19", NULL, "I18I19" },
995
996 { "O00", "I00 Switch", "I00" },
997 { "O01", "I01 Switch", "I01" },
998 { "O02", "I02 Switch", "I02" },
999 { "O03", "I03 Switch", "I03" },
1000 { "O14", "I26 Switch", "I26" },
1001 { "O15", "I12 Switch", "I12" },
1002 { "O16", "I13 Switch", "I13" },
1003 { "O17", "I14 Switch", "I14" },
1004 { "O18", "I15 Switch", "I15" },
1005 { "O19", "I16 Switch", "I16" },
1006 { "O20", "I17 Switch", "I17" },
1007 { "O21", "I18 Switch", "I18" },
1008 { "O22", "I19 Switch", "I19" },
1009 { "O31", "I35 Switch", "I35" },
43a6a7e7
GT		 1010};
1011
1012static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = {
1013 .name = "mt2701-afe-pcm-dai",
1014 .dapm_widgets = mt2701_afe_pcm_widgets,
1015 .num_dapm_widgets = ARRAY_SIZE(mt2701_afe_pcm_widgets),
1016 .dapm_routes = mt2701_afe_pcm_routes,
1017 .num_dapm_routes = ARRAY_SIZE(mt2701_afe_pcm_routes),
1018};
1019
1020static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
1021 {
1022 .name = "DL1",
1023 .id = MT2701_MEMIF_DL1,
1024 .reg_ofs_base = AFE_DL1_BASE,
1025 .reg_ofs_cur = AFE_DL1_CUR,
1026 .fs_reg = AFE_DAC_CON1,
1027 .fs_shift = 0,
1028 .fs_maskbit = 0x1f,
1029 .mono_reg = AFE_DAC_CON3,
1030 .mono_shift = 16,
1031 .enable_reg = AFE_DAC_CON0,
1032 .enable_shift = 1,
1033 .hd_reg = AFE_MEMIF_HD_CON0,
1034 .hd_shift = 0,
1035 .agent_disable_reg = AUDIO_TOP_CON5,
1036 .agent_disable_shift = 6,
1037 .msb_reg = -1,
1038 .msb_shift = -1,
1039 },
1040 {
1041 .name = "DL2",
1042 .id = MT2701_MEMIF_DL2,
1043 .reg_ofs_base = AFE_DL2_BASE,
1044 .reg_ofs_cur = AFE_DL2_CUR,
1045 .fs_reg = AFE_DAC_CON1,
1046 .fs_shift = 5,
1047 .fs_maskbit = 0x1f,
1048 .mono_reg = AFE_DAC_CON3,
1049 .mono_shift = 17,
1050 .enable_reg = AFE_DAC_CON0,
1051 .enable_shift = 2,
1052 .hd_reg = AFE_MEMIF_HD_CON0,
1053 .hd_shift = 2,
1054 .agent_disable_reg = AUDIO_TOP_CON5,
1055 .agent_disable_shift = 7,
1056 .msb_reg = -1,
1057 .msb_shift = -1,
1058 },
1059 {
1060 .name = "DL3",
1061 .id = MT2701_MEMIF_DL3,
1062 .reg_ofs_base = AFE_DL3_BASE,
1063 .reg_ofs_cur = AFE_DL3_CUR,
1064 .fs_reg = AFE_DAC_CON1,
1065 .fs_shift = 10,
1066 .fs_maskbit = 0x1f,
1067 .mono_reg = AFE_DAC_CON3,
1068 .mono_shift = 18,
1069 .enable_reg = AFE_DAC_CON0,
1070 .enable_shift = 3,
1071 .hd_reg = AFE_MEMIF_HD_CON0,
1072 .hd_shift = 4,
1073 .agent_disable_reg = AUDIO_TOP_CON5,
1074 .agent_disable_shift = 8,
1075 .msb_reg = -1,
1076 .msb_shift = -1,
1077 },
1078 {
1079 .name = "DL4",
1080 .id = MT2701_MEMIF_DL4,
1081 .reg_ofs_base = AFE_DL4_BASE,
1082 .reg_ofs_cur = AFE_DL4_CUR,
1083 .fs_reg = AFE_DAC_CON1,
1084 .fs_shift = 15,
1085 .fs_maskbit = 0x1f,
1086 .mono_reg = AFE_DAC_CON3,
1087 .mono_shift = 19,
1088 .enable_reg = AFE_DAC_CON0,
1089 .enable_shift = 4,
1090 .hd_reg = AFE_MEMIF_HD_CON0,
1091 .hd_shift = 6,
1092 .agent_disable_reg = AUDIO_TOP_CON5,
1093 .agent_disable_shift = 9,
1094 .msb_reg = -1,
1095 .msb_shift = -1,
1096 },
1097 {
1098 .name = "DL5",
1099 .id = MT2701_MEMIF_DL5,
1100 .reg_ofs_base = AFE_DL5_BASE,
1101 .reg_ofs_cur = AFE_DL5_CUR,
1102 .fs_reg = AFE_DAC_CON1,
1103 .fs_shift = 20,
1104 .fs_maskbit = 0x1f,
1105 .mono_reg = AFE_DAC_CON3,
1106 .mono_shift = 20,
1107 .enable_reg = AFE_DAC_CON0,
1108 .enable_shift = 5,
1109 .hd_reg = AFE_MEMIF_HD_CON0,
1110 .hd_shift = 8,
1111 .agent_disable_reg = AUDIO_TOP_CON5,
1112 .agent_disable_shift = 10,
1113 .msb_reg = -1,
1114 .msb_shift = -1,
1115 },
1116 {
1117 .name = "DLM",
1118 .id = MT2701_MEMIF_DLM,
1119 .reg_ofs_base = AFE_DLMCH_BASE,
1120 .reg_ofs_cur = AFE_DLMCH_CUR,
1121 .fs_reg = AFE_DAC_CON1,
1122 .fs_shift = 0,
1123 .fs_maskbit = 0x1f,
1124 .mono_reg = -1,
1125 .mono_shift = -1,
1126 .enable_reg = AFE_DAC_CON0,
1127 .enable_shift = 7,
1128 .hd_reg = AFE_MEMIF_PBUF_SIZE,
1129 .hd_shift = 28,
1130 .agent_disable_reg = AUDIO_TOP_CON5,
1131 .agent_disable_shift = 12,
1132 .msb_reg = -1,
1133 .msb_shift = -1,
1134 },
1135 {
1136 .name = "UL1",
1137 .id = MT2701_MEMIF_UL1,
1138 .reg_ofs_base = AFE_VUL_BASE,
1139 .reg_ofs_cur = AFE_VUL_CUR,
1140 .fs_reg = AFE_DAC_CON2,
1141 .fs_shift = 0,
1142 .fs_maskbit = 0x1f,
1143 .mono_reg = AFE_DAC_CON4,
1144 .mono_shift = 0,
1145 .enable_reg = AFE_DAC_CON0,
1146 .enable_shift = 10,
1147 .hd_reg = AFE_MEMIF_HD_CON1,
1148 .hd_shift = 0,
1149 .agent_disable_reg = AUDIO_TOP_CON5,
1150 .agent_disable_shift = 0,
1151 .msb_reg = -1,
1152 .msb_shift = -1,
1153 },
1154 {
1155 .name = "UL2",
1156 .id = MT2701_MEMIF_UL2,
1157 .reg_ofs_base = AFE_UL2_BASE,
1158 .reg_ofs_cur = AFE_UL2_CUR,
1159 .fs_reg = AFE_DAC_CON2,
1160 .fs_shift = 5,
1161 .fs_maskbit = 0x1f,
1162 .mono_reg = AFE_DAC_CON4,
1163 .mono_shift = 2,
1164 .enable_reg = AFE_DAC_CON0,
1165 .enable_shift = 11,
1166 .hd_reg = AFE_MEMIF_HD_CON1,
1167 .hd_shift = 2,
1168 .agent_disable_reg = AUDIO_TOP_CON5,
1169 .agent_disable_shift = 1,
1170 .msb_reg = -1,
1171 .msb_shift = -1,
1172 },
1173 {
1174 .name = "UL3",
1175 .id = MT2701_MEMIF_UL3,
1176 .reg_ofs_base = AFE_UL3_BASE,
1177 .reg_ofs_cur = AFE_UL3_CUR,
1178 .fs_reg = AFE_DAC_CON2,
1179 .fs_shift = 10,
1180 .fs_maskbit = 0x1f,
1181 .mono_reg = AFE_DAC_CON4,
1182 .mono_shift = 4,
1183 .enable_reg = AFE_DAC_CON0,
1184 .enable_shift = 12,
1185 .hd_reg = AFE_MEMIF_HD_CON0,
1186 .hd_shift = 0,
1187 .agent_disable_reg = AUDIO_TOP_CON5,
1188 .agent_disable_shift = 2,
1189 .msb_reg = -1,
1190 .msb_shift = -1,
1191 },
1192 {
1193 .name = "UL4",
1194 .id = MT2701_MEMIF_UL4,
1195 .reg_ofs_base = AFE_UL4_BASE,
1196 .reg_ofs_cur = AFE_UL4_CUR,
1197 .fs_reg = AFE_DAC_CON2,
1198 .fs_shift = 15,
1199 .fs_maskbit = 0x1f,
1200 .mono_reg = AFE_DAC_CON4,
1201 .mono_shift = 6,
1202 .enable_reg = AFE_DAC_CON0,
1203 .enable_shift = 13,
1204 .hd_reg = AFE_MEMIF_HD_CON0,
1205 .hd_shift = 6,
1206 .agent_disable_reg = AUDIO_TOP_CON5,
1207 .agent_disable_shift = 3,
1208 .msb_reg = -1,
1209 .msb_shift = -1,
1210 },
1211 {
1212 .name = "UL5",
1213 .id = MT2701_MEMIF_UL5,
1214 .reg_ofs_base = AFE_UL5_BASE,
1215 .reg_ofs_cur = AFE_UL5_CUR,
1216 .fs_reg = AFE_DAC_CON2,
1217 .fs_shift = 20,
1218 .mono_reg = AFE_DAC_CON4,
1219 .mono_shift = 8,
1220 .fs_maskbit = 0x1f,
1221 .enable_reg = AFE_DAC_CON0,
1222 .enable_shift = 14,
1223 .hd_reg = AFE_MEMIF_HD_CON0,
1224 .hd_shift = 8,
1225 .agent_disable_reg = AUDIO_TOP_CON5,
1226 .agent_disable_shift = 4,
1227 .msb_reg = -1,
1228 .msb_shift = -1,
1229 },
1230 {
1231 .name = "DLBT",
1232 .id = MT2701_MEMIF_DLBT,
1233 .reg_ofs_base = AFE_ARB1_BASE,
1234 .reg_ofs_cur = AFE_ARB1_CUR,
1235 .fs_reg = AFE_DAC_CON3,
1236 .fs_shift = 10,
1237 .fs_maskbit = 0x1f,
1238 .mono_reg = AFE_DAC_CON3,
1239 .mono_shift = 22,
1240 .enable_reg = AFE_DAC_CON0,
1241 .enable_shift = 8,
1242 .hd_reg = AFE_MEMIF_HD_CON0,
1243 .hd_shift = 14,
1244 .agent_disable_reg = AUDIO_TOP_CON5,
1245 .agent_disable_shift = 13,
1246 .msb_reg = -1,
1247 .msb_shift = -1,
1248 },
1249 {
1250 .name = "ULBT",
1251 .id = MT2701_MEMIF_ULBT,
1252 .reg_ofs_base = AFE_DAI_BASE,
1253 .reg_ofs_cur = AFE_DAI_CUR,
1254 .fs_reg = AFE_DAC_CON2,
1255 .fs_shift = 30,
1256 .fs_maskbit = 0x1,
1257 .mono_reg = -1,
1258 .mono_shift = -1,
1259 .enable_reg = AFE_DAC_CON0,
1260 .enable_shift = 17,
1261 .hd_reg = AFE_MEMIF_HD_CON1,
1262 .hd_shift = 20,
1263 .agent_disable_reg = AUDIO_TOP_CON5,
1264 .agent_disable_shift = 16,
1265 .msb_reg = -1,
1266 .msb_shift = -1,
1267 },
1268};
1269
1270static const struct mtk_base_irq_data irq_data[MT2701_IRQ_ASYS_END] = {
1271 {
1272 .id = MT2701_IRQ_ASYS_IRQ1,
1273 .irq_cnt_reg = ASYS_IRQ1_CON,
1274 .irq_cnt_shift = 0,
1275 .irq_cnt_maskbit = 0xffffff,
1276 .irq_fs_reg = ASYS_IRQ1_CON,
1277 .irq_fs_shift = 24,
1278 .irq_fs_maskbit = 0x1f,
1279 .irq_en_reg = ASYS_IRQ1_CON,
1280 .irq_en_shift = 31,
1281 .irq_clr_reg = ASYS_IRQ_CLR,
1282 .irq_clr_shift = 0,
1283 },
1284 {
1285 .id = MT2701_IRQ_ASYS_IRQ2,
1286 .irq_cnt_reg = ASYS_IRQ2_CON,
1287 .irq_cnt_shift = 0,
1288 .irq_cnt_maskbit = 0xffffff,
1289 .irq_fs_reg = ASYS_IRQ2_CON,
1290 .irq_fs_shift = 24,
1291 .irq_fs_maskbit = 0x1f,
1292 .irq_en_reg = ASYS_IRQ2_CON,
1293 .irq_en_shift = 31,
1294 .irq_clr_reg = ASYS_IRQ_CLR,
1295 .irq_clr_shift = 1,
1296 },
1297 {
1298 .id = MT2701_IRQ_ASYS_IRQ3,
1299 .irq_cnt_reg = ASYS_IRQ3_CON,
1300 .irq_cnt_shift = 0,
1301 .irq_cnt_maskbit = 0xffffff,
1302 .irq_fs_reg = ASYS_IRQ3_CON,
1303 .irq_fs_shift = 24,
1304 .irq_fs_maskbit = 0x1f,
1305 .irq_en_reg = ASYS_IRQ3_CON,
1306 .irq_en_shift = 31,
1307 .irq_clr_reg = ASYS_IRQ_CLR,
1308 .irq_clr_shift = 2,
1309 }
1310};
1311
1312static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
1313 {
1314 {
1315 .i2s_ctrl_reg = ASYS_I2SO1_CON,
43a6a7e7
GT		 1316 .i2s_asrc_fs_shift = 0,
1317 .i2s_asrc_fs_mask = 0x1f,
1318
1319 },
1320 {
1321 .i2s_ctrl_reg = ASYS_I2SIN1_CON,
43a6a7e7
GT		 1322 .i2s_asrc_fs_shift = 0,
1323 .i2s_asrc_fs_mask = 0x1f,
1324
1325 },
1326 },
1327 {
1328 {
1329 .i2s_ctrl_reg = ASYS_I2SO2_CON,
43a6a7e7
GT		 1330 .i2s_asrc_fs_shift = 5,
1331 .i2s_asrc_fs_mask = 0x1f,
1332
1333 },
1334 {
1335 .i2s_ctrl_reg = ASYS_I2SIN2_CON,
43a6a7e7
GT		 1336 .i2s_asrc_fs_shift = 5,
1337 .i2s_asrc_fs_mask = 0x1f,
1338
1339 },
1340 },
1341 {
1342 {
1343 .i2s_ctrl_reg = ASYS_I2SO3_CON,
43a6a7e7
GT		 1344 .i2s_asrc_fs_shift = 10,
1345 .i2s_asrc_fs_mask = 0x1f,
1346
1347 },
1348 {
1349 .i2s_ctrl_reg = ASYS_I2SIN3_CON,
43a6a7e7
GT		 1350 .i2s_asrc_fs_shift = 10,
1351 .i2s_asrc_fs_mask = 0x1f,
1352
1353 },
1354 },
1355 {
1356 {
1357 .i2s_ctrl_reg = ASYS_I2SO4_CON,
43a6a7e7
GT		 1358 .i2s_asrc_fs_shift = 15,
1359 .i2s_asrc_fs_mask = 0x1f,
1360
1361 },
1362 {
1363 .i2s_ctrl_reg = ASYS_I2SIN4_CON,
43a6a7e7
GT		 1364 .i2s_asrc_fs_shift = 15,
1365 .i2s_asrc_fs_mask = 0x1f,
1366
1367 },
1368 },
1369};
1370
1371static const struct regmap_config mt2701_afe_regmap_config = {
1372 .reg_bits = 32,
1373 .reg_stride = 4,
1374 .val_bits = 32,
1375 .max_register = AFE_END_ADDR,
1376 .cache_type = REGCACHE_NONE,
1377};
1378
1379static irqreturn_t mt2701_asys_isr(int irq_id, void *dev)
1380{
1381 int id;
1382 struct mtk_base_afe *afe = dev;
1383 struct mtk_base_afe_memif *memif;
1384 struct mtk_base_afe_irq *irq;
1385 u32 status;
1386
1387 regmap_read(afe->regmap, ASYS_IRQ_STATUS, &status);
1388 regmap_write(afe->regmap, ASYS_IRQ_CLR, status);
1389
1390 for (id = 0; id < MT2701_MEMIF_NUM; ++id) {
1391 memif = &afe->memif[id];
1392 if (memif->irq_usage < 0)
1393 continue;
1394 irq = &afe->irqs[memif->irq_usage];
1395 if (status & 1 << (irq->irq_data->irq_clr_shift))
1396 snd_pcm_period_elapsed(memif->substream);
1397 }
1398 return IRQ_HANDLED;
1399}
1400
1401static int mt2701_afe_runtime_suspend(struct device *dev)
1402{
1403 struct mtk_base_afe *afe = dev_get_drvdata(dev);
1404
d8d99d8e 1405 return mt2701_afe_disable_clock(afe);
43a6a7e7
GT		 1406}
1407
1408static int mt2701_afe_runtime_resume(struct device *dev)
1409{
1410 struct mtk_base_afe *afe = dev_get_drvdata(dev);
1411
1412 return mt2701_afe_enable_clock(afe);
1413}
1414
1415static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
1416{
43a6a7e7
GT		 1417 struct mtk_base_afe *afe;
1418 struct mt2701_afe_private *afe_priv;
1419 struct resource *res;
1420 struct device *dev;
f6c1626e 1421 int i, irq_id, ret;
43a6a7e7 1422
43a6a7e7 1423 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
b02c5cc7
DC		 1424 if (!afe)
1425 return -ENOMEM;
600b2fd4 1426
43a6a7e7
GT		 1427 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1428 GFP_KERNEL);
b02c5cc7 1429 if (!afe->platform_priv)
43a6a7e7
GT		 1430 return -ENOMEM;
1431
600b2fd4 1432 afe_priv = afe->platform_priv;
43a6a7e7
GT		 1433 afe->dev = &pdev->dev;
1434 dev = afe->dev;
1435
f6c1626e
RL		 1436 irq_id = platform_get_irq_byname(pdev, "asys");
1437 if (irq_id < 0) {
1438 dev_err(dev, "unable to get ASYS IRQ\n");
1439 return irq_id;
43a6a7e7 1440 }
f6c1626e 1441
43a6a7e7
GT		 1442 ret = devm_request_irq(dev, irq_id, mt2701_asys_isr,
1443 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
1444 if (ret) {
1445 dev_err(dev, "could not request_irq for asys-isr\n");
1446 return ret;
1447 }
1448
1449 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1450
1451 afe->base_addr = devm_ioremap_resource(&pdev->dev, res);
1452
1453 if (IS_ERR(afe->base_addr))
1454 return PTR_ERR(afe->base_addr);
1455
1456 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
1457 &mt2701_afe_regmap_config);
1458 if (IS_ERR(afe->regmap))
1459 return PTR_ERR(afe->regmap);
1460
1461 mutex_init(&afe->irq_alloc_lock);
1462
1463 /* memif initialize */
1464 afe->memif_size = MT2701_MEMIF_NUM;
1465 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
1466 GFP_KERNEL);
43a6a7e7
GT		 1467 if (!afe->memif)
1468 return -ENOMEM;
1469
1470 for (i = 0; i < afe->memif_size; i++) {
1471 afe->memif[i].data = &memif_data[i];
1472 afe->memif[i].irq_usage = -1;
1473 }
1474
1475 /* irq initialize */
1476 afe->irqs_size = MT2701_IRQ_ASYS_END;
1477 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
1478 GFP_KERNEL);
43a6a7e7
GT		 1479 if (!afe->irqs)
1480 return -ENOMEM;
1481
1482 for (i = 0; i < afe->irqs_size; i++)
1483 afe->irqs[i].irq_data = &irq_data[i];
1484
1485 /* I2S initialize */
1486 for (i = 0; i < MT2701_I2S_NUM; i++) {
1487 afe_priv->i2s_path[i].i2s_data[I2S_OUT]
1488 = &mt2701_i2s_data[i][I2S_OUT];
1489 afe_priv->i2s_path[i].i2s_data[I2S_IN]
1490 = &mt2701_i2s_data[i][I2S_IN];
1491 }
1492
1493 afe->mtk_afe_hardware = &mt2701_afe_hardware;
1494 afe->memif_fs = mt2701_memif_fs;
1495 afe->irq_fs = mt2701_irq_fs;
43a6a7e7
GT		 1496 afe->reg_back_up_list = mt2701_afe_backup_list;
1497 afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list);
1498 afe->runtime_resume = mt2701_afe_runtime_resume;
1499 afe->runtime_suspend = mt2701_afe_runtime_suspend;
1500
1501 /* initial audio related clock */
1502 ret = mt2701_init_clock(afe);
1503 if (ret) {
1504 dev_err(dev, "init clock error\n");
1505 return ret;
1506 }
1507
1508 platform_set_drvdata(pdev, afe);
43a6a7e7 1509
dd6bb9b1
RL		 1510 pm_runtime_enable(dev);
1511 if (!pm_runtime_enabled(dev)) {
1512 ret = mt2701_afe_runtime_resume(dev);
1513 if (ret)
1514 goto err_pm_disable;
1515 }
1516 pm_runtime_get_sync(dev);
1517
1518 ret = snd_soc_register_platform(dev, &mtk_afe_pcm_platform);
43a6a7e7
GT		 1519 if (ret) {
1520 dev_warn(dev, "err_platform\n");
1521 goto err_platform;
1522 }
1523
1524 ret = snd_soc_register_component(&pdev->dev,
1525 &mt2701_afe_pcm_dai_component,
1526 mt2701_afe_pcm_dais,
1527 ARRAY_SIZE(mt2701_afe_pcm_dais));
1528 if (ret) {
1529 dev_warn(dev, "err_dai_component\n");
1530 goto err_dai_component;
1531 }
1532
43a6a7e7
GT		 1533 return 0;
1534
1535err_dai_component:
dd6bb9b1 1536 snd_soc_unregister_platform(dev);
43a6a7e7 1537err_platform:
dd6bb9b1 1538 pm_runtime_put_sync(dev);
43a6a7e7 1539err_pm_disable:
dd6bb9b1 1540 pm_runtime_disable(dev);
43a6a7e7
GT		 1541
1542 return ret;
1543}
1544
1545static int mt2701_afe_pcm_dev_remove(struct platform_device *pdev)
1546{
dd6bb9b1 1547 pm_runtime_put_sync(&pdev->dev);
43a6a7e7
GT		 1548 pm_runtime_disable(&pdev->dev);
1549 if (!pm_runtime_status_suspended(&pdev->dev))
1550 mt2701_afe_runtime_suspend(&pdev->dev);
1551
1552 snd_soc_unregister_component(&pdev->dev);
1553 snd_soc_unregister_platform(&pdev->dev);
dd6bb9b1 1554
43a6a7e7
GT		 1555 return 0;
1556}
1557
1558static const struct of_device_id mt2701_afe_pcm_dt_match[] = {
1559 { .compatible = "mediatek,mt2701-audio", },
1560 {},
1561};
1562MODULE_DEVICE_TABLE(of, mt2701_afe_pcm_dt_match);
1563
1564static const struct dev_pm_ops mt2701_afe_pm_ops = {
1565 SET_RUNTIME_PM_OPS(mt2701_afe_runtime_suspend,
1566 mt2701_afe_runtime_resume, NULL)
1567};
1568
1569static struct platform_driver mt2701_afe_pcm_driver = {
1570 .driver = {
1571 .name = "mt2701-audio",
1572 .of_match_table = mt2701_afe_pcm_dt_match,
1573#ifdef CONFIG_PM
1574 .pm = &mt2701_afe_pm_ops,
1575#endif
1576 },
1577 .probe = mt2701_afe_pcm_dev_probe,
1578 .remove = mt2701_afe_pcm_dev_remove,
1579};
1580
1581module_platform_driver(mt2701_afe_pcm_driver);
1582
1583MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701");
1584MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
1585MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)