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Merge remote-tracking branch 'asoc/topic/pcm5102a' into asoc-next
[linux-2.6-block.git] / sound / soc / mediatek / mt2701 / mt2701-afe-pcm.c
CommitLineData
43a6a7e7
GT		 1/*
2 * Mediatek ALSA SoC AFE platform driver for 2701
3 *
4 * Copyright (c) 2016 MediaTek Inc.
5 * Author: Garlic Tseng <garlic.tseng@mediatek.com>
6 * Ir Lian <ir.lian@mediatek.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 and
10 * only version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/delay.h>
19#include <linux/module.h>
dfa3cbb8 20#include <linux/mfd/syscon.h>
43a6a7e7
GT		 21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/pm_runtime.h>
43a6a7e7
GT		 24
25#include "mt2701-afe-common.h"
43a6a7e7
GT		 26#include "mt2701-afe-clock-ctrl.h"
27#include "../common/mtk-afe-platform-driver.h"
28#include "../common/mtk-afe-fe-dai.h"
29
43a6a7e7
GT		 30static const struct snd_pcm_hardware mt2701_afe_hardware = {
31 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED
32 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID,
33 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE
34 | SNDRV_PCM_FMTBIT_S32_LE,
35 .period_bytes_min = 1024,
36 .period_bytes_max = 1024 * 256,
37 .periods_min = 4,
38 .periods_max = 1024,
39 .buffer_bytes_max = 1024 * 1024 * 16,
40 .fifo_size = 0,
41};
42
43struct mt2701_afe_rate {
44 unsigned int rate;
45 unsigned int regvalue;
46};
47
48static const struct mt2701_afe_rate mt2701_afe_i2s_rates[] = {
49 { .rate = 8000, .regvalue = 0 },
50 { .rate = 12000, .regvalue = 1 },
51 { .rate = 16000, .regvalue = 2 },
52 { .rate = 24000, .regvalue = 3 },
53 { .rate = 32000, .regvalue = 4 },
54 { .rate = 48000, .regvalue = 5 },
55 { .rate = 96000, .regvalue = 6 },
56 { .rate = 192000, .regvalue = 7 },
57 { .rate = 384000, .regvalue = 8 },
58 { .rate = 7350, .regvalue = 16 },
59 { .rate = 11025, .regvalue = 17 },
60 { .rate = 14700, .regvalue = 18 },
61 { .rate = 22050, .regvalue = 19 },
62 { .rate = 29400, .regvalue = 20 },
63 { .rate = 44100, .regvalue = 21 },
64 { .rate = 88200, .regvalue = 22 },
65 { .rate = 176400, .regvalue = 23 },
66 { .rate = 352800, .regvalue = 24 },
67};
68
25d01dc6 69static int mt2701_dai_num_to_i2s(struct mtk_base_afe *afe, int num)
43a6a7e7
GT		 70{
71 int val = num - MT2701_IO_I2S;
72
73 if (val < 0 || val >= MT2701_I2S_NUM) {
74 dev_err(afe->dev, "%s, num not available, num %d, val %d\n",
75 __func__, num, val);
76 return -EINVAL;
77 }
78 return val;
79}
80
81static int mt2701_afe_i2s_fs(unsigned int sample_rate)
82{
83 int i;
84
85 for (i = 0; i < ARRAY_SIZE(mt2701_afe_i2s_rates); i++)
86 if (mt2701_afe_i2s_rates[i].rate == sample_rate)
87 return mt2701_afe_i2s_rates[i].regvalue;
88
89 return -EINVAL;
90}
91
92static int mt2701_afe_i2s_startup(struct snd_pcm_substream *substream,
93 struct snd_soc_dai *dai)
94{
95 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f1b5bf07
KM		 96 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
97 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
43a6a7e7 98 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
43a6a7e7
GT		 99
100 if (i2s_num < 0)
101 return i2s_num;
102
d8d99d8e 103 return mt2701_afe_enable_mclk(afe, i2s_num);
43a6a7e7
GT		 104}
105
106static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream,
107 struct snd_soc_dai *dai,
600b2fd4 108 int i2s_num,
43a6a7e7
GT		 109 int dir_invert)
110{
111 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f1b5bf07
KM		 112 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
113 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
43a6a7e7 114 struct mt2701_afe_private *afe_priv = afe->platform_priv;
600b2fd4 115 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
43a6a7e7
GT		 116 const struct mt2701_i2s_data *i2s_data;
117 int stream_dir = substream->stream;
118
43a6a7e7
GT		 119 if (dir_invert) {
120 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
121 stream_dir = SNDRV_PCM_STREAM_CAPTURE;
122 else
123 stream_dir = SNDRV_PCM_STREAM_PLAYBACK;
124 }
125 i2s_data = i2s_path->i2s_data[stream_dir];
126
127 i2s_path->on[stream_dir]--;
128 if (i2s_path->on[stream_dir] < 0) {
129 dev_warn(afe->dev, "i2s_path->on: %d, dir: %d\n",
130 i2s_path->on[stream_dir], stream_dir);
131 i2s_path->on[stream_dir] = 0;
132 }
133 if (i2s_path->on[stream_dir])
134 return 0;
135
136 /* disable i2s */
137 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
138 ASYS_I2S_CON_I2S_EN, 0);
d8d99d8e
RL		 139
140 mt2701_afe_disable_i2s(afe, i2s_num, stream_dir);
141
43a6a7e7
GT		 142 return 0;
143}
144
145static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
146 struct snd_soc_dai *dai)
147{
148 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f1b5bf07
KM		 149 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
150 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
43a6a7e7
GT		 151 struct mt2701_afe_private *afe_priv = afe->platform_priv;
152 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
153 struct mt2701_i2s_path *i2s_path;
43a6a7e7
GT		 154
155 if (i2s_num < 0)
156 return;
157
158 i2s_path = &afe_priv->i2s_path[i2s_num];
159
160 if (i2s_path->occupied[substream->stream])
161 i2s_path->occupied[substream->stream] = 0;
162 else
163 goto I2S_UNSTART;
164
600b2fd4 165 mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 0);
43a6a7e7
GT		 166
167 /* need to disable i2s-out path when disable i2s-in */
168 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
600b2fd4 169 mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 1);
43a6a7e7
GT		 170
171I2S_UNSTART:
172 /* disable mclk */
d8d99d8e 173 mt2701_afe_disable_mclk(afe, i2s_num);
43a6a7e7
GT		 174}
175
176static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream,
177 struct snd_soc_dai *dai,
600b2fd4 178 int i2s_num,
43a6a7e7
GT		 179 int dir_invert)
180{
181 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f1b5bf07
KM		 182 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
183 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
43a6a7e7 184 struct mt2701_afe_private *afe_priv = afe->platform_priv;
600b2fd4 185 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
43a6a7e7
GT		 186 const struct mt2701_i2s_data *i2s_data;
187 struct snd_pcm_runtime * const runtime = substream->runtime;
188 int reg, fs, w_len = 1; /* now we support bck 64bits only */
189 int stream_dir = substream->stream;
190 unsigned int mask = 0, val = 0;
191
43a6a7e7
GT		 192 if (dir_invert) {
193 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
194 stream_dir = SNDRV_PCM_STREAM_CAPTURE;
195 else
196 stream_dir = SNDRV_PCM_STREAM_PLAYBACK;
197 }
198 i2s_data = i2s_path->i2s_data[stream_dir];
199
200 /* no need to enable if already done */
201 i2s_path->on[stream_dir]++;
202
203 if (i2s_path->on[stream_dir] != 1)
204 return 0;
205
206 fs = mt2701_afe_i2s_fs(runtime->rate);
207
208 mask = ASYS_I2S_CON_FS |
209 ASYS_I2S_CON_I2S_COUPLE_MODE | /* 0 */
210 ASYS_I2S_CON_I2S_MODE |
211 ASYS_I2S_CON_WIDE_MODE;
212
213 val = ASYS_I2S_CON_FS_SET(fs) |
214 ASYS_I2S_CON_I2S_MODE |
215 ASYS_I2S_CON_WIDE_MODE_SET(w_len);
216
217 if (stream_dir == SNDRV_PCM_STREAM_CAPTURE) {
218 mask |= ASYS_I2S_IN_PHASE_FIX;
219 val |= ASYS_I2S_IN_PHASE_FIX;
220 }
221
222 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, mask, val);
223
224 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
225 reg = ASMO_TIMING_CON1;
226 else
227 reg = ASMI_TIMING_CON1;
228
229 regmap_update_bits(afe->regmap, reg,
230 i2s_data->i2s_asrc_fs_mask
231 << i2s_data->i2s_asrc_fs_shift,
232 fs << i2s_data->i2s_asrc_fs_shift);
233
234 /* enable i2s */
d8d99d8e 235 mt2701_afe_enable_i2s(afe, i2s_num, stream_dir);
43a6a7e7
GT		 236
237 /* reset i2s hw status before enable */
238 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
239 ASYS_I2S_CON_RESET, ASYS_I2S_CON_RESET);
240 udelay(1);
241 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
242 ASYS_I2S_CON_RESET, 0);
243 udelay(1);
244 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
245 ASYS_I2S_CON_I2S_EN, ASYS_I2S_CON_I2S_EN);
246 return 0;
247}
248
249static int mt2701_afe_i2s_prepare(struct snd_pcm_substream *substream,
250 struct snd_soc_dai *dai)
251{
252 int clk_domain;
253 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f1b5bf07
KM		 254 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
255 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
43a6a7e7
GT		 256 struct mt2701_afe_private *afe_priv = afe->platform_priv;
257 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
258 struct mt2701_i2s_path *i2s_path;
259 int mclk_rate;
260
261 if (i2s_num < 0)
262 return i2s_num;
263
264 i2s_path = &afe_priv->i2s_path[i2s_num];
265 mclk_rate = i2s_path->mclk_rate;
266
267 if (i2s_path->occupied[substream->stream])
268 return -EBUSY;
269 i2s_path->occupied[substream->stream] = 1;
270
271 if (MT2701_PLL_DOMAIN_0_RATE % mclk_rate == 0) {
272 clk_domain = 0;
273 } else if (MT2701_PLL_DOMAIN_1_RATE % mclk_rate == 0) {
274 clk_domain = 1;
275 } else {
276 dev_err(dai->dev, "%s() bad mclk rate %d\n",
277 __func__, mclk_rate);
278 return -EINVAL;
279 }
280 mt2701_mclk_configuration(afe, i2s_num, clk_domain, mclk_rate);
281
282 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
600b2fd4 283 mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
43a6a7e7
GT		 284 } else {
285 /* need to enable i2s-out path when enable i2s-in */
286 /* prepare for another direction "out" */
600b2fd4 287 mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 1);
43a6a7e7 288 /* prepare for "in" */
600b2fd4 289 mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
43a6a7e7
GT		 290 }
291
292 return 0;
293}
294
295static int mt2701_afe_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
296 unsigned int freq, int dir)
297{
298 struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
299 struct mt2701_afe_private *afe_priv = afe->platform_priv;
300 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
301
302 if (i2s_num < 0)
303 return i2s_num;
304
305 /* mclk */
306 if (dir == SND_SOC_CLOCK_IN) {
307 dev_warn(dai->dev,
308 "%s() warning: mt2701 doesn't support mclk input\n",
309 __func__);
310 return -EINVAL;
311 }
312 afe_priv->i2s_path[i2s_num].mclk_rate = freq;
313 return 0;
314}
315
4bdc8d45
GT		 316static int mt2701_btmrg_startup(struct snd_pcm_substream *substream,
317 struct snd_soc_dai *dai)
318{
319 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f1b5bf07
KM		 320 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
321 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
4bdc8d45 322 struct mt2701_afe_private *afe_priv = afe->platform_priv;
d8d99d8e 323 int ret;
4bdc8d45 324
d8d99d8e
RL		 325 ret = mt2701_enable_btmrg_clk(afe);
326 if (ret)
327 return ret;
4bdc8d45
GT		 328
329 afe_priv->mrg_enable[substream->stream] = 1;
330 return 0;
331}
332
333static int mt2701_btmrg_hw_params(struct snd_pcm_substream *substream,
334 struct snd_pcm_hw_params *params,
335 struct snd_soc_dai *dai)
336{
337 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f1b5bf07
KM		 338 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
339 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
4bdc8d45
GT		 340 int stream_fs;
341 u32 val, msk;
342
343 stream_fs = params_rate(params);
344
345 if ((stream_fs != 8000) && (stream_fs != 16000)) {
346 dev_err(afe->dev, "%s() btmgr not supprt this stream_fs %d\n",
347 __func__, stream_fs);
348 return -EINVAL;
349 }
350
351 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
352 AFE_MRGIF_CON_I2S_MODE_MASK,
353 AFE_MRGIF_CON_I2S_MODE_32K);
354
355 val = AFE_DAIBT_CON0_BT_FUNC_EN | AFE_DAIBT_CON0_BT_FUNC_RDY
356 | AFE_DAIBT_CON0_MRG_USE;
357 msk = val;
358
359 if (stream_fs == 16000)
360 val |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
361
362 msk |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
363
364 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0, msk, val);
365
366 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
367 AFE_DAIBT_CON0_DAIBT_EN,
368 AFE_DAIBT_CON0_DAIBT_EN);
369 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
370 AFE_MRGIF_CON_MRG_I2S_EN,
371 AFE_MRGIF_CON_MRG_I2S_EN);
372 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
373 AFE_MRGIF_CON_MRG_EN,
374 AFE_MRGIF_CON_MRG_EN);
375 return 0;
376}
377
378static void mt2701_btmrg_shutdown(struct snd_pcm_substream *substream,
379 struct snd_soc_dai *dai)
380{
381 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f1b5bf07
KM		 382 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
383 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
4bdc8d45
GT		 384 struct mt2701_afe_private *afe_priv = afe->platform_priv;
385
386 /* if the other direction stream is not occupied */
387 if (!afe_priv->mrg_enable[!substream->stream]) {
388 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
389 AFE_DAIBT_CON0_DAIBT_EN, 0);
390 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
391 AFE_MRGIF_CON_MRG_EN, 0);
392 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
393 AFE_MRGIF_CON_MRG_I2S_EN, 0);
d8d99d8e 394 mt2701_disable_btmrg_clk(afe);
4bdc8d45
GT		 395 }
396 afe_priv->mrg_enable[substream->stream] = 0;
397}
398
43a6a7e7
GT		 399static int mt2701_simple_fe_startup(struct snd_pcm_substream *substream,
400 struct snd_soc_dai *dai)
401{
402 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f1b5bf07
KM		 403 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
404 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
43a6a7e7
GT		 405 int stream_dir = substream->stream;
406 int memif_num = rtd->cpu_dai->id;
407 struct mtk_base_afe_memif *memif_tmp;
408
409 /* can't run single DL & DLM at the same time */
410 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) {
411 memif_tmp = &afe->memif[MT2701_MEMIF_DLM];
412 if (memif_tmp->substream) {
413 dev_warn(afe->dev, "%s memif is not available, stream_dir %d, memif_num %d\n",
414 __func__, stream_dir, memif_num);
415 return -EBUSY;
416 }
417 }
418 return mtk_afe_fe_startup(substream, dai);
419}
420
421static int mt2701_simple_fe_hw_params(struct snd_pcm_substream *substream,
422 struct snd_pcm_hw_params *params,
423 struct snd_soc_dai *dai)
424{
425 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f1b5bf07
KM		 426 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
427 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
43a6a7e7
GT		 428 int stream_dir = substream->stream;
429
430 /* single DL use PAIR_INTERLEAVE */
431 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) {
432 regmap_update_bits(afe->regmap,
433 AFE_MEMIF_PBUF_SIZE,
434 AFE_MEMIF_PBUF_SIZE_DLM_MASK,
435 AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE);
436 }
437 return mtk_afe_fe_hw_params(substream, params, dai);
438}
439
440static int mt2701_dlm_fe_startup(struct snd_pcm_substream *substream,
441 struct snd_soc_dai *dai)
442{
443 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f1b5bf07
KM		 444 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
445 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
43a6a7e7
GT		 446 struct mtk_base_afe_memif *memif_tmp;
447 const struct mtk_base_memif_data *memif_data;
448 int i;
449
450 for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
451 memif_tmp = &afe->memif[i];
452 if (memif_tmp->substream)
453 return -EBUSY;
454 }
455
456 /* enable agent for all signal DL (due to hw design) */
457 for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
458 memif_data = afe->memif[i].data;
459 regmap_update_bits(afe->regmap,
460 memif_data->agent_disable_reg,
461 1 << memif_data->agent_disable_shift,
462 0 << memif_data->agent_disable_shift);
463 }
464
465 return mtk_afe_fe_startup(substream, dai);
466}
467
468static void mt2701_dlm_fe_shutdown(struct snd_pcm_substream *substream,
469 struct snd_soc_dai *dai)
470{
471 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f1b5bf07
KM		 472 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
473 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
43a6a7e7
GT		 474 const struct mtk_base_memif_data *memif_data;
475 int i;
476
477 for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
478 memif_data = afe->memif[i].data;
479 regmap_update_bits(afe->regmap,
480 memif_data->agent_disable_reg,
481 1 << memif_data->agent_disable_shift,
482 1 << memif_data->agent_disable_shift);
483 }
484 return mtk_afe_fe_shutdown(substream, dai);
485}
486
487static int mt2701_dlm_fe_hw_params(struct snd_pcm_substream *substream,
488 struct snd_pcm_hw_params *params,
489 struct snd_soc_dai *dai)
490{
491 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f1b5bf07
KM		 492 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
493 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
43a6a7e7
GT		 494 int channels = params_channels(params);
495
496 regmap_update_bits(afe->regmap,
497 AFE_MEMIF_PBUF_SIZE,
498 AFE_MEMIF_PBUF_SIZE_DLM_MASK,
499 AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE);
500 regmap_update_bits(afe->regmap,
501 AFE_MEMIF_PBUF_SIZE,
502 AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK,
503 AFE_MEMIF_PBUF_SIZE_DLM_32BYTES);
504 regmap_update_bits(afe->regmap,
505 AFE_MEMIF_PBUF_SIZE,
506 AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK,
507 AFE_MEMIF_PBUF_SIZE_DLM_CH(channels));
508
509 return mtk_afe_fe_hw_params(substream, params, dai);
510}
511
512static int mt2701_dlm_fe_trigger(struct snd_pcm_substream *substream,
513 int cmd, struct snd_soc_dai *dai)
514{
515 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f1b5bf07
KM		 516 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
517 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
43a6a7e7
GT		 518 struct mtk_base_afe_memif *memif_tmp = &afe->memif[MT2701_MEMIF_DL1];
519
520 switch (cmd) {
521 case SNDRV_PCM_TRIGGER_START:
522 case SNDRV_PCM_TRIGGER_RESUME:
523 regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
524 1 << memif_tmp->data->enable_shift,
525 1 << memif_tmp->data->enable_shift);
526 mtk_afe_fe_trigger(substream, cmd, dai);
527 return 0;
528 case SNDRV_PCM_TRIGGER_STOP:
529 case SNDRV_PCM_TRIGGER_SUSPEND:
530 mtk_afe_fe_trigger(substream, cmd, dai);
531 regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
532 1 << memif_tmp->data->enable_shift, 0);
533
534 return 0;
535 default:
536 return -EINVAL;
537 }
538}
539
540static int mt2701_memif_fs(struct snd_pcm_substream *substream,
541 unsigned int rate)
542{
543 struct snd_soc_pcm_runtime *rtd = substream->private_data;
544 int fs;
545
546 if (rtd->cpu_dai->id != MT2701_MEMIF_ULBT)
547 fs = mt2701_afe_i2s_fs(rate);
548 else
549 fs = (rate == 16000 ? 1 : 0);
550 return fs;
551}
552
553static int mt2701_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
554{
555 return mt2701_afe_i2s_fs(rate);
556}
557
558/* FE DAIs */
559static const struct snd_soc_dai_ops mt2701_single_memif_dai_ops = {
560 .startup = mt2701_simple_fe_startup,
561 .shutdown = mtk_afe_fe_shutdown,
562 .hw_params = mt2701_simple_fe_hw_params,
563 .hw_free = mtk_afe_fe_hw_free,
564 .prepare = mtk_afe_fe_prepare,
565 .trigger = mtk_afe_fe_trigger,
43a6a7e7
GT		 566};
567
568static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = {
569 .startup = mt2701_dlm_fe_startup,
570 .shutdown = mt2701_dlm_fe_shutdown,
571 .hw_params = mt2701_dlm_fe_hw_params,
572 .hw_free = mtk_afe_fe_hw_free,
573 .prepare = mtk_afe_fe_prepare,
574 .trigger = mt2701_dlm_fe_trigger,
575};
576
577/* I2S BE DAIs */
578static const struct snd_soc_dai_ops mt2701_afe_i2s_ops = {
579 .startup = mt2701_afe_i2s_startup,
580 .shutdown = mt2701_afe_i2s_shutdown,
581 .prepare = mt2701_afe_i2s_prepare,
582 .set_sysclk = mt2701_afe_i2s_set_sysclk,
583};
584
4bdc8d45 585/* MRG BE DAIs */
549acff9 586static const struct snd_soc_dai_ops mt2701_btmrg_ops = {
4bdc8d45
GT		 587 .startup = mt2701_btmrg_startup,
588 .shutdown = mt2701_btmrg_shutdown,
589 .hw_params = mt2701_btmrg_hw_params,
590};
591
43a6a7e7
GT		 592static struct snd_soc_dai_driver mt2701_afe_pcm_dais[] = {
593 /* FE DAIs: memory intefaces to CPU */
8625c1db
RL		 594 {
595 .name = "PCMO0",
596 .id = MT2701_MEMIF_DL1,
597 .suspend = mtk_afe_dai_suspend,
598 .resume = mtk_afe_dai_resume,
599 .playback = {
600 .stream_name = "DL1",
601 .channels_min = 1,
602 .channels_max = 2,
603 .rates = SNDRV_PCM_RATE_8000_192000,
604 .formats = (SNDRV_PCM_FMTBIT_S16_LE
605 | SNDRV_PCM_FMTBIT_S24_LE
606 | SNDRV_PCM_FMTBIT_S32_LE)
607 },
608 .ops = &mt2701_single_memif_dai_ops,
609 },
43a6a7e7
GT		 610 {
611 .name = "PCM_multi",
612 .id = MT2701_MEMIF_DLM,
613 .suspend = mtk_afe_dai_suspend,
614 .resume = mtk_afe_dai_resume,
615 .playback = {
616 .stream_name = "DLM",
617 .channels_min = 1,
618 .channels_max = 8,
619 .rates = SNDRV_PCM_RATE_8000_192000,
620 .formats = (SNDRV_PCM_FMTBIT_S16_LE
621 | SNDRV_PCM_FMTBIT_S24_LE
622 | SNDRV_PCM_FMTBIT_S32_LE)
623
624 },
625 .ops = &mt2701_dlm_memif_dai_ops,
626 },
627 {
628 .name = "PCM0",
629 .id = MT2701_MEMIF_UL1,
630 .suspend = mtk_afe_dai_suspend,
631 .resume = mtk_afe_dai_resume,
632 .capture = {
633 .stream_name = "UL1",
634 .channels_min = 1,
635 .channels_max = 2,
636 .rates = SNDRV_PCM_RATE_8000_48000,
637 .formats = (SNDRV_PCM_FMTBIT_S16_LE
638 | SNDRV_PCM_FMTBIT_S24_LE
639 | SNDRV_PCM_FMTBIT_S32_LE)
640 },
641 .ops = &mt2701_single_memif_dai_ops,
642 },
643 {
644 .name = "PCM1",
645 .id = MT2701_MEMIF_UL2,
646 .suspend = mtk_afe_dai_suspend,
647 .resume = mtk_afe_dai_resume,
648 .capture = {
649 .stream_name = "UL2",
650 .channels_min = 1,
651 .channels_max = 2,
652 .rates = SNDRV_PCM_RATE_8000_192000,
653 .formats = (SNDRV_PCM_FMTBIT_S16_LE
654 | SNDRV_PCM_FMTBIT_S24_LE
655 | SNDRV_PCM_FMTBIT_S32_LE)
656
657 },
658 .ops = &mt2701_single_memif_dai_ops,
659 },
4bdc8d45
GT		 660 {
661 .name = "PCM_BT_DL",
662 .id = MT2701_MEMIF_DLBT,
663 .suspend = mtk_afe_dai_suspend,
664 .resume = mtk_afe_dai_resume,
665 .playback = {
666 .stream_name = "DLBT",
667 .channels_min = 1,
668 .channels_max = 1,
669 .rates = (SNDRV_PCM_RATE_8000
670 | SNDRV_PCM_RATE_16000),
671 .formats = SNDRV_PCM_FMTBIT_S16_LE,
672 },
673 .ops = &mt2701_single_memif_dai_ops,
674 },
675 {
676 .name = "PCM_BT_UL",
677 .id = MT2701_MEMIF_ULBT,
678 .suspend = mtk_afe_dai_suspend,
679 .resume = mtk_afe_dai_resume,
680 .capture = {
681 .stream_name = "ULBT",
682 .channels_min = 1,
683 .channels_max = 1,
684 .rates = (SNDRV_PCM_RATE_8000
685 | SNDRV_PCM_RATE_16000),
686 .formats = SNDRV_PCM_FMTBIT_S16_LE,
687 },
688 .ops = &mt2701_single_memif_dai_ops,
689 },
43a6a7e7
GT		 690 /* BE DAIs */
691 {
692 .name = "I2S0",
693 .id = MT2701_IO_I2S,
694 .playback = {
695 .stream_name = "I2S0 Playback",
696 .channels_min = 1,
697 .channels_max = 2,
698 .rates = SNDRV_PCM_RATE_8000_192000,
699 .formats = (SNDRV_PCM_FMTBIT_S16_LE
700 | SNDRV_PCM_FMTBIT_S24_LE
701 | SNDRV_PCM_FMTBIT_S32_LE)
702
703 },
704 .capture = {
705 .stream_name = "I2S0 Capture",
706 .channels_min = 1,
707 .channels_max = 2,
708 .rates = SNDRV_PCM_RATE_8000_192000,
709 .formats = (SNDRV_PCM_FMTBIT_S16_LE
710 | SNDRV_PCM_FMTBIT_S24_LE
711 | SNDRV_PCM_FMTBIT_S32_LE)
712
713 },
714 .ops = &mt2701_afe_i2s_ops,
715 .symmetric_rates = 1,
716 },
717 {
718 .name = "I2S1",
719 .id = MT2701_IO_2ND_I2S,
720 .playback = {
721 .stream_name = "I2S1 Playback",
722 .channels_min = 1,
723 .channels_max = 2,
724 .rates = SNDRV_PCM_RATE_8000_192000,
725 .formats = (SNDRV_PCM_FMTBIT_S16_LE
726 | SNDRV_PCM_FMTBIT_S24_LE
727 | SNDRV_PCM_FMTBIT_S32_LE)
728 },
729 .capture = {
730 .stream_name = "I2S1 Capture",
731 .channels_min = 1,
732 .channels_max = 2,
733 .rates = SNDRV_PCM_RATE_8000_192000,
734 .formats = (SNDRV_PCM_FMTBIT_S16_LE
735 | SNDRV_PCM_FMTBIT_S24_LE
736 | SNDRV_PCM_FMTBIT_S32_LE)
737 },
738 .ops = &mt2701_afe_i2s_ops,
739 .symmetric_rates = 1,
740 },
741 {
742 .name = "I2S2",
743 .id = MT2701_IO_3RD_I2S,
744 .playback = {
745 .stream_name = "I2S2 Playback",
746 .channels_min = 1,
747 .channels_max = 2,
748 .rates = SNDRV_PCM_RATE_8000_192000,
749 .formats = (SNDRV_PCM_FMTBIT_S16_LE
750 | SNDRV_PCM_FMTBIT_S24_LE
751 | SNDRV_PCM_FMTBIT_S32_LE)
752 },
753 .capture = {
754 .stream_name = "I2S2 Capture",
755 .channels_min = 1,
756 .channels_max = 2,
757 .rates = SNDRV_PCM_RATE_8000_192000,
758 .formats = (SNDRV_PCM_FMTBIT_S16_LE
759 | SNDRV_PCM_FMTBIT_S24_LE
760 | SNDRV_PCM_FMTBIT_S32_LE)
761 },
762 .ops = &mt2701_afe_i2s_ops,
763 .symmetric_rates = 1,
764 },
765 {
766 .name = "I2S3",
767 .id = MT2701_IO_4TH_I2S,
768 .playback = {
769 .stream_name = "I2S3 Playback",
770 .channels_min = 1,
771 .channels_max = 2,
772 .rates = SNDRV_PCM_RATE_8000_192000,
773 .formats = (SNDRV_PCM_FMTBIT_S16_LE
774 | SNDRV_PCM_FMTBIT_S24_LE
775 | SNDRV_PCM_FMTBIT_S32_LE)
776 },
777 .capture = {
778 .stream_name = "I2S3 Capture",
779 .channels_min = 1,
780 .channels_max = 2,
781 .rates = SNDRV_PCM_RATE_8000_192000,
782 .formats = (SNDRV_PCM_FMTBIT_S16_LE
783 | SNDRV_PCM_FMTBIT_S24_LE
784 | SNDRV_PCM_FMTBIT_S32_LE)
785 },
786 .ops = &mt2701_afe_i2s_ops,
787 .symmetric_rates = 1,
788 },
4bdc8d45
GT		 789 {
790 .name = "MRG BT",
791 .id = MT2701_IO_MRG,
792 .playback = {
793 .stream_name = "BT Playback",
794 .channels_min = 1,
795 .channels_max = 1,
796 .rates = (SNDRV_PCM_RATE_8000
797 | SNDRV_PCM_RATE_16000),
798 .formats = SNDRV_PCM_FMTBIT_S16_LE,
799 },
800 .capture = {
801 .stream_name = "BT Capture",
802 .channels_min = 1,
803 .channels_max = 1,
804 .rates = (SNDRV_PCM_RATE_8000
805 | SNDRV_PCM_RATE_16000),
806 .formats = SNDRV_PCM_FMTBIT_S16_LE,
807 },
808 .ops = &mt2701_btmrg_ops,
809 .symmetric_rates = 1,
810 }
43a6a7e7
GT		 811};
812
813static const struct snd_kcontrol_new mt2701_afe_o00_mix[] = {
814 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN0, 0, 1, 0),
815};
816
817static const struct snd_kcontrol_new mt2701_afe_o01_mix[] = {
818 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN1, 1, 1, 0),
819};
820
821static const struct snd_kcontrol_new mt2701_afe_o02_mix[] = {
822 SOC_DAPM_SINGLE_AUTODISABLE("I02 Switch", AFE_CONN2, 2, 1, 0),
823};
824
825static const struct snd_kcontrol_new mt2701_afe_o03_mix[] = {
826 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 3, 1, 0),
827};
828
829static const struct snd_kcontrol_new mt2701_afe_o14_mix[] = {
830 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN14, 26, 1, 0),
831};
832
833static const struct snd_kcontrol_new mt2701_afe_o15_mix[] = {
834 SOC_DAPM_SINGLE_AUTODISABLE("I12 Switch", AFE_CONN15, 12, 1, 0),
835};
836
837static const struct snd_kcontrol_new mt2701_afe_o16_mix[] = {
838 SOC_DAPM_SINGLE_AUTODISABLE("I13 Switch", AFE_CONN16, 13, 1, 0),
839};
840
841static const struct snd_kcontrol_new mt2701_afe_o17_mix[] = {
842 SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN17, 14, 1, 0),
843};
844
845static const struct snd_kcontrol_new mt2701_afe_o18_mix[] = {
846 SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN18, 15, 1, 0),
847};
848
849static const struct snd_kcontrol_new mt2701_afe_o19_mix[] = {
850 SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN19, 16, 1, 0),
851};
852
853static const struct snd_kcontrol_new mt2701_afe_o20_mix[] = {
854 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN20, 17, 1, 0),
855};
856
857static const struct snd_kcontrol_new mt2701_afe_o21_mix[] = {
858 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN21, 18, 1, 0),
859};
860
861static const struct snd_kcontrol_new mt2701_afe_o22_mix[] = {
862 SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN22, 19, 1, 0),
863};
864
865static const struct snd_kcontrol_new mt2701_afe_o23_mix[] = {
866 SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN23, 20, 1, 0),
867};
868
869static const struct snd_kcontrol_new mt2701_afe_o24_mix[] = {
870 SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN24, 21, 1, 0),
871};
872
873static const struct snd_kcontrol_new mt2701_afe_o31_mix[] = {
874 SOC_DAPM_SINGLE_AUTODISABLE("I35 Switch", AFE_CONN41, 9, 1, 0),
875};
876
877static const struct snd_kcontrol_new mt2701_afe_i02_mix[] = {
878 SOC_DAPM_SINGLE("I2S0 Switch", SND_SOC_NOPM, 0, 1, 0),
879};
880
881static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s0[] = {
882 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S0 Out Switch",
883 ASYS_I2SO1_CON, 26, 1, 0),
884};
885
886static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s1[] = {
887 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S1 Out Switch",
888 ASYS_I2SO2_CON, 26, 1, 0),
889};
890
891static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s2[] = {
892 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S2 Out Switch",
893 PWR2_TOP_CON, 17, 1, 0),
894};
895
896static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s3[] = {
897 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S3 Out Switch",
898 PWR2_TOP_CON, 18, 1, 0),
899};
900
901static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s4[] = {
902 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S4 Out Switch",
903 PWR2_TOP_CON, 19, 1, 0),
904};
905
43a6a7e7
GT		 906static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
907 /* inter-connections */
908 SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
909 SND_SOC_DAPM_MIXER("I01", SND_SOC_NOPM, 0, 0, NULL, 0),
910 SND_SOC_DAPM_MIXER("I02", SND_SOC_NOPM, 0, 0, mt2701_afe_i02_mix,
911 ARRAY_SIZE(mt2701_afe_i02_mix)),
912 SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
913 SND_SOC_DAPM_MIXER("I12", SND_SOC_NOPM, 0, 0, NULL, 0),
914 SND_SOC_DAPM_MIXER("I13", SND_SOC_NOPM, 0, 0, NULL, 0),
915 SND_SOC_DAPM_MIXER("I14", SND_SOC_NOPM, 0, 0, NULL, 0),
916 SND_SOC_DAPM_MIXER("I15", SND_SOC_NOPM, 0, 0, NULL, 0),
917 SND_SOC_DAPM_MIXER("I16", SND_SOC_NOPM, 0, 0, NULL, 0),
918 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
919 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
920 SND_SOC_DAPM_MIXER("I19", SND_SOC_NOPM, 0, 0, NULL, 0),
921 SND_SOC_DAPM_MIXER("I26", SND_SOC_NOPM, 0, 0, NULL, 0),
922 SND_SOC_DAPM_MIXER("I35", SND_SOC_NOPM, 0, 0, NULL, 0),
923
924 SND_SOC_DAPM_MIXER("O00", SND_SOC_NOPM, 0, 0, mt2701_afe_o00_mix,
925 ARRAY_SIZE(mt2701_afe_o00_mix)),
926 SND_SOC_DAPM_MIXER("O01", SND_SOC_NOPM, 0, 0, mt2701_afe_o01_mix,
927 ARRAY_SIZE(mt2701_afe_o01_mix)),
928 SND_SOC_DAPM_MIXER("O02", SND_SOC_NOPM, 0, 0, mt2701_afe_o02_mix,
929 ARRAY_SIZE(mt2701_afe_o02_mix)),
930 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0, mt2701_afe_o03_mix,
931 ARRAY_SIZE(mt2701_afe_o03_mix)),
932 SND_SOC_DAPM_MIXER("O14", SND_SOC_NOPM, 0, 0, mt2701_afe_o14_mix,
933 ARRAY_SIZE(mt2701_afe_o14_mix)),
934 SND_SOC_DAPM_MIXER("O15", SND_SOC_NOPM, 0, 0, mt2701_afe_o15_mix,
935 ARRAY_SIZE(mt2701_afe_o15_mix)),
936 SND_SOC_DAPM_MIXER("O16", SND_SOC_NOPM, 0, 0, mt2701_afe_o16_mix,
937 ARRAY_SIZE(mt2701_afe_o16_mix)),
938 SND_SOC_DAPM_MIXER("O17", SND_SOC_NOPM, 0, 0, mt2701_afe_o17_mix,
939 ARRAY_SIZE(mt2701_afe_o17_mix)),
940 SND_SOC_DAPM_MIXER("O18", SND_SOC_NOPM, 0, 0, mt2701_afe_o18_mix,
941 ARRAY_SIZE(mt2701_afe_o18_mix)),
942 SND_SOC_DAPM_MIXER("O19", SND_SOC_NOPM, 0, 0, mt2701_afe_o19_mix,
943 ARRAY_SIZE(mt2701_afe_o19_mix)),
944 SND_SOC_DAPM_MIXER("O20", SND_SOC_NOPM, 0, 0, mt2701_afe_o20_mix,
945 ARRAY_SIZE(mt2701_afe_o20_mix)),
946 SND_SOC_DAPM_MIXER("O21", SND_SOC_NOPM, 0, 0, mt2701_afe_o21_mix,
947 ARRAY_SIZE(mt2701_afe_o21_mix)),
948 SND_SOC_DAPM_MIXER("O22", SND_SOC_NOPM, 0, 0, mt2701_afe_o22_mix,
949 ARRAY_SIZE(mt2701_afe_o22_mix)),
950 SND_SOC_DAPM_MIXER("O31", SND_SOC_NOPM, 0, 0, mt2701_afe_o31_mix,
951 ARRAY_SIZE(mt2701_afe_o31_mix)),
952
953 SND_SOC_DAPM_MIXER("I12I13", SND_SOC_NOPM, 0, 0,
954 mt2701_afe_multi_ch_out_i2s0,
955 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s0)),
956 SND_SOC_DAPM_MIXER("I14I15", SND_SOC_NOPM, 0, 0,
957 mt2701_afe_multi_ch_out_i2s1,
958 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s1)),
959 SND_SOC_DAPM_MIXER("I16I17", SND_SOC_NOPM, 0, 0,
960 mt2701_afe_multi_ch_out_i2s2,
961 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s2)),
962 SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0,
963 mt2701_afe_multi_ch_out_i2s3,
964 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)),
43a6a7e7
GT		 965};
966
967static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
968 {"I12", NULL, "DL1"},
969 {"I13", NULL, "DL1"},
970 {"I35", NULL, "DLBT"},
971
972 {"I2S0 Playback", NULL, "O15"},
973 {"I2S0 Playback", NULL, "O16"},
43a6a7e7
GT		 974 {"I2S1 Playback", NULL, "O17"},
975 {"I2S1 Playback", NULL, "O18"},
976 {"I2S2 Playback", NULL, "O19"},
977 {"I2S2 Playback", NULL, "O20"},
978 {"I2S3 Playback", NULL, "O21"},
979 {"I2S3 Playback", NULL, "O22"},
980 {"BT Playback", NULL, "O31"},
981
982 {"UL1", NULL, "O00"},
983 {"UL1", NULL, "O01"},
984 {"UL2", NULL, "O02"},
985 {"UL2", NULL, "O03"},
986 {"ULBT", NULL, "O14"},
987
988 {"I00", NULL, "I2S0 Capture"},
989 {"I01", NULL, "I2S0 Capture"},
43a6a7e7
GT		 990 {"I02", NULL, "I2S1 Capture"},
991 {"I03", NULL, "I2S1 Capture"},
992 /* I02,03 link to UL2, also need to open I2S0 */
993 {"I02", "I2S0 Switch", "I2S0 Capture"},
994
995 {"I26", NULL, "BT Capture"},
996
600b2fd4
RL		 997 {"I12I13", "Multich I2S0 Out Switch", "DLM"},
998 {"I14I15", "Multich I2S1 Out Switch", "DLM"},
999 {"I16I17", "Multich I2S2 Out Switch", "DLM"},
1000 {"I18I19", "Multich I2S3 Out Switch", "DLM"},
43a6a7e7
GT		 1001
1002 { "I12", NULL, "I12I13" },
1003 { "I13", NULL, "I12I13" },
1004 { "I14", NULL, "I14I15" },
1005 { "I15", NULL, "I14I15" },
1006 { "I16", NULL, "I16I17" },
1007 { "I17", NULL, "I16I17" },
1008 { "I18", NULL, "I18I19" },
1009 { "I19", NULL, "I18I19" },
1010
1011 { "O00", "I00 Switch", "I00" },
1012 { "O01", "I01 Switch", "I01" },
1013 { "O02", "I02 Switch", "I02" },
1014 { "O03", "I03 Switch", "I03" },
1015 { "O14", "I26 Switch", "I26" },
1016 { "O15", "I12 Switch", "I12" },
1017 { "O16", "I13 Switch", "I13" },
1018 { "O17", "I14 Switch", "I14" },
1019 { "O18", "I15 Switch", "I15" },
1020 { "O19", "I16 Switch", "I16" },
1021 { "O20", "I17 Switch", "I17" },
1022 { "O21", "I18 Switch", "I18" },
1023 { "O22", "I19 Switch", "I19" },
1024 { "O31", "I35 Switch", "I35" },
43a6a7e7
GT		 1025};
1026
1027static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = {
1028 .name = "mt2701-afe-pcm-dai",
1029 .dapm_widgets = mt2701_afe_pcm_widgets,
1030 .num_dapm_widgets = ARRAY_SIZE(mt2701_afe_pcm_widgets),
1031 .dapm_routes = mt2701_afe_pcm_routes,
1032 .num_dapm_routes = ARRAY_SIZE(mt2701_afe_pcm_routes),
1033};
1034
1035static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
1036 {
1037 .name = "DL1",
1038 .id = MT2701_MEMIF_DL1,
1039 .reg_ofs_base = AFE_DL1_BASE,
1040 .reg_ofs_cur = AFE_DL1_CUR,
1041 .fs_reg = AFE_DAC_CON1,
1042 .fs_shift = 0,
1043 .fs_maskbit = 0x1f,
1044 .mono_reg = AFE_DAC_CON3,
1045 .mono_shift = 16,
1046 .enable_reg = AFE_DAC_CON0,
1047 .enable_shift = 1,
1048 .hd_reg = AFE_MEMIF_HD_CON0,
1049 .hd_shift = 0,
1050 .agent_disable_reg = AUDIO_TOP_CON5,
1051 .agent_disable_shift = 6,
1052 .msb_reg = -1,
1053 .msb_shift = -1,
1054 },
1055 {
1056 .name = "DL2",
1057 .id = MT2701_MEMIF_DL2,
1058 .reg_ofs_base = AFE_DL2_BASE,
1059 .reg_ofs_cur = AFE_DL2_CUR,
1060 .fs_reg = AFE_DAC_CON1,
1061 .fs_shift = 5,
1062 .fs_maskbit = 0x1f,
1063 .mono_reg = AFE_DAC_CON3,
1064 .mono_shift = 17,
1065 .enable_reg = AFE_DAC_CON0,
1066 .enable_shift = 2,
1067 .hd_reg = AFE_MEMIF_HD_CON0,
1068 .hd_shift = 2,
1069 .agent_disable_reg = AUDIO_TOP_CON5,
1070 .agent_disable_shift = 7,
1071 .msb_reg = -1,
1072 .msb_shift = -1,
1073 },
1074 {
1075 .name = "DL3",
1076 .id = MT2701_MEMIF_DL3,
1077 .reg_ofs_base = AFE_DL3_BASE,
1078 .reg_ofs_cur = AFE_DL3_CUR,
1079 .fs_reg = AFE_DAC_CON1,
1080 .fs_shift = 10,
1081 .fs_maskbit = 0x1f,
1082 .mono_reg = AFE_DAC_CON3,
1083 .mono_shift = 18,
1084 .enable_reg = AFE_DAC_CON0,
1085 .enable_shift = 3,
1086 .hd_reg = AFE_MEMIF_HD_CON0,
1087 .hd_shift = 4,
1088 .agent_disable_reg = AUDIO_TOP_CON5,
1089 .agent_disable_shift = 8,
1090 .msb_reg = -1,
1091 .msb_shift = -1,
1092 },
1093 {
1094 .name = "DL4",
1095 .id = MT2701_MEMIF_DL4,
1096 .reg_ofs_base = AFE_DL4_BASE,
1097 .reg_ofs_cur = AFE_DL4_CUR,
1098 .fs_reg = AFE_DAC_CON1,
1099 .fs_shift = 15,
1100 .fs_maskbit = 0x1f,
1101 .mono_reg = AFE_DAC_CON3,
1102 .mono_shift = 19,
1103 .enable_reg = AFE_DAC_CON0,
1104 .enable_shift = 4,
1105 .hd_reg = AFE_MEMIF_HD_CON0,
1106 .hd_shift = 6,
1107 .agent_disable_reg = AUDIO_TOP_CON5,
1108 .agent_disable_shift = 9,
1109 .msb_reg = -1,
1110 .msb_shift = -1,
1111 },
1112 {
1113 .name = "DL5",
1114 .id = MT2701_MEMIF_DL5,
1115 .reg_ofs_base = AFE_DL5_BASE,
1116 .reg_ofs_cur = AFE_DL5_CUR,
1117 .fs_reg = AFE_DAC_CON1,
1118 .fs_shift = 20,
1119 .fs_maskbit = 0x1f,
1120 .mono_reg = AFE_DAC_CON3,
1121 .mono_shift = 20,
1122 .enable_reg = AFE_DAC_CON0,
1123 .enable_shift = 5,
1124 .hd_reg = AFE_MEMIF_HD_CON0,
1125 .hd_shift = 8,
1126 .agent_disable_reg = AUDIO_TOP_CON5,
1127 .agent_disable_shift = 10,
1128 .msb_reg = -1,
1129 .msb_shift = -1,
1130 },
1131 {
1132 .name = "DLM",
1133 .id = MT2701_MEMIF_DLM,
1134 .reg_ofs_base = AFE_DLMCH_BASE,
1135 .reg_ofs_cur = AFE_DLMCH_CUR,
1136 .fs_reg = AFE_DAC_CON1,
1137 .fs_shift = 0,
1138 .fs_maskbit = 0x1f,
1139 .mono_reg = -1,
1140 .mono_shift = -1,
1141 .enable_reg = AFE_DAC_CON0,
1142 .enable_shift = 7,
1143 .hd_reg = AFE_MEMIF_PBUF_SIZE,
1144 .hd_shift = 28,
1145 .agent_disable_reg = AUDIO_TOP_CON5,
1146 .agent_disable_shift = 12,
1147 .msb_reg = -1,
1148 .msb_shift = -1,
1149 },
1150 {
1151 .name = "UL1",
1152 .id = MT2701_MEMIF_UL1,
1153 .reg_ofs_base = AFE_VUL_BASE,
1154 .reg_ofs_cur = AFE_VUL_CUR,
1155 .fs_reg = AFE_DAC_CON2,
1156 .fs_shift = 0,
1157 .fs_maskbit = 0x1f,
1158 .mono_reg = AFE_DAC_CON4,
1159 .mono_shift = 0,
1160 .enable_reg = AFE_DAC_CON0,
1161 .enable_shift = 10,
1162 .hd_reg = AFE_MEMIF_HD_CON1,
1163 .hd_shift = 0,
1164 .agent_disable_reg = AUDIO_TOP_CON5,
1165 .agent_disable_shift = 0,
1166 .msb_reg = -1,
1167 .msb_shift = -1,
1168 },
1169 {
1170 .name = "UL2",
1171 .id = MT2701_MEMIF_UL2,
1172 .reg_ofs_base = AFE_UL2_BASE,
1173 .reg_ofs_cur = AFE_UL2_CUR,
1174 .fs_reg = AFE_DAC_CON2,
1175 .fs_shift = 5,
1176 .fs_maskbit = 0x1f,
1177 .mono_reg = AFE_DAC_CON4,
1178 .mono_shift = 2,
1179 .enable_reg = AFE_DAC_CON0,
1180 .enable_shift = 11,
1181 .hd_reg = AFE_MEMIF_HD_CON1,
1182 .hd_shift = 2,
1183 .agent_disable_reg = AUDIO_TOP_CON5,
1184 .agent_disable_shift = 1,
1185 .msb_reg = -1,
1186 .msb_shift = -1,
1187 },
1188 {
1189 .name = "UL3",
1190 .id = MT2701_MEMIF_UL3,
1191 .reg_ofs_base = AFE_UL3_BASE,
1192 .reg_ofs_cur = AFE_UL3_CUR,
1193 .fs_reg = AFE_DAC_CON2,
1194 .fs_shift = 10,
1195 .fs_maskbit = 0x1f,
1196 .mono_reg = AFE_DAC_CON4,
1197 .mono_shift = 4,
1198 .enable_reg = AFE_DAC_CON0,
1199 .enable_shift = 12,
1200 .hd_reg = AFE_MEMIF_HD_CON0,
1201 .hd_shift = 0,
1202 .agent_disable_reg = AUDIO_TOP_CON5,
1203 .agent_disable_shift = 2,
1204 .msb_reg = -1,
1205 .msb_shift = -1,
1206 },
1207 {
1208 .name = "UL4",
1209 .id = MT2701_MEMIF_UL4,
1210 .reg_ofs_base = AFE_UL4_BASE,
1211 .reg_ofs_cur = AFE_UL4_CUR,
1212 .fs_reg = AFE_DAC_CON2,
1213 .fs_shift = 15,
1214 .fs_maskbit = 0x1f,
1215 .mono_reg = AFE_DAC_CON4,
1216 .mono_shift = 6,
1217 .enable_reg = AFE_DAC_CON0,
1218 .enable_shift = 13,
1219 .hd_reg = AFE_MEMIF_HD_CON0,
1220 .hd_shift = 6,
1221 .agent_disable_reg = AUDIO_TOP_CON5,
1222 .agent_disable_shift = 3,
1223 .msb_reg = -1,
1224 .msb_shift = -1,
1225 },
1226 {
1227 .name = "UL5",
1228 .id = MT2701_MEMIF_UL5,
1229 .reg_ofs_base = AFE_UL5_BASE,
1230 .reg_ofs_cur = AFE_UL5_CUR,
1231 .fs_reg = AFE_DAC_CON2,
1232 .fs_shift = 20,
1233 .mono_reg = AFE_DAC_CON4,
1234 .mono_shift = 8,
1235 .fs_maskbit = 0x1f,
1236 .enable_reg = AFE_DAC_CON0,
1237 .enable_shift = 14,
1238 .hd_reg = AFE_MEMIF_HD_CON0,
1239 .hd_shift = 8,
1240 .agent_disable_reg = AUDIO_TOP_CON5,
1241 .agent_disable_shift = 4,
1242 .msb_reg = -1,
1243 .msb_shift = -1,
1244 },
1245 {
1246 .name = "DLBT",
1247 .id = MT2701_MEMIF_DLBT,
1248 .reg_ofs_base = AFE_ARB1_BASE,
1249 .reg_ofs_cur = AFE_ARB1_CUR,
1250 .fs_reg = AFE_DAC_CON3,
1251 .fs_shift = 10,
1252 .fs_maskbit = 0x1f,
1253 .mono_reg = AFE_DAC_CON3,
1254 .mono_shift = 22,
1255 .enable_reg = AFE_DAC_CON0,
1256 .enable_shift = 8,
1257 .hd_reg = AFE_MEMIF_HD_CON0,
1258 .hd_shift = 14,
1259 .agent_disable_reg = AUDIO_TOP_CON5,
1260 .agent_disable_shift = 13,
1261 .msb_reg = -1,
1262 .msb_shift = -1,
1263 },
1264 {
1265 .name = "ULBT",
1266 .id = MT2701_MEMIF_ULBT,
1267 .reg_ofs_base = AFE_DAI_BASE,
1268 .reg_ofs_cur = AFE_DAI_CUR,
1269 .fs_reg = AFE_DAC_CON2,
1270 .fs_shift = 30,
1271 .fs_maskbit = 0x1,
1272 .mono_reg = -1,
1273 .mono_shift = -1,
1274 .enable_reg = AFE_DAC_CON0,
1275 .enable_shift = 17,
1276 .hd_reg = AFE_MEMIF_HD_CON1,
1277 .hd_shift = 20,
1278 .agent_disable_reg = AUDIO_TOP_CON5,
1279 .agent_disable_shift = 16,
1280 .msb_reg = -1,
1281 .msb_shift = -1,
1282 },
1283};
1284
1285static const struct mtk_base_irq_data irq_data[MT2701_IRQ_ASYS_END] = {
1286 {
1287 .id = MT2701_IRQ_ASYS_IRQ1,
1288 .irq_cnt_reg = ASYS_IRQ1_CON,
1289 .irq_cnt_shift = 0,
1290 .irq_cnt_maskbit = 0xffffff,
1291 .irq_fs_reg = ASYS_IRQ1_CON,
1292 .irq_fs_shift = 24,
1293 .irq_fs_maskbit = 0x1f,
1294 .irq_en_reg = ASYS_IRQ1_CON,
1295 .irq_en_shift = 31,
1296 .irq_clr_reg = ASYS_IRQ_CLR,
1297 .irq_clr_shift = 0,
1298 },
1299 {
1300 .id = MT2701_IRQ_ASYS_IRQ2,
1301 .irq_cnt_reg = ASYS_IRQ2_CON,
1302 .irq_cnt_shift = 0,
1303 .irq_cnt_maskbit = 0xffffff,
1304 .irq_fs_reg = ASYS_IRQ2_CON,
1305 .irq_fs_shift = 24,
1306 .irq_fs_maskbit = 0x1f,
1307 .irq_en_reg = ASYS_IRQ2_CON,
1308 .irq_en_shift = 31,
1309 .irq_clr_reg = ASYS_IRQ_CLR,
1310 .irq_clr_shift = 1,
1311 },
1312 {
1313 .id = MT2701_IRQ_ASYS_IRQ3,
1314 .irq_cnt_reg = ASYS_IRQ3_CON,
1315 .irq_cnt_shift = 0,
1316 .irq_cnt_maskbit = 0xffffff,
1317 .irq_fs_reg = ASYS_IRQ3_CON,
1318 .irq_fs_shift = 24,
1319 .irq_fs_maskbit = 0x1f,
1320 .irq_en_reg = ASYS_IRQ3_CON,
1321 .irq_en_shift = 31,
1322 .irq_clr_reg = ASYS_IRQ_CLR,
1323 .irq_clr_shift = 2,
1324 }
1325};
1326
1327static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
1328 {
1329 {
1330 .i2s_ctrl_reg = ASYS_I2SO1_CON,
43a6a7e7
GT		 1331 .i2s_asrc_fs_shift = 0,
1332 .i2s_asrc_fs_mask = 0x1f,
1333
1334 },
1335 {
1336 .i2s_ctrl_reg = ASYS_I2SIN1_CON,
43a6a7e7
GT		 1337 .i2s_asrc_fs_shift = 0,
1338 .i2s_asrc_fs_mask = 0x1f,
1339
1340 },
1341 },
1342 {
1343 {
1344 .i2s_ctrl_reg = ASYS_I2SO2_CON,
43a6a7e7
GT		 1345 .i2s_asrc_fs_shift = 5,
1346 .i2s_asrc_fs_mask = 0x1f,
1347
1348 },
1349 {
1350 .i2s_ctrl_reg = ASYS_I2SIN2_CON,
43a6a7e7
GT		 1351 .i2s_asrc_fs_shift = 5,
1352 .i2s_asrc_fs_mask = 0x1f,
1353
1354 },
1355 },
1356 {
1357 {
1358 .i2s_ctrl_reg = ASYS_I2SO3_CON,
43a6a7e7
GT		 1359 .i2s_asrc_fs_shift = 10,
1360 .i2s_asrc_fs_mask = 0x1f,
1361
1362 },
1363 {
1364 .i2s_ctrl_reg = ASYS_I2SIN3_CON,
43a6a7e7
GT		 1365 .i2s_asrc_fs_shift = 10,
1366 .i2s_asrc_fs_mask = 0x1f,
1367
1368 },
1369 },
1370 {
1371 {
1372 .i2s_ctrl_reg = ASYS_I2SO4_CON,
43a6a7e7
GT		 1373 .i2s_asrc_fs_shift = 15,
1374 .i2s_asrc_fs_mask = 0x1f,
1375
1376 },
1377 {
1378 .i2s_ctrl_reg = ASYS_I2SIN4_CON,
43a6a7e7
GT		 1379 .i2s_asrc_fs_shift = 15,
1380 .i2s_asrc_fs_mask = 0x1f,
1381
1382 },
1383 },
1384};
1385
43a6a7e7
GT		 1386static irqreturn_t mt2701_asys_isr(int irq_id, void *dev)
1387{
1388 int id;
1389 struct mtk_base_afe *afe = dev;
1390 struct mtk_base_afe_memif *memif;
1391 struct mtk_base_afe_irq *irq;
1392 u32 status;
1393
1394 regmap_read(afe->regmap, ASYS_IRQ_STATUS, &status);
1395 regmap_write(afe->regmap, ASYS_IRQ_CLR, status);
1396
1397 for (id = 0; id < MT2701_MEMIF_NUM; ++id) {
1398 memif = &afe->memif[id];
1399 if (memif->irq_usage < 0)
1400 continue;
1401 irq = &afe->irqs[memif->irq_usage];
1402 if (status & 1 << (irq->irq_data->irq_clr_shift))
1403 snd_pcm_period_elapsed(memif->substream);
1404 }
1405 return IRQ_HANDLED;
1406}
1407
1408static int mt2701_afe_runtime_suspend(struct device *dev)
1409{
1410 struct mtk_base_afe *afe = dev_get_drvdata(dev);
1411
d8d99d8e 1412 return mt2701_afe_disable_clock(afe);
43a6a7e7
GT		 1413}
1414
1415static int mt2701_afe_runtime_resume(struct device *dev)
1416{
1417 struct mtk_base_afe *afe = dev_get_drvdata(dev);
1418
1419 return mt2701_afe_enable_clock(afe);
1420}
1421
dc2a17f4 1422static int mt2701_afe_add_component(struct mtk_base_afe *afe)
43a6a7e7 1423{
dfa3cbb8 1424 struct snd_soc_component *component;
dc2a17f4
RL		 1425
1426 component = kzalloc(sizeof(*component), GFP_KERNEL);
1427 if (!component)
1428 return -ENOMEM;
1429
1430 component->regmap = afe->regmap;
1431
1432 return snd_soc_add_component(afe->dev, component,
1433 &mt2701_afe_pcm_dai_component,
1434 mt2701_afe_pcm_dais,
1435 ARRAY_SIZE(mt2701_afe_pcm_dais));
1436}
1437
1438static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
1439{
43a6a7e7
GT		 1440 struct mtk_base_afe *afe;
1441 struct mt2701_afe_private *afe_priv;
43a6a7e7 1442 struct device *dev;
f6c1626e 1443 int i, irq_id, ret;
43a6a7e7 1444
43a6a7e7 1445 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
b02c5cc7
DC		 1446 if (!afe)
1447 return -ENOMEM;
600b2fd4 1448
43a6a7e7
GT		 1449 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1450 GFP_KERNEL);
b02c5cc7 1451 if (!afe->platform_priv)
43a6a7e7
GT		 1452 return -ENOMEM;
1453
600b2fd4 1454 afe_priv = afe->platform_priv;
43a6a7e7
GT		 1455 afe->dev = &pdev->dev;
1456 dev = afe->dev;
1457
f6c1626e
RL		 1458 irq_id = platform_get_irq_byname(pdev, "asys");
1459 if (irq_id < 0) {
1460 dev_err(dev, "unable to get ASYS IRQ\n");
1461 return irq_id;
43a6a7e7 1462 }
f6c1626e 1463
43a6a7e7
GT		 1464 ret = devm_request_irq(dev, irq_id, mt2701_asys_isr,
1465 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
1466 if (ret) {
1467 dev_err(dev, "could not request_irq for asys-isr\n");
1468 return ret;
1469 }
1470
dfa3cbb8 1471 afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
3e8052d9 1472 if (IS_ERR(afe->regmap)) {
dfa3cbb8 1473 dev_err(dev, "could not get regmap from parent\n");
3e8052d9 1474 return PTR_ERR(afe->regmap);
dfa3cbb8 1475 }
43a6a7e7
GT		 1476
1477 mutex_init(&afe->irq_alloc_lock);
1478
1479 /* memif initialize */
1480 afe->memif_size = MT2701_MEMIF_NUM;
1481 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
1482 GFP_KERNEL);
43a6a7e7
GT		 1483 if (!afe->memif)
1484 return -ENOMEM;
1485
1486 for (i = 0; i < afe->memif_size; i++) {
1487 afe->memif[i].data = &memif_data[i];
1488 afe->memif[i].irq_usage = -1;
1489 }
1490
1491 /* irq initialize */
1492 afe->irqs_size = MT2701_IRQ_ASYS_END;
1493 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
1494 GFP_KERNEL);
43a6a7e7
GT		 1495 if (!afe->irqs)
1496 return -ENOMEM;
1497
1498 for (i = 0; i < afe->irqs_size; i++)
1499 afe->irqs[i].irq_data = &irq_data[i];
1500
1501 /* I2S initialize */
1502 for (i = 0; i < MT2701_I2S_NUM; i++) {
1503 afe_priv->i2s_path[i].i2s_data[I2S_OUT]
1504 = &mt2701_i2s_data[i][I2S_OUT];
1505 afe_priv->i2s_path[i].i2s_data[I2S_IN]
1506 = &mt2701_i2s_data[i][I2S_IN];
1507 }
1508
1509 afe->mtk_afe_hardware = &mt2701_afe_hardware;
1510 afe->memif_fs = mt2701_memif_fs;
1511 afe->irq_fs = mt2701_irq_fs;
43a6a7e7
GT		 1512 afe->reg_back_up_list = mt2701_afe_backup_list;
1513 afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list);
1514 afe->runtime_resume = mt2701_afe_runtime_resume;
1515 afe->runtime_suspend = mt2701_afe_runtime_suspend;
1516
1517 /* initial audio related clock */
1518 ret = mt2701_init_clock(afe);
1519 if (ret) {
1520 dev_err(dev, "init clock error\n");
dc2a17f4 1521 return ret;
43a6a7e7
GT		 1522 }
1523
1524 platform_set_drvdata(pdev, afe);
43a6a7e7 1525
dd6bb9b1
RL		 1526 pm_runtime_enable(dev);
1527 if (!pm_runtime_enabled(dev)) {
1528 ret = mt2701_afe_runtime_resume(dev);
1529 if (ret)
1530 goto err_pm_disable;
1531 }
1532 pm_runtime_get_sync(dev);
1533
f1b5bf07
KM		 1534 ret = devm_snd_soc_register_component(&pdev->dev, &mtk_afe_pcm_platform,
1535 NULL, 0);
43a6a7e7
GT		 1536 if (ret) {
1537 dev_warn(dev, "err_platform\n");
1538 goto err_platform;
1539 }
1540
dc2a17f4 1541 ret = mt2701_afe_add_component(afe);
43a6a7e7
GT		 1542 if (ret) {
1543 dev_warn(dev, "err_dai_component\n");
f1b5bf07 1544 goto err_platform;
43a6a7e7
GT		 1545 }
1546
43a6a7e7
GT		 1547 return 0;
1548
43a6a7e7 1549err_platform:
dd6bb9b1 1550 pm_runtime_put_sync(dev);
43a6a7e7 1551err_pm_disable:
dd6bb9b1 1552 pm_runtime_disable(dev);
43a6a7e7
GT		 1553
1554 return ret;
1555}
1556
1557static int mt2701_afe_pcm_dev_remove(struct platform_device *pdev)
1558{
dd6bb9b1 1559 pm_runtime_put_sync(&pdev->dev);
43a6a7e7
GT		 1560 pm_runtime_disable(&pdev->dev);
1561 if (!pm_runtime_status_suspended(&pdev->dev))
1562 mt2701_afe_runtime_suspend(&pdev->dev);
1563
43a6a7e7
GT		 1564 return 0;
1565}
1566
1567static const struct of_device_id mt2701_afe_pcm_dt_match[] = {
1568 { .compatible = "mediatek,mt2701-audio", },
1569 {},
1570};
1571MODULE_DEVICE_TABLE(of, mt2701_afe_pcm_dt_match);
1572
1573static const struct dev_pm_ops mt2701_afe_pm_ops = {
1574 SET_RUNTIME_PM_OPS(mt2701_afe_runtime_suspend,
1575 mt2701_afe_runtime_resume, NULL)
1576};
1577
1578static struct platform_driver mt2701_afe_pcm_driver = {
1579 .driver = {
1580 .name = "mt2701-audio",
1581 .of_match_table = mt2701_afe_pcm_dt_match,
1582#ifdef CONFIG_PM
1583 .pm = &mt2701_afe_pm_ops,
1584#endif
1585 },
1586 .probe = mt2701_afe_pcm_dev_probe,
1587 .remove = mt2701_afe_pcm_dev_remove,
1588};
1589
1590module_platform_driver(mt2701_afe_pcm_driver);
1591
1592MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701");
1593MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
1594MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)