[linux-2.6-block.git] / sound / soc / jz4740 / jz4740-i2s.c

/*
 *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under  the terms of the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <linux/clk.h>
#include <linux/delay.h>

#include <linux/dma-mapping.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/dmaengine_pcm.h>

#include <asm/mach-jz4740/dma.h>

#include "jz4740-i2s.h"

#define JZ_REG_AIC_CONF		0x00
#define JZ_REG_AIC_CTRL		0x04
#define JZ_REG_AIC_I2S_FMT	0x10
#define JZ_REG_AIC_FIFO_STATUS	0x14
#define JZ_REG_AIC_I2S_STATUS	0x1c
#define JZ_REG_AIC_CLK_DIV	0x30
#define JZ_REG_AIC_FIFO		0x34

#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf <<  8)
#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
#define JZ_AIC_CONF_I2S BIT(4)
#define JZ_AIC_CONF_RESET BIT(3)
#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
#define JZ_AIC_CONF_ENABLE BIT(0)

#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8

#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
#define JZ_AIC_CTRL_FLUSH		BIT(8)
#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)

#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET  16

#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
#define JZ_AIC_I2S_FMT_MSB BIT(0)

#define JZ_AIC_I2S_STATUS_BUSY BIT(2)

#define JZ_AIC_CLK_DIV_MASK 0xf

struct jz4740_i2s {
	struct resource *mem;
	void __iomem *base;
	dma_addr_t phys_base;

	struct clk *clk_aic;
	struct clk *clk_i2s;

	struct snd_dmaengine_dai_dma_data playback_dma_data;
	struct snd_dmaengine_dai_dma_data capture_dma_data;
};

static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
	unsigned int reg)
{
	return readl(i2s->base + reg);
}

static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
	unsigned int reg, uint32_t value)
{
	writel(value, i2s->base + reg);
}

static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	uint32_t conf, ctrl;

	if (dai->active)
		return 0;

	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
	ctrl |= JZ_AIC_CTRL_FLUSH;
	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);

	clk_prepare_enable(i2s->clk_i2s);

	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	conf |= JZ_AIC_CONF_ENABLE;
	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

	return 0;
}

static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	uint32_t conf;

	if (dai->active)
		return;

	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	conf &= ~JZ_AIC_CONF_ENABLE;
	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

	clk_disable_unprepare(i2s->clk_i2s);
}

static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
	struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	uint32_t ctrl;
	uint32_t mask;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
	else
		mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;

	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		ctrl |= mask;
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		ctrl &= ~mask;
		break;
	default:
		return -EINVAL;
	}

	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);

	return 0;
}

static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	uint32_t format = 0;
	uint32_t conf;

	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);

	conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
		format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
		break;
	case SND_SOC_DAIFMT_CBS_CFM:
		conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_MSB:
		format |= JZ_AIC_I2S_FMT_MSB;
		break;
	case SND_SOC_DAIFMT_I2S:
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		break;
	default:
		return -EINVAL;
	}

	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);

	return 0;
}

static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	unsigned int sample_size;
	uint32_t ctrl;

	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		sample_size = 0;
		break;
	case SNDRV_PCM_FORMAT_S16:
		sample_size = 1;
		break;
	default:
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
		ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
		if (params_channels(params) == 1)
			ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
		else
			ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
	} else {
		ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
		ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
	}

	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);

	return 0;
}

static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
	unsigned int freq, int dir)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	struct clk *parent;
	int ret = 0;

	switch (clk_id) {
	case JZ4740_I2S_CLKSRC_EXT:
		parent = clk_get(NULL, "ext");
		clk_set_parent(i2s->clk_i2s, parent);
		break;
	case JZ4740_I2S_CLKSRC_PLL:
		parent = clk_get(NULL, "pll half");
		clk_set_parent(i2s->clk_i2s, parent);
		ret = clk_set_rate(i2s->clk_i2s, freq);
		break;
	default:
		return -EINVAL;
	}
	clk_put(parent);

	return ret;
}

static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	uint32_t conf;

	if (dai->active) {
		conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
		conf &= ~JZ_AIC_CONF_ENABLE;
		jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

		clk_disable_unprepare(i2s->clk_i2s);
	}

	clk_disable_unprepare(i2s->clk_aic);

	return 0;
}

static int jz4740_i2s_resume(struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	uint32_t conf;

	clk_prepare_enable(i2s->clk_aic);

	if (dai->active) {
		clk_prepare_enable(i2s->clk_i2s);

		conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
		conf |= JZ_AIC_CONF_ENABLE;
		jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	}

	return 0;
}

static void jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
{
	struct snd_dmaengine_dai_dma_data *dma_data;

	/* Playback */
	dma_data = &i2s->playback_dma_data;
	dma_data->maxburst = 16;
	dma_data->slave_id = JZ4740_DMA_TYPE_AIC_TRANSMIT;
	dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;

	/* Capture */
	dma_data = &i2s->capture_dma_data;
	dma_data->maxburst = 16;
	dma_data->slave_id = JZ4740_DMA_TYPE_AIC_RECEIVE;
	dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
}

static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	uint32_t conf;

	clk_prepare_enable(i2s->clk_aic);

	jz4740_i2c_init_pcm_config(i2s);
	snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
		&i2s->capture_dma_data);

	conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
		(8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
		JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
		JZ_AIC_CONF_I2S |
		JZ_AIC_CONF_INTERNAL_CODEC;

	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

	return 0;
}

static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
{
	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);

	clk_disable_unprepare(i2s->clk_aic);
	return 0;
}

static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
	.startup = jz4740_i2s_startup,
	.shutdown = jz4740_i2s_shutdown,
	.trigger = jz4740_i2s_trigger,
	.hw_params = jz4740_i2s_hw_params,
	.set_fmt = jz4740_i2s_set_fmt,
	.set_sysclk = jz4740_i2s_set_sysclk,
};

#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
		SNDRV_PCM_FMTBIT_S16_LE)

static struct snd_soc_dai_driver jz4740_i2s_dai = {
	.probe = jz4740_i2s_dai_probe,
	.remove = jz4740_i2s_dai_remove,
	.playback = {
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = JZ4740_I2S_FMTS,
	},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = JZ4740_I2S_FMTS,
	},
	.symmetric_rates = 1,
	.ops = &jz4740_i2s_dai_ops,
	.suspend = jz4740_i2s_suspend,
	.resume = jz4740_i2s_resume,
};

static const struct snd_soc_component_driver jz4740_i2s_component = {
	.name		= "jz4740-i2s",
};

static int jz4740_i2s_dev_probe(struct platform_device *pdev)
{
	struct jz4740_i2s *i2s;
	struct resource *mem;
	int ret;

	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
	if (!i2s)
		return -ENOMEM;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	i2s->base = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(i2s->base))
		return PTR_ERR(i2s->base);

	i2s->phys_base = mem->start;

	i2s->clk_aic = devm_clk_get(&pdev->dev, "aic");
	if (IS_ERR(i2s->clk_aic))
		return PTR_ERR(i2s->clk_aic);

	i2s->clk_i2s = devm_clk_get(&pdev->dev, "i2s");
	if (IS_ERR(i2s->clk_i2s))
		return PTR_ERR(i2s->clk_i2s);

	platform_set_drvdata(pdev, i2s);

	ret = devm_snd_soc_register_component(&pdev->dev,
		&jz4740_i2s_component, &jz4740_i2s_dai, 1);
	if (ret)
		return ret;

	return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
		SND_DMAENGINE_PCM_FLAG_COMPAT);
}

static struct platform_driver jz4740_i2s_driver = {
	.probe = jz4740_i2s_dev_probe,
	.driver = {
		.name = "jz4740-i2s",
		.owner = THIS_MODULE,
	},
};

module_platform_driver(jz4740_i2s_driver);

MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:jz4740-i2s");
Commit	Line	Data
11bd3dd1 LPC	1	/*
	2	* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the
	6	* Free Software Foundation; either version 2 of the License, or (at your
	7	* option) any later version.
	8	*
	9	* You should have received a copy of the GNU General Public License along
	10	* with this program; if not, write to the Free Software Foundation, Inc.,
	11	* 675 Mass Ave, Cambridge, MA 02139, USA.
	12	*
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/io.h>
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/slab.h>
	21
	22	#include <linux/clk.h>
	23	#include <linux/delay.h>
	24
	25	#include <linux/dma-mapping.h>
	26
	27	#include <sound/core.h>
	28	#include <sound/pcm.h>
	29	#include <sound/pcm_params.h>
	30	#include <sound/soc.h>
11bd3dd1	31	#include <sound/initval.h>
0406a40a LPC	32	#include <sound/dmaengine_pcm.h>
	33
	34	#include <asm/mach-jz4740/dma.h>
11bd3dd1 LPC	35
11bd3dd1 LPC	36	#include "jz4740-i2s.h"
11bd3dd1 LPC	37
	38	#define JZ_REG_AIC_CONF 0x00
	39	#define JZ_REG_AIC_CTRL 0x04
	40	#define JZ_REG_AIC_I2S_FMT 0x10
	41	#define JZ_REG_AIC_FIFO_STATUS 0x14
	42	#define JZ_REG_AIC_I2S_STATUS 0x1c
	43	#define JZ_REG_AIC_CLK_DIV 0x30
	44	#define JZ_REG_AIC_FIFO 0x34
	45
	46	#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
	47	#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8)
	48	#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
	49	#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
	50	#define JZ_AIC_CONF_I2S BIT(4)
	51	#define JZ_AIC_CONF_RESET BIT(3)
	52	#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
	53	#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
	54	#define JZ_AIC_CONF_ENABLE BIT(0)
	55
	56	#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
	57	#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
	58
	59	#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
	60	#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
	61	#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
	62	#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
	63	#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
	64	#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
	65	#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
	66	#define JZ_AIC_CTRL_FLUSH BIT(8)
	67	#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
	68	#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
	69	#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
	70	#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
	71	#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
	72	#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
	73	#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
	74
	75	#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
	76	#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16
	77
	78	#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
	79	#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
	80	#define JZ_AIC_I2S_FMT_MSB BIT(0)
	81
	82	#define JZ_AIC_I2S_STATUS_BUSY BIT(2)
	83
	84	#define JZ_AIC_CLK_DIV_MASK 0xf
	85
	86	struct jz4740_i2s {
	87	struct resource *mem;
	88	void __iomem *base;
	89	dma_addr_t phys_base;
	90
	91	struct clk *clk_aic;
	92	struct clk *clk_i2s;
	93
0406a40a LPC	94	struct snd_dmaengine_dai_dma_data playback_dma_data;
0406a40a LPC	95	struct snd_dmaengine_dai_dma_data capture_dma_data;
11bd3dd1 LPC	96	};
	97
	98	static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
	99	unsigned int reg)
	100	{
	101	return readl(i2s->base + reg);
	102	}
	103
	104	static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
	105	unsigned int reg, uint32_t value)
	106	{
	107	writel(value, i2s->base + reg);
	108	}
	109
11bd3dd1 LPC	110	static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
	111	struct snd_soc_dai *dai)
	112	{
f0fba2ad	113	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	114	uint32_t conf, ctrl;
	115
	116	if (dai->active)
	117	return 0;
	118
	119	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
	120	ctrl \|= JZ_AIC_CTRL_FLUSH;
	121	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
	122
010187fb	123	clk_prepare_enable(i2s->clk_i2s);
11bd3dd1 LPC	124
	125	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	126	conf \|= JZ_AIC_CONF_ENABLE;
	127	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	128
	129	return 0;
	130	}
	131
	132	static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
	133	struct snd_soc_dai *dai)
	134	{
f0fba2ad	135	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	136	uint32_t conf;
11bd3dd1 LPC	137
005967a1	138	if (dai->active)
11bd3dd1 LPC	139	return;
	140
	141	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	142	conf &= ~JZ_AIC_CONF_ENABLE;
	143	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	144
010187fb	145	clk_disable_unprepare(i2s->clk_i2s);
11bd3dd1 LPC	146	}
	147
	148	static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
	149	struct snd_soc_dai *dai)
	150	{
f0fba2ad	151	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	152
	153	uint32_t ctrl;
	154	uint32_t mask;
	155
	156	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	157	mask = JZ_AIC_CTRL_ENABLE_PLAYBACK \| JZ_AIC_CTRL_ENABLE_TX_DMA;
	158	else
	159	mask = JZ_AIC_CTRL_ENABLE_CAPTURE \| JZ_AIC_CTRL_ENABLE_RX_DMA;
	160
	161	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
	162
	163	switch (cmd) {
	164	case SNDRV_PCM_TRIGGER_START:
	165	case SNDRV_PCM_TRIGGER_RESUME:
	166	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	167	ctrl \|= mask;
	168	break;
	169	case SNDRV_PCM_TRIGGER_STOP:
	170	case SNDRV_PCM_TRIGGER_SUSPEND:
	171	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	172	ctrl &= ~mask;
	173	break;
	174	default:
	175	return -EINVAL;
	176	}
	177
	178	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
	179
	180	return 0;
	181	}
	182
	183	static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
	184	{
f0fba2ad	185	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	186
	187	uint32_t format = 0;
	188	uint32_t conf;
	189
	190	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	191
	192	conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER \| JZ_AIC_CONF_SYNC_CLK_MASTER);
	193
	194	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	195	case SND_SOC_DAIFMT_CBS_CFS:
	196	conf \|= JZ_AIC_CONF_BIT_CLK_MASTER \| JZ_AIC_CONF_SYNC_CLK_MASTER;
	197	format \|= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
	198	break;
	199	case SND_SOC_DAIFMT_CBM_CFS:
	200	conf \|= JZ_AIC_CONF_SYNC_CLK_MASTER;
	201	break;
	202	case SND_SOC_DAIFMT_CBS_CFM:
	203	conf \|= JZ_AIC_CONF_BIT_CLK_MASTER;
	204	break;
	205	case SND_SOC_DAIFMT_CBM_CFM:
	206	break;
	207	default:
	208	return -EINVAL;
	209	}
	210
	211	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	212	case SND_SOC_DAIFMT_MSB:
	213	format \|= JZ_AIC_I2S_FMT_MSB;
	214	break;
	215	case SND_SOC_DAIFMT_I2S:
	216	break;
	217	default:
	218	return -EINVAL;
	219	}
	220
	221	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	222	case SND_SOC_DAIFMT_NB_NF:
	223	break;
	224	default:
	225	return -EINVAL;
	226	}
	227
	228	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	229	jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
	230
	231	return 0;
	232	}
	233
	234	static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
	235	struct snd_pcm_hw_params params, struct snd_soc_dai dai)
	236	{
f0fba2ad	237	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	238	unsigned int sample_size;
	239	uint32_t ctrl;
	240
	241	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
	242
	243	switch (params_format(params)) {
	244	case SNDRV_PCM_FORMAT_S8:
	245	sample_size = 0;
11bd3dd1 LPC	246	break;
	247	case SNDRV_PCM_FORMAT_S16:
	248	sample_size = 1;
11bd3dd1 LPC	249	break;
	250	default:
	251	return -EINVAL;
	252	}
	253
	254	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	255	ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
	256	ctrl \|= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
	257	if (params_channels(params) == 1)
	258	ctrl \|= JZ_AIC_CTRL_MONO_TO_STEREO;
	259	else
	260	ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
11bd3dd1 LPC	261	} else {
	262	ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
	263	ctrl \|= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
11bd3dd1 LPC	264	}
	265
	266	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
	267
11bd3dd1 LPC	268	return 0;
	269	}
	270
	271	static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
	272	unsigned int freq, int dir)
	273	{
f0fba2ad	274	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	275	struct clk *parent;
	276	int ret = 0;
	277
	278	switch (clk_id) {
	279	case JZ4740_I2S_CLKSRC_EXT:
	280	parent = clk_get(NULL, "ext");
	281	clk_set_parent(i2s->clk_i2s, parent);
	282	break;
	283	case JZ4740_I2S_CLKSRC_PLL:
	284	parent = clk_get(NULL, "pll half");
	285	clk_set_parent(i2s->clk_i2s, parent);
	286	ret = clk_set_rate(i2s->clk_i2s, freq);
	287	break;
	288	default:
	289	return -EINVAL;
	290	}
	291	clk_put(parent);
	292
	293	return ret;
	294	}
	295
	296	static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
	297	{
f0fba2ad	298	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	299	uint32_t conf;
	300
	301	if (dai->active) {
	302	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	303	conf &= ~JZ_AIC_CONF_ENABLE;
	304	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	305
010187fb	306	clk_disable_unprepare(i2s->clk_i2s);
11bd3dd1 LPC	307	}
11bd3dd1 LPC	308
010187fb	309	clk_disable_unprepare(i2s->clk_aic);
11bd3dd1 LPC	310
	311	return 0;
	312	}
	313
	314	static int jz4740_i2s_resume(struct snd_soc_dai *dai)
	315	{
f0fba2ad	316	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	317	uint32_t conf;
11bd3dd1 LPC	318
010187fb	319	clk_prepare_enable(i2s->clk_aic);
11bd3dd1 LPC	320
11bd3dd1 LPC	321	if (dai->active) {
010187fb	322	clk_prepare_enable(i2s->clk_i2s);
11bd3dd1 LPC	323
	324	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
	325	conf \|= JZ_AIC_CONF_ENABLE;
	326	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	327	}
	328
	329	return 0;
	330	}
	331
f0fba2ad	332	static void jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
11bd3dd1	333	{
0406a40a	334	struct snd_dmaengine_dai_dma_data *dma_data;
f0fba2ad LG	335
f0fba2ad LG	336	/* Playback */
0406a40a LPC	337	dma_data = &i2s->playback_dma_data;
	338	dma_data->maxburst = 16;
	339	dma_data->slave_id = JZ4740_DMA_TYPE_AIC_TRANSMIT;
	340	dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
f0fba2ad LG	341
f0fba2ad LG	342	/* Capture */
0406a40a LPC	343	dma_data = &i2s->capture_dma_data;
	344	dma_data->maxburst = 16;
	345	dma_data->slave_id = JZ4740_DMA_TYPE_AIC_RECEIVE;
	346	dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
f0fba2ad LG	347	}
	348
	349	static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
	350	{
	351	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
11bd3dd1 LPC	352	uint32_t conf;
11bd3dd1 LPC	353
010187fb	354	clk_prepare_enable(i2s->clk_aic);
f0fba2ad LG	355
f0fba2ad LG	356	jz4740_i2c_init_pcm_config(i2s);
0406a40a LPC	357	snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
0406a40a LPC	358	&i2s->capture_dma_data);
f0fba2ad	359
11bd3dd1 LPC	360	conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) \|
	361	(8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) \|
	362	JZ_AIC_CONF_OVERFLOW_PLAY_LAST \|
	363	JZ_AIC_CONF_I2S \|
	364	JZ_AIC_CONF_INTERNAL_CODEC;
	365
	366	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
	367	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
	368
	369	return 0;
	370	}
	371
f0fba2ad LG	372	static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
	373	{
	374	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
	375
010187fb	376	clk_disable_unprepare(i2s->clk_aic);
f0fba2ad LG	377	return 0;
	378	}
	379
85e7652d	380	static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
11bd3dd1 LPC	381	.startup = jz4740_i2s_startup,
	382	.shutdown = jz4740_i2s_shutdown,
	383	.trigger = jz4740_i2s_trigger,
	384	.hw_params = jz4740_i2s_hw_params,
	385	.set_fmt = jz4740_i2s_set_fmt,
	386	.set_sysclk = jz4740_i2s_set_sysclk,
	387	};
	388
	389	#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 \| \
	390	SNDRV_PCM_FMTBIT_S16_LE)
	391
f0fba2ad LG	392	static struct snd_soc_dai_driver jz4740_i2s_dai = {
	393	.probe = jz4740_i2s_dai_probe,
	394	.remove = jz4740_i2s_dai_remove,
11bd3dd1 LPC	395	.playback = {
	396	.channels_min = 1,
	397	.channels_max = 2,
	398	.rates = SNDRV_PCM_RATE_8000_48000,
	399	.formats = JZ4740_I2S_FMTS,
	400	},
	401	.capture = {
	402	.channels_min = 2,
	403	.channels_max = 2,
	404	.rates = SNDRV_PCM_RATE_8000_48000,
	405	.formats = JZ4740_I2S_FMTS,
	406	},
	407	.symmetric_rates = 1,
	408	.ops = &jz4740_i2s_dai_ops,
	409	.suspend = jz4740_i2s_suspend,
	410	.resume = jz4740_i2s_resume,
	411	};
11bd3dd1	412
29cc15cf KM	413	static const struct snd_soc_component_driver jz4740_i2s_component = {
	414	.name = "jz4740-i2s",
	415	};
	416
d6a29e3d	417	static int jz4740_i2s_dev_probe(struct platform_device *pdev)
11bd3dd1 LPC	418	{
11bd3dd1 LPC	419	struct jz4740_i2s *i2s;
b84c9ce8	420	struct resource *mem;
11bd3dd1 LPC	421	int ret;
11bd3dd1 LPC	422
b84c9ce8	423	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
11bd3dd1 LPC	424	if (!i2s)
	425	return -ENOMEM;
	426
b84c9ce8 LPC	427	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	428	i2s->base = devm_ioremap_resource(&pdev->dev, mem);
	429	if (IS_ERR(i2s->base))
	430	return PTR_ERR(i2s->base);
11bd3dd1	431
b84c9ce8	432	i2s->phys_base = mem->start;
11bd3dd1	433
b84c9ce8 LPC	434	i2s->clk_aic = devm_clk_get(&pdev->dev, "aic");
	435	if (IS_ERR(i2s->clk_aic))
	436	return PTR_ERR(i2s->clk_aic);
11bd3dd1	437
b84c9ce8 LPC	438	i2s->clk_i2s = devm_clk_get(&pdev->dev, "i2s");
	439	if (IS_ERR(i2s->clk_i2s))
	440	return PTR_ERR(i2s->clk_i2s);
11bd3dd1	441
f0fba2ad	442	platform_set_drvdata(pdev, i2s);
11bd3dd1	443
0406a40a	444	ret = devm_snd_soc_register_component(&pdev->dev,
b84c9ce8	445	&jz4740_i2s_component, &jz4740_i2s_dai, 1);
0406a40a LPC	446	if (ret)
	447	return ret;
	448
	449	return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
	450	SND_DMAENGINE_PCM_FLAG_COMPAT);
11bd3dd1 LPC	451	}
	452
	453	static struct platform_driver jz4740_i2s_driver = {
	454	.probe = jz4740_i2s_dev_probe,
11bd3dd1 LPC	455	.driver = {
	456	.name = "jz4740-i2s",
	457	.owner = THIS_MODULE,
	458	},
	459	};
	460
c32986e6	461	module_platform_driver(jz4740_i2s_driver);
11bd3dd1 LPC	462
	463	MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
	464	MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
	465	MODULE_LICENSE("GPL");
	466	MODULE_ALIAS("platform:jz4740-i2s");