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Merge remote-tracking branch 'asoc/topic/w-codec' into asoc-next
[linux-2.6-block.git] / sound / soc / intel / sst-haswell-ipc.c
CommitLineData
a4b12990
MB		 1/*
2 * Intel SST Haswell/Broadwell IPC Support
3 *
4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/types.h>
18#include <linux/kernel.h>
19#include <linux/list.h>
20#include <linux/device.h>
21#include <linux/wait.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/export.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
a4b12990
MB		 28#include <linux/platform_device.h>
29#include <linux/kthread.h>
30#include <linux/firmware.h>
31#include <linux/dma-mapping.h>
32#include <linux/debugfs.h>
aed3c7b7 33#include <linux/pm_runtime.h>
a4b12990
MB		 34
35#include "sst-haswell-ipc.h"
36#include "sst-dsp.h"
37#include "sst-dsp-priv.h"
38
39/* Global Message - Generic */
40#define IPC_GLB_TYPE_SHIFT 24
41#define IPC_GLB_TYPE_MASK (0x1f << IPC_GLB_TYPE_SHIFT)
42#define IPC_GLB_TYPE(x) (x << IPC_GLB_TYPE_SHIFT)
43
44/* Global Message - Reply */
45#define IPC_GLB_REPLY_SHIFT 0
46#define IPC_GLB_REPLY_MASK (0x1f << IPC_GLB_REPLY_SHIFT)
47#define IPC_GLB_REPLY_TYPE(x) (x << IPC_GLB_REPLY_TYPE_SHIFT)
48
49/* Stream Message - Generic */
50#define IPC_STR_TYPE_SHIFT 20
51#define IPC_STR_TYPE_MASK (0xf << IPC_STR_TYPE_SHIFT)
52#define IPC_STR_TYPE(x) (x << IPC_STR_TYPE_SHIFT)
53#define IPC_STR_ID_SHIFT 16
54#define IPC_STR_ID_MASK (0xf << IPC_STR_ID_SHIFT)
55#define IPC_STR_ID(x) (x << IPC_STR_ID_SHIFT)
56
57/* Stream Message - Reply */
58#define IPC_STR_REPLY_SHIFT 0
59#define IPC_STR_REPLY_MASK (0x1f << IPC_STR_REPLY_SHIFT)
60
61/* Stream Stage Message - Generic */
62#define IPC_STG_TYPE_SHIFT 12
63#define IPC_STG_TYPE_MASK (0xf << IPC_STG_TYPE_SHIFT)
64#define IPC_STG_TYPE(x) (x << IPC_STG_TYPE_SHIFT)
65#define IPC_STG_ID_SHIFT 10
66#define IPC_STG_ID_MASK (0x3 << IPC_STG_ID_SHIFT)
67#define IPC_STG_ID(x) (x << IPC_STG_ID_SHIFT)
68
69/* Stream Stage Message - Reply */
70#define IPC_STG_REPLY_SHIFT 0
71#define IPC_STG_REPLY_MASK (0x1f << IPC_STG_REPLY_SHIFT)
72
73/* Debug Log Message - Generic */
74#define IPC_LOG_OP_SHIFT 20
75#define IPC_LOG_OP_MASK (0xf << IPC_LOG_OP_SHIFT)
76#define IPC_LOG_OP_TYPE(x) (x << IPC_LOG_OP_SHIFT)
77#define IPC_LOG_ID_SHIFT 16
78#define IPC_LOG_ID_MASK (0xf << IPC_LOG_ID_SHIFT)
79#define IPC_LOG_ID(x) (x << IPC_LOG_ID_SHIFT)
80
81/* IPC message timeout (msecs) */
82#define IPC_TIMEOUT_MSECS 300
83#define IPC_BOOT_MSECS 200
84#define IPC_MSG_WAIT 0
85#define IPC_MSG_NOWAIT 1
86
87/* Firmware Ready Message */
88#define IPC_FW_READY (0x1 << 29)
89#define IPC_STATUS_MASK (0x3 << 30)
90
91#define IPC_EMPTY_LIST_SIZE 8
92#define IPC_MAX_STREAMS 4
93
94/* Mailbox */
95#define IPC_MAX_MAILBOX_BYTES 256
96
97/* Global Message - Types and Replies */
98enum ipc_glb_type {
99 IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
100 IPC_GLB_PERFORMANCE_MONITOR = 1, /* Performance monitoring actions */
101 IPC_GLB_ALLOCATE_STREAM = 3, /* Request to allocate new stream */
102 IPC_GLB_FREE_STREAM = 4, /* Request to free stream */
103 IPC_GLB_GET_FW_CAPABILITIES = 5, /* Retrieves firmware capabilities */
104 IPC_GLB_STREAM_MESSAGE = 6, /* Message directed to stream or its stages */
105 /* Request to store firmware context during D0->D3 transition */
106 IPC_GLB_REQUEST_DUMP = 7,
107 /* Request to restore firmware context during D3->D0 transition */
108 IPC_GLB_RESTORE_CONTEXT = 8,
109 IPC_GLB_GET_DEVICE_FORMATS = 9, /* Set device format */
110 IPC_GLB_SET_DEVICE_FORMATS = 10, /* Get device format */
111 IPC_GLB_SHORT_REPLY = 11,
112 IPC_GLB_ENTER_DX_STATE = 12,
113 IPC_GLB_GET_MIXER_STREAM_INFO = 13, /* Request mixer stream params */
114 IPC_GLB_DEBUG_LOG_MESSAGE = 14, /* Message to or from the debug logger. */
115 IPC_GLB_REQUEST_TRANSFER = 16, /* < Request Transfer for host */
116 IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17, /* Maximum message number */
117};
118
119enum ipc_glb_reply {
120 IPC_GLB_REPLY_SUCCESS = 0, /* The operation was successful. */
121 IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1, /* Invalid parameter was passed. */
122 IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */
123 IPC_GLB_REPLY_OUT_OF_RESOURCES = 3, /* No resources to satisfy the request. */
124 IPC_GLB_REPLY_BUSY = 4, /* The system or resource is busy. */
125 IPC_GLB_REPLY_PENDING = 5, /* The action was scheduled for processing. */
126 IPC_GLB_REPLY_FAILURE = 6, /* Critical error happened. */
127 IPC_GLB_REPLY_INVALID_REQUEST = 7, /* Request can not be completed. */
128 IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8, /* Processing stage was uninitialized. */
129 IPC_GLB_REPLY_NOT_FOUND = 9, /* Required resource can not be found. */
130 IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10, /* Source was not started. */
131};
132
133/* Stream Message - Types */
134enum ipc_str_operation {
135 IPC_STR_RESET = 0,
136 IPC_STR_PAUSE = 1,
137 IPC_STR_RESUME = 2,
138 IPC_STR_STAGE_MESSAGE = 3,
139 IPC_STR_NOTIFICATION = 4,
140 IPC_STR_MAX_MESSAGE
141};
142
143/* Stream Stage Message Types */
144enum ipc_stg_operation {
145 IPC_STG_GET_VOLUME = 0,
146 IPC_STG_SET_VOLUME,
147 IPC_STG_SET_WRITE_POSITION,
148 IPC_STG_SET_FX_ENABLE,
149 IPC_STG_SET_FX_DISABLE,
150 IPC_STG_SET_FX_GET_PARAM,
151 IPC_STG_SET_FX_SET_PARAM,
152 IPC_STG_SET_FX_GET_INFO,
153 IPC_STG_MUTE_LOOPBACK,
154 IPC_STG_MAX_MESSAGE
155};
156
157/* Stream Stage Message Types For Notification*/
158enum ipc_stg_operation_notify {
159 IPC_POSITION_CHANGED = 0,
160 IPC_STG_GLITCH,
161 IPC_STG_MAX_NOTIFY
162};
163
164enum ipc_glitch_type {
165 IPC_GLITCH_UNDERRUN = 1,
166 IPC_GLITCH_DECODER_ERROR,
167 IPC_GLITCH_DOUBLED_WRITE_POS,
168 IPC_GLITCH_MAX
169};
170
171/* Debug Control */
172enum ipc_debug_operation {
173 IPC_DEBUG_ENABLE_LOG = 0,
174 IPC_DEBUG_DISABLE_LOG = 1,
175 IPC_DEBUG_REQUEST_LOG_DUMP = 2,
176 IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
177 IPC_DEBUG_MAX_DEBUG_LOG
178};
179
180/* Firmware Ready */
181struct sst_hsw_ipc_fw_ready {
182 u32 inbox_offset;
183 u32 outbox_offset;
184 u32 inbox_size;
185 u32 outbox_size;
186 u32 fw_info_size;
249adddb 187 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
a4b12990
MB		 188} __attribute__((packed));
189
190struct ipc_message {
191 struct list_head list;
192 u32 header;
193
194 /* direction wrt host CPU */
195 char tx_data[IPC_MAX_MAILBOX_BYTES];
196 size_t tx_size;
197 char rx_data[IPC_MAX_MAILBOX_BYTES];
198 size_t rx_size;
199
200 wait_queue_head_t waitq;
201 bool pending;
202 bool complete;
203 bool wait;
204 int errno;
205};
206
207struct sst_hsw_stream;
208struct sst_hsw;
209
210/* Stream infomation */
211struct sst_hsw_stream {
212 /* configuration */
213 struct sst_hsw_ipc_stream_alloc_req request;
214 struct sst_hsw_ipc_stream_alloc_reply reply;
215 struct sst_hsw_ipc_stream_free_req free_req;
216
217 /* Mixer info */
218 u32 mute_volume[SST_HSW_NO_CHANNELS];
219 u32 mute[SST_HSW_NO_CHANNELS];
220
221 /* runtime info */
222 struct sst_hsw *hsw;
223 int host_id;
224 bool commited;
225 bool running;
226
227 /* Notification work */
228 struct work_struct notify_work;
229 u32 header;
230
231 /* Position info from DSP */
232 struct sst_hsw_ipc_stream_set_position wpos;
233 struct sst_hsw_ipc_stream_get_position rpos;
234 struct sst_hsw_ipc_stream_glitch_position glitch;
235
236 /* Volume info */
237 struct sst_hsw_ipc_volume_req vol_req;
238
239 /* driver callback */
240 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
241 void *pdata;
242
243 struct list_head node;
244};
245
246/* FW log ring information */
247struct sst_hsw_log_stream {
248 dma_addr_t dma_addr;
249 unsigned char *dma_area;
250 unsigned char *ring_descr;
251 int pages;
252 int size;
253
254 /* Notification work */
255 struct work_struct notify_work;
256 wait_queue_head_t readers_wait_q;
257 struct mutex rw_mutex;
258
259 u32 last_pos;
260 u32 curr_pos;
261 u32 reader_pos;
262
263 /* fw log config */
264 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
265
266 struct sst_hsw *hsw;
267};
268
269/* SST Haswell IPC data */
270struct sst_hsw {
271 struct device *dev;
272 struct sst_dsp *dsp;
273 struct platform_device *pdev_pcm;
274
275 /* FW config */
276 struct sst_hsw_ipc_fw_ready fw_ready;
277 struct sst_hsw_ipc_fw_version version;
278 struct sst_module *scratch;
279 bool fw_done;
aed3c7b7 280 struct sst_fw *sst_fw;
a4b12990
MB		 281
282 /* stream */
283 struct list_head stream_list;
284
285 /* global mixer */
286 struct sst_hsw_ipc_stream_info_reply mixer_info;
287 enum sst_hsw_volume_curve curve_type;
288 u32 curve_duration;
289 u32 mute[SST_HSW_NO_CHANNELS];
290 u32 mute_volume[SST_HSW_NO_CHANNELS];
291
292 /* DX */
293 struct sst_hsw_ipc_dx_reply dx;
aed3c7b7
LG		 294 void *dx_context;
295 dma_addr_t dx_context_paddr;
a4b12990
MB		 296
297 /* boot */
298 wait_queue_head_t boot_wait;
299 bool boot_complete;
300 bool shutdown;
301
302 /* IPC messaging */
303 struct list_head tx_list;
304 struct list_head rx_list;
305 struct list_head empty_list;
306 wait_queue_head_t wait_txq;
307 struct task_struct *tx_thread;
308 struct kthread_worker kworker;
309 struct kthread_work kwork;
310 bool pending;
311 struct ipc_message *msg;
312
313 /* FW log stream */
314 struct sst_hsw_log_stream log_stream;
315};
316
317#define CREATE_TRACE_POINTS
318#include <trace/events/hswadsp.h>
319
320static inline u32 msg_get_global_type(u32 msg)
321{
322 return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
323}
324
325static inline u32 msg_get_global_reply(u32 msg)
326{
327 return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
328}
329
330static inline u32 msg_get_stream_type(u32 msg)
331{
332 return (msg & IPC_STR_TYPE_MASK) >> IPC_STR_TYPE_SHIFT;
333}
334
335static inline u32 msg_get_stage_type(u32 msg)
336{
337 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
338}
339
340static inline u32 msg_set_stage_type(u32 msg, u32 type)
341{
342 return (msg & ~IPC_STG_TYPE_MASK) +
343 (type << IPC_STG_TYPE_SHIFT);
344}
345
346static inline u32 msg_get_stream_id(u32 msg)
347{
348 return (msg & IPC_STR_ID_MASK) >> IPC_STR_ID_SHIFT;
349}
350
351static inline u32 msg_get_notify_reason(u32 msg)
352{
353 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
354}
355
356u32 create_channel_map(enum sst_hsw_channel_config config)
357{
358 switch (config) {
359 case SST_HSW_CHANNEL_CONFIG_MONO:
360 return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
361 case SST_HSW_CHANNEL_CONFIG_STEREO:
362 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
363 | (SST_HSW_CHANNEL_RIGHT << 4));
364 case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
365 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
366 | (SST_HSW_CHANNEL_RIGHT << 4)
367 | (SST_HSW_CHANNEL_LFE << 8 ));
368 case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
369 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
370 | (SST_HSW_CHANNEL_CENTER << 4)
371 | (SST_HSW_CHANNEL_RIGHT << 8));
372 case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
373 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
374 | (SST_HSW_CHANNEL_CENTER << 4)
375 | (SST_HSW_CHANNEL_RIGHT << 8)
376 | (SST_HSW_CHANNEL_LFE << 12));
377 case SST_HSW_CHANNEL_CONFIG_QUATRO:
378 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
379 | (SST_HSW_CHANNEL_RIGHT << 4)
380 | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
381 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
382 case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
383 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
384 | (SST_HSW_CHANNEL_CENTER << 4)
385 | (SST_HSW_CHANNEL_RIGHT << 8)
386 | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
387 case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
388 return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
389 | (SST_HSW_CHANNEL_CENTER << 4)
390 | (SST_HSW_CHANNEL_RIGHT << 8)
391 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
392 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
393 case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
394 return (0xFF000000 | SST_HSW_CHANNEL_CENTER
395 | (SST_HSW_CHANNEL_LEFT << 4)
396 | (SST_HSW_CHANNEL_RIGHT << 8)
397 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
398 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
399 | (SST_HSW_CHANNEL_LFE << 20));
400 case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
401 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
402 | (SST_HSW_CHANNEL_LEFT << 4));
403 default:
404 return 0xFFFFFFFF;
405 }
406}
407
408static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
409 int stream_id)
410{
411 struct sst_hsw_stream *stream;
412
413 list_for_each_entry(stream, &hsw->stream_list, node) {
414 if (stream->reply.stream_hw_id == stream_id)
415 return stream;
416 }
417
418 return NULL;
419}
420
421static void ipc_shim_dbg(struct sst_hsw *hsw, const char *text)
422{
423 struct sst_dsp *sst = hsw->dsp;
424 u32 isr, ipcd, imrx, ipcx;
425
426 ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
427 isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
428 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
429 imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
430
431 dev_err(hsw->dev, "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
432 text, ipcx, isr, ipcd, imrx);
433}
434
435/* locks held by caller */
436static struct ipc_message *msg_get_empty(struct sst_hsw *hsw)
437{
438 struct ipc_message *msg = NULL;
439
440 if (!list_empty(&hsw->empty_list)) {
441 msg = list_first_entry(&hsw->empty_list, struct ipc_message,
442 list);
443 list_del(&msg->list);
444 }
445
446 return msg;
447}
448
449static void ipc_tx_msgs(struct kthread_work *work)
450{
451 struct sst_hsw *hsw =
452 container_of(work, struct sst_hsw, kwork);
453 struct ipc_message *msg;
454 unsigned long flags;
455 u32 ipcx;
456
457 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
458
459 if (list_empty(&hsw->tx_list) || hsw->pending) {
460 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
461 return;
462 }
463
94ce3345
PP		 464 /* if the DSP is busy, we will TX messages after IRQ.
465 * also postpone if we are in the middle of procesing completion irq*/
a4b12990 466 ipcx = sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX);
94ce3345 467 if (ipcx & (SST_IPCX_BUSY | SST_IPCX_DONE)) {
a4b12990
MB		 468 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
469 return;
470 }
471
472 msg = list_first_entry(&hsw->tx_list, struct ipc_message, list);
473
474 list_move(&msg->list, &hsw->rx_list);
475
476 /* send the message */
477 sst_dsp_outbox_write(hsw->dsp, msg->tx_data, msg->tx_size);
478 sst_dsp_ipc_msg_tx(hsw->dsp, msg->header | SST_IPCX_BUSY);
479
480 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
481}
482
483/* locks held by caller */
484static void tx_msg_reply_complete(struct sst_hsw *hsw, struct ipc_message *msg)
485{
486 msg->complete = true;
487 trace_ipc_reply("completed", msg->header);
488
489 if (!msg->wait)
490 list_add_tail(&msg->list, &hsw->empty_list);
491 else
492 wake_up(&msg->waitq);
493}
494
495static int tx_wait_done(struct sst_hsw *hsw, struct ipc_message *msg,
496 void *rx_data)
497{
498 unsigned long flags;
499 int ret;
500
501 /* wait for DSP completion (in all cases atm inc pending) */
502 ret = wait_event_timeout(msg->waitq, msg->complete,
503 msecs_to_jiffies(IPC_TIMEOUT_MSECS));
504
505 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
506 if (ret == 0) {
507 ipc_shim_dbg(hsw, "message timeout");
508
509 trace_ipc_error("error message timeout for", msg->header);
97cfc751 510 list_del(&msg->list);
a4b12990
MB		 511 ret = -ETIMEDOUT;
512 } else {
513
514 /* copy the data returned from DSP */
515 if (msg->rx_size)
516 memcpy(rx_data, msg->rx_data, msg->rx_size);
517 ret = msg->errno;
518 }
519
520 list_add_tail(&msg->list, &hsw->empty_list);
521 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
522 return ret;
523}
524
525static int ipc_tx_message(struct sst_hsw *hsw, u32 header, void *tx_data,
526 size_t tx_bytes, void *rx_data, size_t rx_bytes, int wait)
527{
528 struct ipc_message *msg;
529 unsigned long flags;
530
531 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
532
533 msg = msg_get_empty(hsw);
534 if (msg == NULL) {
535 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
536 return -EBUSY;
537 }
538
539 if (tx_bytes)
540 memcpy(msg->tx_data, tx_data, tx_bytes);
541
542 msg->header = header;
543 msg->tx_size = tx_bytes;
544 msg->rx_size = rx_bytes;
545 msg->wait = wait;
546 msg->errno = 0;
547 msg->pending = false;
548 msg->complete = false;
549
550 list_add_tail(&msg->list, &hsw->tx_list);
551 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
552
553 queue_kthread_work(&hsw->kworker, &hsw->kwork);
554
555 if (wait)
556 return tx_wait_done(hsw, msg, rx_data);
557 else
558 return 0;
559}
560
561static inline int ipc_tx_message_wait(struct sst_hsw *hsw, u32 header,
562 void *tx_data, size_t tx_bytes, void *rx_data, size_t rx_bytes)
563{
564 return ipc_tx_message(hsw, header, tx_data, tx_bytes, rx_data,
565 rx_bytes, 1);
566}
567
568static inline int ipc_tx_message_nowait(struct sst_hsw *hsw, u32 header,
569 void *tx_data, size_t tx_bytes)
570{
571 return ipc_tx_message(hsw, header, tx_data, tx_bytes, NULL, 0, 0);
572}
573
574static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
575{
576 struct sst_hsw_ipc_fw_ready fw_ready;
577 u32 offset;
249adddb
JY		 578 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
579 char *tmp[5], *pinfo;
580 int i = 0;
a4b12990
MB		 581
582 offset = (header & 0x1FFFFFFF) << 3;
583
584 dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
585 header, offset);
586
587 /* copy data from the DSP FW ready offset */
588 sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
589
590 sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
591 fw_ready.inbox_size, fw_ready.outbox_offset,
592 fw_ready.outbox_size);
593
594 hsw->boot_complete = true;
595 wake_up(&hsw->boot_wait);
596
597 dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
598 fw_ready.inbox_offset, fw_ready.inbox_size);
599 dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
600 fw_ready.outbox_offset, fw_ready.outbox_size);
249adddb
JY		 601 if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) {
602 fw_ready.fw_info[fw_ready.fw_info_size] = 0;
603 dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info);
604
605 /* log the FW version info got from the mailbox here. */
606 memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size);
607 pinfo = &fw_info[0];
608 for (i = 0; i < sizeof(tmp) / sizeof(char *); i++)
609 tmp[i] = strsep(&pinfo, " ");
610 dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - "
611 "version: %s.%s, build %s, source commit id: %s\n",
612 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]);
613 }
a4b12990
MB		 614}
615
616static void hsw_notification_work(struct work_struct *work)
617{
618 struct sst_hsw_stream *stream = container_of(work,
619 struct sst_hsw_stream, notify_work);
620 struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
621 struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
622 struct sst_hsw *hsw = stream->hsw;
623 u32 reason;
624
625 reason = msg_get_notify_reason(stream->header);
626
627 switch (reason) {
628 case IPC_STG_GLITCH:
629 trace_ipc_notification("DSP stream under/overrun",
630 stream->reply.stream_hw_id);
631 sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
632
633 dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
634 glitch->glitch_type, glitch->present_pos,
635 glitch->write_pos);
636 break;
637
638 case IPC_POSITION_CHANGED:
639 trace_ipc_notification("DSP stream position changed for",
640 stream->reply.stream_hw_id);
7897ab78 641 sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
a4b12990
MB		 642
643 if (stream->notify_position)
644 stream->notify_position(stream, stream->pdata);
645
646 break;
647 default:
648 dev_err(hsw->dev, "error: unknown notification 0x%x\n",
649 stream->header);
650 break;
651 }
652
653 /* tell DSP that notification has been handled */
09a34aa5 654 sst_dsp_shim_update_bits(hsw->dsp, SST_IPCD,
a4b12990
MB		 655 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
656
657 /* unmask busy interrupt */
09a34aa5 658 sst_dsp_shim_update_bits(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
a4b12990
MB		 659}
660
661static struct ipc_message *reply_find_msg(struct sst_hsw *hsw, u32 header)
662{
663 struct ipc_message *msg;
664
665 /* clear reply bits & status bits */
666 header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
667
668 if (list_empty(&hsw->rx_list)) {
669 dev_err(hsw->dev, "error: rx list empty but received 0x%x\n",
670 header);
671 return NULL;
672 }
673
674 list_for_each_entry(msg, &hsw->rx_list, list) {
675 if (msg->header == header)
676 return msg;
677 }
678
679 return NULL;
680}
681
682static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
683{
684 struct sst_hsw_stream *stream;
685 u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
686 u32 stream_id = msg_get_stream_id(header);
687 u32 stream_msg = msg_get_stream_type(header);
688
689 stream = get_stream_by_id(hsw, stream_id);
690 if (stream == NULL)
691 return;
692
693 switch (stream_msg) {
694 case IPC_STR_STAGE_MESSAGE:
695 case IPC_STR_NOTIFICATION:
81552612 696 break;
a4b12990 697 case IPC_STR_RESET:
81552612 698 trace_ipc_notification("stream reset", stream->reply.stream_hw_id);
a4b12990
MB		 699 break;
700 case IPC_STR_PAUSE:
701 stream->running = false;
702 trace_ipc_notification("stream paused",
703 stream->reply.stream_hw_id);
704 break;
705 case IPC_STR_RESUME:
706 stream->running = true;
707 trace_ipc_notification("stream running",
708 stream->reply.stream_hw_id);
709 break;
710 }
711}
712
713static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
714{
715 struct ipc_message *msg;
716 u32 reply = msg_get_global_reply(header);
717
718 trace_ipc_reply("processing -->", header);
719
720 msg = reply_find_msg(hsw, header);
721 if (msg == NULL) {
722 trace_ipc_error("error: can't find message header", header);
723 return -EIO;
724 }
725
726 /* first process the header */
727 switch (reply) {
728 case IPC_GLB_REPLY_PENDING:
729 trace_ipc_pending_reply("received", header);
730 msg->pending = true;
731 hsw->pending = true;
732 return 1;
733 case IPC_GLB_REPLY_SUCCESS:
734 if (msg->pending) {
735 trace_ipc_pending_reply("completed", header);
736 sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
737 msg->rx_size);
738 hsw->pending = false;
739 } else {
740 /* copy data from the DSP */
741 sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
742 msg->rx_size);
743 }
744 break;
745 /* these will be rare - but useful for debug */
746 case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
747 trace_ipc_error("error: unknown message type", header);
748 msg->errno = -EBADMSG;
749 break;
750 case IPC_GLB_REPLY_OUT_OF_RESOURCES:
751 trace_ipc_error("error: out of resources", header);
752 msg->errno = -ENOMEM;
753 break;
754 case IPC_GLB_REPLY_BUSY:
755 trace_ipc_error("error: reply busy", header);
756 msg->errno = -EBUSY;
757 break;
758 case IPC_GLB_REPLY_FAILURE:
759 trace_ipc_error("error: reply failure", header);
760 msg->errno = -EINVAL;
761 break;
762 case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
763 trace_ipc_error("error: stage uninitialized", header);
764 msg->errno = -EINVAL;
765 break;
766 case IPC_GLB_REPLY_NOT_FOUND:
767 trace_ipc_error("error: reply not found", header);
768 msg->errno = -EINVAL;
769 break;
770 case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
771 trace_ipc_error("error: source not started", header);
772 msg->errno = -EINVAL;
773 break;
774 case IPC_GLB_REPLY_INVALID_REQUEST:
775 trace_ipc_error("error: invalid request", header);
776 msg->errno = -EINVAL;
777 break;
778 case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
779 trace_ipc_error("error: invalid parameter", header);
780 msg->errno = -EINVAL;
781 break;
782 default:
783 trace_ipc_error("error: unknown reply", header);
784 msg->errno = -EINVAL;
785 break;
786 }
787
788 /* update any stream states */
d6e08617
PP		 789 if (msg_get_global_type(header) == IPC_GLB_STREAM_MESSAGE)
790 hsw_stream_update(hsw, msg);
a4b12990
MB		 791
792 /* wake up and return the error if we have waiters on this message ? */
793 list_del(&msg->list);
794 tx_msg_reply_complete(hsw, msg);
795
796 return 1;
797}
798
799static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
800{
801 u32 stream_msg, stream_id, stage_type;
802 struct sst_hsw_stream *stream;
803 int handled = 0;
804
805 stream_msg = msg_get_stream_type(header);
806 stream_id = msg_get_stream_id(header);
807 stage_type = msg_get_stage_type(header);
808
809 stream = get_stream_by_id(hsw, stream_id);
810 if (stream == NULL)
811 return handled;
812
813 stream->header = header;
814
815 switch (stream_msg) {
816 case IPC_STR_STAGE_MESSAGE:
817 dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
818 header);
819 break;
820 case IPC_STR_NOTIFICATION:
821 schedule_work(&stream->notify_work);
822 break;
823 default:
824 /* handle pending message complete request */
825 handled = hsw_process_reply(hsw, header);
826 break;
827 }
828
829 return handled;
830}
831
832static int hsw_log_message(struct sst_hsw *hsw, u32 header)
833{
834 u32 operation = (header & IPC_LOG_OP_MASK) >> IPC_LOG_OP_SHIFT;
835 struct sst_hsw_log_stream *stream = &hsw->log_stream;
836 int ret = 1;
837
838 if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
839 dev_err(hsw->dev,
840 "error: log msg not implemented 0x%8.8x\n", header);
841 return 0;
842 }
843
844 mutex_lock(&stream->rw_mutex);
845 stream->last_pos = stream->curr_pos;
846 sst_dsp_inbox_read(
847 hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
848 mutex_unlock(&stream->rw_mutex);
849
850 schedule_work(&stream->notify_work);
851
852 return ret;
853}
854
855static int hsw_process_notification(struct sst_hsw *hsw)
856{
857 struct sst_dsp *sst = hsw->dsp;
858 u32 type, header;
859 int handled = 1;
860
861 header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
862 type = msg_get_global_type(header);
863
864 trace_ipc_request("processing -->", header);
865
866 /* FW Ready is a special case */
867 if (!hsw->boot_complete && header & IPC_FW_READY) {
868 hsw_fw_ready(hsw, header);
869 return handled;
870 }
871
872 switch (type) {
873 case IPC_GLB_GET_FW_VERSION:
874 case IPC_GLB_ALLOCATE_STREAM:
875 case IPC_GLB_FREE_STREAM:
876 case IPC_GLB_GET_FW_CAPABILITIES:
877 case IPC_GLB_REQUEST_DUMP:
878 case IPC_GLB_GET_DEVICE_FORMATS:
879 case IPC_GLB_SET_DEVICE_FORMATS:
880 case IPC_GLB_ENTER_DX_STATE:
881 case IPC_GLB_GET_MIXER_STREAM_INFO:
882 case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
883 case IPC_GLB_RESTORE_CONTEXT:
884 case IPC_GLB_SHORT_REPLY:
885 dev_err(hsw->dev, "error: message type %d header 0x%x\n",
886 type, header);
887 break;
888 case IPC_GLB_STREAM_MESSAGE:
889 handled = hsw_stream_message(hsw, header);
890 break;
891 case IPC_GLB_DEBUG_LOG_MESSAGE:
892 handled = hsw_log_message(hsw, header);
893 break;
894 default:
895 dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
896 type, header);
897 break;
898 }
899
900 return handled;
901}
902
903static irqreturn_t hsw_irq_thread(int irq, void *context)
904{
905 struct sst_dsp *sst = (struct sst_dsp *) context;
906 struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
907 u32 ipcx, ipcd;
908 int handled;
909 unsigned long flags;
910
911 spin_lock_irqsave(&sst->spinlock, flags);
912
913 ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
914 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
915
916 /* reply message from DSP */
917 if (ipcx & SST_IPCX_DONE) {
918
919 /* Handle Immediate reply from DSP Core */
920 handled = hsw_process_reply(hsw, ipcx);
921
922 if (handled > 0) {
923 /* clear DONE bit - tell DSP we have completed */
924 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
925 SST_IPCX_DONE, 0);
926
927 /* unmask Done interrupt */
928 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
929 SST_IMRX_DONE, 0);
930 }
931 }
932
933 /* new message from DSP */
934 if (ipcd & SST_IPCD_BUSY) {
935
936 /* Handle Notification and Delayed reply from DSP Core */
937 handled = hsw_process_notification(hsw);
938
939 /* clear BUSY bit and set DONE bit - accept new messages */
940 if (handled > 0) {
941 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
942 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
943
944 /* unmask busy interrupt */
945 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
946 SST_IMRX_BUSY, 0);
947 }
948 }
949
950 spin_unlock_irqrestore(&sst->spinlock, flags);
951
952 /* continue to send any remaining messages... */
953 queue_kthread_work(&hsw->kworker, &hsw->kwork);
954
955 return IRQ_HANDLED;
956}
957
958int sst_hsw_fw_get_version(struct sst_hsw *hsw,
959 struct sst_hsw_ipc_fw_version *version)
960{
961 int ret;
962
963 ret = ipc_tx_message_wait(hsw, IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
964 NULL, 0, version, sizeof(*version));
965 if (ret < 0)
966 dev_err(hsw->dev, "error: get version failed\n");
967
968 return ret;
969}
970
971/* Mixer Controls */
972int sst_hsw_stream_mute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
973 u32 stage_id, u32 channel)
974{
975 int ret;
976
977 ret = sst_hsw_stream_get_volume(hsw, stream, stage_id, channel,
978 &stream->mute_volume[channel]);
979 if (ret < 0)
980 return ret;
981
982 ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel, 0);
983 if (ret < 0) {
984 dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
985 stream->reply.stream_hw_id, channel);
986 return ret;
987 }
988
989 stream->mute[channel] = 1;
990 return 0;
991}
992
993int sst_hsw_stream_unmute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
994 u32 stage_id, u32 channel)
995
996{
997 int ret;
998
999 stream->mute[channel] = 0;
1000 ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel,
1001 stream->mute_volume[channel]);
1002 if (ret < 0) {
1003 dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
1004 stream->reply.stream_hw_id, channel);
1005 return ret;
1006 }
1007
1008 return 0;
1009}
1010
1011int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1012 u32 stage_id, u32 channel, u32 *volume)
1013{
1014 if (channel > 1)
1015 return -EINVAL;
1016
1017 sst_dsp_read(hsw->dsp, volume,
bf657d24
CE		 1018 stream->reply.volume_register_address[channel],
1019 sizeof(*volume));
a4b12990
MB		 1020
1021 return 0;
1022}
1023
1024int sst_hsw_stream_set_volume_curve(struct sst_hsw *hsw,
1025 struct sst_hsw_stream *stream, u64 curve_duration,
1026 enum sst_hsw_volume_curve curve)
1027{
1028 /* curve duration in steps of 100ns */
1029 stream->vol_req.curve_duration = curve_duration;
1030 stream->vol_req.curve_type = curve;
1031
1032 return 0;
1033}
1034
1035/* stream volume */
1036int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
1037 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
1038{
1039 struct sst_hsw_ipc_volume_req *req;
1040 u32 header;
1041 int ret;
1042
1043 trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
1044
f1e59825 1045 if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
a4b12990
MB		 1046 return -EINVAL;
1047
a4b12990
MB		 1048 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1049 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1050 header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
1051 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
1052 header |= (stage_id << IPC_STG_ID_SHIFT);
1053
1054 req = &stream->vol_req;
a4b12990
MB		 1055 req->target_volume = volume;
1056
f1e59825
JY		 1057 /* set both at same time ? */
1058 if (channel == SST_HSW_CHANNELS_ALL) {
1059 if (hsw->mute[0] && hsw->mute[1]) {
1060 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
1061 return 0;
1062 } else if (hsw->mute[0])
1063 req->channel = 1;
1064 else if (hsw->mute[1])
1065 req->channel = 0;
1066 else
1067 req->channel = SST_HSW_CHANNELS_ALL;
1068 } else {
1069 /* set only 1 channel */
1070 if (hsw->mute[channel]) {
1071 hsw->mute_volume[channel] = volume;
1072 return 0;
1073 }
1074 req->channel = channel;
1075 }
1076
a4b12990
MB		 1077 ret = ipc_tx_message_wait(hsw, header, req, sizeof(*req), NULL, 0);
1078 if (ret < 0) {
1079 dev_err(hsw->dev, "error: set stream volume failed\n");
1080 return ret;
1081 }
1082
1083 return 0;
1084}
1085
1086int sst_hsw_mixer_mute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
1087{
1088 int ret;
1089
1090 ret = sst_hsw_mixer_get_volume(hsw, stage_id, channel,
1091 &hsw->mute_volume[channel]);
1092 if (ret < 0)
1093 return ret;
1094
1095 ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel, 0);
1096 if (ret < 0) {
1097 dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
1098 channel);
1099 return ret;
1100 }
1101
1102 hsw->mute[channel] = 1;
1103 return 0;
1104}
1105
1106int sst_hsw_mixer_unmute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
1107{
1108 int ret;
1109
1110 ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel,
1111 hsw->mixer_info.volume_register_address[channel]);
1112 if (ret < 0) {
1113 dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
1114 channel);
1115 return ret;
1116 }
1117
1118 hsw->mute[channel] = 0;
1119 return 0;
1120}
1121
1122int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
1123 u32 *volume)
1124{
1125 if (channel > 1)
1126 return -EINVAL;
1127
1128 sst_dsp_read(hsw->dsp, volume,
1129 hsw->mixer_info.volume_register_address[channel],
1130 sizeof(*volume));
1131
1132 return 0;
1133}
1134
1135int sst_hsw_mixer_set_volume_curve(struct sst_hsw *hsw,
1136 u64 curve_duration, enum sst_hsw_volume_curve curve)
1137{
1138 /* curve duration in steps of 100ns */
1139 hsw->curve_duration = curve_duration;
1140 hsw->curve_type = curve;
1141
1142 return 0;
1143}
1144
1145/* global mixer volume */
1146int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
1147 u32 volume)
1148{
1149 struct sst_hsw_ipc_volume_req req;
1150 u32 header;
1151 int ret;
1152
1153 trace_ipc_request("set mixer volume", volume);
1154
f1e59825
JY		 1155 if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
1156 return -EINVAL;
1157
a4b12990 1158 /* set both at same time ? */
f1e59825 1159 if (channel == SST_HSW_CHANNELS_ALL) {
a4b12990
MB		 1160 if (hsw->mute[0] && hsw->mute[1]) {
1161 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
1162 return 0;
1163 } else if (hsw->mute[0])
1164 req.channel = 1;
1165 else if (hsw->mute[1])
1166 req.channel = 0;
1167 else
f1e59825 1168 req.channel = SST_HSW_CHANNELS_ALL;
a4b12990
MB		 1169 } else {
1170 /* set only 1 channel */
1171 if (hsw->mute[channel]) {
1172 hsw->mute_volume[channel] = volume;
1173 return 0;
1174 }
1175 req.channel = channel;
1176 }
1177
1178 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1179 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1180 header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
1181 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
1182 header |= (stage_id << IPC_STG_ID_SHIFT);
1183
1184 req.curve_duration = hsw->curve_duration;
1185 req.curve_type = hsw->curve_type;
1186 req.target_volume = volume;
1187
1188 ret = ipc_tx_message_wait(hsw, header, &req, sizeof(req), NULL, 0);
1189 if (ret < 0) {
1190 dev_err(hsw->dev, "error: set mixer volume failed\n");
1191 return ret;
1192 }
1193
1194 return 0;
1195}
1196
1197/* Stream API */
1198struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
1199 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
1200 void *data)
1201{
1202 struct sst_hsw_stream *stream;
d132cb0a
WD		 1203 struct sst_dsp *sst = hsw->dsp;
1204 unsigned long flags;
a4b12990
MB		 1205
1206 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
1207 if (stream == NULL)
1208 return NULL;
1209
d132cb0a 1210 spin_lock_irqsave(&sst->spinlock, flags);
a4b12990
MB		 1211 list_add(&stream->node, &hsw->stream_list);
1212 stream->notify_position = notify_position;
1213 stream->pdata = data;
1214 stream->hsw = hsw;
1215 stream->host_id = id;
1216
1217 /* work to process notification messages */
1218 INIT_WORK(&stream->notify_work, hsw_notification_work);
d132cb0a 1219 spin_unlock_irqrestore(&sst->spinlock, flags);
a4b12990
MB		 1220
1221 return stream;
1222}
1223
1224int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1225{
1226 u32 header;
1227 int ret = 0;
d132cb0a
WD		 1228 struct sst_dsp *sst = hsw->dsp;
1229 unsigned long flags;
a4b12990 1230
f81677b4
JY		 1231 if (!stream) {
1232 dev_warn(hsw->dev, "warning: stream is NULL, no stream to free, ignore it.\n");
1233 return 0;
1234 }
1235
a4b12990
MB		 1236 /* dont free DSP streams that are not commited */
1237 if (!stream->commited)
1238 goto out;
1239
1240 trace_ipc_request("stream free", stream->host_id);
1241
1242 stream->free_req.stream_id = stream->reply.stream_hw_id;
1243 header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
1244
1245 ret = ipc_tx_message_wait(hsw, header, &stream->free_req,
1246 sizeof(stream->free_req), NULL, 0);
1247 if (ret < 0) {
1248 dev_err(hsw->dev, "error: free stream %d failed\n",
1249 stream->free_req.stream_id);
1250 return -EAGAIN;
1251 }
1252
1253 trace_hsw_stream_free_req(stream, &stream->free_req);
1254
1255out:
de30a2cc 1256 cancel_work_sync(&stream->notify_work);
d132cb0a 1257 spin_lock_irqsave(&sst->spinlock, flags);
a4b12990
MB		 1258 list_del(&stream->node);
1259 kfree(stream);
d132cb0a 1260 spin_unlock_irqrestore(&sst->spinlock, flags);
a4b12990
MB		 1261
1262 return ret;
1263}
1264
1265int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
1266 struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
1267{
1268 if (stream->commited) {
1269 dev_err(hsw->dev, "error: stream committed for set bits\n");
1270 return -EINVAL;
1271 }
1272
1273 stream->request.format.bitdepth = bits;
1274 return 0;
1275}
1276
1277int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
1278 struct sst_hsw_stream *stream, int channels)
1279{
1280 if (stream->commited) {
1281 dev_err(hsw->dev, "error: stream committed for set channels\n");
1282 return -EINVAL;
1283 }
1284
a4b12990
MB		 1285 stream->request.format.ch_num = channels;
1286 return 0;
1287}
1288
1289int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
1290 struct sst_hsw_stream *stream, int rate)
1291{
1292 if (stream->commited) {
1293 dev_err(hsw->dev, "error: stream committed for set rate\n");
1294 return -EINVAL;
1295 }
1296
1297 stream->request.format.frequency = rate;
1298 return 0;
1299}
1300
1301int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
1302 struct sst_hsw_stream *stream, u32 map,
1303 enum sst_hsw_channel_config config)
1304{
1305 if (stream->commited) {
1306 dev_err(hsw->dev, "error: stream committed for set map\n");
1307 return -EINVAL;
1308 }
1309
1310 stream->request.format.map = map;
1311 stream->request.format.config = config;
1312 return 0;
1313}
1314
1315int sst_hsw_stream_set_style(struct sst_hsw *hsw,
1316 struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
1317{
1318 if (stream->commited) {
1319 dev_err(hsw->dev, "error: stream committed for set style\n");
1320 return -EINVAL;
1321 }
1322
1323 stream->request.format.style = style;
1324 return 0;
1325}
1326
1327int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
1328 struct sst_hsw_stream *stream, u32 bits)
1329{
1330 if (stream->commited) {
1331 dev_err(hsw->dev, "error: stream committed for set valid bits\n");
1332 return -EINVAL;
1333 }
1334
1335 stream->request.format.valid_bit = bits;
1336 return 0;
1337}
1338
1339/* Stream Configuration */
1340int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1341 enum sst_hsw_stream_path_id path_id,
1342 enum sst_hsw_stream_type stream_type,
1343 enum sst_hsw_stream_format format_id)
1344{
1345 if (stream->commited) {
1346 dev_err(hsw->dev, "error: stream committed for set format\n");
1347 return -EINVAL;
1348 }
1349
1350 stream->request.path_id = path_id;
1351 stream->request.stream_type = stream_type;
1352 stream->request.format_id = format_id;
1353
1354 trace_hsw_stream_alloc_request(stream, &stream->request);
1355
1356 return 0;
1357}
1358
1359int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1360 u32 ring_pt_address, u32 num_pages,
1361 u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
1362{
1363 if (stream->commited) {
1364 dev_err(hsw->dev, "error: stream committed for buffer\n");
1365 return -EINVAL;
1366 }
1367
1368 stream->request.ringinfo.ring_pt_address = ring_pt_address;
1369 stream->request.ringinfo.num_pages = num_pages;
1370 stream->request.ringinfo.ring_size = ring_size;
1371 stream->request.ringinfo.ring_offset = ring_offset;
1372 stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
1373
1374 trace_hsw_stream_buffer(stream);
1375
1376 return 0;
1377}
1378
1379int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
e9600bc1 1380 struct sst_hsw_stream *stream, struct sst_module_runtime *runtime)
a4b12990
MB		 1381{
1382 struct sst_hsw_module_map *map = &stream->request.map;
e9600bc1
LG		 1383 struct sst_dsp *dsp = sst_hsw_get_dsp(hsw);
1384 struct sst_module *module = runtime->module;
a4b12990
MB		 1385
1386 if (stream->commited) {
1387 dev_err(hsw->dev, "error: stream committed for set module\n");
1388 return -EINVAL;
1389 }
1390
1391 /* only support initial module atm */
1392 map->module_entries_count = 1;
e9600bc1
LG		 1393 map->module_entries[0].module_id = module->id;
1394 map->module_entries[0].entry_point = module->entry;
1395
1396 stream->request.persistent_mem.offset =
1397 sst_dsp_get_offset(dsp, runtime->persistent_offset, SST_MEM_DRAM);
1398 stream->request.persistent_mem.size = module->persistent_size;
1399
1400 stream->request.scratch_mem.offset =
1401 sst_dsp_get_offset(dsp, dsp->scratch_offset, SST_MEM_DRAM);
1402 stream->request.scratch_mem.size = dsp->scratch_size;
1403
1404 dev_dbg(hsw->dev, "module %d runtime %d using:\n", module->id,
1405 runtime->id);
1406 dev_dbg(hsw->dev, " persistent offset 0x%x bytes 0x%x\n",
1407 stream->request.persistent_mem.offset,
1408 stream->request.persistent_mem.size);
1409 dev_dbg(hsw->dev, " scratch offset 0x%x bytes 0x%x\n",
1410 stream->request.scratch_mem.offset,
1411 stream->request.scratch_mem.size);
a4b12990
MB		 1412
1413 return 0;
1414}
1415
1416int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1417{
1418 struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
1419 struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
1420 u32 header;
1421 int ret;
1422
f81677b4
JY		 1423 if (!stream) {
1424 dev_warn(hsw->dev, "warning: stream is NULL, no stream to commit, ignore it.\n");
1425 return 0;
1426 }
1427
1428 if (stream->commited) {
1429 dev_warn(hsw->dev, "warning: stream is already committed, ignore it.\n");
1430 return 0;
1431 }
1432
a4b12990
MB		 1433 trace_ipc_request("stream alloc", stream->host_id);
1434
1435 header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
1436
1437 ret = ipc_tx_message_wait(hsw, header, str_req, sizeof(*str_req),
1438 reply, sizeof(*reply));
1439 if (ret < 0) {
1440 dev_err(hsw->dev, "error: stream commit failed\n");
1441 return ret;
1442 }
1443
1444 stream->commited = 1;
1445 trace_hsw_stream_alloc_reply(stream);
1446
1447 return 0;
1448}
1449
1450/* Stream Information - these calls could be inline but we want the IPC
1451 ABI to be opaque to client PCM drivers to cope with any future ABI changes */
1452int sst_hsw_stream_get_hw_id(struct sst_hsw *hsw,
1453 struct sst_hsw_stream *stream)
1454{
1455 return stream->reply.stream_hw_id;
1456}
1457
1458int sst_hsw_stream_get_mixer_id(struct sst_hsw *hsw,
1459 struct sst_hsw_stream *stream)
1460{
1461 return stream->reply.mixer_hw_id;
1462}
1463
1464u32 sst_hsw_stream_get_read_reg(struct sst_hsw *hsw,
1465 struct sst_hsw_stream *stream)
1466{
1467 return stream->reply.read_position_register_address;
1468}
1469
1470u32 sst_hsw_stream_get_pointer_reg(struct sst_hsw *hsw,
1471 struct sst_hsw_stream *stream)
1472{
1473 return stream->reply.presentation_position_register_address;
1474}
1475
1476u32 sst_hsw_stream_get_peak_reg(struct sst_hsw *hsw,
1477 struct sst_hsw_stream *stream, u32 channel)
1478{
1479 if (channel >= 2)
1480 return 0;
1481
1482 return stream->reply.peak_meter_register_address[channel];
1483}
1484
1485u32 sst_hsw_stream_get_vol_reg(struct sst_hsw *hsw,
1486 struct sst_hsw_stream *stream, u32 channel)
1487{
1488 if (channel >= 2)
1489 return 0;
1490
1491 return stream->reply.volume_register_address[channel];
1492}
1493
1494int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
1495{
1496 struct sst_hsw_ipc_stream_info_reply *reply;
1497 u32 header;
1498 int ret;
1499
1500 reply = &hsw->mixer_info;
1501 header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
1502
1503 trace_ipc_request("get global mixer info", 0);
1504
1505 ret = ipc_tx_message_wait(hsw, header, NULL, 0, reply, sizeof(*reply));
1506 if (ret < 0) {
1507 dev_err(hsw->dev, "error: get stream info failed\n");
1508 return ret;
1509 }
1510
1511 trace_hsw_mixer_info_reply(reply);
1512
1513 return 0;
1514}
1515
1516/* Send stream command */
1517static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
1518 int stream_id, int wait)
1519{
1520 u32 header;
1521
1522 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
1523 header |= (stream_id << IPC_STR_ID_SHIFT);
1524
1525 if (wait)
1526 return ipc_tx_message_wait(hsw, header, NULL, 0, NULL, 0);
1527 else
1528 return ipc_tx_message_nowait(hsw, header, NULL, 0);
1529}
1530
1531/* Stream ALSA trigger operations */
1532int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1533 int wait)
1534{
1535 int ret;
1536
f81677b4
JY		 1537 if (!stream) {
1538 dev_warn(hsw->dev, "warning: stream is NULL, no stream to pause, ignore it.\n");
1539 return 0;
1540 }
1541
a4b12990
MB		 1542 trace_ipc_request("stream pause", stream->reply.stream_hw_id);
1543
1544 ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
1545 stream->reply.stream_hw_id, wait);
1546 if (ret < 0)
1547 dev_err(hsw->dev, "error: failed to pause stream %d\n",
1548 stream->reply.stream_hw_id);
1549
1550 return ret;
1551}
1552
1553int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1554 int wait)
1555{
1556 int ret;
1557
f81677b4
JY		 1558 if (!stream) {
1559 dev_warn(hsw->dev, "warning: stream is NULL, no stream to resume, ignore it.\n");
1560 return 0;
1561 }
1562
a4b12990
MB		 1563 trace_ipc_request("stream resume", stream->reply.stream_hw_id);
1564
1565 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
1566 stream->reply.stream_hw_id, wait);
1567 if (ret < 0)
1568 dev_err(hsw->dev, "error: failed to resume stream %d\n",
1569 stream->reply.stream_hw_id);
1570
1571 return ret;
1572}
1573
1574int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1575{
1576 int ret, tries = 10;
1577
f81677b4
JY		 1578 if (!stream) {
1579 dev_warn(hsw->dev, "warning: stream is NULL, no stream to reset, ignore it.\n");
1580 return 0;
1581 }
1582
a4b12990
MB		 1583 /* dont reset streams that are not commited */
1584 if (!stream->commited)
1585 return 0;
1586
1587 /* wait for pause to complete before we reset the stream */
1588 while (stream->running && tries--)
1589 msleep(1);
1590 if (!tries) {
1591 dev_err(hsw->dev, "error: reset stream %d still running\n",
1592 stream->reply.stream_hw_id);
1593 return -EINVAL;
1594 }
1595
1596 trace_ipc_request("stream reset", stream->reply.stream_hw_id);
1597
1598 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
1599 stream->reply.stream_hw_id, 1);
1600 if (ret < 0)
1601 dev_err(hsw->dev, "error: failed to reset stream %d\n",
1602 stream->reply.stream_hw_id);
1603 return ret;
1604}
1605
1606/* Stream pointer positions */
51b4e24f 1607u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
a4b12990
MB		 1608 struct sst_hsw_stream *stream)
1609{
51b4e24f
LG		 1610 u32 rpos;
1611
1612 sst_dsp_read(hsw->dsp, &rpos,
1613 stream->reply.read_position_register_address, sizeof(rpos));
1614
1615 return rpos;
1616}
1617
1618/* Stream presentation (monotonic) positions */
1619u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
1620 struct sst_hsw_stream *stream)
1621{
1622 u64 ppos;
1623
1624 sst_dsp_read(hsw->dsp, &ppos,
1625 stream->reply.presentation_position_register_address,
1626 sizeof(ppos));
1627
1628 return ppos;
a4b12990
MB		 1629}
1630
1631int sst_hsw_stream_set_write_position(struct sst_hsw *hsw,
1632 struct sst_hsw_stream *stream, u32 stage_id, u32 position)
1633{
1634 u32 header;
1635 int ret;
1636
1637 trace_stream_write_position(stream->reply.stream_hw_id, position);
1638
1639 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1640 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1641 header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
1642 header |= (IPC_STG_SET_WRITE_POSITION << IPC_STG_TYPE_SHIFT);
1643 header |= (stage_id << IPC_STG_ID_SHIFT);
1644 stream->wpos.position = position;
1645
1646 ret = ipc_tx_message_nowait(hsw, header, &stream->wpos,
1647 sizeof(stream->wpos));
1648 if (ret < 0)
1649 dev_err(hsw->dev, "error: stream %d set position %d failed\n",
1650 stream->reply.stream_hw_id, position);
1651
1652 return ret;
1653}
1654
1655/* physical BE config */
1656int sst_hsw_device_set_config(struct sst_hsw *hsw,
1657 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
1658 enum sst_hsw_device_mode mode, u32 clock_divider)
1659{
1660 struct sst_hsw_ipc_device_config_req config;
1661 u32 header;
1662 int ret;
1663
1664 trace_ipc_request("set device config", dev);
1665
1666 config.ssp_interface = dev;
1667 config.clock_frequency = mclk;
1668 config.mode = mode;
1669 config.clock_divider = clock_divider;
f07e51c5
LG		 1670 if (mode == SST_HSW_DEVICE_TDM_CLOCK_MASTER)
1671 config.channels = 4;
1672 else
1673 config.channels = 2;
a4b12990
MB		 1674
1675 trace_hsw_device_config_req(&config);
1676
1677 header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
1678
1679 ret = ipc_tx_message_wait(hsw, header, &config, sizeof(config),
1680 NULL, 0);
1681 if (ret < 0)
1682 dev_err(hsw->dev, "error: set device formats failed\n");
1683
1684 return ret;
1685}
1686EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
1687
1688/* DX Config */
1689int sst_hsw_dx_set_state(struct sst_hsw *hsw,
1690 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
1691{
1692 u32 header, state_;
543ec637 1693 int ret, item;
a4b12990
MB		 1694
1695 header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
1696 state_ = state;
1697
1698 trace_ipc_request("PM enter Dx state", state);
1699
1700 ret = ipc_tx_message_wait(hsw, header, &state_, sizeof(state_),
7897ab78 1701 dx, sizeof(*dx));
a4b12990
MB		 1702 if (ret < 0) {
1703 dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
1704 return ret;
1705 }
1706
543ec637
LG		 1707 for (item = 0; item < dx->entries_no; item++) {
1708 dev_dbg(hsw->dev,
1709 "Item[%d] offset[%x] - size[%x] - source[%x]\n",
1710 item, dx->mem_info[item].offset,
1711 dx->mem_info[item].size,
1712 dx->mem_info[item].source);
1713 }
a4b12990
MB		 1714 dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
1715 dx->entries_no, state);
1716
e9600bc1 1717 return ret;
a4b12990
MB		 1718}
1719
e9600bc1
LG		 1720struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
1721 int mod_id, int offset)
a4b12990 1722{
e9600bc1
LG		 1723 struct sst_dsp *dsp = hsw->dsp;
1724 struct sst_module *module;
1725 struct sst_module_runtime *runtime;
1726 int err;
a4b12990 1727
e9600bc1
LG		 1728 module = sst_module_get_from_id(dsp, mod_id);
1729 if (module == NULL) {
1730 dev_err(dsp->dev, "error: failed to get module %d for pcm\n",
1731 mod_id);
1732 return NULL;
1733 }
a4b12990 1734
e9600bc1
LG		 1735 runtime = sst_module_runtime_new(module, mod_id, NULL);
1736 if (runtime == NULL) {
1737 dev_err(dsp->dev, "error: failed to create module %d runtime\n",
1738 mod_id);
1739 return NULL;
1740 }
a4b12990 1741
e9600bc1
LG		 1742 err = sst_module_runtime_alloc_blocks(runtime, offset);
1743 if (err < 0) {
1744 dev_err(dsp->dev, "error: failed to alloc blocks for module %d runtime\n",
1745 mod_id);
1746 sst_module_runtime_free(runtime);
1747 return NULL;
1748 }
a4b12990 1749
e9600bc1
LG		 1750 dev_dbg(dsp->dev, "runtime id %d created for module %d\n", runtime->id,
1751 mod_id);
1752 return runtime;
1753}
a4b12990 1754
e9600bc1
LG		 1755void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime)
1756{
1757 sst_module_runtime_free_blocks(runtime);
1758 sst_module_runtime_free(runtime);
a4b12990
MB		 1759}
1760
35e03a88 1761#ifdef CONFIG_PM
aed3c7b7
LG		 1762static int sst_hsw_dx_state_dump(struct sst_hsw *hsw)
1763{
1764 struct sst_dsp *sst = hsw->dsp;
1765 u32 item, offset, size;
1766 int ret = 0;
1767
1768 trace_ipc_request("PM state dump. Items #", SST_HSW_MAX_DX_REGIONS);
1769
1770 if (hsw->dx.entries_no > SST_HSW_MAX_DX_REGIONS) {
1771 dev_err(hsw->dev,
1772 "error: number of FW context regions greater than %d\n",
1773 SST_HSW_MAX_DX_REGIONS);
1774 memset(&hsw->dx, 0, sizeof(hsw->dx));
1775 return -EINVAL;
1776 }
1777
1778 ret = sst_dsp_dma_get_channel(sst, 0);
1779 if (ret < 0) {
1780 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1781 return ret;
1782 }
1783
1784 /* set on-demond mode on engine 0 channel 3 */
1785 sst_dsp_shim_update_bits(sst, SST_HMDC,
1786 SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
1787 SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
1788
1789 for (item = 0; item < hsw->dx.entries_no; item++) {
1790 if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1791 && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1792 && hsw->dx.mem_info[item].offset <
1793 DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1794
1795 offset = hsw->dx.mem_info[item].offset
1796 - DSP_DRAM_ADDR_OFFSET;
1797 size = (hsw->dx.mem_info[item].size + 3) & (~3);
1798
1799 ret = sst_dsp_dma_copyfrom(sst, hsw->dx_context_paddr + offset,
1800 sst->addr.lpe_base + offset, size);
1801 if (ret < 0) {
1802 dev_err(hsw->dev,
1803 "error: FW context dump failed\n");
1804 memset(&hsw->dx, 0, sizeof(hsw->dx));
1805 goto out;
1806 }
1807 }
1808 }
1809
1810out:
1811 sst_dsp_dma_put_channel(sst);
1812 return ret;
1813}
1814
1815static int sst_hsw_dx_state_restore(struct sst_hsw *hsw)
1816{
1817 struct sst_dsp *sst = hsw->dsp;
1818 u32 item, offset, size;
1819 int ret;
1820
1821 for (item = 0; item < hsw->dx.entries_no; item++) {
1822 if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1823 && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1824 && hsw->dx.mem_info[item].offset <
1825 DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1826
1827 offset = hsw->dx.mem_info[item].offset
1828 - DSP_DRAM_ADDR_OFFSET;
1829 size = (hsw->dx.mem_info[item].size + 3) & (~3);
1830
1831 ret = sst_dsp_dma_copyto(sst, sst->addr.lpe_base + offset,
1832 hsw->dx_context_paddr + offset, size);
1833 if (ret < 0) {
1834 dev_err(hsw->dev,
1835 "error: FW context restore failed\n");
1836 return ret;
1837 }
1838 }
1839 }
1840
1841 return 0;
1842}
1843
1844static void sst_hsw_drop_all(struct sst_hsw *hsw)
1845{
1846 struct ipc_message *msg, *tmp;
1847 unsigned long flags;
1848 int tx_drop_cnt = 0, rx_drop_cnt = 0;
1849
1850 /* drop all TX and Rx messages before we stall + reset DSP */
1851 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
1852
1853 list_for_each_entry_safe(msg, tmp, &hsw->tx_list, list) {
1854 list_move(&msg->list, &hsw->empty_list);
1855 tx_drop_cnt++;
1856 }
1857
1858 list_for_each_entry_safe(msg, tmp, &hsw->rx_list, list) {
1859 list_move(&msg->list, &hsw->empty_list);
1860 rx_drop_cnt++;
1861 }
1862
1863 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
1864
1865 if (tx_drop_cnt || rx_drop_cnt)
1866 dev_err(hsw->dev, "dropped IPC msg RX=%d, TX=%d\n",
1867 tx_drop_cnt, rx_drop_cnt);
1868}
1869
1870int sst_hsw_dsp_load(struct sst_hsw *hsw)
1871{
1872 struct sst_dsp *dsp = hsw->dsp;
1873 int ret;
1874
1875 dev_dbg(hsw->dev, "loading audio DSP....");
1876
1877 ret = sst_dsp_wake(dsp);
1878 if (ret < 0) {
1879 dev_err(hsw->dev, "error: failed to wake audio DSP\n");
1880 return -ENODEV;
1881 }
1882
1883 ret = sst_dsp_dma_get_channel(dsp, 0);
1884 if (ret < 0) {
1885 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1886 return ret;
1887 }
1888
1889 ret = sst_fw_reload(hsw->sst_fw);
1890 if (ret < 0) {
1891 dev_err(hsw->dev, "error: SST FW reload failed\n");
1892 sst_dsp_dma_put_channel(dsp);
1893 return -ENOMEM;
1894 }
1895
1896 sst_dsp_dma_put_channel(dsp);
1897 return 0;
1898}
1899
1900static int sst_hsw_dsp_restore(struct sst_hsw *hsw)
1901{
1902 struct sst_dsp *dsp = hsw->dsp;
1903 int ret;
1904
1905 dev_dbg(hsw->dev, "restoring audio DSP....");
1906
1907 ret = sst_dsp_dma_get_channel(dsp, 0);
1908 if (ret < 0) {
1909 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1910 return ret;
1911 }
1912
1913 ret = sst_hsw_dx_state_restore(hsw);
1914 if (ret < 0) {
1915 dev_err(hsw->dev, "error: SST FW context restore failed\n");
1916 sst_dsp_dma_put_channel(dsp);
1917 return -ENOMEM;
1918 }
1919 sst_dsp_dma_put_channel(dsp);
1920
1921 /* wait for DSP boot completion */
1922 sst_dsp_boot(dsp);
1923
1924 return ret;
1925}
1926
1927int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw)
1928{
1929 int ret;
1930
1931 dev_dbg(hsw->dev, "audio dsp runtime suspend\n");
1932
1933 ret = sst_hsw_dx_set_state(hsw, SST_HSW_DX_STATE_D3, &hsw->dx);
1934 if (ret < 0)
1935 return ret;
1936
1937 sst_dsp_stall(hsw->dsp);
1938
1939 ret = sst_hsw_dx_state_dump(hsw);
1940 if (ret < 0)
1941 return ret;
1942
1943 sst_hsw_drop_all(hsw);
1944
1945 return 0;
1946}
1947
1948int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw)
1949{
1950 sst_fw_unload(hsw->sst_fw);
1951 sst_block_free_scratch(hsw->dsp);
1952
1953 hsw->boot_complete = false;
1954
1955 sst_dsp_sleep(hsw->dsp);
1956
1957 return 0;
1958}
1959
1960int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw)
1961{
1962 struct device *dev = hsw->dev;
1963 int ret;
1964
1965 dev_dbg(dev, "audio dsp runtime resume\n");
1966
1967 if (hsw->boot_complete)
1968 return 1; /* tell caller no action is required */
1969
1970 ret = sst_hsw_dsp_restore(hsw);
1971 if (ret < 0)
1972 dev_err(dev, "error: audio DSP boot failure\n");
1973
1974 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
1975 msecs_to_jiffies(IPC_BOOT_MSECS));
1976 if (ret == 0) {
b891f62f
LG		 1977 dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
1978 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
1979 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
aed3c7b7
LG		 1980 return -EIO;
1981 }
1982
1983 /* Set ADSP SSP port settings */
1984 ret = sst_hsw_device_set_config(hsw, SST_HSW_DEVICE_SSP_0,
1985 SST_HSW_DEVICE_MCLK_FREQ_24_MHZ,
1986 SST_HSW_DEVICE_CLOCK_MASTER, 9);
1987 if (ret < 0)
1988 dev_err(dev, "error: SSP re-initialization failed\n");
1989
1990 return ret;
1991}
1992#endif
1993
a4b12990
MB		 1994static int msg_empty_list_init(struct sst_hsw *hsw)
1995{
1996 int i;
1997
1998 hsw->msg = kzalloc(sizeof(struct ipc_message) *
1999 IPC_EMPTY_LIST_SIZE, GFP_KERNEL);
2000 if (hsw->msg == NULL)
2001 return -ENOMEM;
2002
2003 for (i = 0; i < IPC_EMPTY_LIST_SIZE; i++) {
2004 init_waitqueue_head(&hsw->msg[i].waitq);
2005 list_add(&hsw->msg[i].list, &hsw->empty_list);
2006 }
2007
2008 return 0;
2009}
2010
a4b12990
MB		 2011struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
2012{
2013 return hsw->dsp;
2014}
2015
2016static struct sst_dsp_device hsw_dev = {
2017 .thread = hsw_irq_thread,
2018 .ops = &haswell_ops,
2019};
2020
2021int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
2022{
2023 struct sst_hsw_ipc_fw_version version;
2024 struct sst_hsw *hsw;
a4b12990
MB		 2025 int ret;
2026
2027 dev_dbg(dev, "initialising Audio DSP IPC\n");
2028
2029 hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
2030 if (hsw == NULL)
2031 return -ENOMEM;
2032
2033 hsw->dev = dev;
2034 INIT_LIST_HEAD(&hsw->stream_list);
2035 INIT_LIST_HEAD(&hsw->tx_list);
2036 INIT_LIST_HEAD(&hsw->rx_list);
2037 INIT_LIST_HEAD(&hsw->empty_list);
2038 init_waitqueue_head(&hsw->boot_wait);
2039 init_waitqueue_head(&hsw->wait_txq);
2040
2041 ret = msg_empty_list_init(hsw);
2042 if (ret < 0)
9cf0e452 2043 return -ENOMEM;
a4b12990
MB		 2044
2045 /* start the IPC message thread */
2046 init_kthread_worker(&hsw->kworker);
2047 hsw->tx_thread = kthread_run(kthread_worker_fn,
35386320 2048 &hsw->kworker, "%s",
a4b12990
MB		 2049 dev_name(hsw->dev));
2050 if (IS_ERR(hsw->tx_thread)) {
2051 ret = PTR_ERR(hsw->tx_thread);
2052 dev_err(hsw->dev, "error: failed to create message TX task\n");
9cf0e452 2053 goto err_free_msg;
a4b12990
MB		 2054 }
2055 init_kthread_work(&hsw->kwork, ipc_tx_msgs);
2056
2057 hsw_dev.thread_context = hsw;
2058
2059 /* init SST shim */
2060 hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
2061 if (hsw->dsp == NULL) {
2062 ret = -ENODEV;
9cf0e452 2063 goto dsp_err;
a4b12990
MB		 2064 }
2065
aed3c7b7
LG		 2066 /* allocate DMA buffer for context storage */
2067 hsw->dx_context = dma_alloc_coherent(hsw->dsp->dma_dev,
2068 SST_HSW_DX_CONTEXT_SIZE, &hsw->dx_context_paddr, GFP_KERNEL);
2069 if (hsw->dx_context == NULL) {
2070 ret = -ENOMEM;
2071 goto dma_err;
2072 }
2073
a4b12990
MB		 2074 /* keep the DSP in reset state for base FW loading */
2075 sst_dsp_reset(hsw->dsp);
2076
aed3c7b7
LG		 2077 hsw->sst_fw = sst_fw_new(hsw->dsp, pdata->fw, hsw);
2078 if (hsw->sst_fw == NULL) {
a4b12990
MB		 2079 ret = -ENODEV;
2080 dev_err(dev, "error: failed to load firmware\n");
2081 goto fw_err;
2082 }
2083
2084 /* wait for DSP boot completion */
2085 sst_dsp_boot(hsw->dsp);
2086 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
2087 msecs_to_jiffies(IPC_BOOT_MSECS));
2088 if (ret == 0) {
2089 ret = -EIO;
b891f62f
LG		 2090 dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
2091 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
2092 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
a4b12990
MB		 2093 goto boot_err;
2094 }
2095
2096 /* get the FW version */
2097 sst_hsw_fw_get_version(hsw, &version);
a4b12990
MB		 2098
2099 /* get the globalmixer */
2100 ret = sst_hsw_mixer_get_info(hsw);
2101 if (ret < 0) {
2102 dev_err(hsw->dev, "error: failed to get stream info\n");
2103 goto boot_err;
2104 }
2105
2106 pdata->dsp = hsw;
2107 return 0;
2108
2109boot_err:
2110 sst_dsp_reset(hsw->dsp);
aed3c7b7 2111 sst_fw_free(hsw->sst_fw);
a4b12990 2112fw_err:
aed3c7b7
LG		 2113 dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2114 hsw->dx_context, hsw->dx_context_paddr);
2115dma_err:
a4b12990 2116 sst_dsp_free(hsw->dsp);
9cf0e452
ID		 2117dsp_err:
2118 kthread_stop(hsw->tx_thread);
2119err_free_msg:
a4b12990 2120 kfree(hsw->msg);
9cf0e452 2121
a4b12990
MB		 2122 return ret;
2123}
2124EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
2125
2126void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
2127{
2128 struct sst_hsw *hsw = pdata->dsp;
2129
2130 sst_dsp_reset(hsw->dsp);
2131 sst_fw_free_all(hsw->dsp);
aed3c7b7
LG		 2132 dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2133 hsw->dx_context, hsw->dx_context_paddr);
a4b12990
MB		 2134 sst_dsp_free(hsw->dsp);
2135 kfree(hsw->scratch);
9cf0e452 2136 kthread_stop(hsw->tx_thread);
a4b12990
MB		 2137 kfree(hsw->msg);
2138}
2139EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);
Linux 6.x block layer and io_uring tree(s)