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e4e2d2f4 JK |
1 | /* |
2 | * skl-topology.c - Implements Platform component ALSA controls/widget | |
3 | * handlers. | |
4 | * | |
5 | * Copyright (C) 2014-2015 Intel Corp | |
6 | * Author: Jeeja KP <jeeja.kp@intel.com> | |
7 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as version 2, as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | */ | |
18 | ||
19 | #include <linux/slab.h> | |
20 | #include <linux/types.h> | |
21 | #include <linux/firmware.h> | |
22 | #include <sound/soc.h> | |
23 | #include <sound/soc-topology.h> | |
24 | #include "skl-sst-dsp.h" | |
25 | #include "skl-sst-ipc.h" | |
26 | #include "skl-topology.h" | |
27 | #include "skl.h" | |
28 | #include "skl-tplg-interface.h" | |
6c5768b3 D |
29 | #include "../common/sst-dsp.h" |
30 | #include "../common/sst-dsp-priv.h" | |
e4e2d2f4 | 31 | |
f7590d4f JK |
32 | #define SKL_CH_FIXUP_MASK (1 << 0) |
33 | #define SKL_RATE_FIXUP_MASK (1 << 1) | |
34 | #define SKL_FMT_FIXUP_MASK (1 << 2) | |
35 | ||
e4e2d2f4 JK |
36 | /* |
37 | * SKL DSP driver modelling uses only few DAPM widgets so for rest we will | |
38 | * ignore. This helpers checks if the SKL driver handles this widget type | |
39 | */ | |
40 | static int is_skl_dsp_widget_type(struct snd_soc_dapm_widget *w) | |
41 | { | |
42 | switch (w->id) { | |
43 | case snd_soc_dapm_dai_link: | |
44 | case snd_soc_dapm_dai_in: | |
45 | case snd_soc_dapm_aif_in: | |
46 | case snd_soc_dapm_aif_out: | |
47 | case snd_soc_dapm_dai_out: | |
48 | case snd_soc_dapm_switch: | |
49 | return false; | |
50 | default: | |
51 | return true; | |
52 | } | |
53 | } | |
54 | ||
55 | /* | |
56 | * Each pipelines needs memory to be allocated. Check if we have free memory | |
9ba8ffef | 57 | * from available pool. |
e4e2d2f4 | 58 | */ |
9ba8ffef | 59 | static bool skl_is_pipe_mem_avail(struct skl *skl, |
e4e2d2f4 JK |
60 | struct skl_module_cfg *mconfig) |
61 | { | |
62 | struct skl_sst *ctx = skl->skl_sst; | |
63 | ||
64 | if (skl->resource.mem + mconfig->pipe->memory_pages > | |
65 | skl->resource.max_mem) { | |
66 | dev_err(ctx->dev, | |
67 | "%s: module_id %d instance %d\n", __func__, | |
68 | mconfig->id.module_id, | |
69 | mconfig->id.instance_id); | |
70 | dev_err(ctx->dev, | |
71 | "exceeds ppl memory available %d mem %d\n", | |
72 | skl->resource.max_mem, skl->resource.mem); | |
73 | return false; | |
9ba8ffef D |
74 | } else { |
75 | return true; | |
e4e2d2f4 | 76 | } |
9ba8ffef | 77 | } |
e4e2d2f4 | 78 | |
9ba8ffef D |
79 | /* |
80 | * Add the mem to the mem pool. This is freed when pipe is deleted. | |
81 | * Note: DSP does actual memory management we only keep track for complete | |
82 | * pool | |
83 | */ | |
84 | static void skl_tplg_alloc_pipe_mem(struct skl *skl, | |
85 | struct skl_module_cfg *mconfig) | |
86 | { | |
e4e2d2f4 | 87 | skl->resource.mem += mconfig->pipe->memory_pages; |
e4e2d2f4 JK |
88 | } |
89 | ||
90 | /* | |
91 | * Pipeline needs needs DSP CPU resources for computation, this is | |
92 | * quantified in MCPS (Million Clocks Per Second) required for module/pipe | |
93 | * | |
94 | * Each pipelines needs mcps to be allocated. Check if we have mcps for this | |
9ba8ffef | 95 | * pipe. |
e4e2d2f4 | 96 | */ |
9ba8ffef D |
97 | |
98 | static bool skl_is_pipe_mcps_avail(struct skl *skl, | |
e4e2d2f4 JK |
99 | struct skl_module_cfg *mconfig) |
100 | { | |
101 | struct skl_sst *ctx = skl->skl_sst; | |
102 | ||
103 | if (skl->resource.mcps + mconfig->mcps > skl->resource.max_mcps) { | |
104 | dev_err(ctx->dev, | |
105 | "%s: module_id %d instance %d\n", __func__, | |
106 | mconfig->id.module_id, mconfig->id.instance_id); | |
107 | dev_err(ctx->dev, | |
7ca42f5a | 108 | "exceeds ppl mcps available %d > mem %d\n", |
e4e2d2f4 JK |
109 | skl->resource.max_mcps, skl->resource.mcps); |
110 | return false; | |
9ba8ffef D |
111 | } else { |
112 | return true; | |
e4e2d2f4 | 113 | } |
9ba8ffef | 114 | } |
e4e2d2f4 | 115 | |
9ba8ffef D |
116 | static void skl_tplg_alloc_pipe_mcps(struct skl *skl, |
117 | struct skl_module_cfg *mconfig) | |
118 | { | |
e4e2d2f4 | 119 | skl->resource.mcps += mconfig->mcps; |
e4e2d2f4 JK |
120 | } |
121 | ||
122 | /* | |
123 | * Free the mcps when tearing down | |
124 | */ | |
125 | static void | |
126 | skl_tplg_free_pipe_mcps(struct skl *skl, struct skl_module_cfg *mconfig) | |
127 | { | |
128 | skl->resource.mcps -= mconfig->mcps; | |
129 | } | |
130 | ||
131 | /* | |
132 | * Free the memory when tearing down | |
133 | */ | |
134 | static void | |
135 | skl_tplg_free_pipe_mem(struct skl *skl, struct skl_module_cfg *mconfig) | |
136 | { | |
137 | skl->resource.mem -= mconfig->pipe->memory_pages; | |
138 | } | |
139 | ||
f7590d4f JK |
140 | |
141 | static void skl_dump_mconfig(struct skl_sst *ctx, | |
142 | struct skl_module_cfg *mcfg) | |
143 | { | |
144 | dev_dbg(ctx->dev, "Dumping config\n"); | |
145 | dev_dbg(ctx->dev, "Input Format:\n"); | |
4cd9899f HS |
146 | dev_dbg(ctx->dev, "channels = %d\n", mcfg->in_fmt[0].channels); |
147 | dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->in_fmt[0].s_freq); | |
148 | dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->in_fmt[0].ch_cfg); | |
149 | dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->in_fmt[0].valid_bit_depth); | |
f7590d4f | 150 | dev_dbg(ctx->dev, "Output Format:\n"); |
4cd9899f HS |
151 | dev_dbg(ctx->dev, "channels = %d\n", mcfg->out_fmt[0].channels); |
152 | dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->out_fmt[0].s_freq); | |
153 | dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->out_fmt[0].valid_bit_depth); | |
154 | dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->out_fmt[0].ch_cfg); | |
f7590d4f JK |
155 | } |
156 | ||
ea5a137d SP |
157 | static void skl_tplg_update_chmap(struct skl_module_fmt *fmt, int chs) |
158 | { | |
159 | int slot_map = 0xFFFFFFFF; | |
160 | int start_slot = 0; | |
161 | int i; | |
162 | ||
163 | for (i = 0; i < chs; i++) { | |
164 | /* | |
165 | * For 2 channels with starting slot as 0, slot map will | |
166 | * look like 0xFFFFFF10. | |
167 | */ | |
168 | slot_map &= (~(0xF << (4 * i)) | (start_slot << (4 * i))); | |
169 | start_slot++; | |
170 | } | |
171 | fmt->ch_map = slot_map; | |
172 | } | |
173 | ||
f7590d4f JK |
174 | static void skl_tplg_update_params(struct skl_module_fmt *fmt, |
175 | struct skl_pipe_params *params, int fixup) | |
176 | { | |
177 | if (fixup & SKL_RATE_FIXUP_MASK) | |
178 | fmt->s_freq = params->s_freq; | |
ea5a137d | 179 | if (fixup & SKL_CH_FIXUP_MASK) { |
f7590d4f | 180 | fmt->channels = params->ch; |
ea5a137d SP |
181 | skl_tplg_update_chmap(fmt, fmt->channels); |
182 | } | |
98256f83 JK |
183 | if (fixup & SKL_FMT_FIXUP_MASK) { |
184 | fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt); | |
185 | ||
186 | /* | |
187 | * 16 bit is 16 bit container whereas 24 bit is in 32 bit | |
188 | * container so update bit depth accordingly | |
189 | */ | |
190 | switch (fmt->valid_bit_depth) { | |
191 | case SKL_DEPTH_16BIT: | |
192 | fmt->bit_depth = fmt->valid_bit_depth; | |
193 | break; | |
194 | ||
195 | default: | |
196 | fmt->bit_depth = SKL_DEPTH_32BIT; | |
197 | break; | |
198 | } | |
199 | } | |
200 | ||
f7590d4f JK |
201 | } |
202 | ||
203 | /* | |
204 | * A pipeline may have modules which impact the pcm parameters, like SRC, | |
205 | * channel converter, format converter. | |
206 | * We need to calculate the output params by applying the 'fixup' | |
207 | * Topology will tell driver which type of fixup is to be applied by | |
208 | * supplying the fixup mask, so based on that we calculate the output | |
209 | * | |
210 | * Now In FE the pcm hw_params is source/target format. Same is applicable | |
211 | * for BE with its hw_params invoked. | |
212 | * here based on FE, BE pipeline and direction we calculate the input and | |
213 | * outfix and then apply that for a module | |
214 | */ | |
215 | static void skl_tplg_update_params_fixup(struct skl_module_cfg *m_cfg, | |
216 | struct skl_pipe_params *params, bool is_fe) | |
217 | { | |
218 | int in_fixup, out_fixup; | |
219 | struct skl_module_fmt *in_fmt, *out_fmt; | |
220 | ||
4cd9899f HS |
221 | /* Fixups will be applied to pin 0 only */ |
222 | in_fmt = &m_cfg->in_fmt[0]; | |
223 | out_fmt = &m_cfg->out_fmt[0]; | |
f7590d4f JK |
224 | |
225 | if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
226 | if (is_fe) { | |
227 | in_fixup = m_cfg->params_fixup; | |
228 | out_fixup = (~m_cfg->converter) & | |
229 | m_cfg->params_fixup; | |
230 | } else { | |
231 | out_fixup = m_cfg->params_fixup; | |
232 | in_fixup = (~m_cfg->converter) & | |
233 | m_cfg->params_fixup; | |
234 | } | |
235 | } else { | |
236 | if (is_fe) { | |
237 | out_fixup = m_cfg->params_fixup; | |
238 | in_fixup = (~m_cfg->converter) & | |
239 | m_cfg->params_fixup; | |
240 | } else { | |
241 | in_fixup = m_cfg->params_fixup; | |
242 | out_fixup = (~m_cfg->converter) & | |
243 | m_cfg->params_fixup; | |
244 | } | |
245 | } | |
246 | ||
247 | skl_tplg_update_params(in_fmt, params, in_fixup); | |
248 | skl_tplg_update_params(out_fmt, params, out_fixup); | |
249 | } | |
250 | ||
251 | /* | |
252 | * A module needs input and output buffers, which are dependent upon pcm | |
253 | * params, so once we have calculate params, we need buffer calculation as | |
254 | * well. | |
255 | */ | |
256 | static void skl_tplg_update_buffer_size(struct skl_sst *ctx, | |
257 | struct skl_module_cfg *mcfg) | |
258 | { | |
259 | int multiplier = 1; | |
4cd9899f | 260 | struct skl_module_fmt *in_fmt, *out_fmt; |
f0c8e1d9 | 261 | int in_rate, out_rate; |
4cd9899f HS |
262 | |
263 | ||
264 | /* Since fixups is applied to pin 0 only, ibs, obs needs | |
265 | * change for pin 0 only | |
266 | */ | |
267 | in_fmt = &mcfg->in_fmt[0]; | |
268 | out_fmt = &mcfg->out_fmt[0]; | |
f7590d4f JK |
269 | |
270 | if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT) | |
271 | multiplier = 5; | |
f0c8e1d9 SP |
272 | |
273 | if (in_fmt->s_freq % 1000) | |
274 | in_rate = (in_fmt->s_freq / 1000) + 1; | |
275 | else | |
276 | in_rate = (in_fmt->s_freq / 1000); | |
277 | ||
278 | mcfg->ibs = in_rate * (mcfg->in_fmt->channels) * | |
279 | (mcfg->in_fmt->bit_depth >> 3) * | |
280 | multiplier; | |
281 | ||
282 | if (mcfg->out_fmt->s_freq % 1000) | |
283 | out_rate = (mcfg->out_fmt->s_freq / 1000) + 1; | |
284 | else | |
285 | out_rate = (mcfg->out_fmt->s_freq / 1000); | |
286 | ||
287 | mcfg->obs = out_rate * (mcfg->out_fmt->channels) * | |
288 | (mcfg->out_fmt->bit_depth >> 3) * | |
289 | multiplier; | |
f7590d4f JK |
290 | } |
291 | ||
2d1419a3 JK |
292 | static int skl_tplg_update_be_blob(struct snd_soc_dapm_widget *w, |
293 | struct skl_sst *ctx) | |
294 | { | |
295 | struct skl_module_cfg *m_cfg = w->priv; | |
296 | int link_type, dir; | |
297 | u32 ch, s_freq, s_fmt; | |
298 | struct nhlt_specific_cfg *cfg; | |
299 | struct skl *skl = get_skl_ctx(ctx->dev); | |
300 | ||
301 | /* check if we already have blob */ | |
302 | if (m_cfg->formats_config.caps_size > 0) | |
303 | return 0; | |
304 | ||
c7c6c736 | 305 | dev_dbg(ctx->dev, "Applying default cfg blob\n"); |
2d1419a3 JK |
306 | switch (m_cfg->dev_type) { |
307 | case SKL_DEVICE_DMIC: | |
308 | link_type = NHLT_LINK_DMIC; | |
c7c6c736 | 309 | dir = SNDRV_PCM_STREAM_CAPTURE; |
2d1419a3 JK |
310 | s_freq = m_cfg->in_fmt[0].s_freq; |
311 | s_fmt = m_cfg->in_fmt[0].bit_depth; | |
312 | ch = m_cfg->in_fmt[0].channels; | |
313 | break; | |
314 | ||
315 | case SKL_DEVICE_I2S: | |
316 | link_type = NHLT_LINK_SSP; | |
317 | if (m_cfg->hw_conn_type == SKL_CONN_SOURCE) { | |
c7c6c736 | 318 | dir = SNDRV_PCM_STREAM_PLAYBACK; |
2d1419a3 JK |
319 | s_freq = m_cfg->out_fmt[0].s_freq; |
320 | s_fmt = m_cfg->out_fmt[0].bit_depth; | |
321 | ch = m_cfg->out_fmt[0].channels; | |
c7c6c736 JK |
322 | } else { |
323 | dir = SNDRV_PCM_STREAM_CAPTURE; | |
324 | s_freq = m_cfg->in_fmt[0].s_freq; | |
325 | s_fmt = m_cfg->in_fmt[0].bit_depth; | |
326 | ch = m_cfg->in_fmt[0].channels; | |
2d1419a3 JK |
327 | } |
328 | break; | |
329 | ||
330 | default: | |
331 | return -EINVAL; | |
332 | } | |
333 | ||
334 | /* update the blob based on virtual bus_id and default params */ | |
335 | cfg = skl_get_ep_blob(skl, m_cfg->vbus_id, link_type, | |
336 | s_fmt, ch, s_freq, dir); | |
337 | if (cfg) { | |
338 | m_cfg->formats_config.caps_size = cfg->size; | |
339 | m_cfg->formats_config.caps = (u32 *) &cfg->caps; | |
340 | } else { | |
341 | dev_err(ctx->dev, "Blob NULL for id %x type %d dirn %d\n", | |
342 | m_cfg->vbus_id, link_type, dir); | |
343 | dev_err(ctx->dev, "PCM: ch %d, freq %d, fmt %d\n", | |
344 | ch, s_freq, s_fmt); | |
345 | return -EIO; | |
346 | } | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
f7590d4f JK |
351 | static void skl_tplg_update_module_params(struct snd_soc_dapm_widget *w, |
352 | struct skl_sst *ctx) | |
353 | { | |
354 | struct skl_module_cfg *m_cfg = w->priv; | |
355 | struct skl_pipe_params *params = m_cfg->pipe->p_params; | |
356 | int p_conn_type = m_cfg->pipe->conn_type; | |
357 | bool is_fe; | |
358 | ||
359 | if (!m_cfg->params_fixup) | |
360 | return; | |
361 | ||
362 | dev_dbg(ctx->dev, "Mconfig for widget=%s BEFORE updation\n", | |
363 | w->name); | |
364 | ||
365 | skl_dump_mconfig(ctx, m_cfg); | |
366 | ||
367 | if (p_conn_type == SKL_PIPE_CONN_TYPE_FE) | |
368 | is_fe = true; | |
369 | else | |
370 | is_fe = false; | |
371 | ||
372 | skl_tplg_update_params_fixup(m_cfg, params, is_fe); | |
373 | skl_tplg_update_buffer_size(ctx, m_cfg); | |
374 | ||
375 | dev_dbg(ctx->dev, "Mconfig for widget=%s AFTER updation\n", | |
376 | w->name); | |
377 | ||
378 | skl_dump_mconfig(ctx, m_cfg); | |
379 | } | |
380 | ||
abb74003 JK |
381 | /* |
382 | * some modules can have multiple params set from user control and | |
383 | * need to be set after module is initialized. If set_param flag is | |
384 | * set module params will be done after module is initialised. | |
385 | */ | |
386 | static int skl_tplg_set_module_params(struct snd_soc_dapm_widget *w, | |
387 | struct skl_sst *ctx) | |
388 | { | |
389 | int i, ret; | |
390 | struct skl_module_cfg *mconfig = w->priv; | |
391 | const struct snd_kcontrol_new *k; | |
392 | struct soc_bytes_ext *sb; | |
393 | struct skl_algo_data *bc; | |
394 | struct skl_specific_cfg *sp_cfg; | |
395 | ||
396 | if (mconfig->formats_config.caps_size > 0 && | |
4ced1827 | 397 | mconfig->formats_config.set_params == SKL_PARAM_SET) { |
abb74003 JK |
398 | sp_cfg = &mconfig->formats_config; |
399 | ret = skl_set_module_params(ctx, sp_cfg->caps, | |
400 | sp_cfg->caps_size, | |
401 | sp_cfg->param_id, mconfig); | |
402 | if (ret < 0) | |
403 | return ret; | |
404 | } | |
405 | ||
406 | for (i = 0; i < w->num_kcontrols; i++) { | |
407 | k = &w->kcontrol_news[i]; | |
408 | if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { | |
409 | sb = (void *) k->private_value; | |
410 | bc = (struct skl_algo_data *)sb->dobj.private; | |
411 | ||
4ced1827 | 412 | if (bc->set_params == SKL_PARAM_SET) { |
abb74003 JK |
413 | ret = skl_set_module_params(ctx, |
414 | (u32 *)bc->params, bc->max, | |
415 | bc->param_id, mconfig); | |
416 | if (ret < 0) | |
417 | return ret; | |
418 | } | |
419 | } | |
420 | } | |
421 | ||
422 | return 0; | |
423 | } | |
424 | ||
425 | /* | |
426 | * some module param can set from user control and this is required as | |
427 | * when module is initailzed. if module param is required in init it is | |
428 | * identifed by set_param flag. if set_param flag is not set, then this | |
429 | * parameter needs to set as part of module init. | |
430 | */ | |
431 | static int skl_tplg_set_module_init_data(struct snd_soc_dapm_widget *w) | |
432 | { | |
433 | const struct snd_kcontrol_new *k; | |
434 | struct soc_bytes_ext *sb; | |
435 | struct skl_algo_data *bc; | |
436 | struct skl_module_cfg *mconfig = w->priv; | |
437 | int i; | |
438 | ||
439 | for (i = 0; i < w->num_kcontrols; i++) { | |
440 | k = &w->kcontrol_news[i]; | |
441 | if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { | |
442 | sb = (struct soc_bytes_ext *)k->private_value; | |
443 | bc = (struct skl_algo_data *)sb->dobj.private; | |
444 | ||
4ced1827 | 445 | if (bc->set_params != SKL_PARAM_INIT) |
abb74003 JK |
446 | continue; |
447 | ||
448 | mconfig->formats_config.caps = (u32 *)&bc->params; | |
449 | mconfig->formats_config.caps_size = bc->max; | |
450 | ||
451 | break; | |
452 | } | |
453 | } | |
454 | ||
455 | return 0; | |
456 | } | |
457 | ||
e4e2d2f4 JK |
458 | /* |
459 | * Inside a pipe instance, we can have various modules. These modules need | |
460 | * to instantiated in DSP by invoking INIT_MODULE IPC, which is achieved by | |
461 | * skl_init_module() routine, so invoke that for all modules in a pipeline | |
462 | */ | |
463 | static int | |
464 | skl_tplg_init_pipe_modules(struct skl *skl, struct skl_pipe *pipe) | |
465 | { | |
466 | struct skl_pipe_module *w_module; | |
467 | struct snd_soc_dapm_widget *w; | |
468 | struct skl_module_cfg *mconfig; | |
469 | struct skl_sst *ctx = skl->skl_sst; | |
470 | int ret = 0; | |
471 | ||
472 | list_for_each_entry(w_module, &pipe->w_list, node) { | |
473 | w = w_module->w; | |
474 | mconfig = w->priv; | |
475 | ||
476 | /* check resource available */ | |
9ba8ffef | 477 | if (!skl_is_pipe_mcps_avail(skl, mconfig)) |
e4e2d2f4 JK |
478 | return -ENOMEM; |
479 | ||
6c5768b3 D |
480 | if (mconfig->is_loadable && ctx->dsp->fw_ops.load_mod) { |
481 | ret = ctx->dsp->fw_ops.load_mod(ctx->dsp, | |
482 | mconfig->id.module_id, mconfig->guid); | |
483 | if (ret < 0) | |
484 | return ret; | |
d643678b JK |
485 | |
486 | mconfig->m_state = SKL_MODULE_LOADED; | |
6c5768b3 D |
487 | } |
488 | ||
2d1419a3 JK |
489 | /* update blob if blob is null for be with default value */ |
490 | skl_tplg_update_be_blob(w, ctx); | |
491 | ||
f7590d4f JK |
492 | /* |
493 | * apply fix/conversion to module params based on | |
494 | * FE/BE params | |
495 | */ | |
496 | skl_tplg_update_module_params(w, ctx); | |
abb74003 JK |
497 | |
498 | skl_tplg_set_module_init_data(w); | |
9939a9c3 | 499 | ret = skl_init_module(ctx, mconfig); |
e4e2d2f4 JK |
500 | if (ret < 0) |
501 | return ret; | |
abb74003 | 502 | |
260eb73a | 503 | skl_tplg_alloc_pipe_mcps(skl, mconfig); |
abb74003 | 504 | ret = skl_tplg_set_module_params(w, ctx); |
e4e2d2f4 JK |
505 | if (ret < 0) |
506 | return ret; | |
507 | } | |
508 | ||
509 | return 0; | |
510 | } | |
d93f8e55 | 511 | |
6c5768b3 D |
512 | static int skl_tplg_unload_pipe_modules(struct skl_sst *ctx, |
513 | struct skl_pipe *pipe) | |
514 | { | |
515 | struct skl_pipe_module *w_module = NULL; | |
516 | struct skl_module_cfg *mconfig = NULL; | |
517 | ||
518 | list_for_each_entry(w_module, &pipe->w_list, node) { | |
519 | mconfig = w_module->w->priv; | |
520 | ||
d643678b JK |
521 | if (mconfig->is_loadable && ctx->dsp->fw_ops.unload_mod && |
522 | mconfig->m_state > SKL_MODULE_UNINIT) | |
6c5768b3 D |
523 | return ctx->dsp->fw_ops.unload_mod(ctx->dsp, |
524 | mconfig->id.module_id); | |
525 | } | |
526 | ||
527 | /* no modules to unload in this path, so return */ | |
528 | return 0; | |
529 | } | |
530 | ||
d93f8e55 VK |
531 | /* |
532 | * Mixer module represents a pipeline. So in the Pre-PMU event of mixer we | |
533 | * need create the pipeline. So we do following: | |
534 | * - check the resources | |
535 | * - Create the pipeline | |
536 | * - Initialize the modules in pipeline | |
537 | * - finally bind all modules together | |
538 | */ | |
539 | static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w, | |
540 | struct skl *skl) | |
541 | { | |
542 | int ret; | |
543 | struct skl_module_cfg *mconfig = w->priv; | |
544 | struct skl_pipe_module *w_module; | |
545 | struct skl_pipe *s_pipe = mconfig->pipe; | |
546 | struct skl_module_cfg *src_module = NULL, *dst_module; | |
547 | struct skl_sst *ctx = skl->skl_sst; | |
548 | ||
549 | /* check resource available */ | |
9ba8ffef | 550 | if (!skl_is_pipe_mcps_avail(skl, mconfig)) |
d93f8e55 VK |
551 | return -EBUSY; |
552 | ||
9ba8ffef | 553 | if (!skl_is_pipe_mem_avail(skl, mconfig)) |
d93f8e55 VK |
554 | return -ENOMEM; |
555 | ||
556 | /* | |
557 | * Create a list of modules for pipe. | |
558 | * This list contains modules from source to sink | |
559 | */ | |
560 | ret = skl_create_pipeline(ctx, mconfig->pipe); | |
561 | if (ret < 0) | |
562 | return ret; | |
563 | ||
260eb73a D |
564 | skl_tplg_alloc_pipe_mem(skl, mconfig); |
565 | skl_tplg_alloc_pipe_mcps(skl, mconfig); | |
566 | ||
d93f8e55 VK |
567 | /* Init all pipe modules from source to sink */ |
568 | ret = skl_tplg_init_pipe_modules(skl, s_pipe); | |
569 | if (ret < 0) | |
570 | return ret; | |
571 | ||
572 | /* Bind modules from source to sink */ | |
573 | list_for_each_entry(w_module, &s_pipe->w_list, node) { | |
574 | dst_module = w_module->w->priv; | |
575 | ||
576 | if (src_module == NULL) { | |
577 | src_module = dst_module; | |
578 | continue; | |
579 | } | |
580 | ||
581 | ret = skl_bind_modules(ctx, src_module, dst_module); | |
582 | if (ret < 0) | |
583 | return ret; | |
584 | ||
585 | src_module = dst_module; | |
586 | } | |
587 | ||
588 | return 0; | |
589 | } | |
590 | ||
cc6a4044 JK |
591 | /* |
592 | * Some modules require params to be set after the module is bound to | |
593 | * all pins connected. | |
594 | * | |
595 | * The module provider initializes set_param flag for such modules and we | |
596 | * send params after binding | |
597 | */ | |
598 | static int skl_tplg_set_module_bind_params(struct snd_soc_dapm_widget *w, | |
599 | struct skl_module_cfg *mcfg, struct skl_sst *ctx) | |
600 | { | |
601 | int i, ret; | |
602 | struct skl_module_cfg *mconfig = w->priv; | |
603 | const struct snd_kcontrol_new *k; | |
604 | struct soc_bytes_ext *sb; | |
605 | struct skl_algo_data *bc; | |
606 | struct skl_specific_cfg *sp_cfg; | |
607 | ||
608 | /* | |
609 | * check all out/in pins are in bind state. | |
610 | * if so set the module param | |
611 | */ | |
612 | for (i = 0; i < mcfg->max_out_queue; i++) { | |
613 | if (mcfg->m_out_pin[i].pin_state != SKL_PIN_BIND_DONE) | |
614 | return 0; | |
615 | } | |
616 | ||
617 | for (i = 0; i < mcfg->max_in_queue; i++) { | |
618 | if (mcfg->m_in_pin[i].pin_state != SKL_PIN_BIND_DONE) | |
619 | return 0; | |
620 | } | |
621 | ||
622 | if (mconfig->formats_config.caps_size > 0 && | |
623 | mconfig->formats_config.set_params == SKL_PARAM_BIND) { | |
624 | sp_cfg = &mconfig->formats_config; | |
625 | ret = skl_set_module_params(ctx, sp_cfg->caps, | |
626 | sp_cfg->caps_size, | |
627 | sp_cfg->param_id, mconfig); | |
628 | if (ret < 0) | |
629 | return ret; | |
630 | } | |
631 | ||
632 | for (i = 0; i < w->num_kcontrols; i++) { | |
633 | k = &w->kcontrol_news[i]; | |
634 | if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { | |
635 | sb = (void *) k->private_value; | |
636 | bc = (struct skl_algo_data *)sb->dobj.private; | |
637 | ||
638 | if (bc->set_params == SKL_PARAM_BIND) { | |
639 | ret = skl_set_module_params(ctx, | |
640 | (u32 *)bc->params, bc->max, | |
641 | bc->param_id, mconfig); | |
642 | if (ret < 0) | |
643 | return ret; | |
644 | } | |
645 | } | |
646 | } | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
8724ff17 JK |
651 | static int skl_tplg_bind_sinks(struct snd_soc_dapm_widget *w, |
652 | struct skl *skl, | |
6bd4cf85 | 653 | struct snd_soc_dapm_widget *src_w, |
8724ff17 | 654 | struct skl_module_cfg *src_mconfig) |
d93f8e55 VK |
655 | { |
656 | struct snd_soc_dapm_path *p; | |
0ed95d76 | 657 | struct snd_soc_dapm_widget *sink = NULL, *next_sink = NULL; |
8724ff17 | 658 | struct skl_module_cfg *sink_mconfig; |
d93f8e55 | 659 | struct skl_sst *ctx = skl->skl_sst; |
8724ff17 | 660 | int ret; |
d93f8e55 | 661 | |
8724ff17 | 662 | snd_soc_dapm_widget_for_each_sink_path(w, p) { |
d93f8e55 VK |
663 | if (!p->connect) |
664 | continue; | |
665 | ||
666 | dev_dbg(ctx->dev, "%s: src widget=%s\n", __func__, w->name); | |
667 | dev_dbg(ctx->dev, "%s: sink widget=%s\n", __func__, p->sink->name); | |
668 | ||
0ed95d76 | 669 | next_sink = p->sink; |
6bd4cf85 JK |
670 | |
671 | if (!is_skl_dsp_widget_type(p->sink)) | |
672 | return skl_tplg_bind_sinks(p->sink, skl, src_w, src_mconfig); | |
673 | ||
d93f8e55 VK |
674 | /* |
675 | * here we will check widgets in sink pipelines, so that | |
676 | * can be any widgets type and we are only interested if | |
677 | * they are ones used for SKL so check that first | |
678 | */ | |
679 | if ((p->sink->priv != NULL) && | |
680 | is_skl_dsp_widget_type(p->sink)) { | |
681 | ||
682 | sink = p->sink; | |
d93f8e55 VK |
683 | sink_mconfig = sink->priv; |
684 | ||
cc6a4044 JK |
685 | if (src_mconfig->m_state == SKL_MODULE_UNINIT || |
686 | sink_mconfig->m_state == SKL_MODULE_UNINIT) | |
687 | continue; | |
688 | ||
d93f8e55 VK |
689 | /* Bind source to sink, mixin is always source */ |
690 | ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig); | |
691 | if (ret) | |
692 | return ret; | |
693 | ||
cc6a4044 JK |
694 | /* set module params after bind */ |
695 | skl_tplg_set_module_bind_params(src_w, src_mconfig, ctx); | |
696 | skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx); | |
697 | ||
d93f8e55 VK |
698 | /* Start sinks pipe first */ |
699 | if (sink_mconfig->pipe->state != SKL_PIPE_STARTED) { | |
d1730c3d JK |
700 | if (sink_mconfig->pipe->conn_type != |
701 | SKL_PIPE_CONN_TYPE_FE) | |
702 | ret = skl_run_pipe(ctx, | |
703 | sink_mconfig->pipe); | |
d93f8e55 VK |
704 | if (ret) |
705 | return ret; | |
706 | } | |
d93f8e55 VK |
707 | } |
708 | } | |
709 | ||
8724ff17 | 710 | if (!sink) |
6bd4cf85 | 711 | return skl_tplg_bind_sinks(next_sink, skl, src_w, src_mconfig); |
8724ff17 JK |
712 | |
713 | return 0; | |
714 | } | |
715 | ||
716 | /* | |
717 | * A PGA represents a module in a pipeline. So in the Pre-PMU event of PGA | |
718 | * we need to do following: | |
719 | * - Bind to sink pipeline | |
720 | * Since the sink pipes can be running and we don't get mixer event on | |
721 | * connect for already running mixer, we need to find the sink pipes | |
722 | * here and bind to them. This way dynamic connect works. | |
723 | * - Start sink pipeline, if not running | |
724 | * - Then run current pipe | |
725 | */ | |
726 | static int skl_tplg_pga_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w, | |
727 | struct skl *skl) | |
728 | { | |
729 | struct skl_module_cfg *src_mconfig; | |
730 | struct skl_sst *ctx = skl->skl_sst; | |
731 | int ret = 0; | |
732 | ||
733 | src_mconfig = w->priv; | |
734 | ||
735 | /* | |
736 | * find which sink it is connected to, bind with the sink, | |
737 | * if sink is not started, start sink pipe first, then start | |
738 | * this pipe | |
739 | */ | |
6bd4cf85 | 740 | ret = skl_tplg_bind_sinks(w, skl, w, src_mconfig); |
d93f8e55 VK |
741 | if (ret) |
742 | return ret; | |
743 | ||
d93f8e55 | 744 | /* Start source pipe last after starting all sinks */ |
d1730c3d JK |
745 | if (src_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE) |
746 | return skl_run_pipe(ctx, src_mconfig->pipe); | |
d93f8e55 VK |
747 | |
748 | return 0; | |
749 | } | |
750 | ||
8724ff17 JK |
751 | static struct snd_soc_dapm_widget *skl_get_src_dsp_widget( |
752 | struct snd_soc_dapm_widget *w, struct skl *skl) | |
753 | { | |
754 | struct snd_soc_dapm_path *p; | |
755 | struct snd_soc_dapm_widget *src_w = NULL; | |
756 | struct skl_sst *ctx = skl->skl_sst; | |
757 | ||
758 | snd_soc_dapm_widget_for_each_source_path(w, p) { | |
759 | src_w = p->source; | |
760 | if (!p->connect) | |
761 | continue; | |
762 | ||
763 | dev_dbg(ctx->dev, "sink widget=%s\n", w->name); | |
764 | dev_dbg(ctx->dev, "src widget=%s\n", p->source->name); | |
765 | ||
766 | /* | |
767 | * here we will check widgets in sink pipelines, so that can | |
768 | * be any widgets type and we are only interested if they are | |
769 | * ones used for SKL so check that first | |
770 | */ | |
771 | if ((p->source->priv != NULL) && | |
772 | is_skl_dsp_widget_type(p->source)) { | |
773 | return p->source; | |
774 | } | |
775 | } | |
776 | ||
777 | if (src_w != NULL) | |
778 | return skl_get_src_dsp_widget(src_w, skl); | |
779 | ||
780 | return NULL; | |
781 | } | |
782 | ||
d93f8e55 VK |
783 | /* |
784 | * in the Post-PMU event of mixer we need to do following: | |
785 | * - Check if this pipe is running | |
786 | * - if not, then | |
787 | * - bind this pipeline to its source pipeline | |
788 | * if source pipe is already running, this means it is a dynamic | |
789 | * connection and we need to bind only to that pipe | |
790 | * - start this pipeline | |
791 | */ | |
792 | static int skl_tplg_mixer_dapm_post_pmu_event(struct snd_soc_dapm_widget *w, | |
793 | struct skl *skl) | |
794 | { | |
795 | int ret = 0; | |
d93f8e55 VK |
796 | struct snd_soc_dapm_widget *source, *sink; |
797 | struct skl_module_cfg *src_mconfig, *sink_mconfig; | |
798 | struct skl_sst *ctx = skl->skl_sst; | |
799 | int src_pipe_started = 0; | |
800 | ||
801 | sink = w; | |
802 | sink_mconfig = sink->priv; | |
803 | ||
804 | /* | |
805 | * If source pipe is already started, that means source is driving | |
806 | * one more sink before this sink got connected, Since source is | |
807 | * started, bind this sink to source and start this pipe. | |
808 | */ | |
8724ff17 JK |
809 | source = skl_get_src_dsp_widget(w, skl); |
810 | if (source != NULL) { | |
811 | src_mconfig = source->priv; | |
812 | sink_mconfig = sink->priv; | |
813 | src_pipe_started = 1; | |
d93f8e55 VK |
814 | |
815 | /* | |
8724ff17 JK |
816 | * check pipe state, then no need to bind or start the |
817 | * pipe | |
d93f8e55 | 818 | */ |
8724ff17 JK |
819 | if (src_mconfig->pipe->state != SKL_PIPE_STARTED) |
820 | src_pipe_started = 0; | |
d93f8e55 VK |
821 | } |
822 | ||
823 | if (src_pipe_started) { | |
824 | ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig); | |
825 | if (ret) | |
826 | return ret; | |
827 | ||
cc6a4044 JK |
828 | /* set module params after bind */ |
829 | skl_tplg_set_module_bind_params(source, src_mconfig, ctx); | |
830 | skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx); | |
831 | ||
d1730c3d JK |
832 | if (sink_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE) |
833 | ret = skl_run_pipe(ctx, sink_mconfig->pipe); | |
d93f8e55 VK |
834 | } |
835 | ||
836 | return ret; | |
837 | } | |
838 | ||
839 | /* | |
840 | * in the Pre-PMD event of mixer we need to do following: | |
841 | * - Stop the pipe | |
842 | * - find the source connections and remove that from dapm_path_list | |
843 | * - unbind with source pipelines if still connected | |
844 | */ | |
845 | static int skl_tplg_mixer_dapm_pre_pmd_event(struct snd_soc_dapm_widget *w, | |
846 | struct skl *skl) | |
847 | { | |
d93f8e55 | 848 | struct skl_module_cfg *src_mconfig, *sink_mconfig; |
ce1b5551 | 849 | int ret = 0, i; |
d93f8e55 VK |
850 | struct skl_sst *ctx = skl->skl_sst; |
851 | ||
ce1b5551 | 852 | sink_mconfig = w->priv; |
d93f8e55 VK |
853 | |
854 | /* Stop the pipe */ | |
855 | ret = skl_stop_pipe(ctx, sink_mconfig->pipe); | |
856 | if (ret) | |
857 | return ret; | |
858 | ||
ce1b5551 JK |
859 | for (i = 0; i < sink_mconfig->max_in_queue; i++) { |
860 | if (sink_mconfig->m_in_pin[i].pin_state == SKL_PIN_BIND_DONE) { | |
861 | src_mconfig = sink_mconfig->m_in_pin[i].tgt_mcfg; | |
862 | if (!src_mconfig) | |
863 | continue; | |
864 | /* | |
865 | * If path_found == 1, that means pmd for source | |
866 | * pipe has not occurred, source is connected to | |
867 | * some other sink. so its responsibility of sink | |
868 | * to unbind itself from source. | |
869 | */ | |
870 | ret = skl_stop_pipe(ctx, src_mconfig->pipe); | |
871 | if (ret < 0) | |
872 | return ret; | |
d93f8e55 | 873 | |
ce1b5551 JK |
874 | ret = skl_unbind_modules(ctx, |
875 | src_mconfig, sink_mconfig); | |
d93f8e55 | 876 | } |
d93f8e55 VK |
877 | } |
878 | ||
879 | return ret; | |
880 | } | |
881 | ||
882 | /* | |
883 | * in the Post-PMD event of mixer we need to do following: | |
884 | * - Free the mcps used | |
885 | * - Free the mem used | |
886 | * - Unbind the modules within the pipeline | |
887 | * - Delete the pipeline (modules are not required to be explicitly | |
888 | * deleted, pipeline delete is enough here | |
889 | */ | |
890 | static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w, | |
891 | struct skl *skl) | |
892 | { | |
893 | struct skl_module_cfg *mconfig = w->priv; | |
894 | struct skl_pipe_module *w_module; | |
895 | struct skl_module_cfg *src_module = NULL, *dst_module; | |
896 | struct skl_sst *ctx = skl->skl_sst; | |
897 | struct skl_pipe *s_pipe = mconfig->pipe; | |
898 | int ret = 0; | |
899 | ||
260eb73a D |
900 | if (s_pipe->state == SKL_PIPE_INVALID) |
901 | return -EINVAL; | |
902 | ||
d93f8e55 | 903 | skl_tplg_free_pipe_mcps(skl, mconfig); |
65976878 | 904 | skl_tplg_free_pipe_mem(skl, mconfig); |
d93f8e55 VK |
905 | |
906 | list_for_each_entry(w_module, &s_pipe->w_list, node) { | |
907 | dst_module = w_module->w->priv; | |
908 | ||
260eb73a D |
909 | if (mconfig->m_state >= SKL_MODULE_INIT_DONE) |
910 | skl_tplg_free_pipe_mcps(skl, dst_module); | |
d93f8e55 VK |
911 | if (src_module == NULL) { |
912 | src_module = dst_module; | |
913 | continue; | |
914 | } | |
915 | ||
7ca42f5a | 916 | skl_unbind_modules(ctx, src_module, dst_module); |
d93f8e55 VK |
917 | src_module = dst_module; |
918 | } | |
919 | ||
920 | ret = skl_delete_pipe(ctx, mconfig->pipe); | |
d93f8e55 | 921 | |
6c5768b3 | 922 | return skl_tplg_unload_pipe_modules(ctx, s_pipe); |
d93f8e55 VK |
923 | } |
924 | ||
925 | /* | |
926 | * in the Post-PMD event of PGA we need to do following: | |
927 | * - Free the mcps used | |
928 | * - Stop the pipeline | |
929 | * - In source pipe is connected, unbind with source pipelines | |
930 | */ | |
931 | static int skl_tplg_pga_dapm_post_pmd_event(struct snd_soc_dapm_widget *w, | |
932 | struct skl *skl) | |
933 | { | |
d93f8e55 | 934 | struct skl_module_cfg *src_mconfig, *sink_mconfig; |
ce1b5551 | 935 | int ret = 0, i; |
d93f8e55 VK |
936 | struct skl_sst *ctx = skl->skl_sst; |
937 | ||
ce1b5551 | 938 | src_mconfig = w->priv; |
d93f8e55 | 939 | |
d93f8e55 VK |
940 | /* Stop the pipe since this is a mixin module */ |
941 | ret = skl_stop_pipe(ctx, src_mconfig->pipe); | |
942 | if (ret) | |
943 | return ret; | |
944 | ||
ce1b5551 JK |
945 | for (i = 0; i < src_mconfig->max_out_queue; i++) { |
946 | if (src_mconfig->m_out_pin[i].pin_state == SKL_PIN_BIND_DONE) { | |
947 | sink_mconfig = src_mconfig->m_out_pin[i].tgt_mcfg; | |
948 | if (!sink_mconfig) | |
949 | continue; | |
950 | /* | |
951 | * This is a connecter and if path is found that means | |
952 | * unbind between source and sink has not happened yet | |
953 | */ | |
ce1b5551 JK |
954 | ret = skl_unbind_modules(ctx, src_mconfig, |
955 | sink_mconfig); | |
d93f8e55 VK |
956 | } |
957 | } | |
958 | ||
d93f8e55 VK |
959 | return ret; |
960 | } | |
961 | ||
962 | /* | |
963 | * In modelling, we assume there will be ONLY one mixer in a pipeline. If | |
964 | * mixer is not required then it is treated as static mixer aka vmixer with | |
965 | * a hard path to source module | |
966 | * So we don't need to check if source is started or not as hard path puts | |
967 | * dependency on each other | |
968 | */ | |
969 | static int skl_tplg_vmixer_event(struct snd_soc_dapm_widget *w, | |
970 | struct snd_kcontrol *k, int event) | |
971 | { | |
972 | struct snd_soc_dapm_context *dapm = w->dapm; | |
973 | struct skl *skl = get_skl_ctx(dapm->dev); | |
974 | ||
975 | switch (event) { | |
976 | case SND_SOC_DAPM_PRE_PMU: | |
977 | return skl_tplg_mixer_dapm_pre_pmu_event(w, skl); | |
978 | ||
de1fedf2 JK |
979 | case SND_SOC_DAPM_POST_PMU: |
980 | return skl_tplg_mixer_dapm_post_pmu_event(w, skl); | |
981 | ||
982 | case SND_SOC_DAPM_PRE_PMD: | |
983 | return skl_tplg_mixer_dapm_pre_pmd_event(w, skl); | |
984 | ||
d93f8e55 VK |
985 | case SND_SOC_DAPM_POST_PMD: |
986 | return skl_tplg_mixer_dapm_post_pmd_event(w, skl); | |
987 | } | |
988 | ||
989 | return 0; | |
990 | } | |
991 | ||
992 | /* | |
993 | * In modelling, we assume there will be ONLY one mixer in a pipeline. If a | |
994 | * second one is required that is created as another pipe entity. | |
995 | * The mixer is responsible for pipe management and represent a pipeline | |
996 | * instance | |
997 | */ | |
998 | static int skl_tplg_mixer_event(struct snd_soc_dapm_widget *w, | |
999 | struct snd_kcontrol *k, int event) | |
1000 | { | |
1001 | struct snd_soc_dapm_context *dapm = w->dapm; | |
1002 | struct skl *skl = get_skl_ctx(dapm->dev); | |
1003 | ||
1004 | switch (event) { | |
1005 | case SND_SOC_DAPM_PRE_PMU: | |
1006 | return skl_tplg_mixer_dapm_pre_pmu_event(w, skl); | |
1007 | ||
1008 | case SND_SOC_DAPM_POST_PMU: | |
1009 | return skl_tplg_mixer_dapm_post_pmu_event(w, skl); | |
1010 | ||
1011 | case SND_SOC_DAPM_PRE_PMD: | |
1012 | return skl_tplg_mixer_dapm_pre_pmd_event(w, skl); | |
1013 | ||
1014 | case SND_SOC_DAPM_POST_PMD: | |
1015 | return skl_tplg_mixer_dapm_post_pmd_event(w, skl); | |
1016 | } | |
1017 | ||
1018 | return 0; | |
1019 | } | |
1020 | ||
1021 | /* | |
1022 | * In modelling, we assumed rest of the modules in pipeline are PGA. But we | |
1023 | * are interested in last PGA (leaf PGA) in a pipeline to disconnect with | |
1024 | * the sink when it is running (two FE to one BE or one FE to two BE) | |
1025 | * scenarios | |
1026 | */ | |
1027 | static int skl_tplg_pga_event(struct snd_soc_dapm_widget *w, | |
1028 | struct snd_kcontrol *k, int event) | |
1029 | ||
1030 | { | |
1031 | struct snd_soc_dapm_context *dapm = w->dapm; | |
1032 | struct skl *skl = get_skl_ctx(dapm->dev); | |
1033 | ||
1034 | switch (event) { | |
1035 | case SND_SOC_DAPM_PRE_PMU: | |
1036 | return skl_tplg_pga_dapm_pre_pmu_event(w, skl); | |
1037 | ||
1038 | case SND_SOC_DAPM_POST_PMD: | |
1039 | return skl_tplg_pga_dapm_post_pmd_event(w, skl); | |
1040 | } | |
1041 | ||
1042 | return 0; | |
1043 | } | |
cfb0a873 | 1044 | |
140adfba JK |
1045 | static int skl_tplg_tlv_control_get(struct snd_kcontrol *kcontrol, |
1046 | unsigned int __user *data, unsigned int size) | |
1047 | { | |
1048 | struct soc_bytes_ext *sb = | |
1049 | (struct soc_bytes_ext *)kcontrol->private_value; | |
1050 | struct skl_algo_data *bc = (struct skl_algo_data *)sb->dobj.private; | |
7d9f2911 OA |
1051 | struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol); |
1052 | struct skl_module_cfg *mconfig = w->priv; | |
1053 | struct skl *skl = get_skl_ctx(w->dapm->dev); | |
1054 | ||
1055 | if (w->power) | |
1056 | skl_get_module_params(skl->skl_sst, (u32 *)bc->params, | |
1057 | bc->max, bc->param_id, mconfig); | |
140adfba | 1058 | |
41556f68 VK |
1059 | /* decrement size for TLV header */ |
1060 | size -= 2 * sizeof(u32); | |
1061 | ||
1062 | /* check size as we don't want to send kernel data */ | |
1063 | if (size > bc->max) | |
1064 | size = bc->max; | |
1065 | ||
140adfba JK |
1066 | if (bc->params) { |
1067 | if (copy_to_user(data, &bc->param_id, sizeof(u32))) | |
1068 | return -EFAULT; | |
e8bc3c99 | 1069 | if (copy_to_user(data + 1, &size, sizeof(u32))) |
140adfba | 1070 | return -EFAULT; |
e8bc3c99 | 1071 | if (copy_to_user(data + 2, bc->params, size)) |
140adfba JK |
1072 | return -EFAULT; |
1073 | } | |
1074 | ||
1075 | return 0; | |
1076 | } | |
1077 | ||
1078 | #define SKL_PARAM_VENDOR_ID 0xff | |
1079 | ||
1080 | static int skl_tplg_tlv_control_set(struct snd_kcontrol *kcontrol, | |
1081 | const unsigned int __user *data, unsigned int size) | |
1082 | { | |
1083 | struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol); | |
1084 | struct skl_module_cfg *mconfig = w->priv; | |
1085 | struct soc_bytes_ext *sb = | |
1086 | (struct soc_bytes_ext *)kcontrol->private_value; | |
1087 | struct skl_algo_data *ac = (struct skl_algo_data *)sb->dobj.private; | |
1088 | struct skl *skl = get_skl_ctx(w->dapm->dev); | |
1089 | ||
1090 | if (ac->params) { | |
1091 | /* | |
1092 | * if the param_is is of type Vendor, firmware expects actual | |
1093 | * parameter id and size from the control. | |
1094 | */ | |
1095 | if (ac->param_id == SKL_PARAM_VENDOR_ID) { | |
1096 | if (copy_from_user(ac->params, data, size)) | |
1097 | return -EFAULT; | |
1098 | } else { | |
1099 | if (copy_from_user(ac->params, | |
65b4bcb8 | 1100 | data + 2, size)) |
140adfba JK |
1101 | return -EFAULT; |
1102 | } | |
1103 | ||
1104 | if (w->power) | |
1105 | return skl_set_module_params(skl->skl_sst, | |
1106 | (u32 *)ac->params, ac->max, | |
1107 | ac->param_id, mconfig); | |
1108 | } | |
1109 | ||
1110 | return 0; | |
1111 | } | |
1112 | ||
cfb0a873 VK |
1113 | /* |
1114 | * The FE params are passed by hw_params of the DAI. | |
1115 | * On hw_params, the params are stored in Gateway module of the FE and we | |
1116 | * need to calculate the format in DSP module configuration, that | |
1117 | * conversion is done here | |
1118 | */ | |
1119 | int skl_tplg_update_pipe_params(struct device *dev, | |
1120 | struct skl_module_cfg *mconfig, | |
1121 | struct skl_pipe_params *params) | |
1122 | { | |
1123 | struct skl_pipe *pipe = mconfig->pipe; | |
1124 | struct skl_module_fmt *format = NULL; | |
1125 | ||
1126 | memcpy(pipe->p_params, params, sizeof(*params)); | |
1127 | ||
1128 | if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
4cd9899f | 1129 | format = &mconfig->in_fmt[0]; |
cfb0a873 | 1130 | else |
4cd9899f | 1131 | format = &mconfig->out_fmt[0]; |
cfb0a873 VK |
1132 | |
1133 | /* set the hw_params */ | |
1134 | format->s_freq = params->s_freq; | |
1135 | format->channels = params->ch; | |
1136 | format->valid_bit_depth = skl_get_bit_depth(params->s_fmt); | |
1137 | ||
1138 | /* | |
1139 | * 16 bit is 16 bit container whereas 24 bit is in 32 bit | |
1140 | * container so update bit depth accordingly | |
1141 | */ | |
1142 | switch (format->valid_bit_depth) { | |
1143 | case SKL_DEPTH_16BIT: | |
1144 | format->bit_depth = format->valid_bit_depth; | |
1145 | break; | |
1146 | ||
1147 | case SKL_DEPTH_24BIT: | |
6654f39e | 1148 | case SKL_DEPTH_32BIT: |
cfb0a873 VK |
1149 | format->bit_depth = SKL_DEPTH_32BIT; |
1150 | break; | |
1151 | ||
1152 | default: | |
1153 | dev_err(dev, "Invalid bit depth %x for pipe\n", | |
1154 | format->valid_bit_depth); | |
1155 | return -EINVAL; | |
1156 | } | |
1157 | ||
1158 | if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
1159 | mconfig->ibs = (format->s_freq / 1000) * | |
1160 | (format->channels) * | |
1161 | (format->bit_depth >> 3); | |
1162 | } else { | |
1163 | mconfig->obs = (format->s_freq / 1000) * | |
1164 | (format->channels) * | |
1165 | (format->bit_depth >> 3); | |
1166 | } | |
1167 | ||
1168 | return 0; | |
1169 | } | |
1170 | ||
1171 | /* | |
1172 | * Query the module config for the FE DAI | |
1173 | * This is used to find the hw_params set for that DAI and apply to FE | |
1174 | * pipeline | |
1175 | */ | |
1176 | struct skl_module_cfg * | |
1177 | skl_tplg_fe_get_cpr_module(struct snd_soc_dai *dai, int stream) | |
1178 | { | |
1179 | struct snd_soc_dapm_widget *w; | |
1180 | struct snd_soc_dapm_path *p = NULL; | |
1181 | ||
1182 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
1183 | w = dai->playback_widget; | |
f0900eb2 | 1184 | snd_soc_dapm_widget_for_each_sink_path(w, p) { |
cfb0a873 | 1185 | if (p->connect && p->sink->power && |
a28f51db | 1186 | !is_skl_dsp_widget_type(p->sink)) |
cfb0a873 VK |
1187 | continue; |
1188 | ||
1189 | if (p->sink->priv) { | |
1190 | dev_dbg(dai->dev, "set params for %s\n", | |
1191 | p->sink->name); | |
1192 | return p->sink->priv; | |
1193 | } | |
1194 | } | |
1195 | } else { | |
1196 | w = dai->capture_widget; | |
f0900eb2 | 1197 | snd_soc_dapm_widget_for_each_source_path(w, p) { |
cfb0a873 | 1198 | if (p->connect && p->source->power && |
a28f51db | 1199 | !is_skl_dsp_widget_type(p->source)) |
cfb0a873 VK |
1200 | continue; |
1201 | ||
1202 | if (p->source->priv) { | |
1203 | dev_dbg(dai->dev, "set params for %s\n", | |
1204 | p->source->name); | |
1205 | return p->source->priv; | |
1206 | } | |
1207 | } | |
1208 | } | |
1209 | ||
1210 | return NULL; | |
1211 | } | |
1212 | ||
718a42b5 D |
1213 | static struct skl_module_cfg *skl_get_mconfig_pb_cpr( |
1214 | struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w) | |
1215 | { | |
1216 | struct snd_soc_dapm_path *p; | |
1217 | struct skl_module_cfg *mconfig = NULL; | |
1218 | ||
1219 | snd_soc_dapm_widget_for_each_source_path(w, p) { | |
1220 | if (w->endpoints[SND_SOC_DAPM_DIR_OUT] > 0) { | |
1221 | if (p->connect && | |
1222 | (p->sink->id == snd_soc_dapm_aif_out) && | |
1223 | p->source->priv) { | |
1224 | mconfig = p->source->priv; | |
1225 | return mconfig; | |
1226 | } | |
1227 | mconfig = skl_get_mconfig_pb_cpr(dai, p->source); | |
1228 | if (mconfig) | |
1229 | return mconfig; | |
1230 | } | |
1231 | } | |
1232 | return mconfig; | |
1233 | } | |
1234 | ||
1235 | static struct skl_module_cfg *skl_get_mconfig_cap_cpr( | |
1236 | struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w) | |
1237 | { | |
1238 | struct snd_soc_dapm_path *p; | |
1239 | struct skl_module_cfg *mconfig = NULL; | |
1240 | ||
1241 | snd_soc_dapm_widget_for_each_sink_path(w, p) { | |
1242 | if (w->endpoints[SND_SOC_DAPM_DIR_IN] > 0) { | |
1243 | if (p->connect && | |
1244 | (p->source->id == snd_soc_dapm_aif_in) && | |
1245 | p->sink->priv) { | |
1246 | mconfig = p->sink->priv; | |
1247 | return mconfig; | |
1248 | } | |
1249 | mconfig = skl_get_mconfig_cap_cpr(dai, p->sink); | |
1250 | if (mconfig) | |
1251 | return mconfig; | |
1252 | } | |
1253 | } | |
1254 | return mconfig; | |
1255 | } | |
1256 | ||
1257 | struct skl_module_cfg * | |
1258 | skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, int stream) | |
1259 | { | |
1260 | struct snd_soc_dapm_widget *w; | |
1261 | struct skl_module_cfg *mconfig; | |
1262 | ||
1263 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
1264 | w = dai->playback_widget; | |
1265 | mconfig = skl_get_mconfig_pb_cpr(dai, w); | |
1266 | } else { | |
1267 | w = dai->capture_widget; | |
1268 | mconfig = skl_get_mconfig_cap_cpr(dai, w); | |
1269 | } | |
1270 | return mconfig; | |
1271 | } | |
1272 | ||
cfb0a873 VK |
1273 | static u8 skl_tplg_be_link_type(int dev_type) |
1274 | { | |
1275 | int ret; | |
1276 | ||
1277 | switch (dev_type) { | |
1278 | case SKL_DEVICE_BT: | |
1279 | ret = NHLT_LINK_SSP; | |
1280 | break; | |
1281 | ||
1282 | case SKL_DEVICE_DMIC: | |
1283 | ret = NHLT_LINK_DMIC; | |
1284 | break; | |
1285 | ||
1286 | case SKL_DEVICE_I2S: | |
1287 | ret = NHLT_LINK_SSP; | |
1288 | break; | |
1289 | ||
1290 | case SKL_DEVICE_HDALINK: | |
1291 | ret = NHLT_LINK_HDA; | |
1292 | break; | |
1293 | ||
1294 | default: | |
1295 | ret = NHLT_LINK_INVALID; | |
1296 | break; | |
1297 | } | |
1298 | ||
1299 | return ret; | |
1300 | } | |
1301 | ||
1302 | /* | |
1303 | * Fill the BE gateway parameters | |
1304 | * The BE gateway expects a blob of parameters which are kept in the ACPI | |
1305 | * NHLT blob, so query the blob for interface type (i2s/pdm) and instance. | |
1306 | * The port can have multiple settings so pick based on the PCM | |
1307 | * parameters | |
1308 | */ | |
1309 | static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai, | |
1310 | struct skl_module_cfg *mconfig, | |
1311 | struct skl_pipe_params *params) | |
1312 | { | |
1313 | struct skl_pipe *pipe = mconfig->pipe; | |
1314 | struct nhlt_specific_cfg *cfg; | |
1315 | struct skl *skl = get_skl_ctx(dai->dev); | |
1316 | int link_type = skl_tplg_be_link_type(mconfig->dev_type); | |
1317 | ||
1318 | memcpy(pipe->p_params, params, sizeof(*params)); | |
1319 | ||
b30c275e JK |
1320 | if (link_type == NHLT_LINK_HDA) |
1321 | return 0; | |
1322 | ||
cfb0a873 VK |
1323 | /* update the blob based on virtual bus_id*/ |
1324 | cfg = skl_get_ep_blob(skl, mconfig->vbus_id, link_type, | |
1325 | params->s_fmt, params->ch, | |
1326 | params->s_freq, params->stream); | |
1327 | if (cfg) { | |
1328 | mconfig->formats_config.caps_size = cfg->size; | |
bc03281a | 1329 | mconfig->formats_config.caps = (u32 *) &cfg->caps; |
cfb0a873 VK |
1330 | } else { |
1331 | dev_err(dai->dev, "Blob NULL for id %x type %d dirn %d\n", | |
1332 | mconfig->vbus_id, link_type, | |
1333 | params->stream); | |
1334 | dev_err(dai->dev, "PCM: ch %d, freq %d, fmt %d\n", | |
1335 | params->ch, params->s_freq, params->s_fmt); | |
1336 | return -EINVAL; | |
1337 | } | |
1338 | ||
1339 | return 0; | |
1340 | } | |
1341 | ||
1342 | static int skl_tplg_be_set_src_pipe_params(struct snd_soc_dai *dai, | |
1343 | struct snd_soc_dapm_widget *w, | |
1344 | struct skl_pipe_params *params) | |
1345 | { | |
1346 | struct snd_soc_dapm_path *p; | |
4d8adccb | 1347 | int ret = -EIO; |
cfb0a873 | 1348 | |
f0900eb2 | 1349 | snd_soc_dapm_widget_for_each_source_path(w, p) { |
cfb0a873 VK |
1350 | if (p->connect && is_skl_dsp_widget_type(p->source) && |
1351 | p->source->priv) { | |
1352 | ||
9a03cb49 JK |
1353 | ret = skl_tplg_be_fill_pipe_params(dai, |
1354 | p->source->priv, params); | |
1355 | if (ret < 0) | |
1356 | return ret; | |
cfb0a873 | 1357 | } else { |
9a03cb49 JK |
1358 | ret = skl_tplg_be_set_src_pipe_params(dai, |
1359 | p->source, params); | |
4d8adccb SP |
1360 | if (ret < 0) |
1361 | return ret; | |
cfb0a873 VK |
1362 | } |
1363 | } | |
1364 | ||
4d8adccb | 1365 | return ret; |
cfb0a873 VK |
1366 | } |
1367 | ||
1368 | static int skl_tplg_be_set_sink_pipe_params(struct snd_soc_dai *dai, | |
1369 | struct snd_soc_dapm_widget *w, struct skl_pipe_params *params) | |
1370 | { | |
1371 | struct snd_soc_dapm_path *p = NULL; | |
4d8adccb | 1372 | int ret = -EIO; |
cfb0a873 | 1373 | |
f0900eb2 | 1374 | snd_soc_dapm_widget_for_each_sink_path(w, p) { |
cfb0a873 VK |
1375 | if (p->connect && is_skl_dsp_widget_type(p->sink) && |
1376 | p->sink->priv) { | |
1377 | ||
9a03cb49 JK |
1378 | ret = skl_tplg_be_fill_pipe_params(dai, |
1379 | p->sink->priv, params); | |
1380 | if (ret < 0) | |
1381 | return ret; | |
cfb0a873 | 1382 | } else { |
4d8adccb | 1383 | ret = skl_tplg_be_set_sink_pipe_params( |
cfb0a873 | 1384 | dai, p->sink, params); |
4d8adccb SP |
1385 | if (ret < 0) |
1386 | return ret; | |
cfb0a873 VK |
1387 | } |
1388 | } | |
1389 | ||
4d8adccb | 1390 | return ret; |
cfb0a873 VK |
1391 | } |
1392 | ||
1393 | /* | |
1394 | * BE hw_params can be a source parameters (capture) or sink parameters | |
1395 | * (playback). Based on sink and source we need to either find the source | |
1396 | * list or the sink list and set the pipeline parameters | |
1397 | */ | |
1398 | int skl_tplg_be_update_params(struct snd_soc_dai *dai, | |
1399 | struct skl_pipe_params *params) | |
1400 | { | |
1401 | struct snd_soc_dapm_widget *w; | |
1402 | ||
1403 | if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
1404 | w = dai->playback_widget; | |
1405 | ||
1406 | return skl_tplg_be_set_src_pipe_params(dai, w, params); | |
1407 | ||
1408 | } else { | |
1409 | w = dai->capture_widget; | |
1410 | ||
1411 | return skl_tplg_be_set_sink_pipe_params(dai, w, params); | |
1412 | } | |
1413 | ||
1414 | return 0; | |
1415 | } | |
3af36706 VK |
1416 | |
1417 | static const struct snd_soc_tplg_widget_events skl_tplg_widget_ops[] = { | |
1418 | {SKL_MIXER_EVENT, skl_tplg_mixer_event}, | |
1419 | {SKL_VMIXER_EVENT, skl_tplg_vmixer_event}, | |
1420 | {SKL_PGA_EVENT, skl_tplg_pga_event}, | |
1421 | }; | |
1422 | ||
140adfba JK |
1423 | static const struct snd_soc_tplg_bytes_ext_ops skl_tlv_ops[] = { |
1424 | {SKL_CONTROL_TYPE_BYTE_TLV, skl_tplg_tlv_control_get, | |
1425 | skl_tplg_tlv_control_set}, | |
1426 | }; | |
1427 | ||
3af36706 VK |
1428 | /* |
1429 | * The topology binary passes the pin info for a module so initialize the pin | |
1430 | * info passed into module instance | |
1431 | */ | |
6abca1d7 JK |
1432 | static void skl_fill_module_pin_info(struct skl_dfw_module_pin *dfw_pin, |
1433 | struct skl_module_pin *m_pin, | |
1434 | bool is_dynamic, int max_pin) | |
3af36706 VK |
1435 | { |
1436 | int i; | |
1437 | ||
1438 | for (i = 0; i < max_pin; i++) { | |
6abca1d7 JK |
1439 | m_pin[i].id.module_id = dfw_pin[i].module_id; |
1440 | m_pin[i].id.instance_id = dfw_pin[i].instance_id; | |
3af36706 | 1441 | m_pin[i].in_use = false; |
6abca1d7 | 1442 | m_pin[i].is_dynamic = is_dynamic; |
4f745708 | 1443 | m_pin[i].pin_state = SKL_PIN_UNBIND; |
3af36706 VK |
1444 | } |
1445 | } | |
1446 | ||
1447 | /* | |
1448 | * Add pipeline from topology binary into driver pipeline list | |
1449 | * | |
1450 | * If already added we return that instance | |
1451 | * Otherwise we create a new instance and add into driver list | |
1452 | */ | |
1453 | static struct skl_pipe *skl_tplg_add_pipe(struct device *dev, | |
1454 | struct skl *skl, struct skl_dfw_pipe *dfw_pipe) | |
1455 | { | |
1456 | struct skl_pipeline *ppl; | |
1457 | struct skl_pipe *pipe; | |
1458 | struct skl_pipe_params *params; | |
1459 | ||
1460 | list_for_each_entry(ppl, &skl->ppl_list, node) { | |
1461 | if (ppl->pipe->ppl_id == dfw_pipe->pipe_id) | |
1462 | return ppl->pipe; | |
1463 | } | |
1464 | ||
1465 | ppl = devm_kzalloc(dev, sizeof(*ppl), GFP_KERNEL); | |
1466 | if (!ppl) | |
1467 | return NULL; | |
1468 | ||
1469 | pipe = devm_kzalloc(dev, sizeof(*pipe), GFP_KERNEL); | |
1470 | if (!pipe) | |
1471 | return NULL; | |
1472 | ||
1473 | params = devm_kzalloc(dev, sizeof(*params), GFP_KERNEL); | |
1474 | if (!params) | |
1475 | return NULL; | |
1476 | ||
1477 | pipe->ppl_id = dfw_pipe->pipe_id; | |
1478 | pipe->memory_pages = dfw_pipe->memory_pages; | |
1479 | pipe->pipe_priority = dfw_pipe->pipe_priority; | |
1480 | pipe->conn_type = dfw_pipe->conn_type; | |
1481 | pipe->state = SKL_PIPE_INVALID; | |
1482 | pipe->p_params = params; | |
1483 | INIT_LIST_HEAD(&pipe->w_list); | |
1484 | ||
1485 | ppl->pipe = pipe; | |
1486 | list_add(&ppl->node, &skl->ppl_list); | |
1487 | ||
1488 | return ppl->pipe; | |
1489 | } | |
1490 | ||
4cd9899f HS |
1491 | static void skl_tplg_fill_fmt(struct skl_module_fmt *dst_fmt, |
1492 | struct skl_dfw_module_fmt *src_fmt, | |
1493 | int pins) | |
1494 | { | |
1495 | int i; | |
1496 | ||
1497 | for (i = 0; i < pins; i++) { | |
1498 | dst_fmt[i].channels = src_fmt[i].channels; | |
1499 | dst_fmt[i].s_freq = src_fmt[i].freq; | |
1500 | dst_fmt[i].bit_depth = src_fmt[i].bit_depth; | |
1501 | dst_fmt[i].valid_bit_depth = src_fmt[i].valid_bit_depth; | |
1502 | dst_fmt[i].ch_cfg = src_fmt[i].ch_cfg; | |
1503 | dst_fmt[i].ch_map = src_fmt[i].ch_map; | |
1504 | dst_fmt[i].interleaving_style = src_fmt[i].interleaving_style; | |
1505 | dst_fmt[i].sample_type = src_fmt[i].sample_type; | |
1506 | } | |
1507 | } | |
1508 | ||
fe3f4442 D |
1509 | static void skl_clear_pin_config(struct snd_soc_platform *platform, |
1510 | struct snd_soc_dapm_widget *w) | |
1511 | { | |
1512 | int i; | |
1513 | struct skl_module_cfg *mconfig; | |
1514 | struct skl_pipe *pipe; | |
1515 | ||
1516 | if (!strncmp(w->dapm->component->name, platform->component.name, | |
1517 | strlen(platform->component.name))) { | |
1518 | mconfig = w->priv; | |
1519 | pipe = mconfig->pipe; | |
1520 | for (i = 0; i < mconfig->max_in_queue; i++) { | |
1521 | mconfig->m_in_pin[i].in_use = false; | |
1522 | mconfig->m_in_pin[i].pin_state = SKL_PIN_UNBIND; | |
1523 | } | |
1524 | for (i = 0; i < mconfig->max_out_queue; i++) { | |
1525 | mconfig->m_out_pin[i].in_use = false; | |
1526 | mconfig->m_out_pin[i].pin_state = SKL_PIN_UNBIND; | |
1527 | } | |
1528 | pipe->state = SKL_PIPE_INVALID; | |
1529 | mconfig->m_state = SKL_MODULE_UNINIT; | |
1530 | } | |
1531 | } | |
1532 | ||
1533 | void skl_cleanup_resources(struct skl *skl) | |
1534 | { | |
1535 | struct skl_sst *ctx = skl->skl_sst; | |
1536 | struct snd_soc_platform *soc_platform = skl->platform; | |
1537 | struct snd_soc_dapm_widget *w; | |
1538 | struct snd_soc_card *card; | |
1539 | ||
1540 | if (soc_platform == NULL) | |
1541 | return; | |
1542 | ||
1543 | card = soc_platform->component.card; | |
1544 | if (!card || !card->instantiated) | |
1545 | return; | |
1546 | ||
1547 | skl->resource.mem = 0; | |
1548 | skl->resource.mcps = 0; | |
1549 | ||
1550 | list_for_each_entry(w, &card->widgets, list) { | |
1551 | if (is_skl_dsp_widget_type(w) && (w->priv != NULL)) | |
1552 | skl_clear_pin_config(soc_platform, w); | |
1553 | } | |
1554 | ||
1555 | skl_clear_module_cnt(ctx->dsp); | |
1556 | } | |
1557 | ||
3af36706 VK |
1558 | /* |
1559 | * Topology core widget load callback | |
1560 | * | |
1561 | * This is used to save the private data for each widget which gives | |
1562 | * information to the driver about module and pipeline parameters which DSP | |
1563 | * FW expects like ids, resource values, formats etc | |
1564 | */ | |
1565 | static int skl_tplg_widget_load(struct snd_soc_component *cmpnt, | |
b663a8c5 JK |
1566 | struct snd_soc_dapm_widget *w, |
1567 | struct snd_soc_tplg_dapm_widget *tplg_w) | |
3af36706 VK |
1568 | { |
1569 | int ret; | |
1570 | struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt); | |
1571 | struct skl *skl = ebus_to_skl(ebus); | |
1572 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
1573 | struct skl_module_cfg *mconfig; | |
1574 | struct skl_pipe *pipe; | |
b663a8c5 JK |
1575 | struct skl_dfw_module *dfw_config = |
1576 | (struct skl_dfw_module *)tplg_w->priv.data; | |
3af36706 VK |
1577 | |
1578 | if (!tplg_w->priv.size) | |
1579 | goto bind_event; | |
1580 | ||
1581 | mconfig = devm_kzalloc(bus->dev, sizeof(*mconfig), GFP_KERNEL); | |
1582 | ||
1583 | if (!mconfig) | |
1584 | return -ENOMEM; | |
1585 | ||
1586 | w->priv = mconfig; | |
09305da9 SN |
1587 | memcpy(&mconfig->guid, &dfw_config->uuid, 16); |
1588 | ||
ea6b3e94 SN |
1589 | ret = snd_skl_get_module_info(skl->skl_sst, mconfig->guid, dfw_config); |
1590 | if (ret < 0) | |
1591 | return ret; | |
1592 | ||
3af36706 VK |
1593 | mconfig->id.module_id = dfw_config->module_id; |
1594 | mconfig->id.instance_id = dfw_config->instance_id; | |
1595 | mconfig->mcps = dfw_config->max_mcps; | |
1596 | mconfig->ibs = dfw_config->ibs; | |
1597 | mconfig->obs = dfw_config->obs; | |
1598 | mconfig->core_id = dfw_config->core_id; | |
1599 | mconfig->max_in_queue = dfw_config->max_in_queue; | |
1600 | mconfig->max_out_queue = dfw_config->max_out_queue; | |
1601 | mconfig->is_loadable = dfw_config->is_loadable; | |
4cd9899f HS |
1602 | skl_tplg_fill_fmt(mconfig->in_fmt, dfw_config->in_fmt, |
1603 | MODULE_MAX_IN_PINS); | |
1604 | skl_tplg_fill_fmt(mconfig->out_fmt, dfw_config->out_fmt, | |
1605 | MODULE_MAX_OUT_PINS); | |
1606 | ||
3af36706 VK |
1607 | mconfig->params_fixup = dfw_config->params_fixup; |
1608 | mconfig->converter = dfw_config->converter; | |
1609 | mconfig->m_type = dfw_config->module_type; | |
1610 | mconfig->vbus_id = dfw_config->vbus_id; | |
b18c458d | 1611 | mconfig->mem_pages = dfw_config->mem_pages; |
3af36706 VK |
1612 | |
1613 | pipe = skl_tplg_add_pipe(bus->dev, skl, &dfw_config->pipe); | |
1614 | if (pipe) | |
1615 | mconfig->pipe = pipe; | |
1616 | ||
1617 | mconfig->dev_type = dfw_config->dev_type; | |
1618 | mconfig->hw_conn_type = dfw_config->hw_conn_type; | |
1619 | mconfig->time_slot = dfw_config->time_slot; | |
1620 | mconfig->formats_config.caps_size = dfw_config->caps.caps_size; | |
1621 | ||
4cd9899f HS |
1622 | mconfig->m_in_pin = devm_kzalloc(bus->dev, (mconfig->max_in_queue) * |
1623 | sizeof(*mconfig->m_in_pin), | |
1624 | GFP_KERNEL); | |
3af36706 VK |
1625 | if (!mconfig->m_in_pin) |
1626 | return -ENOMEM; | |
1627 | ||
6abca1d7 JK |
1628 | mconfig->m_out_pin = devm_kzalloc(bus->dev, (mconfig->max_out_queue) * |
1629 | sizeof(*mconfig->m_out_pin), | |
1630 | GFP_KERNEL); | |
3af36706 VK |
1631 | if (!mconfig->m_out_pin) |
1632 | return -ENOMEM; | |
1633 | ||
6abca1d7 JK |
1634 | skl_fill_module_pin_info(dfw_config->in_pin, mconfig->m_in_pin, |
1635 | dfw_config->is_dynamic_in_pin, | |
1636 | mconfig->max_in_queue); | |
1637 | ||
1638 | skl_fill_module_pin_info(dfw_config->out_pin, mconfig->m_out_pin, | |
1639 | dfw_config->is_dynamic_out_pin, | |
1640 | mconfig->max_out_queue); | |
1641 | ||
3af36706 VK |
1642 | |
1643 | if (mconfig->formats_config.caps_size == 0) | |
1644 | goto bind_event; | |
1645 | ||
1646 | mconfig->formats_config.caps = (u32 *)devm_kzalloc(bus->dev, | |
b663a8c5 | 1647 | mconfig->formats_config.caps_size, GFP_KERNEL); |
3af36706 VK |
1648 | |
1649 | if (mconfig->formats_config.caps == NULL) | |
1650 | return -ENOMEM; | |
1651 | ||
1652 | memcpy(mconfig->formats_config.caps, dfw_config->caps.caps, | |
abb74003 JK |
1653 | dfw_config->caps.caps_size); |
1654 | mconfig->formats_config.param_id = dfw_config->caps.param_id; | |
1655 | mconfig->formats_config.set_params = dfw_config->caps.set_params; | |
3af36706 VK |
1656 | |
1657 | bind_event: | |
1658 | if (tplg_w->event_type == 0) { | |
3373f716 | 1659 | dev_dbg(bus->dev, "ASoC: No event handler required\n"); |
3af36706 VK |
1660 | return 0; |
1661 | } | |
1662 | ||
1663 | ret = snd_soc_tplg_widget_bind_event(w, skl_tplg_widget_ops, | |
b663a8c5 JK |
1664 | ARRAY_SIZE(skl_tplg_widget_ops), |
1665 | tplg_w->event_type); | |
3af36706 VK |
1666 | |
1667 | if (ret) { | |
1668 | dev_err(bus->dev, "%s: No matching event handlers found for %d\n", | |
1669 | __func__, tplg_w->event_type); | |
1670 | return -EINVAL; | |
1671 | } | |
1672 | ||
1673 | return 0; | |
1674 | } | |
1675 | ||
140adfba JK |
1676 | static int skl_init_algo_data(struct device *dev, struct soc_bytes_ext *be, |
1677 | struct snd_soc_tplg_bytes_control *bc) | |
1678 | { | |
1679 | struct skl_algo_data *ac; | |
1680 | struct skl_dfw_algo_data *dfw_ac = | |
1681 | (struct skl_dfw_algo_data *)bc->priv.data; | |
1682 | ||
1683 | ac = devm_kzalloc(dev, sizeof(*ac), GFP_KERNEL); | |
1684 | if (!ac) | |
1685 | return -ENOMEM; | |
1686 | ||
1687 | /* Fill private data */ | |
1688 | ac->max = dfw_ac->max; | |
1689 | ac->param_id = dfw_ac->param_id; | |
1690 | ac->set_params = dfw_ac->set_params; | |
1691 | ||
1692 | if (ac->max) { | |
1693 | ac->params = (char *) devm_kzalloc(dev, ac->max, GFP_KERNEL); | |
1694 | if (!ac->params) | |
1695 | return -ENOMEM; | |
1696 | ||
edd7ea2d | 1697 | memcpy(ac->params, dfw_ac->params, ac->max); |
140adfba JK |
1698 | } |
1699 | ||
1700 | be->dobj.private = ac; | |
1701 | return 0; | |
1702 | } | |
1703 | ||
1704 | static int skl_tplg_control_load(struct snd_soc_component *cmpnt, | |
1705 | struct snd_kcontrol_new *kctl, | |
1706 | struct snd_soc_tplg_ctl_hdr *hdr) | |
1707 | { | |
1708 | struct soc_bytes_ext *sb; | |
1709 | struct snd_soc_tplg_bytes_control *tplg_bc; | |
1710 | struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt); | |
1711 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
1712 | ||
1713 | switch (hdr->ops.info) { | |
1714 | case SND_SOC_TPLG_CTL_BYTES: | |
1715 | tplg_bc = container_of(hdr, | |
1716 | struct snd_soc_tplg_bytes_control, hdr); | |
1717 | if (kctl->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { | |
1718 | sb = (struct soc_bytes_ext *)kctl->private_value; | |
1719 | if (tplg_bc->priv.size) | |
1720 | return skl_init_algo_data( | |
1721 | bus->dev, sb, tplg_bc); | |
1722 | } | |
1723 | break; | |
1724 | ||
1725 | default: | |
1726 | dev_warn(bus->dev, "Control load not supported %d:%d:%d\n", | |
1727 | hdr->ops.get, hdr->ops.put, hdr->ops.info); | |
1728 | break; | |
1729 | } | |
1730 | ||
1731 | return 0; | |
1732 | } | |
1733 | ||
3af36706 VK |
1734 | static struct snd_soc_tplg_ops skl_tplg_ops = { |
1735 | .widget_load = skl_tplg_widget_load, | |
140adfba JK |
1736 | .control_load = skl_tplg_control_load, |
1737 | .bytes_ext_ops = skl_tlv_ops, | |
1738 | .bytes_ext_ops_count = ARRAY_SIZE(skl_tlv_ops), | |
3af36706 VK |
1739 | }; |
1740 | ||
287af4f9 JK |
1741 | /* |
1742 | * A pipe can have multiple modules, each of them will be a DAPM widget as | |
1743 | * well. While managing a pipeline we need to get the list of all the | |
1744 | * widgets in a pipelines, so this helper - skl_tplg_create_pipe_widget_list() | |
1745 | * helps to get the SKL type widgets in that pipeline | |
1746 | */ | |
1747 | static int skl_tplg_create_pipe_widget_list(struct snd_soc_platform *platform) | |
1748 | { | |
1749 | struct snd_soc_dapm_widget *w; | |
1750 | struct skl_module_cfg *mcfg = NULL; | |
1751 | struct skl_pipe_module *p_module = NULL; | |
1752 | struct skl_pipe *pipe; | |
1753 | ||
1754 | list_for_each_entry(w, &platform->component.card->widgets, list) { | |
1755 | if (is_skl_dsp_widget_type(w) && w->priv != NULL) { | |
1756 | mcfg = w->priv; | |
1757 | pipe = mcfg->pipe; | |
1758 | ||
1759 | p_module = devm_kzalloc(platform->dev, | |
1760 | sizeof(*p_module), GFP_KERNEL); | |
1761 | if (!p_module) | |
1762 | return -ENOMEM; | |
1763 | ||
1764 | p_module->w = w; | |
1765 | list_add_tail(&p_module->node, &pipe->w_list); | |
1766 | } | |
1767 | } | |
1768 | ||
1769 | return 0; | |
1770 | } | |
1771 | ||
3af36706 VK |
1772 | /* This will be read from topology manifest, currently defined here */ |
1773 | #define SKL_MAX_MCPS 30000000 | |
1774 | #define SKL_FW_MAX_MEM 1000000 | |
1775 | ||
1776 | /* | |
1777 | * SKL topology init routine | |
1778 | */ | |
1779 | int skl_tplg_init(struct snd_soc_platform *platform, struct hdac_ext_bus *ebus) | |
1780 | { | |
1781 | int ret; | |
1782 | const struct firmware *fw; | |
1783 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
1784 | struct skl *skl = ebus_to_skl(ebus); | |
1785 | ||
4b235c43 | 1786 | ret = request_firmware(&fw, skl->tplg_name, bus->dev); |
3af36706 | 1787 | if (ret < 0) { |
b663a8c5 | 1788 | dev_err(bus->dev, "tplg fw %s load failed with %d\n", |
4b235c43 VK |
1789 | skl->tplg_name, ret); |
1790 | ret = request_firmware(&fw, "dfw_sst.bin", bus->dev); | |
1791 | if (ret < 0) { | |
1792 | dev_err(bus->dev, "Fallback tplg fw %s load failed with %d\n", | |
1793 | "dfw_sst.bin", ret); | |
1794 | return ret; | |
1795 | } | |
3af36706 VK |
1796 | } |
1797 | ||
1798 | /* | |
1799 | * The complete tplg for SKL is loaded as index 0, we don't use | |
1800 | * any other index | |
1801 | */ | |
b663a8c5 JK |
1802 | ret = snd_soc_tplg_component_load(&platform->component, |
1803 | &skl_tplg_ops, fw, 0); | |
3af36706 VK |
1804 | if (ret < 0) { |
1805 | dev_err(bus->dev, "tplg component load failed%d\n", ret); | |
c14a82c7 | 1806 | release_firmware(fw); |
3af36706 VK |
1807 | return -EINVAL; |
1808 | } | |
1809 | ||
1810 | skl->resource.max_mcps = SKL_MAX_MCPS; | |
1811 | skl->resource.max_mem = SKL_FW_MAX_MEM; | |
1812 | ||
d8018361 | 1813 | skl->tplg = fw; |
287af4f9 JK |
1814 | ret = skl_tplg_create_pipe_widget_list(platform); |
1815 | if (ret < 0) | |
1816 | return ret; | |
d8018361 | 1817 | |
3af36706 VK |
1818 | return 0; |
1819 | } |