[linux-2.6-block.git] / sound / soc / intel / skylake / bxt-sst.c

/*
 *  bxt-sst.c - DSP library functions for BXT platform
 *
 *  Copyright (C) 2015-16 Intel Corp
 *  Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
 *	   Jeeja KP <jeeja.kp@intel.com>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; version 2 of the License.
 *
 *  This program is distributed in the hope that it will be useful, but
 *  WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  General Public License for more details.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/device.h>

#include "../common/sst-dsp.h"
#include "../common/sst-dsp-priv.h"
#include "skl-sst-ipc.h"

#define BXT_BASEFW_TIMEOUT	3000
#define BXT_INIT_TIMEOUT	300
#define BXT_ROM_INIT_TIMEOUT	70
#define BXT_IPC_PURGE_FW	0x01004000

#define BXT_ROM_INIT		0x5
#define BXT_ADSP_SRAM0_BASE	0x80000

/* Firmware status window */
#define BXT_ADSP_FW_STATUS	BXT_ADSP_SRAM0_BASE
#define BXT_ADSP_ERROR_CODE     (BXT_ADSP_FW_STATUS + 0x4)

#define BXT_ADSP_SRAM1_BASE	0xA0000

#define BXT_INSTANCE_ID 0
#define BXT_BASE_FW_MODULE_ID 0

#define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000

/* Delay before scheduling D0i3 entry */
#define BXT_D0I3_DELAY 5000

#define BXT_FW_ROM_INIT_RETRY 3

static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
{
	 return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
}

static int
bxt_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count)
{
	struct snd_dma_buffer dmab;
	struct skl_sst *skl = ctx->thread_context;
	struct firmware stripped_fw;
	int ret = 0, i, dma_id, stream_tag;

	/* library indices start from 1 to N. 0 represents base FW */
	for (i = 1; i < lib_count; i++) {
		ret = skl_prepare_lib_load(skl, &skl->lib_info[i], &stripped_fw,
					BXT_ADSP_FW_BIN_HDR_OFFSET, i);
		if (ret < 0)
			goto load_library_failed;

		stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40,
					stripped_fw.size, &dmab);
		if (stream_tag <= 0) {
			dev_err(ctx->dev, "Lib prepare DMA err: %x\n",
					stream_tag);
			ret = stream_tag;
			goto load_library_failed;
		}

		dma_id = stream_tag - 1;
		memcpy(dmab.area, stripped_fw.data, stripped_fw.size);

		ctx->dsp_ops.trigger(ctx->dev, true, stream_tag);
		ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i, true);
		if (ret < 0)
			dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n",
					linfo[i].name, ret);

		ctx->dsp_ops.trigger(ctx->dev, false, stream_tag);
		ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag);
	}

	return ret;

load_library_failed:
	skl_release_library(linfo, lib_count);
	return ret;
}

/*
 * First boot sequence has some extra steps. Core 0 waits for power
 * status on core 1, so power up core 1 also momentarily, keep it in
 * reset/stall and then turn it off
 */
static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
			const void *fwdata, u32 fwsize)
{
	int stream_tag, ret;

	stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
	if (stream_tag <= 0) {
		dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
				stream_tag);
		return stream_tag;
	}

	ctx->dsp_ops.stream_tag = stream_tag;
	memcpy(ctx->dmab.area, fwdata, fwsize);

	/* Step 1: Power up core 0 and core1 */
	ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK |
				SKL_DSP_CORE_MASK(1));
	if (ret < 0) {
		dev_err(ctx->dev, "dsp core0/1 power up failed\n");
		goto base_fw_load_failed;
	}

	/* Step 2: Purge FW request */
	sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
				(BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9)));

	/* Step 3: Unset core0 reset state & unstall/run core0 */
	ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
	if (ret < 0) {
		dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
		ret = -EIO;
		goto base_fw_load_failed;
	}

	/* Step 4: Wait for DONE Bit */
	ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE,
					SKL_ADSP_REG_HIPCIE_DONE,
					SKL_ADSP_REG_HIPCIE_DONE,
					BXT_INIT_TIMEOUT, "HIPCIE Done");
	if (ret < 0) {
		dev_err(ctx->dev, "Timeout for Purge Request%d\n", ret);
		goto base_fw_load_failed;
	}

	/* Step 5: power down core1 */
	ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
	if (ret < 0) {
		dev_err(ctx->dev, "dsp core1 power down failed\n");
		goto base_fw_load_failed;
	}

	/* Step 6: Enable Interrupt */
	skl_ipc_int_enable(ctx);
	skl_ipc_op_int_enable(ctx);

	/* Step 7: Wait for ROM init */
	ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
			SKL_FW_INIT, BXT_ROM_INIT_TIMEOUT, "ROM Load");
	if (ret < 0) {
		dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret);
		goto base_fw_load_failed;
	}

	return ret;

base_fw_load_failed:
	ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
	skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
	skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
	return ret;
}

static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
{
	int ret;

	ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
	ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
			BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");

	ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
	ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);

	return ret;
}

static int bxt_load_base_firmware(struct sst_dsp *ctx)
{
	struct firmware stripped_fw;
	struct skl_sst *skl = ctx->thread_context;
	int ret, i;

	if (ctx->fw == NULL) {
		ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
		if (ret < 0) {
			dev_err(ctx->dev, "Request firmware failed %d\n", ret);
			return ret;
		}
	}

	/* prase uuids on first boot */
	if (skl->is_first_boot) {
		ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0);
		if (ret < 0)
			goto sst_load_base_firmware_failed;
	}

	stripped_fw.data = ctx->fw->data;
	stripped_fw.size = ctx->fw->size;
	skl_dsp_strip_extended_manifest(&stripped_fw);


	for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) {
		ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
		if (ret == 0)
			break;
	}

	if (ret < 0) {
		dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
			sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
			sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));

		dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
		goto sst_load_base_firmware_failed;
	}

	ret = sst_transfer_fw_host_dma(ctx);
	if (ret < 0) {
		dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
		dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
			sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
			sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));

		skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
	} else {
		dev_dbg(ctx->dev, "Firmware download successful\n");
		ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
					msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
		if (ret == 0) {
			dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
			skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
			ret = -EIO;
		} else {
			ret = 0;
			skl->fw_loaded = true;
		}
	}

	return ret;

sst_load_base_firmware_failed:
	release_firmware(ctx->fw);
	ctx->fw = NULL;
	return ret;
}

/*
 * Decide the D0i3 state that can be targeted based on the usecase
 * ref counts and DSP state
 *
 * Decision Matrix:  (X= dont care; state = target state)
 *
 * DSP state != SKL_DSP_RUNNING ; state = no d0i3
 *
 * DSP state == SKL_DSP_RUNNING , the following matrix applies
 * non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3
 * non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3
 * non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3
 * non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3
 */
static int bxt_d0i3_target_state(struct sst_dsp *ctx)
{
	struct skl_sst *skl = ctx->thread_context;
	struct skl_d0i3_data *d0i3 = &skl->d0i3;

	if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING)
		return SKL_DSP_D0I3_NONE;

	if (d0i3->non_d0i3)
		return SKL_DSP_D0I3_NONE;
	else if (d0i3->streaming)
		return SKL_DSP_D0I3_STREAMING;
	else if (d0i3->non_streaming)
		return SKL_DSP_D0I3_NON_STREAMING;
	else
		return SKL_DSP_D0I3_NONE;
}

static void bxt_set_dsp_D0i3(struct work_struct *work)
{
	int ret;
	struct skl_ipc_d0ix_msg msg;
	struct skl_sst *skl = container_of(work,
			struct skl_sst, d0i3.work.work);
	struct sst_dsp *ctx = skl->dsp;
	struct skl_d0i3_data *d0i3 = &skl->d0i3;
	int target_state;

	dev_dbg(ctx->dev, "In %s:\n", __func__);

	/* D0i3 entry allowed only if core 0 alone is running */
	if (skl_dsp_get_enabled_cores(ctx) !=  SKL_DSP_CORE0_MASK) {
		dev_warn(ctx->dev,
				"D0i3 allowed when only core0 running:Exit\n");
		return;
	}

	target_state = bxt_d0i3_target_state(ctx);
	if (target_state == SKL_DSP_D0I3_NONE)
		return;

	msg.instance_id = 0;
	msg.module_id = 0;
	msg.wake = 1;
	msg.streaming = 0;
	if (target_state == SKL_DSP_D0I3_STREAMING)
		msg.streaming = 1;

	ret =  skl_ipc_set_d0ix(&skl->ipc, &msg);

	if (ret < 0) {
		dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n");
		return;
	}

	/* Set Vendor specific register D0I3C.I3 to enable D0i3*/
	if (skl->update_d0i3c)
		skl->update_d0i3c(skl->dev, true);

	d0i3->state = target_state;
	skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3;
}

static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx)
{
	struct skl_sst *skl = ctx->thread_context;
	struct skl_d0i3_data *d0i3 = &skl->d0i3;

	/* Schedule D0i3 only if the usecase ref counts are appropriate */
	if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) {

		dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__);

		schedule_delayed_work(&d0i3->work,
				msecs_to_jiffies(BXT_D0I3_DELAY));
	}

	return 0;
}

static int bxt_set_dsp_D0i0(struct sst_dsp *ctx)
{
	int ret;
	struct skl_ipc_d0ix_msg msg;
	struct skl_sst *skl = ctx->thread_context;

	dev_dbg(ctx->dev, "In %s:\n", __func__);

	/* First Cancel any pending attempt to put DSP to D0i3 */
	cancel_delayed_work_sync(&skl->d0i3.work);

	/* If DSP is currently in D0i3, bring it to D0i0 */
	if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3)
		return 0;

	dev_dbg(ctx->dev, "Set DSP to D0i0\n");

	msg.instance_id = 0;
	msg.module_id = 0;
	msg.streaming = 0;
	msg.wake = 0;

	if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING)
		msg.streaming = 1;

	/* Clear Vendor specific register D0I3C.I3 to disable D0i3*/
	if (skl->update_d0i3c)
		skl->update_d0i3c(skl->dev, false);

	ret =  skl_ipc_set_d0ix(&skl->ipc, &msg);
	if (ret < 0) {
		dev_err(ctx->dev, "Failed to set DSP to D0i0\n");
		return ret;
	}

	skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING;
	skl->d0i3.state = SKL_DSP_D0I3_NONE;

	return 0;
}

static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
{
	struct skl_sst *skl = ctx->thread_context;
	int ret;
	struct skl_ipc_dxstate_info dx;
	unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);

	if (skl->fw_loaded == false) {
		skl->boot_complete = false;
		ret = bxt_load_base_firmware(ctx);
		if (ret < 0) {
			dev_err(ctx->dev, "reload fw failed: %d\n", ret);
			return ret;
		}

		if (skl->lib_count > 1) {
			ret = bxt_load_library(ctx, skl->lib_info,
						skl->lib_count);
			if (ret < 0) {
				dev_err(ctx->dev, "reload libs failed: %d\n", ret);
				return ret;
			}
		}
		skl->cores.state[core_id] = SKL_DSP_RUNNING;
		return ret;
	}

	/* If core 0 is being turned on, turn on core 1 as well */
	if (core_id == SKL_DSP_CORE0_ID)
		ret = skl_dsp_core_power_up(ctx, core_mask |
				SKL_DSP_CORE_MASK(1));
	else
		ret = skl_dsp_core_power_up(ctx, core_mask);

	if (ret < 0)
		goto err;

	if (core_id == SKL_DSP_CORE0_ID) {

		/*
		 * Enable interrupt after SPA is set and before
		 * DSP is unstalled
		 */
		skl_ipc_int_enable(ctx);
		skl_ipc_op_int_enable(ctx);
		skl->boot_complete = false;
	}

	ret = skl_dsp_start_core(ctx, core_mask);
	if (ret < 0)
		goto err;

	if (core_id == SKL_DSP_CORE0_ID) {
		ret = wait_event_timeout(skl->boot_wait,
				skl->boot_complete,
				msecs_to_jiffies(SKL_IPC_BOOT_MSECS));

	/* If core 1 was turned on for booting core 0, turn it off */
		skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
		if (ret == 0) {
			dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__);
			dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
				sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
				sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
			dev_err(ctx->dev, "Failed to set core0 to D0 state\n");
			ret = -EIO;
			goto err;
		}
	}

	/* Tell FW if additional core in now On */

	if (core_id != SKL_DSP_CORE0_ID) {
		dx.core_mask = core_mask;
		dx.dx_mask = core_mask;

		ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
					BXT_BASE_FW_MODULE_ID, &dx);
		if (ret < 0) {
			dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n",
								core_id, ret);
			goto err;
		}
	}

	skl->cores.state[core_id] = SKL_DSP_RUNNING;
	return 0;
err:
	if (core_id == SKL_DSP_CORE0_ID)
		core_mask |= SKL_DSP_CORE_MASK(1);
	skl_dsp_disable_core(ctx, core_mask);

	return ret;
}

static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
{
	int ret;
	struct skl_ipc_dxstate_info dx;
	struct skl_sst *skl = ctx->thread_context;
	unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);

	dx.core_mask = core_mask;
	dx.dx_mask = SKL_IPC_D3_MASK;

	dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n",
			dx.core_mask, dx.dx_mask);

	ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
				BXT_BASE_FW_MODULE_ID, &dx);
	if (ret < 0) {
		dev_err(ctx->dev,
		"Failed to set DSP to D3:core id = %d;Continue reset\n",
		core_id);
		/*
		 * In case of D3 failure, re-download the firmware, so set
		 * fw_loaded to false.
		 */
		skl->fw_loaded = false;
	}

	if (core_id == SKL_DSP_CORE0_ID) {
		/* disable Interrupt */
		skl_ipc_op_int_disable(ctx);
		skl_ipc_int_disable(ctx);
	}
	ret = skl_dsp_disable_core(ctx, core_mask);
	if (ret < 0) {
		dev_err(ctx->dev, "Failed to disable core %d\n", ret);
		return ret;
	}
	skl->cores.state[core_id] = SKL_DSP_RESET;
	return 0;
}

static const struct skl_dsp_fw_ops bxt_fw_ops = {
	.set_state_D0 = bxt_set_dsp_D0,
	.set_state_D3 = bxt_set_dsp_D3,
	.set_state_D0i3 = bxt_schedule_dsp_D0i3,
	.set_state_D0i0 = bxt_set_dsp_D0i0,
	.load_fw = bxt_load_base_firmware,
	.get_fw_errcode = bxt_get_errorcode,
	.load_library = bxt_load_library,
};

static struct sst_ops skl_ops = {
	.irq_handler = skl_dsp_sst_interrupt,
	.write = sst_shim32_write,
	.read = sst_shim32_read,
	.ram_read = sst_memcpy_fromio_32,
	.ram_write = sst_memcpy_toio_32,
	.free = skl_dsp_free,
};

static struct sst_dsp_device skl_dev = {
	.thread = skl_dsp_irq_thread_handler,
	.ops = &skl_ops,
};

int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
			const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
			struct skl_sst **dsp)
{
	struct skl_sst *skl;
	struct sst_dsp *sst;
	int ret;

	ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &skl_dev);
	if (ret < 0) {
		dev_err(dev, "%s: no device\n", __func__);
		return ret;
	}

	skl = *dsp;
	sst = skl->dsp;
	sst->fw_ops = bxt_fw_ops;
	sst->addr.lpe = mmio_base;
	sst->addr.shim = mmio_base;
	sst->addr.sram0_base = BXT_ADSP_SRAM0_BASE;
	sst->addr.sram1_base = BXT_ADSP_SRAM1_BASE;
	sst->addr.w0_stat_sz = SKL_ADSP_W0_STAT_SZ;
	sst->addr.w0_up_sz = SKL_ADSP_W0_UP_SZ;

	sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
			SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);

	ret = skl_ipc_init(dev, skl);
	if (ret) {
		skl_dsp_free(sst);
		return ret;
	}

	/* set the D0i3 check */
	skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0;

	skl->boot_complete = false;
	init_waitqueue_head(&skl->boot_wait);
	INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3);
	skl->d0i3.state = SKL_DSP_D0I3_NONE;

	return skl_dsp_acquire_irq(sst);
}
EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);

int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx)
{
	int ret;
	struct sst_dsp *sst = ctx->dsp;

	ret = sst->fw_ops.load_fw(sst);
	if (ret < 0) {
		dev_err(dev, "Load base fw failed: %x\n", ret);
		return ret;
	}

	skl_dsp_init_core_state(sst);

	if (ctx->lib_count > 1) {
		ret = sst->fw_ops.load_library(sst, ctx->lib_info,
						ctx->lib_count);
		if (ret < 0) {
			dev_err(dev, "Load Library failed : %x\n", ret);
			return ret;
		}
	}
	ctx->is_first_boot = false;

	return 0;
}
EXPORT_SYMBOL_GPL(bxt_sst_init_fw);

void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
{

	skl_release_library(ctx->lib_info, ctx->lib_count);
	if (ctx->dsp->fw)
		release_firmware(ctx->dsp->fw);
	skl_freeup_uuid_list(ctx);
	skl_ipc_free(&ctx->ipc);
	ctx->dsp->ops->free(ctx->dsp);
}
EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Intel Broxton IPC driver");
Commit	Line	Data
92eb4f62 JK	1	/*
	2	* bxt-sst.c - DSP library functions for BXT platform
	3	*
	4	* Copyright (C) 2015-16 Intel Corp
	5	* Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
	6	* Jeeja KP <jeeja.kp@intel.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; version 2 of the License.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*/
	17
	18	#include <linux/module.h>
	19	#include <linux/delay.h>
	20	#include <linux/firmware.h>
	21	#include <linux/device.h>
	22
	23	#include "../common/sst-dsp.h"
	24	#include "../common/sst-dsp-priv.h"
	25	#include "skl-sst-ipc.h"
	26
	27	#define BXT_BASEFW_TIMEOUT 3000
7d3f91dc JK	28	#define BXT_INIT_TIMEOUT 300
7d3f91dc JK	29	#define BXT_ROM_INIT_TIMEOUT 70
92eb4f62 JK	30	#define BXT_IPC_PURGE_FW 0x01004000
	31
	32	#define BXT_ROM_INIT 0x5
	33	#define BXT_ADSP_SRAM0_BASE 0x80000
	34
	35	/* Firmware status window */
	36	#define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE
	37	#define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4)
	38
	39	#define BXT_ADSP_SRAM1_BASE 0xA0000
	40
e68aca08 J	41	#define BXT_INSTANCE_ID 0
	42	#define BXT_BASE_FW_MODULE_ID 0
	43
1ef015e6 RB	44	#define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000
1ef015e6 RB	45
5bb4cd46 J	46	/* Delay before scheduling D0i3 entry */
	47	#define BXT_D0I3_DELAY 5000
	48
7d3f91dc JK	49	#define BXT_FW_ROM_INIT_RETRY 3
7d3f91dc JK	50
92eb4f62 JK	51	static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
	52	{
	53	return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
	54	}
	55
1ef015e6	56	static int
eee0e16f	57	bxt_load_library(struct sst_dsp ctx, struct skl_lib_info linfo, int lib_count)
1ef015e6 RB	58	{
	59	struct snd_dma_buffer dmab;
	60	struct skl_sst *skl = ctx->thread_context;
1ef015e6 RB	61	struct firmware stripped_fw;
	62	int ret = 0, i, dma_id, stream_tag;
	63
	64	/* library indices start from 1 to N. 0 represents base FW */
eee0e16f	65	for (i = 1; i < lib_count; i++) {
ebe89076	66	ret = skl_prepare_lib_load(skl, &skl->lib_info[i], &stripped_fw,
1ef015e6	67	BXT_ADSP_FW_BIN_HDR_OFFSET, i);
ebe89076 SP	68	if (ret < 0)
ebe89076 SP	69	goto load_library_failed;
1ef015e6 RB	70
	71	stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40,
	72	stripped_fw.size, &dmab);
	73	if (stream_tag <= 0) {
	74	dev_err(ctx->dev, "Lib prepare DMA err: %x\n",
	75	stream_tag);
	76	ret = stream_tag;
	77	goto load_library_failed;
	78	}
	79
	80	dma_id = stream_tag - 1;
	81	memcpy(dmab.area, stripped_fw.data, stripped_fw.size);
	82
	83	ctx->dsp_ops.trigger(ctx->dev, true, stream_tag);
100e7f39	84	ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i, true);
1ef015e6 RB	85	if (ret < 0)
1ef015e6 RB	86	dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n",
eee0e16f	87	linfo[i].name, ret);
1ef015e6 RB	88
	89	ctx->dsp_ops.trigger(ctx->dev, false, stream_tag);
	90	ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag);
1ef015e6 RB	91	}
	92
	93	return ret;
	94
	95	load_library_failed:
ebe89076	96	skl_release_library(linfo, lib_count);
1ef015e6 RB	97	return ret;
	98	}
	99
e68aca08 J	100	/*
	101	* First boot sequence has some extra steps. Core 0 waits for power
	102	* status on core 1, so power up core 1 also momentarily, keep it in
	103	* reset/stall and then turn it off
	104	*/
92eb4f62 JK	105	static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
	106	const void *fwdata, u32 fwsize)
	107	{
eee0e16f	108	int stream_tag, ret;
92eb4f62 JK	109
92eb4f62 JK	110	stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
e68aca08	111	if (stream_tag <= 0) {
92eb4f62 JK	112	dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
	113	stream_tag);
	114	return stream_tag;
	115	}
	116
	117	ctx->dsp_ops.stream_tag = stream_tag;
	118	memcpy(ctx->dmab.area, fwdata, fwsize);
	119
e68aca08 J	120	/* Step 1: Power up core 0 and core1 */
	121	ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK \|
	122	SKL_DSP_CORE_MASK(1));
2023576d	123	if (ret < 0) {
e68aca08	124	dev_err(ctx->dev, "dsp core0/1 power up failed\n");
2023576d SV	125	goto base_fw_load_failed;
	126	}
	127
e68aca08	128	/* Step 2: Purge FW request */
92eb4f62	129	sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY \|
2023576d	130	(BXT_IPC_PURGE_FW \| ((stream_tag - 1) << 9)));
92eb4f62	131
e68aca08	132	/* Step 3: Unset core0 reset state & unstall/run core0 */
052f103c	133	ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
92eb4f62	134	if (ret < 0) {
2023576d	135	dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
92eb4f62 JK	136	ret = -EIO;
	137	goto base_fw_load_failed;
	138	}
	139
e68aca08	140	/* Step 4: Wait for DONE Bit */
1448099d	141	ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE,
92eb4f62	142	SKL_ADSP_REG_HIPCIE_DONE,
1448099d JK	143	SKL_ADSP_REG_HIPCIE_DONE,
	144	BXT_INIT_TIMEOUT, "HIPCIE Done");
	145	if (ret < 0) {
5f75b19e	146	dev_err(ctx->dev, "Timeout for Purge Request%d\n", ret);
1448099d	147	goto base_fw_load_failed;
92eb4f62 JK	148	}
92eb4f62 JK	149
e68aca08 J	150	/* Step 5: power down core1 */
	151	ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
	152	if (ret < 0) {
	153	dev_err(ctx->dev, "dsp core1 power down failed\n");
	154	goto base_fw_load_failed;
	155	}
	156
	157	/* Step 6: Enable Interrupt */
92eb4f62 JK	158	skl_ipc_int_enable(ctx);
	159	skl_ipc_op_int_enable(ctx);
	160
e68aca08	161	/* Step 7: Wait for ROM init */
1448099d	162	ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
7d3f91dc	163	SKL_FW_INIT, BXT_ROM_INIT_TIMEOUT, "ROM Load");
1448099d JK	164	if (ret < 0) {
1448099d JK	165	dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret);
92eb4f62 JK	166	goto base_fw_load_failed;
	167	}
	168
	169	return ret;
	170
	171	base_fw_load_failed:
	172	ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
052f103c	173	skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
c7872267	174	skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
92eb4f62 JK	175	return ret;
	176	}
	177
	178	static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
	179	{
	180	int ret;
	181
	182	ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
	183	ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
	184	BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");
	185
	186	ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
	187	ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
	188
	189	return ret;
	190	}
	191
	192	static int bxt_load_base_firmware(struct sst_dsp *ctx)
	193	{
bf242d19	194	struct firmware stripped_fw;
92eb4f62	195	struct skl_sst *skl = ctx->thread_context;
7d3f91dc	196	int ret, i;
92eb4f62	197
31d648f0 JK	198	if (ctx->fw == NULL) {
	199	ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
	200	if (ret < 0) {
	201	dev_err(ctx->dev, "Request firmware failed %d\n", ret);
	202	return ret;
	203	}
92eb4f62 JK	204	}
92eb4f62 JK	205
0bdd6d8b VK	206	/* prase uuids on first boot */
	207	if (skl->is_first_boot) {
	208	ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0);
	209	if (ret < 0)
	210	goto sst_load_base_firmware_failed;
	211	}
bf242d19 VK	212
	213	stripped_fw.data = ctx->fw->data;
	214	stripped_fw.size = ctx->fw->size;
	215	skl_dsp_strip_extended_manifest(&stripped_fw);
	216
7d3f91dc JK	217
7d3f91dc JK	218	for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) {
bf242d19	219	ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
7d3f91dc JK	220	if (ret == 0)
	221	break;
	222	}
	223
	224	if (ret < 0) {
	225	dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
2023576d SV	226	sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
	227	sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
	228
7d3f91dc JK	229	dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
7d3f91dc JK	230	goto sst_load_base_firmware_failed;
92eb4f62 JK	231	}
	232
	233	ret = sst_transfer_fw_host_dma(ctx);
	234	if (ret < 0) {
	235	dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
	236	dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
	237	sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
	238	sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
	239
052f103c	240	skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
92eb4f62 JK	241	} else {
	242	dev_dbg(ctx->dev, "Firmware download successful\n");
	243	ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
	244	msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
	245	if (ret == 0) {
	246	dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
052f103c	247	skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
92eb4f62 JK	248	ret = -EIO;
92eb4f62 JK	249	} else {
92eb4f62	250	ret = 0;
1665c177	251	skl->fw_loaded = true;
92eb4f62 JK	252	}
	253	}
	254
31d648f0 JK	255	return ret;
31d648f0 JK	256
92eb4f62	257	sst_load_base_firmware_failed:
fdfa82ee	258	release_firmware(ctx->fw);
31d648f0	259	ctx->fw = NULL;
92eb4f62 JK	260	return ret;
	261	}
	262
5bb4cd46 J	263	/*
	264	* Decide the D0i3 state that can be targeted based on the usecase
	265	* ref counts and DSP state
	266	*
	267	* Decision Matrix: (X= dont care; state = target state)
	268	*
	269	* DSP state != SKL_DSP_RUNNING ; state = no d0i3
	270	*
	271	* DSP state == SKL_DSP_RUNNING , the following matrix applies
	272	* non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3
	273	* non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3
	274	* non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3
	275	* non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3
	276	*/
	277	static int bxt_d0i3_target_state(struct sst_dsp *ctx)
	278	{
	279	struct skl_sst *skl = ctx->thread_context;
	280	struct skl_d0i3_data *d0i3 = &skl->d0i3;
	281
	282	if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING)
	283	return SKL_DSP_D0I3_NONE;
	284
	285	if (d0i3->non_d0i3)
	286	return SKL_DSP_D0I3_NONE;
	287	else if (d0i3->streaming)
	288	return SKL_DSP_D0I3_STREAMING;
	289	else if (d0i3->non_streaming)
	290	return SKL_DSP_D0I3_NON_STREAMING;
	291	else
	292	return SKL_DSP_D0I3_NONE;
	293	}
	294
	295	static void bxt_set_dsp_D0i3(struct work_struct *work)
	296	{
	297	int ret;
	298	struct skl_ipc_d0ix_msg msg;
	299	struct skl_sst *skl = container_of(work,
	300	struct skl_sst, d0i3.work.work);
	301	struct sst_dsp *ctx = skl->dsp;
	302	struct skl_d0i3_data *d0i3 = &skl->d0i3;
	303	int target_state;
	304
	305	dev_dbg(ctx->dev, "In %s:\n", __func__);
	306
	307	/* D0i3 entry allowed only if core 0 alone is running */
	308	if (skl_dsp_get_enabled_cores(ctx) != SKL_DSP_CORE0_MASK) {
	309	dev_warn(ctx->dev,
	310	"D0i3 allowed when only core0 running:Exit\n");
	311	return;
	312	}
	313
	314	target_state = bxt_d0i3_target_state(ctx);
	315	if (target_state == SKL_DSP_D0I3_NONE)
	316	return;
	317
	318	msg.instance_id = 0;
	319	msg.module_id = 0;
	320	msg.wake = 1;
	321	msg.streaming = 0;
	322	if (target_state == SKL_DSP_D0I3_STREAMING)
	323	msg.streaming = 1;
	324
	325	ret = skl_ipc_set_d0ix(&skl->ipc, &msg);
	326
327	if (ret < 0) {
328	dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n");
329	return;
330	}
331
332	/* Set Vendor specific register D0I3C.I3 to enable D0i3*/
333	if (skl->update_d0i3c)
334	skl->update_d0i3c(skl->dev, true);
335
336	d0i3->state = target_state;
337	skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3;
338	}
339
340	static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx)
341	{
342	struct skl_sst *skl = ctx->thread_context;
343	struct skl_d0i3_data *d0i3 = &skl->d0i3;
344
345	/* Schedule D0i3 only if the usecase ref counts are appropriate */
346	if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) {
347
348	dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__);
349
350	schedule_delayed_work(&d0i3->work,
351	msecs_to_jiffies(BXT_D0I3_DELAY));
352	}
353
354	return 0;
355	}
356
357	static int bxt_set_dsp_D0i0(struct sst_dsp *ctx)
358	{
359	int ret;
360	struct skl_ipc_d0ix_msg msg;
361	struct skl_sst *skl = ctx->thread_context;
362
363	dev_dbg(ctx->dev, "In %s:\n", __func__);
364
365	/* First Cancel any pending attempt to put DSP to D0i3 */
366	cancel_delayed_work_sync(&skl->d0i3.work);
367
368	/* If DSP is currently in D0i3, bring it to D0i0 */
369	if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3)
370	return 0;
371
372	dev_dbg(ctx->dev, "Set DSP to D0i0\n");
373
374	msg.instance_id = 0;
375	msg.module_id = 0;
376	msg.streaming = 0;
377	msg.wake = 0;
378
379	if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING)
380	msg.streaming = 1;
381
382	/* Clear Vendor specific register D0I3C.I3 to disable D0i3*/
383	if (skl->update_d0i3c)
384	skl->update_d0i3c(skl->dev, false);
385
386	ret = skl_ipc_set_d0ix(&skl->ipc, &msg);
387	if (ret < 0) {
388	dev_err(ctx->dev, "Failed to set DSP to D0i0\n");
389	return ret;
390	}
391
392	skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING;
393	skl->d0i3.state = SKL_DSP_D0I3_NONE;
394
395	return 0;
396	}
397
052f103c	398	static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
92eb4f62 JK	399	{
	400	struct skl_sst *skl = ctx->thread_context;
	401	int ret;
e68aca08 J	402	struct skl_ipc_dxstate_info dx;
e68aca08 J	403	unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
92eb4f62	404
1665c177	405	if (skl->fw_loaded == false) {
c7872267	406	skl->boot_complete = false;
1665c177	407	ret = bxt_load_base_firmware(ctx);
1ef015e6	408	if (ret < 0) {
1665c177	409	dev_err(ctx->dev, "reload fw failed: %d\n", ret);
1ef015e6 RB	410	return ret;
	411	}
	412
eee0e16f JK	413	if (skl->lib_count > 1) {
	414	ret = bxt_load_library(ctx, skl->lib_info,
	415	skl->lib_count);
1ef015e6 RB	416	if (ret < 0) {
	417	dev_err(ctx->dev, "reload libs failed: %d\n", ret);
	418	return ret;
	419	}
	420	}
1fb344a3	421	skl->cores.state[core_id] = SKL_DSP_RUNNING;
92eb4f62 JK	422	return ret;
	423	}
	424
e68aca08 J	425	/* If core 0 is being turned on, turn on core 1 as well */
	426	if (core_id == SKL_DSP_CORE0_ID)
	427	ret = skl_dsp_core_power_up(ctx, core_mask \|
	428	SKL_DSP_CORE_MASK(1));
	429	else
	430	ret = skl_dsp_core_power_up(ctx, core_mask);
	431
	432	if (ret < 0)
	433	goto err;
	434
	435	if (core_id == SKL_DSP_CORE0_ID) {
	436
	437	/*
	438	* Enable interrupt after SPA is set and before
	439	* DSP is unstalled
	440	*/
	441	skl_ipc_int_enable(ctx);
	442	skl_ipc_op_int_enable(ctx);
	443	skl->boot_complete = false;
92eb4f62	444	}
92eb4f62	445
e68aca08 J	446	ret = skl_dsp_start_core(ctx, core_mask);
	447	if (ret < 0)
	448	goto err;
92eb4f62	449
e68aca08 J	450	if (core_id == SKL_DSP_CORE0_ID) {
	451	ret = wait_event_timeout(skl->boot_wait,
	452	skl->boot_complete,
	453	msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
	454
	455	/* If core 1 was turned on for booting core 0, turn it off */
	456	skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
	457	if (ret == 0) {
	458	dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__);
	459	dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
	460	sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
	461	sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
	462	dev_err(ctx->dev, "Failed to set core0 to D0 state\n");
	463	ret = -EIO;
	464	goto err;
	465	}
92eb4f62 JK	466	}
92eb4f62 JK	467
e68aca08 J	468	/* Tell FW if additional core in now On */
	469
	470	if (core_id != SKL_DSP_CORE0_ID) {
	471	dx.core_mask = core_mask;
	472	dx.dx_mask = core_mask;
	473
	474	ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
	475	BXT_BASE_FW_MODULE_ID, &dx);
	476	if (ret < 0) {
	477	dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n",
	478	core_id, ret);
	479	goto err;
	480	}
92eb4f62 JK	481	}
92eb4f62 JK	482
e68aca08	483	skl->cores.state[core_id] = SKL_DSP_RUNNING;
92eb4f62	484	return 0;
e68aca08 J	485	err:
	486	if (core_id == SKL_DSP_CORE0_ID)
	487	core_mask \|= SKL_DSP_CORE_MASK(1);
	488	skl_dsp_disable_core(ctx, core_mask);
	489
	490	return ret;
92eb4f62 JK	491	}
92eb4f62 JK	492
052f103c	493	static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
92eb4f62	494	{
e68aca08	495	int ret;
92eb4f62 JK	496	struct skl_ipc_dxstate_info dx;
92eb4f62 JK	497	struct skl_sst *skl = ctx->thread_context;
e68aca08	498	unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
92eb4f62	499
e68aca08	500	dx.core_mask = core_mask;
92eb4f62 JK	501	dx.dx_mask = SKL_IPC_D3_MASK;
92eb4f62 JK	502
e68aca08 J	503	dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n",
e68aca08 J	504	dx.core_mask, dx.dx_mask);
92eb4f62	505
e68aca08 J	506	ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
e68aca08 J	507	BXT_BASE_FW_MODULE_ID, &dx);
03de8c2e	508	if (ret < 0) {
e68aca08 J	509	dev_err(ctx->dev,
	510	"Failed to set DSP to D3:core id = %d;Continue reset\n",
	511	core_id);
03de8c2e JK	512	/*
	513	* In case of D3 failure, re-download the firmware, so set
	514	* fw_loaded to false.
	515	*/
	516	skl->fw_loaded = false;
	517	}
92eb4f62	518
5518af9f JK	519	if (core_id == SKL_DSP_CORE0_ID) {
	520	/* disable Interrupt */
	521	skl_ipc_op_int_disable(ctx);
	522	skl_ipc_int_disable(ctx);
	523	}
e68aca08	524	ret = skl_dsp_disable_core(ctx, core_mask);
92eb4f62	525	if (ret < 0) {
ecd286a9	526	dev_err(ctx->dev, "Failed to disable core %d\n", ret);
e68aca08	527	return ret;
92eb4f62	528	}
e68aca08	529	skl->cores.state[core_id] = SKL_DSP_RESET;
92eb4f62 JK	530	return 0;
	531	}
	532
2788808a	533	static const struct skl_dsp_fw_ops bxt_fw_ops = {
92eb4f62 JK	534	.set_state_D0 = bxt_set_dsp_D0,
92eb4f62 JK	535	.set_state_D3 = bxt_set_dsp_D3,
5bb4cd46 J	536	.set_state_D0i3 = bxt_schedule_dsp_D0i3,
5bb4cd46 J	537	.set_state_D0i0 = bxt_set_dsp_D0i0,
92eb4f62 JK	538	.load_fw = bxt_load_base_firmware,
92eb4f62 JK	539	.get_fw_errcode = bxt_get_errorcode,
1ef015e6	540	.load_library = bxt_load_library,
92eb4f62 JK	541	};
	542
	543	static struct sst_ops skl_ops = {
	544	.irq_handler = skl_dsp_sst_interrupt,
	545	.write = sst_shim32_write,
	546	.read = sst_shim32_read,
	547	.ram_read = sst_memcpy_fromio_32,
	548	.ram_write = sst_memcpy_toio_32,
	549	.free = skl_dsp_free,
	550	};
	551
	552	static struct sst_dsp_device skl_dev = {
	553	.thread = skl_dsp_irq_thread_handler,
	554	.ops = &skl_ops,
	555	};
	556
	557	int bxt_sst_dsp_init(struct device dev, void __iomem mmio_base, int irq,
	558	const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
	559	struct skl_sst **dsp)
	560	{
	561	struct skl_sst *skl;
	562	struct sst_dsp *sst;
	563	int ret;
	564
9fe9c711 K	565	ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &skl_dev);
9fe9c711 K	566	if (ret < 0) {
351d74e4	567	dev_err(dev, "%s: no device\n", __func__);
9fe9c711	568	return ret;
92eb4f62 JK	569	}
92eb4f62 JK	570
9fe9c711	571	skl = *dsp;
92eb4f62	572	sst = skl->dsp;
92eb4f62 JK	573	sst->fw_ops = bxt_fw_ops;
	574	sst->addr.lpe = mmio_base;
	575	sst->addr.shim = mmio_base;
09e914d6 GS	576	sst->addr.sram0_base = BXT_ADSP_SRAM0_BASE;
	577	sst->addr.sram1_base = BXT_ADSP_SRAM1_BASE;
	578	sst->addr.w0_stat_sz = SKL_ADSP_W0_STAT_SZ;
	579	sst->addr.w0_up_sz = SKL_ADSP_W0_UP_SZ;
92eb4f62 JK	580
	581	sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
	582	SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
	583
2eed1b02	584	ret = skl_ipc_init(dev, skl);
3b3011ad SP	585	if (ret) {
3b3011ad SP	586	skl_dsp_free(sst);
2eed1b02	587	return ret;
3b3011ad	588	}
2eed1b02	589
a83e3b4c VK	590	/* set the D0i3 check */
	591	skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0;
	592
92eb4f62 JK	593	skl->boot_complete = false;
92eb4f62 JK	594	init_waitqueue_head(&skl->boot_wait);
a83e3b4c VK	595	INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3);
a83e3b4c VK	596	skl->d0i3.state = SKL_DSP_D0I3_NONE;
78cdbbda	597
8e9d8e19	598	return skl_dsp_acquire_irq(sst);
78cdbbda VK	599	}
	600	EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);
	601
	602	int bxt_sst_init_fw(struct device dev, struct skl_sst ctx)
	603	{
	604	int ret;
	605	struct sst_dsp *sst = ctx->dsp;
92eb4f62 JK	606
	607	ret = sst->fw_ops.load_fw(sst);
	608	if (ret < 0) {
ecd286a9	609	dev_err(dev, "Load base fw failed: %x\n", ret);
92eb4f62 JK	610	return ret;
	611	}
	612
052f103c J	613	skl_dsp_init_core_state(sst);
052f103c J	614
eee0e16f JK	615	if (ctx->lib_count > 1) {
	616	ret = sst->fw_ops.load_library(sst, ctx->lib_info,
	617	ctx->lib_count);
1ef015e6	618	if (ret < 0) {
ecd286a9	619	dev_err(dev, "Load Library failed : %x\n", ret);
1ef015e6 RB	620	return ret;
	621	}
	622	}
78cdbbda	623	ctx->is_first_boot = false;
92eb4f62 JK	624
	625	return 0;
	626	}
78cdbbda	627	EXPORT_SYMBOL_GPL(bxt_sst_init_fw);
92eb4f62 JK	628
	629	void bxt_sst_dsp_cleanup(struct device dev, struct skl_sst ctx)
	630	{
31d648f0	631
ebe89076	632	skl_release_library(ctx->lib_info, ctx->lib_count);
31d648f0 JK	633	if (ctx->dsp->fw)
31d648f0 JK	634	release_firmware(ctx->dsp->fw);
3467a64d	635	skl_freeup_uuid_list(ctx);
92eb4f62	636	skl_ipc_free(&ctx->ipc);
92eb4f62 JK	637	ctx->dsp->ops->free(ctx->dsp);
	638	}
	639	EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);
	640
	641	MODULE_LICENSE("GPL v2");
	642	MODULE_DESCRIPTION("Intel Broxton IPC driver");