[linux-2.6-block.git] / sound / soc / intel / common / sst-dsp-priv.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Intel Smart Sound Technology
 *
 * Copyright (C) 2013, Intel Corporation
 */

#ifndef __SOUND_SOC_SST_DSP_PRIV_H
#define __SOUND_SOC_SST_DSP_PRIV_H

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/firmware.h>

#include "../skylake/skl-sst-dsp.h"

/*
 * DSP Operations exported by platform Audio DSP driver.
 */
struct sst_ops {
	/* Shim IO */
	void (*write)(void __iomem *addr, u32 offset, u32 value);
	u32 (*read)(void __iomem *addr, u32 offset);

	/* IRQ handlers */
	irqreturn_t (*irq_handler)(int irq, void *context);

	/* SST init and free */
	int (*init)(struct sst_dsp *sst);
	void (*free)(struct sst_dsp *sst);
};

/*
 * Audio DSP memory offsets and addresses.
 */
struct sst_addr {
	u32 sram0_base;
	u32 sram1_base;
	u32 w0_stat_sz;
	u32 w0_up_sz;
	void __iomem *lpe;
	void __iomem *shim;
};

/*
 * Audio DSP Mailbox configuration.
 */
struct sst_mailbox {
	void __iomem *in_base;
	void __iomem *out_base;
	size_t in_size;
	size_t out_size;
};

/*
 * Generic SST Shim Interface.
 */
struct sst_dsp {

	/* Shared for all platforms */

	/* runtime */
	struct sst_dsp_device *sst_dev;
	spinlock_t spinlock;	/* IPC locking */
	struct mutex mutex;	/* DSP FW lock */
	struct device *dev;
	void *thread_context;
	int irq;
	u32 id;

	/* operations */
	struct sst_ops *ops;

	/* debug FS */
	struct dentry *debugfs_root;

	/* base addresses */
	struct sst_addr addr;

	/* mailbox */
	struct sst_mailbox mailbox;

	/* SST FW files loaded and their modules */
	struct list_head module_list;

	/* SKL data */

	const char *fw_name;

	/* To allocate CL dma buffers */
	struct skl_dsp_loader_ops dsp_ops;
	struct skl_dsp_fw_ops fw_ops;
	int sst_state;
	struct skl_cl_dev cl_dev;
	u32 intr_status;
	const struct firmware *fw;
	struct snd_dma_buffer dmab;
};

#endif
Commit	Line	Data
1802d0be	1	/* SPDX-License-Identifier: GPL-2.0-only */
a4b12990 MB	2	/*
	3	* Intel Smart Sound Technology
	4	*
5cf4ffa4	5	* Copyright (C) 2013, Intel Corporation
a4b12990 MB	6	*/
	7
	8	#ifndef __SOUND_SOC_SST_DSP_PRIV_H
	9	#define __SOUND_SOC_SST_DSP_PRIV_H
	10
	11	#include <linux/kernel.h>
	12	#include <linux/types.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/firmware.h>
	15
e973e31a SP	16	#include "../skylake/skl-sst-dsp.h"
e973e31a SP	17
a4b12990 MB	18	/*
	19	* DSP Operations exported by platform Audio DSP driver.
	20	*/
	21	struct sst_ops {
a4b12990 MB	22	/* Shim IO */
	23	void (write)(void __iomem addr, u32 offset, u32 value);
	24	u32 (read)(void __iomem addr, u32 offset);
a4b12990 MB	25
	26	/* IRQ handlers */
	27	irqreturn_t (irq_handler)(int irq, void context);
	28
	29	/* SST init and free */
720811f0	30	int (init)(struct sst_dsp sst);
a4b12990	31	void (free)(struct sst_dsp sst);
a4b12990 MB	32	};
	33
	34	/*
	35	* Audio DSP memory offsets and addresses.
	36	*/
	37	struct sst_addr {
09e914d6 GS	38	u32 sram0_base;
	39	u32 sram1_base;
	40	u32 w0_stat_sz;
	41	u32 w0_up_sz;
a4b12990 MB	42	void __iomem *lpe;
a4b12990 MB	43	void __iomem *shim;
a4b12990 MB	44	};
	45
	46	/*
	47	* Audio DSP Mailbox configuration.
	48	*/
	49	struct sst_mailbox {
	50	void __iomem *in_base;
	51	void __iomem *out_base;
	52	size_t in_size;
	53	size_t out_size;
	54	};
	55
a4b12990 MB	56	/*
	57	* Generic SST Shim Interface.
	58	*/
	59	struct sst_dsp {
	60
f7c765e6 SP	61	/* Shared for all platforms */
f7c765e6 SP	62
a4b12990 MB	63	/* runtime */
	64	struct sst_dsp_device *sst_dev;
	65	spinlock_t spinlock; /* IPC locking */
	66	struct mutex mutex; /* DSP FW lock */
	67	struct device *dev;
	68	void *thread_context;
	69	int irq;
	70	u32 id;
	71
a4b12990 MB	72	/* operations */
	73	struct sst_ops *ops;
	74
	75	/* debug FS */
	76	struct dentry *debugfs_root;
	77
	78	/* base addresses */
	79	struct sst_addr addr;
	80
	81	/* mailbox */
	82	struct sst_mailbox mailbox;
	83
	84	/* SST FW files loaded and their modules */
	85	struct list_head module_list;
b81fd263 SP	86
	87	/* SKL data */
	88
40c3ac46 VK	89	const char *fw_name;
40c3ac46 VK	90
3e40a784 VK	91	/* To allocate CL dma buffers */
3e40a784 VK	92	struct skl_dsp_loader_ops dsp_ops;
e973e31a SP	93	struct skl_dsp_fw_ops fw_ops;
e973e31a SP	94	int sst_state;
3e40a784	95	struct skl_cl_dev cl_dev;
b81fd263	96	u32 intr_status;
84c9e283	97	const struct firmware *fw;
b822ee63	98	struct snd_dma_buffer dmab;
a4b12990 MB	99	};
a4b12990 MB	100
a4b12990	101	#endif