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ASoC: Intel: bytcr_rt5651: Remove IN2 input mappings
[linux-2.6-block.git] / sound / soc / intel / boards / bytcr_rt5651.c
CommitLineData
2bd5bd15
PLB		 1/*
2 * bytcr_rt5651.c - ASoc Machine driver for Intel Byt CR platform
3 * (derived from bytcr_rt5640.c)
4 *
5 * Copyright (C) 2015 Intel Corp
6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
18 */
19
20#include <linux/init.h>
46058aeb 21#include <linux/i2c.h>
2bd5bd15
PLB		 22#include <linux/module.h>
23#include <linux/platform_device.h>
46058aeb 24#include <linux/property.h>
2bd5bd15 25#include <linux/acpi.h>
02c0a3b3 26#include <linux/clk.h>
2bd5bd15
PLB		 27#include <linux/device.h>
28#include <linux/dmi.h>
29#include <linux/slab.h>
8a880a20 30#include <asm/cpu_device_id.h>
02c0a3b3 31#include <asm/platform_sst_audio.h>
2bd5bd15
PLB		 32#include <sound/pcm.h>
33#include <sound/pcm_params.h>
34#include <sound/soc.h>
35#include <sound/jack.h>
7feb2f78 36#include <sound/soc-acpi.h>
2bd5bd15
PLB		 37#include "../../codecs/rt5651.h"
38#include "../atom/sst-atom-controls.h"
02c0a3b3
PLB		 39
40enum {
41 BYT_RT5651_DMIC_MAP,
42 BYT_RT5651_IN1_MAP,
ea261bd0 43 BYT_RT5651_IN1_IN2_MAP,
7f2e2299 44 BYT_RT5651_IN1_HS_IN3_MAP,
02c0a3b3
PLB		 45};
46
46058aeb
HG		 47enum {
48 BYT_RT5651_JD_NULL = (RT5651_JD_NULL << 4),
49 BYT_RT5651_JD1_1 = (RT5651_JD1_1 << 4),
50 BYT_RT5651_JD1_2 = (RT5651_JD1_2 << 4),
51 BYT_RT5651_JD2 = (RT5651_JD2 << 4),
52};
53
8ffaa6a1
HG		 54enum {
55 BYT_RT5651_OVCD_TH_600UA = (6 << 8),
56 BYT_RT5651_OVCD_TH_1500UA = (15 << 8),
57 BYT_RT5651_OVCD_TH_2000UA = (20 << 8),
58};
59
60enum {
61 BYT_RT5651_OVCD_SF_0P5 = (RT5651_OVCD_SF_0P5 << 13),
62 BYT_RT5651_OVCD_SF_0P75 = (RT5651_OVCD_SF_0P75 << 13),
63 BYT_RT5651_OVCD_SF_1P0 = (RT5651_OVCD_SF_1P0 << 13),
64 BYT_RT5651_OVCD_SF_1P5 = (RT5651_OVCD_SF_1P5 << 13),
65};
66
46058aeb
HG		 67#define BYT_RT5651_MAP(quirk) ((quirk) & GENMASK(3, 0))
68#define BYT_RT5651_JDSRC(quirk) (((quirk) & GENMASK(7, 4)) >> 4)
8ffaa6a1
HG		 69#define BYT_RT5651_OVCD_TH(quirk) (((quirk) & GENMASK(12, 8)) >> 8)
70#define BYT_RT5651_OVCD_SF(quirk) (((quirk) & GENMASK(14, 13)) >> 13)
46058aeb
HG		 71#define BYT_RT5651_DMIC_EN BIT(16)
72#define BYT_RT5651_MCLK_EN BIT(17)
73#define BYT_RT5651_MCLK_25MHZ BIT(18)
8a880a20
HG		 74#define BYT_RT5651_SSP2_AIF2 BIT(19) /* default is using AIF1 */
75#define BYT_RT5651_SSP0_AIF1 BIT(20)
76#define BYT_RT5651_SSP0_AIF2 BIT(21)
46058aeb 77
fc7c460f
HG		 78#define BYT_RT5651_DEFAULT_QUIRKS (BYT_RT5651_MCLK_EN | \
79 BYT_RT5651_JD1_1 | \
80 BYT_RT5651_OVCD_TH_2000UA | \
81 BYT_RT5651_OVCD_SF_0P75)
82
8ffaa6a1
HG		 83/* jack-detect-source + dmic-en + ovcd-th + -sf + terminating empty entry */
84#define MAX_NO_PROPS 5
02c0a3b3
PLB		 85
86struct byt_rt5651_private {
87 struct clk *mclk;
d9f8f9b2 88 struct snd_soc_jack jack;
02c0a3b3
PLB		 89};
90
10876d24 91/* Default: jack-detect on JD1_1, internal mic on in1, headsetmic on in3 */
fc7c460f 92static unsigned long byt_rt5651_quirk = BYT_RT5651_DEFAULT_QUIRKS |
10876d24 93 BYT_RT5651_IN1_HS_IN3_MAP;
02c0a3b3
PLB		 94
95static void log_quirks(struct device *dev)
96{
97 if (BYT_RT5651_MAP(byt_rt5651_quirk) == BYT_RT5651_DMIC_MAP)
98 dev_info(dev, "quirk DMIC_MAP enabled");
99 if (BYT_RT5651_MAP(byt_rt5651_quirk) == BYT_RT5651_IN1_MAP)
100 dev_info(dev, "quirk IN1_MAP enabled");
366780df
HG		 101 if (BYT_RT5651_MAP(byt_rt5651_quirk) == BYT_RT5651_IN1_IN2_MAP)
102 dev_info(dev, "quirk IN1_IN2_MAP enabled");
7f2e2299
HG		 103 if (BYT_RT5651_MAP(byt_rt5651_quirk) == BYT_RT5651_IN1_HS_IN3_MAP)
104 dev_info(dev, "quirk IN1_HS_IN3_MAP enabled");
8ffaa6a1 105 if (BYT_RT5651_JDSRC(byt_rt5651_quirk)) {
46058aeb
HG		 106 dev_info(dev, "quirk realtek,jack-detect-source %ld\n",
107 BYT_RT5651_JDSRC(byt_rt5651_quirk));
8ffaa6a1
HG		 108 dev_info(dev, "quirk realtek,over-current-threshold-microamp %ld\n",
109 BYT_RT5651_OVCD_TH(byt_rt5651_quirk) * 100);
110 dev_info(dev, "quirk realtek,over-current-scale-factor %ld\n",
111 BYT_RT5651_OVCD_SF(byt_rt5651_quirk));
112 }
02c0a3b3
PLB		 113 if (byt_rt5651_quirk & BYT_RT5651_DMIC_EN)
114 dev_info(dev, "quirk DMIC enabled");
115 if (byt_rt5651_quirk & BYT_RT5651_MCLK_EN)
116 dev_info(dev, "quirk MCLK_EN enabled");
117 if (byt_rt5651_quirk & BYT_RT5651_MCLK_25MHZ)
118 dev_info(dev, "quirk MCLK_25MHZ enabled");
8a880a20
HG		 119 if (byt_rt5651_quirk & BYT_RT5651_SSP2_AIF2)
120 dev_info(dev, "quirk SSP2_AIF2 enabled\n");
121 if (byt_rt5651_quirk & BYT_RT5651_SSP0_AIF1)
122 dev_info(dev, "quirk SSP0_AIF1 enabled\n");
123 if (byt_rt5651_quirk & BYT_RT5651_SSP0_AIF2)
124 dev_info(dev, "quirk SSP0_AIF2 enabled\n");
02c0a3b3
PLB		 125}
126
127#define BYT_CODEC_DAI1 "rt5651-aif1"
8a880a20 128#define BYT_CODEC_DAI2 "rt5651-aif2"
02c0a3b3 129
aeec6cc0
HG		 130static int byt_rt5651_prepare_and_enable_pll1(struct snd_soc_dai *codec_dai,
131 int rate, int bclk_ratio)
132{
133 int clk_id, clk_freq, ret;
134
135 /* Configure the PLL before selecting it */
136 if (!(byt_rt5651_quirk & BYT_RT5651_MCLK_EN)) {
137 clk_id = RT5651_PLL1_S_BCLK1,
138 clk_freq = rate * bclk_ratio;
139 } else {
140 clk_id = RT5651_PLL1_S_MCLK;
141 if (byt_rt5651_quirk & BYT_RT5651_MCLK_25MHZ)
142 clk_freq = 25000000;
143 else
144 clk_freq = 19200000;
145 }
146 ret = snd_soc_dai_set_pll(codec_dai, 0, clk_id, clk_freq, rate * 512);
147 if (ret < 0) {
2759ba9b 148 dev_err(codec_dai->component->dev, "can't set pll: %d\n", ret);
aeec6cc0
HG		 149 return ret;
150 }
151
152 ret = snd_soc_dai_set_sysclk(codec_dai, RT5651_SCLK_S_PLL1,
153 rate * 512, SND_SOC_CLOCK_IN);
154 if (ret < 0) {
2759ba9b 155 dev_err(codec_dai->component->dev, "can't set clock %d\n", ret);
aeec6cc0
HG		 156 return ret;
157 }
158
159 return 0;
160}
161
02c0a3b3
PLB		 162static int platform_clock_control(struct snd_soc_dapm_widget *w,
163 struct snd_kcontrol *k, int event)
164{
165 struct snd_soc_dapm_context *dapm = w->dapm;
166 struct snd_soc_card *card = dapm->card;
167 struct snd_soc_dai *codec_dai;
168 struct byt_rt5651_private *priv = snd_soc_card_get_drvdata(card);
169 int ret;
170
dfb6ec7a 171 codec_dai = snd_soc_card_get_codec_dai(card, BYT_CODEC_DAI1);
8a880a20
HG		 172 if (!codec_dai)
173 codec_dai = snd_soc_card_get_codec_dai(card, BYT_CODEC_DAI2);
02c0a3b3
PLB		 174 if (!codec_dai) {
175 dev_err(card->dev,
176 "Codec dai not found; Unable to set platform clock\n");
177 return -EIO;
178 }
179
180 if (SND_SOC_DAPM_EVENT_ON(event)) {
181 if (byt_rt5651_quirk & BYT_RT5651_MCLK_EN) {
182 ret = clk_prepare_enable(priv->mclk);
183 if (ret < 0) {
184 dev_err(card->dev,
185 "could not configure MCLK state");
186 return ret;
187 }
188 }
aeec6cc0 189 ret = byt_rt5651_prepare_and_enable_pll1(codec_dai, 48000, 50);
02c0a3b3
PLB		 190 } else {
191 /*
192 * Set codec clock source to internal clock before
193 * turning off the platform clock. Codec needs clock
194 * for Jack detection and button press
195 */
196 ret = snd_soc_dai_set_sysclk(codec_dai, RT5651_SCLK_S_RCCLK,
197 48000 * 512,
198 SND_SOC_CLOCK_IN);
199 if (!ret)
200 if (byt_rt5651_quirk & BYT_RT5651_MCLK_EN)
201 clk_disable_unprepare(priv->mclk);
202 }
203
204 if (ret < 0) {
205 dev_err(card->dev, "can't set codec sysclk: %d\n", ret);
206 return ret;
207 }
208
209 return 0;
210}
2bd5bd15
PLB		 211
212static const struct snd_soc_dapm_widget byt_rt5651_widgets[] = {
213 SND_SOC_DAPM_HP("Headphone", NULL),
214 SND_SOC_DAPM_MIC("Headset Mic", NULL),
215 SND_SOC_DAPM_MIC("Internal Mic", NULL),
216 SND_SOC_DAPM_SPK("Speaker", NULL),
ea39bdcf 217 SND_SOC_DAPM_LINE("Line In", NULL),
02c0a3b3
PLB		 218 SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
219 platform_clock_control, SND_SOC_DAPM_PRE_PMU |
220 SND_SOC_DAPM_POST_PMD),
221
2bd5bd15
PLB		 222};
223
224static const struct snd_soc_dapm_route byt_rt5651_audio_map[] = {
02c0a3b3
PLB		 225 {"Headphone", NULL, "Platform Clock"},
226 {"Headset Mic", NULL, "Platform Clock"},
227 {"Internal Mic", NULL, "Platform Clock"},
228 {"Speaker", NULL, "Platform Clock"},
ea39bdcf 229 {"Line In", NULL, "Platform Clock"},
02c0a3b3 230
2bd5bd15 231 {"Headset Mic", NULL, "micbias1"}, /* lowercase for rt5651 */
2bd5bd15
PLB		 232 {"Headphone", NULL, "HPOL"},
233 {"Headphone", NULL, "HPOR"},
234 {"Speaker", NULL, "LOUTL"},
235 {"Speaker", NULL, "LOUTR"},
ea39bdcf
PLB		 236 {"IN2P", NULL, "Line In"},
237 {"IN2N", NULL, "Line In"},
238
2bd5bd15
PLB		 239};
240
6356c78c 241static const struct snd_soc_dapm_route byt_rt5651_intmic_dmic_map[] = {
39712db8 242 {"IN2P", NULL, "Headset Mic"},
6356c78c
PLB		 243 {"DMIC L1", NULL, "Internal Mic"},
244 {"DMIC R1", NULL, "Internal Mic"},
2bd5bd15
PLB		 245};
246
247static const struct snd_soc_dapm_route byt_rt5651_intmic_in1_map[] = {
248 {"Internal Mic", NULL, "micbias1"},
249 {"IN1P", NULL, "Internal Mic"},
7f2e2299 250 {"IN2P", NULL, "Headset Mic"},
2bd5bd15
PLB		 251};
252
ea261bd0
CC		 253static const struct snd_soc_dapm_route byt_rt5651_intmic_in1_in2_map[] = {
254 {"Internal Mic", NULL, "micbias1"},
255 {"IN1P", NULL, "Internal Mic"},
256 {"IN2P", NULL, "Internal Mic"},
257 {"IN3P", NULL, "Headset Mic"},
258};
259
7f2e2299 260static const struct snd_soc_dapm_route byt_rt5651_intmic_in1_hs_in3_map[] = {
60e3b52e 261 {"Internal Mic", NULL, "micbias1"},
60e3b52e 262 {"IN1P", NULL, "Internal Mic"},
7f2e2299 263 {"IN3P", NULL, "Headset Mic"},
60e3b52e
KJ		 264};
265
8a880a20
HG		 266static const struct snd_soc_dapm_route byt_rt5651_ssp0_aif1_map[] = {
267 {"ssp0 Tx", NULL, "modem_out"},
268 {"modem_in", NULL, "ssp0 Rx"},
269
270 {"AIF1 Playback", NULL, "ssp0 Tx"},
271 {"ssp0 Rx", NULL, "AIF1 Capture"},
272};
273
274static const struct snd_soc_dapm_route byt_rt5651_ssp0_aif2_map[] = {
275 {"ssp0 Tx", NULL, "modem_out"},
276 {"modem_in", NULL, "ssp0 Rx"},
277
278 {"AIF2 Playback", NULL, "ssp0 Tx"},
279 {"ssp0 Rx", NULL, "AIF2 Capture"},
280};
281
282static const struct snd_soc_dapm_route byt_rt5651_ssp2_aif1_map[] = {
283 {"ssp2 Tx", NULL, "codec_out0"},
284 {"ssp2 Tx", NULL, "codec_out1"},
285 {"codec_in0", NULL, "ssp2 Rx"},
286 {"codec_in1", NULL, "ssp2 Rx"},
287
288 {"AIF1 Playback", NULL, "ssp2 Tx"},
289 {"ssp2 Rx", NULL, "AIF1 Capture"},
290};
291
292static const struct snd_soc_dapm_route byt_rt5651_ssp2_aif2_map[] = {
293 {"ssp2 Tx", NULL, "codec_out0"},
294 {"ssp2 Tx", NULL, "codec_out1"},
295 {"codec_in0", NULL, "ssp2 Rx"},
296 {"codec_in1", NULL, "ssp2 Rx"},
297
298 {"AIF2 Playback", NULL, "ssp2 Tx"},
299 {"ssp2 Rx", NULL, "AIF2 Capture"},
300};
301
2bd5bd15
PLB		 302static const struct snd_kcontrol_new byt_rt5651_controls[] = {
303 SOC_DAPM_PIN_SWITCH("Headphone"),
304 SOC_DAPM_PIN_SWITCH("Headset Mic"),
305 SOC_DAPM_PIN_SWITCH("Internal Mic"),
306 SOC_DAPM_PIN_SWITCH("Speaker"),
ea39bdcf 307 SOC_DAPM_PIN_SWITCH("Line In"),
2bd5bd15
PLB		 308};
309
d9f8f9b2
CC		 310static struct snd_soc_jack_pin bytcr_jack_pins[] = {
311 {
312 .pin = "Headphone",
313 .mask = SND_JACK_HEADPHONE,
314 },
315 {
316 .pin = "Headset Mic",
317 .mask = SND_JACK_MICROPHONE,
318 },
319};
320
2bd5bd15
PLB		 321static int byt_rt5651_aif1_hw_params(struct snd_pcm_substream *substream,
322 struct snd_pcm_hw_params *params)
323{
324 struct snd_soc_pcm_runtime *rtd = substream->private_data;
325 struct snd_soc_dai *codec_dai = rtd->codec_dai;
8a880a20 326 snd_pcm_format_t format = params_format(params);
aeec6cc0 327 int rate = params_rate(params);
8a880a20 328 int bclk_ratio;
2bd5bd15 329
8a880a20
HG		 330 if (format == SNDRV_PCM_FORMAT_S16_LE)
331 bclk_ratio = 32;
332 else
333 bclk_ratio = 50;
334
335 return byt_rt5651_prepare_and_enable_pll1(codec_dai, rate, bclk_ratio);
2bd5bd15
PLB		 336}
337
02c0a3b3
PLB		 338static int byt_rt5651_quirk_cb(const struct dmi_system_id *id)
339{
340 byt_rt5651_quirk = (unsigned long)id->driver_data;
341 return 1;
342}
343
2bd5bd15 344static const struct dmi_system_id byt_rt5651_quirk_table[] = {
02c0a3b3
PLB		 345 {
346 .callback = byt_rt5651_quirk_cb,
347 .matches = {
348 DMI_MATCH(DMI_SYS_VENDOR, "Circuitco"),
349 DMI_MATCH(DMI_PRODUCT_NAME, "Minnowboard Max B3 PLATFORM"),
350 },
7f2e2299 351 .driver_data = (void *)(BYT_RT5651_IN1_HS_IN3_MAP),
02c0a3b3 352 },
416f2b51
PLB		 353 {
354 .callback = byt_rt5651_quirk_cb,
355 .matches = {
356 DMI_MATCH(DMI_SYS_VENDOR, "ADI"),
357 DMI_MATCH(DMI_PRODUCT_NAME, "Minnowboard Turbot"),
358 },
359 .driver_data = (void *)(BYT_RT5651_MCLK_EN |
7f2e2299 360 BYT_RT5651_IN1_HS_IN3_MAP),
416f2b51 361 },
2fe30129
CC		 362 {
363 .callback = byt_rt5651_quirk_cb,
364 .matches = {
365 DMI_MATCH(DMI_SYS_VENDOR, "KIANO"),
366 DMI_MATCH(DMI_PRODUCT_NAME, "KIANO SlimNote 14.2"),
367 },
fc7c460f 368 .driver_data = (void *)(BYT_RT5651_DEFAULT_QUIRKS |
56e49aa4 369 BYT_RT5651_IN1_IN2_MAP),
2fe30129 370 },
f026e063
HG		 371 {
372 /* Chuwi Vi8 Plus (CWI519) */
373 .callback = byt_rt5651_quirk_cb,
374 .matches = {
375 DMI_MATCH(DMI_SYS_VENDOR, "Hampoo"),
376 DMI_MATCH(DMI_PRODUCT_NAME, "D2D3_Vi8A1"),
377 },
fc7c460f 378 .driver_data = (void *)(BYT_RT5651_DEFAULT_QUIRKS |
10876d24 379 BYT_RT5651_IN1_HS_IN3_MAP),
f026e063 380 },
f9877eb5
HG		 381 {
382 /* VIOS LTH17 */
383 .callback = byt_rt5651_quirk_cb,
384 .matches = {
385 DMI_MATCH(DMI_SYS_VENDOR, "VIOS"),
386 DMI_MATCH(DMI_PRODUCT_NAME, "LTH17"),
387 },
fc7c460f 388 .driver_data = (void *)(BYT_RT5651_DEFAULT_QUIRKS |
f9877eb5
HG		 389 BYT_RT5651_IN1_IN2_MAP),
390 },
2bd5bd15
PLB		 391 {}
392};
393
46058aeb
HG		 394/*
395 * Note this MUST be called before snd_soc_register_card(), so that the props
396 * are in place before the codec component driver's probe function parses them.
397 */
398static int byt_rt5651_add_codec_device_props(const char *i2c_dev_name)
399{
400 struct property_entry props[MAX_NO_PROPS] = {};
401 struct device *i2c_dev;
402 int ret, cnt = 0;
403
404 i2c_dev = bus_find_device_by_name(&i2c_bus_type, NULL, i2c_dev_name);
405 if (!i2c_dev)
406 return -EPROBE_DEFER;
407
408 props[cnt++] = PROPERTY_ENTRY_U32("realtek,jack-detect-source",
409 BYT_RT5651_JDSRC(byt_rt5651_quirk));
410
8ffaa6a1
HG		 411 props[cnt++] = PROPERTY_ENTRY_U32("realtek,over-current-threshold-microamp",
412 BYT_RT5651_OVCD_TH(byt_rt5651_quirk) * 100);
413
414 props[cnt++] = PROPERTY_ENTRY_U32("realtek,over-current-scale-factor",
415 BYT_RT5651_OVCD_SF(byt_rt5651_quirk));
416
c2f26938
HG		 417 if (byt_rt5651_quirk & BYT_RT5651_DMIC_EN)
418 props[cnt++] = PROPERTY_ENTRY_BOOL("realtek,dmic-en");
419
46058aeb
HG		 420 ret = device_add_properties(i2c_dev, props);
421 put_device(i2c_dev);
422
423 return ret;
424}
425
2bd5bd15
PLB		 426static int byt_rt5651_init(struct snd_soc_pcm_runtime *runtime)
427{
2bd5bd15 428 struct snd_soc_card *card = runtime->card;
17b52010 429 struct snd_soc_component *codec = runtime->codec_dai->component;
02c0a3b3 430 struct byt_rt5651_private *priv = snd_soc_card_get_drvdata(card);
2bd5bd15
PLB		 431 const struct snd_soc_dapm_route *custom_map;
432 int num_routes;
02c0a3b3 433 int ret;
2bd5bd15
PLB		 434
435 card->dapm.idle_bias_off = true;
436
c22969d7
HG		 437 /* Start with RC clk for jack-detect (we disable MCLK below) */
438 if (byt_rt5651_quirk & BYT_RT5651_MCLK_EN)
439 snd_soc_component_update_bits(codec, RT5651_GLB_CLK,
440 RT5651_SCLK_SRC_MASK, RT5651_SCLK_SRC_RCCLK);
441
2bd5bd15
PLB		 442 switch (BYT_RT5651_MAP(byt_rt5651_quirk)) {
443 case BYT_RT5651_IN1_MAP:
444 custom_map = byt_rt5651_intmic_in1_map;
445 num_routes = ARRAY_SIZE(byt_rt5651_intmic_in1_map);
446 break;
ea261bd0
CC		 447 case BYT_RT5651_IN1_IN2_MAP:
448 custom_map = byt_rt5651_intmic_in1_in2_map;
449 num_routes = ARRAY_SIZE(byt_rt5651_intmic_in1_in2_map);
450 break;
7f2e2299
HG		 451 case BYT_RT5651_IN1_HS_IN3_MAP:
452 custom_map = byt_rt5651_intmic_in1_hs_in3_map;
453 num_routes = ARRAY_SIZE(byt_rt5651_intmic_in1_hs_in3_map);
60e3b52e 454 break;
2bd5bd15 455 default:
6356c78c
PLB		 456 custom_map = byt_rt5651_intmic_dmic_map;
457 num_routes = ARRAY_SIZE(byt_rt5651_intmic_dmic_map);
2bd5bd15 458 }
6356c78c
PLB		 459 ret = snd_soc_dapm_add_routes(&card->dapm, custom_map, num_routes);
460 if (ret)
461 return ret;
2bd5bd15 462
8a880a20
HG		 463 if (byt_rt5651_quirk & BYT_RT5651_SSP2_AIF2) {
464 ret = snd_soc_dapm_add_routes(&card->dapm,
465 byt_rt5651_ssp2_aif2_map,
466 ARRAY_SIZE(byt_rt5651_ssp2_aif2_map));
467 } else if (byt_rt5651_quirk & BYT_RT5651_SSP0_AIF1) {
468 ret = snd_soc_dapm_add_routes(&card->dapm,
469 byt_rt5651_ssp0_aif1_map,
470 ARRAY_SIZE(byt_rt5651_ssp0_aif1_map));
471 } else if (byt_rt5651_quirk & BYT_RT5651_SSP0_AIF2) {
472 ret = snd_soc_dapm_add_routes(&card->dapm,
473 byt_rt5651_ssp0_aif2_map,
474 ARRAY_SIZE(byt_rt5651_ssp0_aif2_map));
475 } else {
476 ret = snd_soc_dapm_add_routes(&card->dapm,
477 byt_rt5651_ssp2_aif1_map,
478 ARRAY_SIZE(byt_rt5651_ssp2_aif1_map));
479 }
480 if (ret)
481 return ret;
482
2bd5bd15
PLB		 483 ret = snd_soc_add_card_controls(card, byt_rt5651_controls,
484 ARRAY_SIZE(byt_rt5651_controls));
485 if (ret) {
486 dev_err(card->dev, "unable to add card controls\n");
487 return ret;
488 }
489 snd_soc_dapm_ignore_suspend(&card->dapm, "Headphone");
490 snd_soc_dapm_ignore_suspend(&card->dapm, "Speaker");
491
02c0a3b3
PLB		 492 if (byt_rt5651_quirk & BYT_RT5651_MCLK_EN) {
493 /*
494 * The firmware might enable the clock at
495 * boot (this information may or may not
496 * be reflected in the enable clock register).
497 * To change the rate we must disable the clock
498 * first to cover these cases. Due to common
499 * clock framework restrictions that do not allow
500 * to disable a clock that has not been enabled,
501 * we need to enable the clock first.
502 */
503 ret = clk_prepare_enable(priv->mclk);
504 if (!ret)
505 clk_disable_unprepare(priv->mclk);
506
507 if (byt_rt5651_quirk & BYT_RT5651_MCLK_25MHZ)
508 ret = clk_set_rate(priv->mclk, 25000000);
509 else
510 ret = clk_set_rate(priv->mclk, 19200000);
511
512 if (ret)
513 dev_err(card->dev, "unable to set MCLK rate\n");
514 }
515
aed859a2
HG		 516 if (BYT_RT5651_JDSRC(byt_rt5651_quirk)) {
517 ret = snd_soc_card_jack_new(runtime->card, "Headset",
d9f8f9b2
CC		 518 SND_JACK_HEADSET, &priv->jack,
519 bytcr_jack_pins, ARRAY_SIZE(bytcr_jack_pins));
aed859a2
HG		 520 if (ret) {
521 dev_err(runtime->dev, "jack creation failed %d\n", ret);
522 return ret;
523 }
d9f8f9b2 524
aed859a2
HG		 525 ret = snd_soc_component_set_jack(codec, &priv->jack, NULL);
526 if (ret)
527 return ret;
528 }
d9f8f9b2 529
aed859a2 530 return 0;
2bd5bd15
PLB		 531}
532
533static const struct snd_soc_pcm_stream byt_rt5651_dai_params = {
534 .formats = SNDRV_PCM_FMTBIT_S24_LE,
535 .rate_min = 48000,
536 .rate_max = 48000,
537 .channels_min = 2,
538 .channels_max = 2,
539};
540
541static int byt_rt5651_codec_fixup(struct snd_soc_pcm_runtime *rtd,
542 struct snd_pcm_hw_params *params)
543{
544 struct snd_interval *rate = hw_param_interval(params,
545 SNDRV_PCM_HW_PARAM_RATE);
546 struct snd_interval *channels = hw_param_interval(params,
547 SNDRV_PCM_HW_PARAM_CHANNELS);
8a880a20 548 int ret, bits;
2bd5bd15 549
8a880a20 550 /* The DSP will covert the FE rate to 48k, stereo */
2bd5bd15
PLB		 551 rate->min = rate->max = 48000;
552 channels->min = channels->max = 2;
553
8a880a20
HG		 554 if ((byt_rt5651_quirk & BYT_RT5651_SSP0_AIF1) ||
555 (byt_rt5651_quirk & BYT_RT5651_SSP0_AIF2)) {
556 /* set SSP0 to 16-bit */
557 params_set_format(params, SNDRV_PCM_FORMAT_S16_LE);
558 bits = 16;
559 } else {
560 /* set SSP2 to 24-bit */
561 params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
562 bits = 24;
563 }
2bd5bd15
PLB		 564
565 /*
566 * Default mode for SSP configuration is TDM 4 slot, override config
8a880a20 567 * with explicit setting to I2S 2ch. The word length is set with
2bd5bd15
PLB		 568 * dai_set_tdm_slot() since there is no other API exposed
569 */
570 ret = snd_soc_dai_set_fmt(rtd->cpu_dai,
571 SND_SOC_DAIFMT_I2S |
f12f5c84 572 SND_SOC_DAIFMT_NB_NF |
2bd5bd15
PLB		 573 SND_SOC_DAIFMT_CBS_CFS
574 );
575
576 if (ret < 0) {
577 dev_err(rtd->dev, "can't set format to I2S, err %d\n", ret);
578 return ret;
579 }
580
8a880a20 581 ret = snd_soc_dai_set_tdm_slot(rtd->cpu_dai, 0x3, 0x3, 2, bits);
2bd5bd15
PLB		 582 if (ret < 0) {
583 dev_err(rtd->dev, "can't set I2S config, err %d\n", ret);
584 return ret;
585 }
586
587 return 0;
588}
589
1ebb4d9d 590static const unsigned int rates_48000[] = {
2bd5bd15
PLB		 591 48000,
592};
593
1ebb4d9d 594static const struct snd_pcm_hw_constraint_list constraints_48000 = {
2bd5bd15
PLB		 595 .count = ARRAY_SIZE(rates_48000),
596 .list = rates_48000,
597};
598
599static int byt_rt5651_aif1_startup(struct snd_pcm_substream *substream)
600{
601 return snd_pcm_hw_constraint_list(substream->runtime, 0,
602 SNDRV_PCM_HW_PARAM_RATE,
603 &constraints_48000);
604}
605
9b6fdef6 606static const struct snd_soc_ops byt_rt5651_aif1_ops = {
2bd5bd15
PLB		 607 .startup = byt_rt5651_aif1_startup,
608};
609
9b6fdef6 610static const struct snd_soc_ops byt_rt5651_be_ssp2_ops = {
2bd5bd15
PLB		 611 .hw_params = byt_rt5651_aif1_hw_params,
612};
613
614static struct snd_soc_dai_link byt_rt5651_dais[] = {
615 [MERR_DPCM_AUDIO] = {
616 .name = "Audio Port",
617 .stream_name = "Audio",
618 .cpu_dai_name = "media-cpu-dai",
619 .codec_dai_name = "snd-soc-dummy-dai",
620 .codec_name = "snd-soc-dummy",
621 .platform_name = "sst-mfld-platform",
2bd5bd15
PLB		 622 .nonatomic = true,
623 .dynamic = 1,
624 .dpcm_playback = 1,
625 .dpcm_capture = 1,
626 .ops = &byt_rt5651_aif1_ops,
627 },
628 [MERR_DPCM_DEEP_BUFFER] = {
629 .name = "Deep-Buffer Audio Port",
630 .stream_name = "Deep-Buffer Audio",
631 .cpu_dai_name = "deepbuffer-cpu-dai",
632 .codec_dai_name = "snd-soc-dummy-dai",
633 .codec_name = "snd-soc-dummy",
634 .platform_name = "sst-mfld-platform",
2bd5bd15
PLB		 635 .nonatomic = true,
636 .dynamic = 1,
637 .dpcm_playback = 1,
638 .ops = &byt_rt5651_aif1_ops,
639 },
2bd5bd15
PLB		 640 /* CODEC<->CODEC link */
641 /* back ends */
642 {
643 .name = "SSP2-Codec",
149f7757 644 .id = 0,
2bd5bd15
PLB		 645 .cpu_dai_name = "ssp2-port",
646 .platform_name = "sst-mfld-platform",
647 .no_pcm = 1,
648 .codec_dai_name = "rt5651-aif1",
649 .codec_name = "i2c-10EC5651:00",
650 .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
651 | SND_SOC_DAIFMT_CBS_CFS,
652 .be_hw_params_fixup = byt_rt5651_codec_fixup,
653 .ignore_suspend = 1,
654 .nonatomic = true,
655 .dpcm_playback = 1,
656 .dpcm_capture = 1,
657 .init = byt_rt5651_init,
658 .ops = &byt_rt5651_be_ssp2_ops,
659 },
660};
661
662/* SoC card */
663static struct snd_soc_card byt_rt5651_card = {
664 .name = "bytcr-rt5651",
665 .owner = THIS_MODULE,
666 .dai_link = byt_rt5651_dais,
667 .num_links = ARRAY_SIZE(byt_rt5651_dais),
668 .dapm_widgets = byt_rt5651_widgets,
669 .num_dapm_widgets = ARRAY_SIZE(byt_rt5651_widgets),
670 .dapm_routes = byt_rt5651_audio_map,
671 .num_dapm_routes = ARRAY_SIZE(byt_rt5651_audio_map),
672 .fully_routed = true,
673};
674
2be2d579 675static char byt_rt5651_codec_name[SND_ACPI_I2C_ID_LEN];
8a880a20
HG		 676static char byt_rt5651_codec_aif_name[12]; /* = "rt5651-aif[1|2]" */
677static char byt_rt5651_cpu_dai_name[10]; /* = "ssp[0|2]-port" */
64484cce 678static char byt_rt5651_long_name[40]; /* = "bytcr-rt5651-*-spk-*-mic" */
8a880a20
HG		 679
680static bool is_valleyview(void)
681{
682 static const struct x86_cpu_id cpu_ids[] = {
683 { X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */
684 {}
685 };
686
687 if (!x86_match_cpu(cpu_ids))
688 return false;
689 return true;
690}
691
692struct acpi_chan_package { /* ACPICA seems to require 64 bit integers */
693 u64 aif_value; /* 1: AIF1, 2: AIF2 */
694 u64 mclock_value; /* usually 25MHz (0x17d7940), ignored */
695};
02c0a3b3 696
2bd5bd15
PLB		 697static int snd_byt_rt5651_mc_probe(struct platform_device *pdev)
698{
64484cce 699 const char * const intmic_name[] =
fcdf1391 700 { "dmic", "in1", "in12", "in1" };
64484cce 701 const char * const hsmic_name[] =
fcdf1391 702 { "in2", "in2", "in3", "in3" };
02c0a3b3 703 struct byt_rt5651_private *priv;
7feb2f78 704 struct snd_soc_acpi_mach *mach;
02c0a3b3 705 const char *i2c_name = NULL;
8a880a20 706 bool is_bytcr = false;
2bd5bd15 707 int ret_val = 0;
2193eb96 708 int dai_index = 0;
02c0a3b3
PLB		 709 int i;
710
aa5398e1 711 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
02c0a3b3
PLB		 712 if (!priv)
713 return -ENOMEM;
2bd5bd15
PLB		 714
715 /* register the soc card */
716 byt_rt5651_card.dev = &pdev->dev;
717
02c0a3b3
PLB		 718 mach = byt_rt5651_card.dev->platform_data;
719 snd_soc_card_set_drvdata(&byt_rt5651_card, priv);
720
721 /* fix index of codec dai */
02c0a3b3
PLB		 722 for (i = 0; i < ARRAY_SIZE(byt_rt5651_dais); i++) {
723 if (!strcmp(byt_rt5651_dais[i].codec_name, "i2c-10EC5651:00")) {
724 dai_index = i;
725 break;
726 }
727 }
728
729 /* fixup codec name based on HID */
3a147959 730 i2c_name = acpi_dev_get_first_match_name(mach->id, NULL, -1);
e39cacc1
HG		 731 if (!i2c_name) {
732 dev_err(&pdev->dev, "Error cannot find '%s' dev\n", mach->id);
733 return -ENODEV;
02c0a3b3 734 }
e39cacc1
HG		 735 snprintf(byt_rt5651_codec_name, sizeof(byt_rt5651_codec_name),
736 "%s%s", "i2c-", i2c_name);
737 byt_rt5651_dais[dai_index].codec_name = byt_rt5651_codec_name;
02c0a3b3 738
8a880a20
HG		 739 /*
740 * swap SSP0 if bytcr is detected
741 * (will be overridden if DMI quirk is detected)
742 */
743 if (is_valleyview()) {
744 struct sst_platform_info *p_info = mach->pdata;
745 const struct sst_res_info *res_info = p_info->res_info;
746
747 if (res_info->acpi_ipc_irq_index == 0)
748 is_bytcr = true;
749 }
750
751 if (is_bytcr) {
752 /*
753 * Baytrail CR platforms may have CHAN package in BIOS, try
754 * to find relevant routing quirk based as done on Windows
755 * platforms. We have to read the information directly from the
756 * BIOS, at this stage the card is not created and the links
757 * with the codec driver/pdata are non-existent
758 */
759
760 struct acpi_chan_package chan_package;
761
762 /* format specified: 2 64-bit integers */
763 struct acpi_buffer format = {sizeof("NN"), "NN"};
764 struct acpi_buffer state = {0, NULL};
765 struct snd_soc_acpi_package_context pkg_ctx;
766 bool pkg_found = false;
767
768 state.length = sizeof(chan_package);
769 state.pointer = &chan_package;
770
771 pkg_ctx.name = "CHAN";
772 pkg_ctx.length = 2;
773 pkg_ctx.format = &format;
774 pkg_ctx.state = &state;
775 pkg_ctx.data_valid = false;
776
777 pkg_found = snd_soc_acpi_find_package_from_hid(mach->id,
778 &pkg_ctx);
779 if (pkg_found) {
780 if (chan_package.aif_value == 1) {
781 dev_info(&pdev->dev, "BIOS Routing: AIF1 connected\n");
782 byt_rt5651_quirk |= BYT_RT5651_SSP0_AIF1;
783 } else if (chan_package.aif_value == 2) {
784 dev_info(&pdev->dev, "BIOS Routing: AIF2 connected\n");
785 byt_rt5651_quirk |= BYT_RT5651_SSP0_AIF2;
786 } else {
787 dev_info(&pdev->dev, "BIOS Routing isn't valid, ignored\n");
788 pkg_found = false;
789 }
790 }
791
792 if (!pkg_found) {
793 /* no BIOS indications, assume SSP0-AIF2 connection */
794 byt_rt5651_quirk |= BYT_RT5651_SSP0_AIF2;
795 }
8a880a20
HG		 796 }
797
02c0a3b3
PLB		 798 /* check quirks before creating card */
799 dmi_check_system(byt_rt5651_quirk_table);
46058aeb
HG		 800
801 /* Must be called before register_card, also see declaration comment. */
802 ret_val = byt_rt5651_add_codec_device_props(byt_rt5651_codec_name);
803 if (ret_val)
804 return ret_val;
805
02c0a3b3
PLB		 806 log_quirks(&pdev->dev);
807
8a880a20
HG		 808 if ((byt_rt5651_quirk & BYT_RT5651_SSP2_AIF2) ||
809 (byt_rt5651_quirk & BYT_RT5651_SSP0_AIF2)) {
810 /* fixup codec aif name */
811 snprintf(byt_rt5651_codec_aif_name,
812 sizeof(byt_rt5651_codec_aif_name),
813 "%s", "rt5651-aif2");
814
815 byt_rt5651_dais[dai_index].codec_dai_name =
816 byt_rt5651_codec_aif_name;
817 }
818
819 if ((byt_rt5651_quirk & BYT_RT5651_SSP0_AIF1) ||
820 (byt_rt5651_quirk & BYT_RT5651_SSP0_AIF2)) {
821 /* fixup cpu dai name name */
822 snprintf(byt_rt5651_cpu_dai_name,
823 sizeof(byt_rt5651_cpu_dai_name),
824 "%s", "ssp0-port");
825
826 byt_rt5651_dais[dai_index].cpu_dai_name =
827 byt_rt5651_cpu_dai_name;
828 }
829
02c0a3b3
PLB		 830 if (byt_rt5651_quirk & BYT_RT5651_MCLK_EN) {
831 priv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3");
832 if (IS_ERR(priv->mclk)) {
de5afce2 833 ret_val = PTR_ERR(priv->mclk);
02c0a3b3 834 dev_err(&pdev->dev,
de5afce2
CIK		 835 "Failed to get MCLK from pmc_plt_clk_3: %d\n",
836 ret_val);
02c0a3b3
PLB		 837 /*
838 * Fall back to bit clock usage for -ENOENT (clock not
839 * available likely due to missing dependencies), bail
840 * for all other errors, including -EPROBE_DEFER
841 */
842 if (ret_val != -ENOENT)
843 return ret_val;
844 byt_rt5651_quirk &= ~BYT_RT5651_MCLK_EN;
845 }
846 }
847
64484cce
HG		 848 snprintf(byt_rt5651_long_name, sizeof(byt_rt5651_long_name),
849 "bytcr-rt5651-%s-intmic-%s-hsmic",
850 intmic_name[BYT_RT5651_MAP(byt_rt5651_quirk)],
851 hsmic_name[BYT_RT5651_MAP(byt_rt5651_quirk)]);
852 byt_rt5651_card.long_name = byt_rt5651_long_name;
853
2bd5bd15
PLB		 854 ret_val = devm_snd_soc_register_card(&pdev->dev, &byt_rt5651_card);
855
856 if (ret_val) {
857 dev_err(&pdev->dev, "devm_snd_soc_register_card failed %d\n",
858 ret_val);
859 return ret_val;
860 }
861 platform_set_drvdata(pdev, &byt_rt5651_card);
862 return ret_val;
863}
864
865static struct platform_driver snd_byt_rt5651_mc_driver = {
866 .driver = {
867 .name = "bytcr_rt5651",
2bd5bd15
PLB		 868 },
869 .probe = snd_byt_rt5651_mc_probe,
870};
871
872module_platform_driver(snd_byt_rt5651_mc_driver);
873
874MODULE_DESCRIPTION("ASoC Intel(R) Baytrail CR Machine driver for RT5651");
875MODULE_AUTHOR("Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>");
876MODULE_LICENSE("GPL v2");
877MODULE_ALIAS("platform:bytcr_rt5651");
Linux 6.x block layer and io_uring tree(s)