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ASoC: rt5651: Add IN3 Boost volume control
[linux-2.6-block.git] / sound / soc / intel / boards / bytcr_rt5651.c
CommitLineData
2bd5bd15
PLB		 1/*
2 * bytcr_rt5651.c - ASoc Machine driver for Intel Byt CR platform
3 * (derived from bytcr_rt5640.c)
4 *
5 * Copyright (C) 2015 Intel Corp
6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
18 */
19
20#include <linux/init.h>
46058aeb 21#include <linux/i2c.h>
2bd5bd15
PLB		 22#include <linux/module.h>
23#include <linux/platform_device.h>
46058aeb 24#include <linux/property.h>
2bd5bd15 25#include <linux/acpi.h>
02c0a3b3 26#include <linux/clk.h>
2bd5bd15
PLB		 27#include <linux/device.h>
28#include <linux/dmi.h>
caed9d63 29#include <linux/input.h>
5f6fb23d
HG		 30#include <linux/gpio/consumer.h>
31#include <linux/gpio/machine.h>
2bd5bd15 32#include <linux/slab.h>
8a880a20 33#include <asm/cpu_device_id.h>
fbea16db 34#include <asm/intel-family.h>
02c0a3b3 35#include <asm/platform_sst_audio.h>
2bd5bd15
PLB		 36#include <sound/pcm.h>
37#include <sound/pcm_params.h>
38#include <sound/soc.h>
39#include <sound/jack.h>
7feb2f78 40#include <sound/soc-acpi.h>
2bd5bd15
PLB		 41#include "../../codecs/rt5651.h"
42#include "../atom/sst-atom-controls.h"
02c0a3b3
PLB		 43
44enum {
45 BYT_RT5651_DMIC_MAP,
46 BYT_RT5651_IN1_MAP,
ea261bd0 47 BYT_RT5651_IN1_IN2_MAP,
02c0a3b3
PLB		 48};
49
46058aeb
HG		 50enum {
51 BYT_RT5651_JD_NULL = (RT5651_JD_NULL << 4),
52 BYT_RT5651_JD1_1 = (RT5651_JD1_1 << 4),
53 BYT_RT5651_JD1_2 = (RT5651_JD1_2 << 4),
54 BYT_RT5651_JD2 = (RT5651_JD2 << 4),
55};
56
8ffaa6a1
HG		 57enum {
58 BYT_RT5651_OVCD_TH_600UA = (6 << 8),
59 BYT_RT5651_OVCD_TH_1500UA = (15 << 8),
60 BYT_RT5651_OVCD_TH_2000UA = (20 << 8),
61};
62
63enum {
64 BYT_RT5651_OVCD_SF_0P5 = (RT5651_OVCD_SF_0P5 << 13),
65 BYT_RT5651_OVCD_SF_0P75 = (RT5651_OVCD_SF_0P75 << 13),
66 BYT_RT5651_OVCD_SF_1P0 = (RT5651_OVCD_SF_1P0 << 13),
67 BYT_RT5651_OVCD_SF_1P5 = (RT5651_OVCD_SF_1P5 << 13),
68};
69
46058aeb
HG		 70#define BYT_RT5651_MAP(quirk) ((quirk) & GENMASK(3, 0))
71#define BYT_RT5651_JDSRC(quirk) (((quirk) & GENMASK(7, 4)) >> 4)
8ffaa6a1
HG		 72#define BYT_RT5651_OVCD_TH(quirk) (((quirk) & GENMASK(12, 8)) >> 8)
73#define BYT_RT5651_OVCD_SF(quirk) (((quirk) & GENMASK(14, 13)) >> 13)
46058aeb
HG		 74#define BYT_RT5651_DMIC_EN BIT(16)
75#define BYT_RT5651_MCLK_EN BIT(17)
76#define BYT_RT5651_MCLK_25MHZ BIT(18)
8a880a20
HG		 77#define BYT_RT5651_SSP2_AIF2 BIT(19) /* default is using AIF1 */
78#define BYT_RT5651_SSP0_AIF1 BIT(20)
79#define BYT_RT5651_SSP0_AIF2 BIT(21)
8f250e70 80#define BYT_RT5651_HP_LR_SWAPPED BIT(22)
46058aeb 81
fc7c460f
HG		 82#define BYT_RT5651_DEFAULT_QUIRKS (BYT_RT5651_MCLK_EN | \
83 BYT_RT5651_JD1_1 | \
84 BYT_RT5651_OVCD_TH_2000UA | \
85 BYT_RT5651_OVCD_SF_0P75)
86
8ffaa6a1
HG		 87/* jack-detect-source + dmic-en + ovcd-th + -sf + terminating empty entry */
88#define MAX_NO_PROPS 5
02c0a3b3
PLB		 89
90struct byt_rt5651_private {
91 struct clk *mclk;
5f6fb23d 92 struct gpio_desc *ext_amp_gpio;
d9f8f9b2 93 struct snd_soc_jack jack;
02c0a3b3
PLB		 94};
95
10876d24 96/* Default: jack-detect on JD1_1, internal mic on in1, headsetmic on in3 */
fc7c460f 97static unsigned long byt_rt5651_quirk = BYT_RT5651_DEFAULT_QUIRKS |
de231479 98 BYT_RT5651_IN1_MAP;
02c0a3b3
PLB		 99
100static void log_quirks(struct device *dev)
101{
102 if (BYT_RT5651_MAP(byt_rt5651_quirk) == BYT_RT5651_DMIC_MAP)
103 dev_info(dev, "quirk DMIC_MAP enabled");
104 if (BYT_RT5651_MAP(byt_rt5651_quirk) == BYT_RT5651_IN1_MAP)
105 dev_info(dev, "quirk IN1_MAP enabled");
366780df
HG		 106 if (BYT_RT5651_MAP(byt_rt5651_quirk) == BYT_RT5651_IN1_IN2_MAP)
107 dev_info(dev, "quirk IN1_IN2_MAP enabled");
8ffaa6a1 108 if (BYT_RT5651_JDSRC(byt_rt5651_quirk)) {
46058aeb
HG		 109 dev_info(dev, "quirk realtek,jack-detect-source %ld\n",
110 BYT_RT5651_JDSRC(byt_rt5651_quirk));
8ffaa6a1
HG		 111 dev_info(dev, "quirk realtek,over-current-threshold-microamp %ld\n",
112 BYT_RT5651_OVCD_TH(byt_rt5651_quirk) * 100);
113 dev_info(dev, "quirk realtek,over-current-scale-factor %ld\n",
114 BYT_RT5651_OVCD_SF(byt_rt5651_quirk));
115 }
02c0a3b3
PLB		 116 if (byt_rt5651_quirk & BYT_RT5651_DMIC_EN)
117 dev_info(dev, "quirk DMIC enabled");
118 if (byt_rt5651_quirk & BYT_RT5651_MCLK_EN)
119 dev_info(dev, "quirk MCLK_EN enabled");
120 if (byt_rt5651_quirk & BYT_RT5651_MCLK_25MHZ)
121 dev_info(dev, "quirk MCLK_25MHZ enabled");
8a880a20
HG		 122 if (byt_rt5651_quirk & BYT_RT5651_SSP2_AIF2)
123 dev_info(dev, "quirk SSP2_AIF2 enabled\n");
124 if (byt_rt5651_quirk & BYT_RT5651_SSP0_AIF1)
125 dev_info(dev, "quirk SSP0_AIF1 enabled\n");
126 if (byt_rt5651_quirk & BYT_RT5651_SSP0_AIF2)
127 dev_info(dev, "quirk SSP0_AIF2 enabled\n");
02c0a3b3
PLB		 128}
129
130#define BYT_CODEC_DAI1 "rt5651-aif1"
8a880a20 131#define BYT_CODEC_DAI2 "rt5651-aif2"
02c0a3b3 132
aeec6cc0
HG		 133static int byt_rt5651_prepare_and_enable_pll1(struct snd_soc_dai *codec_dai,
134 int rate, int bclk_ratio)
135{
136 int clk_id, clk_freq, ret;
137
138 /* Configure the PLL before selecting it */
139 if (!(byt_rt5651_quirk & BYT_RT5651_MCLK_EN)) {
140 clk_id = RT5651_PLL1_S_BCLK1,
141 clk_freq = rate * bclk_ratio;
142 } else {
143 clk_id = RT5651_PLL1_S_MCLK;
144 if (byt_rt5651_quirk & BYT_RT5651_MCLK_25MHZ)
145 clk_freq = 25000000;
146 else
147 clk_freq = 19200000;
148 }
149 ret = snd_soc_dai_set_pll(codec_dai, 0, clk_id, clk_freq, rate * 512);
150 if (ret < 0) {
2759ba9b 151 dev_err(codec_dai->component->dev, "can't set pll: %d\n", ret);
aeec6cc0
HG		 152 return ret;
153 }
154
155 ret = snd_soc_dai_set_sysclk(codec_dai, RT5651_SCLK_S_PLL1,
156 rate * 512, SND_SOC_CLOCK_IN);
157 if (ret < 0) {
2759ba9b 158 dev_err(codec_dai->component->dev, "can't set clock %d\n", ret);
aeec6cc0
HG		 159 return ret;
160 }
161
162 return 0;
163}
164
02c0a3b3
PLB		 165static int platform_clock_control(struct snd_soc_dapm_widget *w,
166 struct snd_kcontrol *k, int event)
167{
168 struct snd_soc_dapm_context *dapm = w->dapm;
169 struct snd_soc_card *card = dapm->card;
170 struct snd_soc_dai *codec_dai;
171 struct byt_rt5651_private *priv = snd_soc_card_get_drvdata(card);
172 int ret;
173
dfb6ec7a 174 codec_dai = snd_soc_card_get_codec_dai(card, BYT_CODEC_DAI1);
8a880a20
HG		 175 if (!codec_dai)
176 codec_dai = snd_soc_card_get_codec_dai(card, BYT_CODEC_DAI2);
02c0a3b3
PLB		 177 if (!codec_dai) {
178 dev_err(card->dev,
179 "Codec dai not found; Unable to set platform clock\n");
180 return -EIO;
181 }
182
183 if (SND_SOC_DAPM_EVENT_ON(event)) {
184 if (byt_rt5651_quirk & BYT_RT5651_MCLK_EN) {
185 ret = clk_prepare_enable(priv->mclk);
186 if (ret < 0) {
187 dev_err(card->dev,
188 "could not configure MCLK state");
189 return ret;
190 }
191 }
aeec6cc0 192 ret = byt_rt5651_prepare_and_enable_pll1(codec_dai, 48000, 50);
02c0a3b3
PLB		 193 } else {
194 /*
195 * Set codec clock source to internal clock before
196 * turning off the platform clock. Codec needs clock
197 * for Jack detection and button press
198 */
199 ret = snd_soc_dai_set_sysclk(codec_dai, RT5651_SCLK_S_RCCLK,
200 48000 * 512,
201 SND_SOC_CLOCK_IN);
202 if (!ret)
203 if (byt_rt5651_quirk & BYT_RT5651_MCLK_EN)
204 clk_disable_unprepare(priv->mclk);
205 }
206
207 if (ret < 0) {
208 dev_err(card->dev, "can't set codec sysclk: %d\n", ret);
209 return ret;
210 }
211
212 return 0;
213}
2bd5bd15 214
5f6fb23d
HG		 215static int rt5651_ext_amp_power_event(struct snd_soc_dapm_widget *w,
216 struct snd_kcontrol *kcontrol, int event)
217{
218 struct snd_soc_card *card = w->dapm->card;
219 struct byt_rt5651_private *priv = snd_soc_card_get_drvdata(card);
220
221 if (SND_SOC_DAPM_EVENT_ON(event))
222 gpiod_set_value_cansleep(priv->ext_amp_gpio, 1);
223 else
224 gpiod_set_value_cansleep(priv->ext_amp_gpio, 0);
225
226 return 0;
227}
228
2bd5bd15
PLB		 229static const struct snd_soc_dapm_widget byt_rt5651_widgets[] = {
230 SND_SOC_DAPM_HP("Headphone", NULL),
231 SND_SOC_DAPM_MIC("Headset Mic", NULL),
232 SND_SOC_DAPM_MIC("Internal Mic", NULL),
233 SND_SOC_DAPM_SPK("Speaker", NULL),
ea39bdcf 234 SND_SOC_DAPM_LINE("Line In", NULL),
02c0a3b3
PLB		 235 SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
236 platform_clock_control, SND_SOC_DAPM_PRE_PMU |
237 SND_SOC_DAPM_POST_PMD),
5f6fb23d
HG		 238 SND_SOC_DAPM_SUPPLY("Ext Amp Power", SND_SOC_NOPM, 0, 0,
239 rt5651_ext_amp_power_event,
240 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2bd5bd15
PLB		 241};
242
243static const struct snd_soc_dapm_route byt_rt5651_audio_map[] = {
02c0a3b3
PLB		 244 {"Headphone", NULL, "Platform Clock"},
245 {"Headset Mic", NULL, "Platform Clock"},
246 {"Internal Mic", NULL, "Platform Clock"},
247 {"Speaker", NULL, "Platform Clock"},
5f6fb23d 248 {"Speaker", NULL, "Ext Amp Power"},
ea39bdcf 249 {"Line In", NULL, "Platform Clock"},
02c0a3b3 250
2bd5bd15 251 {"Headset Mic", NULL, "micbias1"}, /* lowercase for rt5651 */
2bd5bd15
PLB		 252 {"Headphone", NULL, "HPOL"},
253 {"Headphone", NULL, "HPOR"},
254 {"Speaker", NULL, "LOUTL"},
255 {"Speaker", NULL, "LOUTR"},
ea39bdcf
PLB		 256 {"IN2P", NULL, "Line In"},
257 {"IN2N", NULL, "Line In"},
258
2bd5bd15
PLB		 259};
260
6356c78c
PLB		 261static const struct snd_soc_dapm_route byt_rt5651_intmic_dmic_map[] = {
262 {"DMIC L1", NULL, "Internal Mic"},
263 {"DMIC R1", NULL, "Internal Mic"},
37c7401e 264 {"IN3P", NULL, "Headset Mic"},
2bd5bd15
PLB		 265};
266
267static const struct snd_soc_dapm_route byt_rt5651_intmic_in1_map[] = {
268 {"Internal Mic", NULL, "micbias1"},
269 {"IN1P", NULL, "Internal Mic"},
de231479 270 {"IN3P", NULL, "Headset Mic"},
2bd5bd15
PLB		 271};
272
ea261bd0
CC		 273static const struct snd_soc_dapm_route byt_rt5651_intmic_in1_in2_map[] = {
274 {"Internal Mic", NULL, "micbias1"},
275 {"IN1P", NULL, "Internal Mic"},
276 {"IN2P", NULL, "Internal Mic"},
277 {"IN3P", NULL, "Headset Mic"},
278};
279
8a880a20
HG		 280static const struct snd_soc_dapm_route byt_rt5651_ssp0_aif1_map[] = {
281 {"ssp0 Tx", NULL, "modem_out"},
282 {"modem_in", NULL, "ssp0 Rx"},
283
284 {"AIF1 Playback", NULL, "ssp0 Tx"},
285 {"ssp0 Rx", NULL, "AIF1 Capture"},
286};
287
288static const struct snd_soc_dapm_route byt_rt5651_ssp0_aif2_map[] = {
289 {"ssp0 Tx", NULL, "modem_out"},
290 {"modem_in", NULL, "ssp0 Rx"},
291
292 {"AIF2 Playback", NULL, "ssp0 Tx"},
293 {"ssp0 Rx", NULL, "AIF2 Capture"},
294};
295
296static const struct snd_soc_dapm_route byt_rt5651_ssp2_aif1_map[] = {
297 {"ssp2 Tx", NULL, "codec_out0"},
298 {"ssp2 Tx", NULL, "codec_out1"},
299 {"codec_in0", NULL, "ssp2 Rx"},
300 {"codec_in1", NULL, "ssp2 Rx"},
301
302 {"AIF1 Playback", NULL, "ssp2 Tx"},
303 {"ssp2 Rx", NULL, "AIF1 Capture"},
304};
305
306static const struct snd_soc_dapm_route byt_rt5651_ssp2_aif2_map[] = {
307 {"ssp2 Tx", NULL, "codec_out0"},
308 {"ssp2 Tx", NULL, "codec_out1"},
309 {"codec_in0", NULL, "ssp2 Rx"},
310 {"codec_in1", NULL, "ssp2 Rx"},
311
312 {"AIF2 Playback", NULL, "ssp2 Tx"},
313 {"ssp2 Rx", NULL, "AIF2 Capture"},
314};
315
2bd5bd15
PLB		 316static const struct snd_kcontrol_new byt_rt5651_controls[] = {
317 SOC_DAPM_PIN_SWITCH("Headphone"),
318 SOC_DAPM_PIN_SWITCH("Headset Mic"),
319 SOC_DAPM_PIN_SWITCH("Internal Mic"),
320 SOC_DAPM_PIN_SWITCH("Speaker"),
ea39bdcf 321 SOC_DAPM_PIN_SWITCH("Line In"),
2bd5bd15
PLB		 322};
323
d9f8f9b2
CC		 324static struct snd_soc_jack_pin bytcr_jack_pins[] = {
325 {
326 .pin = "Headphone",
327 .mask = SND_JACK_HEADPHONE,
328 },
329 {
330 .pin = "Headset Mic",
331 .mask = SND_JACK_MICROPHONE,
332 },
333};
334
2bd5bd15
PLB		 335static int byt_rt5651_aif1_hw_params(struct snd_pcm_substream *substream,
336 struct snd_pcm_hw_params *params)
337{
338 struct snd_soc_pcm_runtime *rtd = substream->private_data;
339 struct snd_soc_dai *codec_dai = rtd->codec_dai;
8a880a20 340 snd_pcm_format_t format = params_format(params);
aeec6cc0 341 int rate = params_rate(params);
8a880a20 342 int bclk_ratio;
2bd5bd15 343
8a880a20
HG		 344 if (format == SNDRV_PCM_FORMAT_S16_LE)
345 bclk_ratio = 32;
346 else
347 bclk_ratio = 50;
348
349 return byt_rt5651_prepare_and_enable_pll1(codec_dai, rate, bclk_ratio);
2bd5bd15
PLB		 350}
351
02c0a3b3
PLB		 352static int byt_rt5651_quirk_cb(const struct dmi_system_id *id)
353{
354 byt_rt5651_quirk = (unsigned long)id->driver_data;
355 return 1;
356}
357
2bd5bd15 358static const struct dmi_system_id byt_rt5651_quirk_table[] = {
02c0a3b3 359 {
55d69c03 360 /* Chuwi Hi8 Pro (CWI513) */
02c0a3b3
PLB		 361 .callback = byt_rt5651_quirk_cb,
362 .matches = {
55d69c03
HG		 363 DMI_MATCH(DMI_SYS_VENDOR, "Hampoo"),
364 DMI_MATCH(DMI_PRODUCT_NAME, "X1D3_C806N"),
02c0a3b3 365 },
55d69c03
HG		 366 .driver_data = (void *)(BYT_RT5651_DEFAULT_QUIRKS |
367 BYT_RT5651_IN1_MAP |
368 BYT_RT5651_HP_LR_SWAPPED),
02c0a3b3 369 },
416f2b51 370 {
55d69c03 371 /* Chuwi Vi8 Plus (CWI519) */
416f2b51
PLB		 372 .callback = byt_rt5651_quirk_cb,
373 .matches = {
55d69c03
HG		 374 DMI_MATCH(DMI_SYS_VENDOR, "Hampoo"),
375 DMI_MATCH(DMI_PRODUCT_NAME, "D2D3_Vi8A1"),
416f2b51 376 },
55d69c03
HG		 377 .driver_data = (void *)(BYT_RT5651_DEFAULT_QUIRKS |
378 BYT_RT5651_IN1_MAP |
379 BYT_RT5651_HP_LR_SWAPPED),
416f2b51 380 },
2fe30129 381 {
55d69c03 382 /* KIANO SlimNote 14.2 */
2fe30129
CC		 383 .callback = byt_rt5651_quirk_cb,
384 .matches = {
385 DMI_MATCH(DMI_SYS_VENDOR, "KIANO"),
386 DMI_MATCH(DMI_PRODUCT_NAME, "KIANO SlimNote 14.2"),
387 },
fc7c460f 388 .driver_data = (void *)(BYT_RT5651_DEFAULT_QUIRKS |
56e49aa4 389 BYT_RT5651_IN1_IN2_MAP),
2fe30129 390 },
8f250e70 391 {
55d69c03 392 /* Minnowboard Max B3 */
8f250e70
HG		 393 .callback = byt_rt5651_quirk_cb,
394 .matches = {
55d69c03
HG		 395 DMI_MATCH(DMI_SYS_VENDOR, "Circuitco"),
396 DMI_MATCH(DMI_PRODUCT_NAME, "Minnowboard Max B3 PLATFORM"),
8f250e70 397 },
55d69c03 398 .driver_data = (void *)(BYT_RT5651_IN1_MAP),
8f250e70 399 },
f026e063 400 {
55d69c03 401 /* Minnowboard Turbot */
f026e063
HG		 402 .callback = byt_rt5651_quirk_cb,
403 .matches = {
55d69c03
HG		 404 DMI_MATCH(DMI_SYS_VENDOR, "ADI"),
405 DMI_MATCH(DMI_PRODUCT_NAME, "Minnowboard Turbot"),
f026e063 406 },
55d69c03
HG		 407 .driver_data = (void *)(BYT_RT5651_MCLK_EN |
408 BYT_RT5651_IN1_MAP),
f026e063 409 },
f9877eb5
HG		 410 {
411 /* VIOS LTH17 */
412 .callback = byt_rt5651_quirk_cb,
413 .matches = {
414 DMI_MATCH(DMI_SYS_VENDOR, "VIOS"),
415 DMI_MATCH(DMI_PRODUCT_NAME, "LTH17"),
416 },
fc7c460f 417 .driver_data = (void *)(BYT_RT5651_DEFAULT_QUIRKS |
f9877eb5
HG		 418 BYT_RT5651_IN1_IN2_MAP),
419 },
2bd5bd15
PLB		 420 {}
421};
422
46058aeb
HG		 423/*
424 * Note this MUST be called before snd_soc_register_card(), so that the props
425 * are in place before the codec component driver's probe function parses them.
426 */
2c375204 427static int byt_rt5651_add_codec_device_props(struct device *i2c_dev)
46058aeb
HG		 428{
429 struct property_entry props[MAX_NO_PROPS] = {};
2c375204 430 int cnt = 0;
46058aeb
HG		 431
432 props[cnt++] = PROPERTY_ENTRY_U32("realtek,jack-detect-source",
433 BYT_RT5651_JDSRC(byt_rt5651_quirk));
434
8ffaa6a1
HG		 435 props[cnt++] = PROPERTY_ENTRY_U32("realtek,over-current-threshold-microamp",
436 BYT_RT5651_OVCD_TH(byt_rt5651_quirk) * 100);
437
438 props[cnt++] = PROPERTY_ENTRY_U32("realtek,over-current-scale-factor",
439 BYT_RT5651_OVCD_SF(byt_rt5651_quirk));
440
c2f26938
HG		 441 if (byt_rt5651_quirk & BYT_RT5651_DMIC_EN)
442 props[cnt++] = PROPERTY_ENTRY_BOOL("realtek,dmic-en");
443
2c375204 444 return device_add_properties(i2c_dev, props);
46058aeb
HG		 445}
446
2bd5bd15
PLB		 447static int byt_rt5651_init(struct snd_soc_pcm_runtime *runtime)
448{
2bd5bd15 449 struct snd_soc_card *card = runtime->card;
17b52010 450 struct snd_soc_component *codec = runtime->codec_dai->component;
02c0a3b3 451 struct byt_rt5651_private *priv = snd_soc_card_get_drvdata(card);
2bd5bd15
PLB		 452 const struct snd_soc_dapm_route *custom_map;
453 int num_routes;
02c0a3b3 454 int ret;
2bd5bd15
PLB		 455
456 card->dapm.idle_bias_off = true;
457
c22969d7
HG		 458 /* Start with RC clk for jack-detect (we disable MCLK below) */
459 if (byt_rt5651_quirk & BYT_RT5651_MCLK_EN)
460 snd_soc_component_update_bits(codec, RT5651_GLB_CLK,
461 RT5651_SCLK_SRC_MASK, RT5651_SCLK_SRC_RCCLK);
462
2bd5bd15
PLB		 463 switch (BYT_RT5651_MAP(byt_rt5651_quirk)) {
464 case BYT_RT5651_IN1_MAP:
465 custom_map = byt_rt5651_intmic_in1_map;
466 num_routes = ARRAY_SIZE(byt_rt5651_intmic_in1_map);
467 break;
ea261bd0
CC		 468 case BYT_RT5651_IN1_IN2_MAP:
469 custom_map = byt_rt5651_intmic_in1_in2_map;
470 num_routes = ARRAY_SIZE(byt_rt5651_intmic_in1_in2_map);
471 break;
2bd5bd15 472 default:
6356c78c
PLB		 473 custom_map = byt_rt5651_intmic_dmic_map;
474 num_routes = ARRAY_SIZE(byt_rt5651_intmic_dmic_map);
2bd5bd15 475 }
6356c78c
PLB		 476 ret = snd_soc_dapm_add_routes(&card->dapm, custom_map, num_routes);
477 if (ret)
478 return ret;
2bd5bd15 479
8a880a20
HG		 480 if (byt_rt5651_quirk & BYT_RT5651_SSP2_AIF2) {
481 ret = snd_soc_dapm_add_routes(&card->dapm,
482 byt_rt5651_ssp2_aif2_map,
483 ARRAY_SIZE(byt_rt5651_ssp2_aif2_map));
484 } else if (byt_rt5651_quirk & BYT_RT5651_SSP0_AIF1) {
485 ret = snd_soc_dapm_add_routes(&card->dapm,
486 byt_rt5651_ssp0_aif1_map,
487 ARRAY_SIZE(byt_rt5651_ssp0_aif1_map));
488 } else if (byt_rt5651_quirk & BYT_RT5651_SSP0_AIF2) {
489 ret = snd_soc_dapm_add_routes(&card->dapm,
490 byt_rt5651_ssp0_aif2_map,
491 ARRAY_SIZE(byt_rt5651_ssp0_aif2_map));
492 } else {
493 ret = snd_soc_dapm_add_routes(&card->dapm,
494 byt_rt5651_ssp2_aif1_map,
495 ARRAY_SIZE(byt_rt5651_ssp2_aif1_map));
496 }
497 if (ret)
498 return ret;
499
2bd5bd15
PLB		 500 ret = snd_soc_add_card_controls(card, byt_rt5651_controls,
501 ARRAY_SIZE(byt_rt5651_controls));
502 if (ret) {
503 dev_err(card->dev, "unable to add card controls\n");
504 return ret;
505 }
506 snd_soc_dapm_ignore_suspend(&card->dapm, "Headphone");
507 snd_soc_dapm_ignore_suspend(&card->dapm, "Speaker");
508
02c0a3b3
PLB		 509 if (byt_rt5651_quirk & BYT_RT5651_MCLK_EN) {
510 /*
511 * The firmware might enable the clock at
512 * boot (this information may or may not
513 * be reflected in the enable clock register).
514 * To change the rate we must disable the clock
515 * first to cover these cases. Due to common
516 * clock framework restrictions that do not allow
517 * to disable a clock that has not been enabled,
518 * we need to enable the clock first.
519 */
520 ret = clk_prepare_enable(priv->mclk);
521 if (!ret)
522 clk_disable_unprepare(priv->mclk);
523
524 if (byt_rt5651_quirk & BYT_RT5651_MCLK_25MHZ)
525 ret = clk_set_rate(priv->mclk, 25000000);
526 else
527 ret = clk_set_rate(priv->mclk, 19200000);
528
529 if (ret)
530 dev_err(card->dev, "unable to set MCLK rate\n");
531 }
532
aed859a2
HG		 533 if (BYT_RT5651_JDSRC(byt_rt5651_quirk)) {
534 ret = snd_soc_card_jack_new(runtime->card, "Headset",
caed9d63
HG		 535 SND_JACK_HEADSET | SND_JACK_BTN_0,
536 &priv->jack, bytcr_jack_pins,
537 ARRAY_SIZE(bytcr_jack_pins));
aed859a2
HG		 538 if (ret) {
539 dev_err(runtime->dev, "jack creation failed %d\n", ret);
540 return ret;
541 }
d9f8f9b2 542
caed9d63
HG		 543 snd_jack_set_key(priv->jack.jack, SND_JACK_BTN_0,
544 KEY_PLAYPAUSE);
545
aed859a2
HG		 546 ret = snd_soc_component_set_jack(codec, &priv->jack, NULL);
547 if (ret)
548 return ret;
549 }
d9f8f9b2 550
aed859a2 551 return 0;
2bd5bd15
PLB		 552}
553
554static const struct snd_soc_pcm_stream byt_rt5651_dai_params = {
555 .formats = SNDRV_PCM_FMTBIT_S24_LE,
556 .rate_min = 48000,
557 .rate_max = 48000,
558 .channels_min = 2,
559 .channels_max = 2,
560};
561
562static int byt_rt5651_codec_fixup(struct snd_soc_pcm_runtime *rtd,
563 struct snd_pcm_hw_params *params)
564{
565 struct snd_interval *rate = hw_param_interval(params,
566 SNDRV_PCM_HW_PARAM_RATE);
567 struct snd_interval *channels = hw_param_interval(params,
568 SNDRV_PCM_HW_PARAM_CHANNELS);
8a880a20 569 int ret, bits;
2bd5bd15 570
8a880a20 571 /* The DSP will covert the FE rate to 48k, stereo */
2bd5bd15
PLB		 572 rate->min = rate->max = 48000;
573 channels->min = channels->max = 2;
574
8a880a20
HG		 575 if ((byt_rt5651_quirk & BYT_RT5651_SSP0_AIF1) ||
576 (byt_rt5651_quirk & BYT_RT5651_SSP0_AIF2)) {
577 /* set SSP0 to 16-bit */
578 params_set_format(params, SNDRV_PCM_FORMAT_S16_LE);
579 bits = 16;
580 } else {
581 /* set SSP2 to 24-bit */
582 params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
583 bits = 24;
584 }
2bd5bd15
PLB		 585
586 /*
587 * Default mode for SSP configuration is TDM 4 slot, override config
8a880a20 588 * with explicit setting to I2S 2ch. The word length is set with
2bd5bd15
PLB		 589 * dai_set_tdm_slot() since there is no other API exposed
590 */
591 ret = snd_soc_dai_set_fmt(rtd->cpu_dai,
592 SND_SOC_DAIFMT_I2S |
f12f5c84 593 SND_SOC_DAIFMT_NB_NF |
2bd5bd15
PLB		 594 SND_SOC_DAIFMT_CBS_CFS
595 );
596
597 if (ret < 0) {
598 dev_err(rtd->dev, "can't set format to I2S, err %d\n", ret);
599 return ret;
600 }
601
8a880a20 602 ret = snd_soc_dai_set_tdm_slot(rtd->cpu_dai, 0x3, 0x3, 2, bits);
2bd5bd15
PLB		 603 if (ret < 0) {
604 dev_err(rtd->dev, "can't set I2S config, err %d\n", ret);
605 return ret;
606 }
607
608 return 0;
609}
610
1ebb4d9d 611static const unsigned int rates_48000[] = {
2bd5bd15
PLB		 612 48000,
613};
614
1ebb4d9d 615static const struct snd_pcm_hw_constraint_list constraints_48000 = {
2bd5bd15
PLB		 616 .count = ARRAY_SIZE(rates_48000),
617 .list = rates_48000,
618};
619
620static int byt_rt5651_aif1_startup(struct snd_pcm_substream *substream)
621{
622 return snd_pcm_hw_constraint_list(substream->runtime, 0,
623 SNDRV_PCM_HW_PARAM_RATE,
624 &constraints_48000);
625}
626
9b6fdef6 627static const struct snd_soc_ops byt_rt5651_aif1_ops = {
2bd5bd15
PLB		 628 .startup = byt_rt5651_aif1_startup,
629};
630
9b6fdef6 631static const struct snd_soc_ops byt_rt5651_be_ssp2_ops = {
2bd5bd15
PLB		 632 .hw_params = byt_rt5651_aif1_hw_params,
633};
634
635static struct snd_soc_dai_link byt_rt5651_dais[] = {
636 [MERR_DPCM_AUDIO] = {
637 .name = "Audio Port",
638 .stream_name = "Audio",
639 .cpu_dai_name = "media-cpu-dai",
640 .codec_dai_name = "snd-soc-dummy-dai",
641 .codec_name = "snd-soc-dummy",
642 .platform_name = "sst-mfld-platform",
2bd5bd15
PLB		 643 .nonatomic = true,
644 .dynamic = 1,
645 .dpcm_playback = 1,
646 .dpcm_capture = 1,
647 .ops = &byt_rt5651_aif1_ops,
648 },
649 [MERR_DPCM_DEEP_BUFFER] = {
650 .name = "Deep-Buffer Audio Port",
651 .stream_name = "Deep-Buffer Audio",
652 .cpu_dai_name = "deepbuffer-cpu-dai",
653 .codec_dai_name = "snd-soc-dummy-dai",
654 .codec_name = "snd-soc-dummy",
655 .platform_name = "sst-mfld-platform",
2bd5bd15
PLB		 656 .nonatomic = true,
657 .dynamic = 1,
658 .dpcm_playback = 1,
659 .ops = &byt_rt5651_aif1_ops,
660 },
2bd5bd15
PLB		 661 /* CODEC<->CODEC link */
662 /* back ends */
663 {
664 .name = "SSP2-Codec",
149f7757 665 .id = 0,
2bd5bd15
PLB		 666 .cpu_dai_name = "ssp2-port",
667 .platform_name = "sst-mfld-platform",
668 .no_pcm = 1,
669 .codec_dai_name = "rt5651-aif1",
670 .codec_name = "i2c-10EC5651:00",
671 .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
672 | SND_SOC_DAIFMT_CBS_CFS,
673 .be_hw_params_fixup = byt_rt5651_codec_fixup,
674 .ignore_suspend = 1,
675 .nonatomic = true,
676 .dpcm_playback = 1,
677 .dpcm_capture = 1,
678 .init = byt_rt5651_init,
679 .ops = &byt_rt5651_be_ssp2_ops,
680 },
681};
682
683/* SoC card */
b91f432c
HG		 684static char byt_rt5651_codec_name[SND_ACPI_I2C_ID_LEN];
685static char byt_rt5651_codec_aif_name[12]; /* = "rt5651-aif[1|2]" */
686static char byt_rt5651_cpu_dai_name[10]; /* = "ssp[0|2]-port" */
687static char byt_rt5651_long_name[40]; /* = "bytcr-rt5651-*-mic[-swapped-hp]" */
688
689static int byt_rt5651_suspend(struct snd_soc_card *card)
690{
691 struct snd_soc_component *component;
692
693 if (!BYT_RT5651_JDSRC(byt_rt5651_quirk))
694 return 0;
695
696 list_for_each_entry(component, &card->component_dev_list, card_list) {
697 if (!strcmp(component->name, byt_rt5651_codec_name)) {
698 dev_dbg(component->dev, "disabling jack detect before suspend\n");
699 snd_soc_component_set_jack(component, NULL, NULL);
700 break;
701 }
702 }
703
704 return 0;
705}
706
707static int byt_rt5651_resume(struct snd_soc_card *card)
708{
709 struct byt_rt5651_private *priv = snd_soc_card_get_drvdata(card);
710 struct snd_soc_component *component;
711
712 if (!BYT_RT5651_JDSRC(byt_rt5651_quirk))
713 return 0;
714
715 list_for_each_entry(component, &card->component_dev_list, card_list) {
716 if (!strcmp(component->name, byt_rt5651_codec_name)) {
717 dev_dbg(component->dev, "re-enabling jack detect after resume\n");
718 snd_soc_component_set_jack(component, &priv->jack, NULL);
719 break;
720 }
721 }
722
723 return 0;
724}
725
2bd5bd15
PLB		 726static struct snd_soc_card byt_rt5651_card = {
727 .name = "bytcr-rt5651",
728 .owner = THIS_MODULE,
729 .dai_link = byt_rt5651_dais,
730 .num_links = ARRAY_SIZE(byt_rt5651_dais),
731 .dapm_widgets = byt_rt5651_widgets,
732 .num_dapm_widgets = ARRAY_SIZE(byt_rt5651_widgets),
733 .dapm_routes = byt_rt5651_audio_map,
734 .num_dapm_routes = ARRAY_SIZE(byt_rt5651_audio_map),
735 .fully_routed = true,
b91f432c
HG		 736 .suspend_pre = byt_rt5651_suspend,
737 .resume_post = byt_rt5651_resume,
2bd5bd15
PLB		 738};
739
fbea16db
HG		 740static const struct x86_cpu_id baytrail_cpu_ids[] = {
741 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 }, /* Valleyview */
742 {}
743};
8a880a20 744
5f6fb23d
HG		 745static const struct x86_cpu_id cherrytrail_cpu_ids[] = {
746 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT }, /* Braswell */
747 {}
748};
749
750static const struct acpi_gpio_params ext_amp_enable_gpios = { 0, 0, false };
751
752static const struct acpi_gpio_mapping byt_rt5651_gpios[] = {
753 { "ext-amp-enable-gpios", &ext_amp_enable_gpios, 1 },
754 { },
755};
756
8a880a20
HG		 757struct acpi_chan_package { /* ACPICA seems to require 64 bit integers */
758 u64 aif_value; /* 1: AIF1, 2: AIF2 */
759 u64 mclock_value; /* usually 25MHz (0x17d7940), ignored */
760};
02c0a3b3 761
2bd5bd15
PLB		 762static int snd_byt_rt5651_mc_probe(struct platform_device *pdev)
763{
8e69cd64 764 const char * const mic_name[] = { "dmic", "in1", "in12" };
02c0a3b3 765 struct byt_rt5651_private *priv;
7feb2f78 766 struct snd_soc_acpi_mach *mach;
2c375204 767 struct device *codec_dev;
02c0a3b3 768 const char *i2c_name = NULL;
8f250e70 769 const char *hp_swapped;
8a880a20 770 bool is_bytcr = false;
2bd5bd15 771 int ret_val = 0;
2193eb96 772 int dai_index = 0;
02c0a3b3
PLB		 773 int i;
774
aa5398e1 775 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
02c0a3b3
PLB		 776 if (!priv)
777 return -ENOMEM;
2bd5bd15
PLB		 778
779 /* register the soc card */
780 byt_rt5651_card.dev = &pdev->dev;
781
02c0a3b3
PLB		 782 mach = byt_rt5651_card.dev->platform_data;
783 snd_soc_card_set_drvdata(&byt_rt5651_card, priv);
784
785 /* fix index of codec dai */
02c0a3b3
PLB		 786 for (i = 0; i < ARRAY_SIZE(byt_rt5651_dais); i++) {
787 if (!strcmp(byt_rt5651_dais[i].codec_name, "i2c-10EC5651:00")) {
788 dai_index = i;
789 break;
790 }
791 }
792
793 /* fixup codec name based on HID */
3a147959 794 i2c_name = acpi_dev_get_first_match_name(mach->id, NULL, -1);
e39cacc1
HG		 795 if (!i2c_name) {
796 dev_err(&pdev->dev, "Error cannot find '%s' dev\n", mach->id);
797 return -ENODEV;
02c0a3b3 798 }
e39cacc1
HG		 799 snprintf(byt_rt5651_codec_name, sizeof(byt_rt5651_codec_name),
800 "%s%s", "i2c-", i2c_name);
801 byt_rt5651_dais[dai_index].codec_name = byt_rt5651_codec_name;
02c0a3b3 802
2c375204
HG		 803 codec_dev = bus_find_device_by_name(&i2c_bus_type, NULL,
804 byt_rt5651_codec_name);
805 if (!codec_dev)
806 return -EPROBE_DEFER;
807
8a880a20
HG		 808 /*
809 * swap SSP0 if bytcr is detected
810 * (will be overridden if DMI quirk is detected)
811 */
fbea16db 812 if (x86_match_cpu(baytrail_cpu_ids)) {
8a880a20
HG		 813 struct sst_platform_info *p_info = mach->pdata;
814 const struct sst_res_info *res_info = p_info->res_info;
815
816 if (res_info->acpi_ipc_irq_index == 0)
817 is_bytcr = true;
818 }
819
820 if (is_bytcr) {
821 /*
822 * Baytrail CR platforms may have CHAN package in BIOS, try
823 * to find relevant routing quirk based as done on Windows
824 * platforms. We have to read the information directly from the
825 * BIOS, at this stage the card is not created and the links
826 * with the codec driver/pdata are non-existent
827 */
828
829 struct acpi_chan_package chan_package;
830
831 /* format specified: 2 64-bit integers */
832 struct acpi_buffer format = {sizeof("NN"), "NN"};
833 struct acpi_buffer state = {0, NULL};
834 struct snd_soc_acpi_package_context pkg_ctx;
835 bool pkg_found = false;
836
837 state.length = sizeof(chan_package);
838 state.pointer = &chan_package;
839
840 pkg_ctx.name = "CHAN";
841 pkg_ctx.length = 2;
842 pkg_ctx.format = &format;
843 pkg_ctx.state = &state;
844 pkg_ctx.data_valid = false;
845
846 pkg_found = snd_soc_acpi_find_package_from_hid(mach->id,
847 &pkg_ctx);
848 if (pkg_found) {
849 if (chan_package.aif_value == 1) {
850 dev_info(&pdev->dev, "BIOS Routing: AIF1 connected\n");
851 byt_rt5651_quirk |= BYT_RT5651_SSP0_AIF1;
852 } else if (chan_package.aif_value == 2) {
853 dev_info(&pdev->dev, "BIOS Routing: AIF2 connected\n");
854 byt_rt5651_quirk |= BYT_RT5651_SSP0_AIF2;
855 } else {
856 dev_info(&pdev->dev, "BIOS Routing isn't valid, ignored\n");
857 pkg_found = false;
858 }
859 }
860
861 if (!pkg_found) {
862 /* no BIOS indications, assume SSP0-AIF2 connection */
863 byt_rt5651_quirk |= BYT_RT5651_SSP0_AIF2;
864 }
8a880a20
HG		 865 }
866
02c0a3b3
PLB		 867 /* check quirks before creating card */
868 dmi_check_system(byt_rt5651_quirk_table);
46058aeb
HG		 869
870 /* Must be called before register_card, also see declaration comment. */
2c375204 871 ret_val = byt_rt5651_add_codec_device_props(codec_dev);
5f6fb23d
HG		 872 if (ret_val) {
873 put_device(codec_dev);
46058aeb 874 return ret_val;
5f6fb23d
HG		 875 }
876
877 /* Cherry Trail devices use an external amplifier enable gpio */
878 if (x86_match_cpu(cherrytrail_cpu_ids)) {
879 devm_acpi_dev_add_driver_gpios(codec_dev, byt_rt5651_gpios);
880 priv->ext_amp_gpio = devm_fwnode_get_index_gpiod_from_child(
881 &pdev->dev, "ext-amp-enable", 0,
882 codec_dev->fwnode,
883 GPIOD_OUT_LOW, "speaker-amp");
884 if (IS_ERR(priv->ext_amp_gpio)) {
885 ret_val = PTR_ERR(priv->ext_amp_gpio);
886 switch (ret_val) {
887 case -ENOENT:
888 priv->ext_amp_gpio = NULL;
889 break;
890 default:
891 dev_err(&pdev->dev, "Failed to get ext-amp-enable GPIO: %d\n",
892 ret_val);
893 /* fall through */
894 case -EPROBE_DEFER:
895 put_device(codec_dev);
896 return ret_val;
897 }
898 }
899 }
900
901 put_device(codec_dev);
46058aeb 902
02c0a3b3
PLB		 903 log_quirks(&pdev->dev);
904
8a880a20
HG		 905 if ((byt_rt5651_quirk & BYT_RT5651_SSP2_AIF2) ||
906 (byt_rt5651_quirk & BYT_RT5651_SSP0_AIF2)) {
907 /* fixup codec aif name */
908 snprintf(byt_rt5651_codec_aif_name,
909 sizeof(byt_rt5651_codec_aif_name),
910 "%s", "rt5651-aif2");
911
912 byt_rt5651_dais[dai_index].codec_dai_name =
913 byt_rt5651_codec_aif_name;
914 }
915
916 if ((byt_rt5651_quirk & BYT_RT5651_SSP0_AIF1) ||
917 (byt_rt5651_quirk & BYT_RT5651_SSP0_AIF2)) {
918 /* fixup cpu dai name name */
919 snprintf(byt_rt5651_cpu_dai_name,
920 sizeof(byt_rt5651_cpu_dai_name),
921 "%s", "ssp0-port");
922
923 byt_rt5651_dais[dai_index].cpu_dai_name =
924 byt_rt5651_cpu_dai_name;
925 }
926
02c0a3b3
PLB		 927 if (byt_rt5651_quirk & BYT_RT5651_MCLK_EN) {
928 priv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3");
929 if (IS_ERR(priv->mclk)) {
de5afce2 930 ret_val = PTR_ERR(priv->mclk);
02c0a3b3 931 dev_err(&pdev->dev,
de5afce2
CIK		 932 "Failed to get MCLK from pmc_plt_clk_3: %d\n",
933 ret_val);
02c0a3b3
PLB		 934 /*
935 * Fall back to bit clock usage for -ENOENT (clock not
936 * available likely due to missing dependencies), bail
937 * for all other errors, including -EPROBE_DEFER
938 */
939 if (ret_val != -ENOENT)
940 return ret_val;
941 byt_rt5651_quirk &= ~BYT_RT5651_MCLK_EN;
942 }
943 }
944
8f250e70
HG		 945 if (byt_rt5651_quirk & BYT_RT5651_HP_LR_SWAPPED)
946 hp_swapped = "-hp-swapped";
947 else
948 hp_swapped = "";
949
64484cce 950 snprintf(byt_rt5651_long_name, sizeof(byt_rt5651_long_name),
8f250e70
HG		 951 "bytcr-rt5651-%s-mic%s",
952 mic_name[BYT_RT5651_MAP(byt_rt5651_quirk)], hp_swapped);
64484cce
HG		 953 byt_rt5651_card.long_name = byt_rt5651_long_name;
954
2bd5bd15
PLB		 955 ret_val = devm_snd_soc_register_card(&pdev->dev, &byt_rt5651_card);
956
957 if (ret_val) {
958 dev_err(&pdev->dev, "devm_snd_soc_register_card failed %d\n",
959 ret_val);
960 return ret_val;
961 }
962 platform_set_drvdata(pdev, &byt_rt5651_card);
963 return ret_val;
964}
965
966static struct platform_driver snd_byt_rt5651_mc_driver = {
967 .driver = {
968 .name = "bytcr_rt5651",
2bd5bd15
PLB		 969 },
970 .probe = snd_byt_rt5651_mc_probe,
971};
972
973module_platform_driver(snd_byt_rt5651_mc_driver);
974
975MODULE_DESCRIPTION("ASoC Intel(R) Baytrail CR Machine driver for RT5651");
976MODULE_AUTHOR("Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>");
977MODULE_LICENSE("GPL v2");
978MODULE_ALIAS("platform:bytcr_rt5651");
Linux 6.x block layer and io_uring tree(s)