Merge tag 'linux_kselftest-fixes-6.12-rc2' of git://git.kernel.org/pub/scm/linux...
[linux-block.git] / sound / soc / fsl / mpc5200_dma.c
CommitLineData
ac097cac 1// SPDX-License-Identifier: GPL-2.0-only
1edfc248
AD
2//
3// Freescale MPC5200 PSC DMA
4// ALSA SoC Platform driver
5//
6// Copyright (C) 2008 Secret Lab Technologies Ltd.
7// Copyright (C) 2009 Jon Smirl, Digispeaker
89dd0842 8
89dd0842 9#include <linux/module.h>
07a38b1b 10#include <linux/dma-mapping.h>
5a0e3ad6 11#include <linux/slab.h>
340d79a1 12#include <linux/of.h>
5af50730
RH
13#include <linux/of_address.h>
14#include <linux/of_irq.h>
340d79a1 15#include <linux/platform_device.h>
89dd0842 16
89dd0842 17#include <sound/soc.h>
89dd0842 18
9a322993
PDM
19#include <linux/fsl/bestcomm/bestcomm.h>
20#include <linux/fsl/bestcomm/gen_bd.h>
89dd0842
JS
21#include <asm/mpc52xx_psc.h>
22
23#include "mpc5200_dma.h"
24
60bceb80
KM
25#define DRV_NAME "mpc5200_dma"
26
89dd0842
JS
27/*
28 * Interrupt handlers
29 */
cebe7767 30static irqreturn_t psc_dma_status_irq(int irq, void *_psc_dma)
89dd0842 31{
cebe7767
JS
32 struct psc_dma *psc_dma = _psc_dma;
33 struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
89dd0842
JS
34 u16 isr;
35
36 isr = in_be16(&regs->mpc52xx_psc_isr);
37
38 /* Playback underrun error */
cebe7767
JS
39 if (psc_dma->playback.active && (isr & MPC52xx_PSC_IMR_TXEMP))
40 psc_dma->stats.underrun_count++;
89dd0842
JS
41
42 /* Capture overrun error */
cebe7767
JS
43 if (psc_dma->capture.active && (isr & MPC52xx_PSC_IMR_ORERR))
44 psc_dma->stats.overrun_count++;
89dd0842 45
dbcc3475 46 out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
89dd0842
JS
47
48 return IRQ_HANDLED;
49}
50
51/**
cebe7767 52 * psc_dma_bcom_enqueue_next_buffer - Enqueue another audio buffer
89dd0842
JS
53 * @s: pointer to stream private data structure
54 *
55 * Enqueues another audio period buffer into the bestcomm queue.
56 *
57 * Note: The routine must only be called when there is space available in
58 * the queue. Otherwise the enqueue will fail and the audio ring buffer
59 * will get out of sync
60 */
cebe7767 61static void psc_dma_bcom_enqueue_next_buffer(struct psc_dma_stream *s)
89dd0842
JS
62{
63 struct bcom_bd *bd;
64
65 /* Prepare and enqueue the next buffer descriptor */
66 bd = bcom_prepare_next_buffer(s->bcom_task);
67 bd->status = s->period_bytes;
8f159d72 68 bd->data[0] = s->runtime->dma_addr + (s->period_next * s->period_bytes);
89dd0842
JS
69 bcom_submit_next_buffer(s->bcom_task, NULL);
70
71 /* Update for next period */
8f159d72 72 s->period_next = (s->period_next + 1) % s->runtime->periods;
89dd0842
JS
73}
74
75/* Bestcomm DMA irq handler */
a68cc8da 76static irqreturn_t psc_dma_bcom_irq(int irq, void *_psc_dma_stream)
89dd0842 77{
dbcc3475 78 struct psc_dma_stream *s = _psc_dma_stream;
89dd0842 79
dbcc3475
JS
80 spin_lock(&s->psc_dma->lock);
81 /* For each finished period, dequeue the completed period buffer
82 * and enqueue a new one in it's place. */
83 while (bcom_buffer_done(s->bcom_task)) {
84 bcom_retrieve_buffer(s->bcom_task, NULL, NULL);
89dd0842 85
8f159d72 86 s->period_current = (s->period_current+1) % s->runtime->periods;
c4878274 87 s->period_count++;
dbcc3475
JS
88
89 psc_dma_bcom_enqueue_next_buffer(s);
89dd0842 90 }
dbcc3475 91 spin_unlock(&s->psc_dma->lock);
89dd0842 92
dbcc3475
JS
93 /* If the stream is active, then also inform the PCM middle layer
94 * of the period finished event. */
95 if (s->active)
96 snd_pcm_period_elapsed(s->stream);
97
98 return IRQ_HANDLED;
89dd0842
JS
99}
100
89dd0842 101/**
cebe7767 102 * psc_dma_trigger: start and stop the DMA transfer.
4a221b2e
KM
103 * @component: triggered component
104 * @substream: triggered substream
105 * @cmd: triggered command
89dd0842
JS
106 *
107 * This function is called by ALSA to start, stop, pause, and resume the DMA
108 * transfer of data.
109 */
6d1048bc
KM
110static int psc_dma_trigger(struct snd_soc_component *component,
111 struct snd_pcm_substream *substream, int cmd)
89dd0842 112{
14ec63f6
KM
113 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
114 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));
89dd0842 115 struct snd_pcm_runtime *runtime = substream->runtime;
1d8222e8 116 struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
cebe7767 117 struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
89dd0842 118 u16 imr;
89dd0842 119 unsigned long flags;
dbcc3475 120 int i;
89dd0842 121
89dd0842
JS
122 switch (cmd) {
123 case SNDRV_PCM_TRIGGER_START:
c4878274
GL
124 dev_dbg(psc_dma->dev, "START: stream=%i fbits=%u ps=%u #p=%u\n",
125 substream->pstr->stream, runtime->frame_bits,
126 (int)runtime->period_size, runtime->periods);
89dd0842
JS
127 s->period_bytes = frames_to_bytes(runtime,
128 runtime->period_size);
8f159d72
GL
129 s->period_next = 0;
130 s->period_current = 0;
89dd0842 131 s->active = 1;
c4878274 132 s->period_count = 0;
dbcc3475 133 s->runtime = runtime;
dbcc3475
JS
134
135 /* Fill up the bestcomm bd queue and enable DMA.
136 * This will begin filling the PSC's fifo.
137 */
138 spin_lock_irqsave(&psc_dma->lock, flags);
139
d56b6eb6 140 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
dbcc3475 141 bcom_gen_bd_rx_reset(s->bcom_task);
d56b6eb6 142 else
dbcc3475 143 bcom_gen_bd_tx_reset(s->bcom_task);
d56b6eb6
GL
144
145 for (i = 0; i < runtime->periods; i++)
146 if (!bcom_queue_full(s->bcom_task))
147 psc_dma_bcom_enqueue_next_buffer(s);
89dd0842 148
89dd0842 149 bcom_enable(s->bcom_task);
cebe7767 150 spin_unlock_irqrestore(&psc_dma->lock, flags);
89dd0842 151
dbcc3475
JS
152 out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
153
89dd0842
JS
154 break;
155
156 case SNDRV_PCM_TRIGGER_STOP:
c4878274
GL
157 dev_dbg(psc_dma->dev, "STOP: stream=%i periods_count=%i\n",
158 substream->pstr->stream, s->period_count);
89dd0842 159 s->active = 0;
89dd0842 160
dbcc3475 161 spin_lock_irqsave(&psc_dma->lock, flags);
89dd0842 162 bcom_disable(s->bcom_task);
dbcc3475
JS
163 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
164 bcom_gen_bd_rx_reset(s->bcom_task);
165 else
166 bcom_gen_bd_tx_reset(s->bcom_task);
167 spin_unlock_irqrestore(&psc_dma->lock, flags);
89dd0842
JS
168
169 break;
170
171 default:
c4878274
GL
172 dev_dbg(psc_dma->dev, "unhandled trigger: stream=%i cmd=%i\n",
173 substream->pstr->stream, cmd);
89dd0842
JS
174 return -EINVAL;
175 }
176
177 /* Update interrupt enable settings */
178 imr = 0;
cebe7767 179 if (psc_dma->playback.active)
89dd0842 180 imr |= MPC52xx_PSC_IMR_TXEMP;
cebe7767 181 if (psc_dma->capture.active)
89dd0842 182 imr |= MPC52xx_PSC_IMR_ORERR;
dbcc3475 183 out_be16(&regs->isr_imr.imr, psc_dma->imr | imr);
89dd0842
JS
184
185 return 0;
186}
187
89dd0842
JS
188
189/* ---------------------------------------------------------------------
190 * The PSC DMA 'ASoC platform' driver
191 *
192 * Can be referenced by an 'ASoC machine' driver
193 * This driver only deals with the audio bus; it doesn't have any
194 * interaction with the attached codec
195 */
196
dbcc3475 197static const struct snd_pcm_hardware psc_dma_hardware = {
89dd0842
JS
198 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
199 SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
200 SNDRV_PCM_INFO_BATCH,
201 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE |
dbcc3475 202 SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE,
89dd0842
JS
203 .period_bytes_max = 1024 * 1024,
204 .period_bytes_min = 32,
205 .periods_min = 2,
206 .periods_max = 256,
207 .buffer_bytes_max = 2 * 1024 * 1024,
dbcc3475 208 .fifo_size = 512,
89dd0842
JS
209};
210
6d1048bc
KM
211static int psc_dma_open(struct snd_soc_component *component,
212 struct snd_pcm_substream *substream)
89dd0842 213{
dbcc3475 214 struct snd_pcm_runtime *runtime = substream->runtime;
14ec63f6
KM
215 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
216 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));
cebe7767 217 struct psc_dma_stream *s;
dbcc3475 218 int rc;
89dd0842 219
dbcc3475 220 dev_dbg(psc_dma->dev, "psc_dma_open(substream=%p)\n", substream);
89dd0842
JS
221
222 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
cebe7767 223 s = &psc_dma->capture;
89dd0842 224 else
cebe7767 225 s = &psc_dma->playback;
89dd0842 226
dbcc3475
JS
227 snd_soc_set_runtime_hwparams(substream, &psc_dma_hardware);
228
229 rc = snd_pcm_hw_constraint_integer(runtime,
230 SNDRV_PCM_HW_PARAM_PERIODS);
231 if (rc < 0) {
232 dev_err(substream->pcm->card->dev, "invalid buffer size\n");
233 return rc;
234 }
89dd0842
JS
235
236 s->stream = substream;
237 return 0;
238}
239
6d1048bc
KM
240static int psc_dma_close(struct snd_soc_component *component,
241 struct snd_pcm_substream *substream)
89dd0842 242{
14ec63f6
KM
243 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
244 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));
cebe7767 245 struct psc_dma_stream *s;
89dd0842 246
dbcc3475 247 dev_dbg(psc_dma->dev, "psc_dma_close(substream=%p)\n", substream);
89dd0842
JS
248
249 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
cebe7767 250 s = &psc_dma->capture;
89dd0842 251 else
cebe7767 252 s = &psc_dma->playback;
89dd0842 253
dbcc3475
JS
254 if (!psc_dma->playback.active &&
255 !psc_dma->capture.active) {
256
257 /* Disable all interrupts and reset the PSC */
258 out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
259 out_8(&psc_dma->psc_regs->command, 4 << 4); /* reset error */
260 }
89dd0842
JS
261 s->stream = NULL;
262 return 0;
263}
264
265static snd_pcm_uframes_t
6d1048bc
KM
266psc_dma_pointer(struct snd_soc_component *component,
267 struct snd_pcm_substream *substream)
89dd0842 268{
14ec63f6
KM
269 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
270 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));
cebe7767 271 struct psc_dma_stream *s;
89dd0842
JS
272 dma_addr_t count;
273
274 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
cebe7767 275 s = &psc_dma->capture;
89dd0842 276 else
cebe7767 277 s = &psc_dma->playback;
89dd0842 278
8f159d72 279 count = s->period_current * s->period_bytes;
89dd0842
JS
280
281 return bytes_to_frames(substream->runtime, count);
282}
283
6d1048bc
KM
284static int psc_dma_new(struct snd_soc_component *component,
285 struct snd_soc_pcm_runtime *rtd)
89dd0842 286{
552d1ef6 287 struct snd_card *card = rtd->card->snd_card;
14ec63f6 288 struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0);
552d1ef6 289 struct snd_pcm *pcm = rtd->pcm;
dbcc3475 290 size_t size = psc_dma_hardware.buffer_bytes_max;
c9bd5e69 291 int rc;
89dd0842 292
60bceb80 293 dev_dbg(component->dev, "psc_dma_new(card=%p, dai=%p, pcm=%p)\n",
89dd0842
JS
294 card, dai, pcm);
295
c9bd5e69
RK
296 rc = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
297 if (rc)
298 return rc;
89dd0842 299
3610a6d1
TI
300 return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, card->dev,
301 size);
89dd0842
JS
302}
303
60bceb80
KM
304static const struct snd_soc_component_driver mpc5200_audio_dma_component = {
305 .name = DRV_NAME,
6d1048bc
KM
306 .open = psc_dma_open,
307 .close = psc_dma_close,
6d1048bc
KM
308 .pointer = psc_dma_pointer,
309 .trigger = psc_dma_trigger,
6d1048bc 310 .pcm_construct = psc_dma_new,
89dd0842 311};
dbcc3475 312
f515b673 313int mpc5200_audio_dma_create(struct platform_device *op)
dbcc3475
JS
314{
315 phys_addr_t fifo;
316 struct psc_dma *psc_dma;
317 struct resource res;
318 int size, irq, rc;
319 const __be32 *prop;
320 void __iomem *regs;
33d7f778 321 int ret;
dbcc3475
JS
322
323 /* Fetch the registers and IRQ of the PSC */
61c7a080
GL
324 irq = irq_of_parse_and_map(op->dev.of_node, 0);
325 if (of_address_to_resource(op->dev.of_node, 0, &res)) {
dbcc3475
JS
326 dev_err(&op->dev, "Missing reg property\n");
327 return -ENODEV;
328 }
28f65c11 329 regs = ioremap(res.start, resource_size(&res));
dbcc3475
JS
330 if (!regs) {
331 dev_err(&op->dev, "Could not map registers\n");
332 return -ENODEV;
333 }
334
335 /* Allocate and initialize the driver private data */
336 psc_dma = kzalloc(sizeof *psc_dma, GFP_KERNEL);
337 if (!psc_dma) {
33d7f778
JL
338 ret = -ENOMEM;
339 goto out_unmap;
dbcc3475
JS
340 }
341
342 /* Get the PSC ID */
61c7a080 343 prop = of_get_property(op->dev.of_node, "cell-index", &size);
33d7f778
JL
344 if (!prop || size < sizeof *prop) {
345 ret = -ENODEV;
346 goto out_free;
347 }
dbcc3475
JS
348
349 spin_lock_init(&psc_dma->lock);
0827d6ba 350 mutex_init(&psc_dma->mutex);
dbcc3475
JS
351 psc_dma->id = be32_to_cpu(*prop);
352 psc_dma->irq = irq;
353 psc_dma->psc_regs = regs;
354 psc_dma->fifo_regs = regs + sizeof *psc_dma->psc_regs;
355 psc_dma->dev = &op->dev;
356 psc_dma->playback.psc_dma = psc_dma;
357 psc_dma->capture.psc_dma = psc_dma;
91ab7743 358 snprintf(psc_dma->name, sizeof(psc_dma->name), "PSC%d", psc_dma->id);
dbcc3475
JS
359
360 /* Find the address of the fifo data registers and setup the
361 * DMA tasks */
362 fifo = res.start + offsetof(struct mpc52xx_psc, buffer.buffer_32);
363 psc_dma->capture.bcom_task =
364 bcom_psc_gen_bd_rx_init(psc_dma->id, 10, fifo, 512);
365 psc_dma->playback.bcom_task =
366 bcom_psc_gen_bd_tx_init(psc_dma->id, 10, fifo);
367 if (!psc_dma->capture.bcom_task ||
368 !psc_dma->playback.bcom_task) {
369 dev_err(&op->dev, "Could not allocate bestcomm tasks\n");
33d7f778
JL
370 ret = -ENODEV;
371 goto out_free;
dbcc3475
JS
372 }
373
374 /* Disable all interrupts and reset the PSC */
375 out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
376 /* reset receiver */
377 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_RX);
378 /* reset transmitter */
379 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_TX);
380 /* reset error */
381 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_ERR_STAT);
382 /* reset mode */
383 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_SEL_MODE_REG_1);
384
385 /* Set up mode register;
386 * First write: RxRdy (FIFO Alarm) generates rx FIFO irq
387 * Second write: register Normal mode for non loopback
388 */
389 out_8(&psc_dma->psc_regs->mode, 0);
390 out_8(&psc_dma->psc_regs->mode, 0);
391
392 /* Set the TX and RX fifo alarm thresholds */
393 out_be16(&psc_dma->fifo_regs->rfalarm, 0x100);
394 out_8(&psc_dma->fifo_regs->rfcntl, 0x4);
395 out_be16(&psc_dma->fifo_regs->tfalarm, 0x100);
396 out_8(&psc_dma->fifo_regs->tfcntl, 0x7);
397
398 /* Lookup the IRQ numbers */
399 psc_dma->playback.irq =
400 bcom_get_task_irq(psc_dma->playback.bcom_task);
401 psc_dma->capture.irq =
402 bcom_get_task_irq(psc_dma->capture.bcom_task);
403
404 rc = request_irq(psc_dma->irq, &psc_dma_status_irq, IRQF_SHARED,
405 "psc-dma-status", psc_dma);
a68cc8da 406 rc |= request_irq(psc_dma->capture.irq, &psc_dma_bcom_irq, IRQF_SHARED,
dbcc3475 407 "psc-dma-capture", &psc_dma->capture);
a68cc8da 408 rc |= request_irq(psc_dma->playback.irq, &psc_dma_bcom_irq, IRQF_SHARED,
dbcc3475
JS
409 "psc-dma-playback", &psc_dma->playback);
410 if (rc) {
33d7f778
JL
411 ret = -ENODEV;
412 goto out_irq;
dbcc3475 413 }
89dd0842 414
dbcc3475
JS
415 /* Save what we've done so it can be found again later */
416 dev_set_drvdata(&op->dev, psc_dma);
417
418 /* Tell the ASoC OF helpers about it */
60bceb80
KM
419 return devm_snd_soc_register_component(&op->dev,
420 &mpc5200_audio_dma_component, NULL, 0);
33d7f778
JL
421out_irq:
422 free_irq(psc_dma->irq, psc_dma);
423 free_irq(psc_dma->capture.irq, &psc_dma->capture);
424 free_irq(psc_dma->playback.irq, &psc_dma->playback);
425out_free:
426 kfree(psc_dma);
427out_unmap:
428 iounmap(regs);
429 return ret;
dbcc3475 430}
f515b673 431EXPORT_SYMBOL_GPL(mpc5200_audio_dma_create);
dbcc3475 432
f515b673 433int mpc5200_audio_dma_destroy(struct platform_device *op)
dbcc3475
JS
434{
435 struct psc_dma *psc_dma = dev_get_drvdata(&op->dev);
436
437 dev_dbg(&op->dev, "mpc5200_audio_dma_destroy()\n");
438
dbcc3475
JS
439 bcom_gen_bd_rx_release(psc_dma->capture.bcom_task);
440 bcom_gen_bd_tx_release(psc_dma->playback.bcom_task);
441
442 /* Release irqs */
443 free_irq(psc_dma->irq, psc_dma);
444 free_irq(psc_dma->capture.irq, &psc_dma->capture);
445 free_irq(psc_dma->playback.irq, &psc_dma->playback);
446
447 iounmap(psc_dma->psc_regs);
448 kfree(psc_dma);
449 dev_set_drvdata(&op->dev, NULL);
450
451 return 0;
452}
f515b673 453EXPORT_SYMBOL_GPL(mpc5200_audio_dma_destroy);
dbcc3475
JS
454
455MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
456MODULE_DESCRIPTION("Freescale MPC5200 PSC in DMA mode ASoC Driver");
457MODULE_LICENSE("GPL");