Merge tag 'drm-fixes-2019-06-21' of git://anongit.freedesktop.org/drm/drm
[linux-2.6-block.git] / sound / soc / fsl / mpc5200_dma.c
CommitLineData
ac097cac 1// SPDX-License-Identifier: GPL-2.0-only
1edfc248
AD
2//
3// Freescale MPC5200 PSC DMA
4// ALSA SoC Platform driver
5//
6// Copyright (C) 2008 Secret Lab Technologies Ltd.
7// Copyright (C) 2009 Jon Smirl, Digispeaker
89dd0842 8
89dd0842 9#include <linux/module.h>
89dd0842 10#include <linux/of_device.h>
07a38b1b 11#include <linux/dma-mapping.h>
5a0e3ad6 12#include <linux/slab.h>
5af50730
RH
13#include <linux/of_address.h>
14#include <linux/of_irq.h>
f0fba2ad 15#include <linux/of_platform.h>
89dd0842 16
89dd0842 17#include <sound/soc.h>
89dd0842 18
9a322993
PDM
19#include <linux/fsl/bestcomm/bestcomm.h>
20#include <linux/fsl/bestcomm/gen_bd.h>
89dd0842
JS
21#include <asm/mpc52xx_psc.h>
22
23#include "mpc5200_dma.h"
24
60bceb80
KM
25#define DRV_NAME "mpc5200_dma"
26
89dd0842
JS
27/*
28 * Interrupt handlers
29 */
cebe7767 30static irqreturn_t psc_dma_status_irq(int irq, void *_psc_dma)
89dd0842 31{
cebe7767
JS
32 struct psc_dma *psc_dma = _psc_dma;
33 struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
89dd0842
JS
34 u16 isr;
35
36 isr = in_be16(&regs->mpc52xx_psc_isr);
37
38 /* Playback underrun error */
cebe7767
JS
39 if (psc_dma->playback.active && (isr & MPC52xx_PSC_IMR_TXEMP))
40 psc_dma->stats.underrun_count++;
89dd0842
JS
41
42 /* Capture overrun error */
cebe7767
JS
43 if (psc_dma->capture.active && (isr & MPC52xx_PSC_IMR_ORERR))
44 psc_dma->stats.overrun_count++;
89dd0842 45
dbcc3475 46 out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
89dd0842
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47
48 return IRQ_HANDLED;
49}
50
51/**
cebe7767 52 * psc_dma_bcom_enqueue_next_buffer - Enqueue another audio buffer
89dd0842
JS
53 * @s: pointer to stream private data structure
54 *
55 * Enqueues another audio period buffer into the bestcomm queue.
56 *
57 * Note: The routine must only be called when there is space available in
58 * the queue. Otherwise the enqueue will fail and the audio ring buffer
59 * will get out of sync
60 */
cebe7767 61static void psc_dma_bcom_enqueue_next_buffer(struct psc_dma_stream *s)
89dd0842
JS
62{
63 struct bcom_bd *bd;
64
65 /* Prepare and enqueue the next buffer descriptor */
66 bd = bcom_prepare_next_buffer(s->bcom_task);
67 bd->status = s->period_bytes;
8f159d72 68 bd->data[0] = s->runtime->dma_addr + (s->period_next * s->period_bytes);
89dd0842
JS
69 bcom_submit_next_buffer(s->bcom_task, NULL);
70
71 /* Update for next period */
8f159d72 72 s->period_next = (s->period_next + 1) % s->runtime->periods;
89dd0842
JS
73}
74
75/* Bestcomm DMA irq handler */
a68cc8da 76static irqreturn_t psc_dma_bcom_irq(int irq, void *_psc_dma_stream)
89dd0842 77{
dbcc3475 78 struct psc_dma_stream *s = _psc_dma_stream;
89dd0842 79
dbcc3475
JS
80 spin_lock(&s->psc_dma->lock);
81 /* For each finished period, dequeue the completed period buffer
82 * and enqueue a new one in it's place. */
83 while (bcom_buffer_done(s->bcom_task)) {
84 bcom_retrieve_buffer(s->bcom_task, NULL, NULL);
89dd0842 85
8f159d72 86 s->period_current = (s->period_current+1) % s->runtime->periods;
c4878274 87 s->period_count++;
dbcc3475
JS
88
89 psc_dma_bcom_enqueue_next_buffer(s);
89dd0842 90 }
dbcc3475 91 spin_unlock(&s->psc_dma->lock);
89dd0842 92
dbcc3475
JS
93 /* If the stream is active, then also inform the PCM middle layer
94 * of the period finished event. */
95 if (s->active)
96 snd_pcm_period_elapsed(s->stream);
97
98 return IRQ_HANDLED;
89dd0842
JS
99}
100
dbcc3475 101static int psc_dma_hw_free(struct snd_pcm_substream *substream)
89dd0842
JS
102{
103 snd_pcm_set_runtime_buffer(substream, NULL);
104 return 0;
105}
106
107/**
cebe7767 108 * psc_dma_trigger: start and stop the DMA transfer.
89dd0842
JS
109 *
110 * This function is called by ALSA to start, stop, pause, and resume the DMA
111 * transfer of data.
112 */
dbcc3475 113static int psc_dma_trigger(struct snd_pcm_substream *substream, int cmd)
89dd0842
JS
114{
115 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 116 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
89dd0842 117 struct snd_pcm_runtime *runtime = substream->runtime;
1d8222e8 118 struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
cebe7767 119 struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
89dd0842 120 u16 imr;
89dd0842 121 unsigned long flags;
dbcc3475 122 int i;
89dd0842 123
89dd0842
JS
124 switch (cmd) {
125 case SNDRV_PCM_TRIGGER_START:
c4878274
GL
126 dev_dbg(psc_dma->dev, "START: stream=%i fbits=%u ps=%u #p=%u\n",
127 substream->pstr->stream, runtime->frame_bits,
128 (int)runtime->period_size, runtime->periods);
89dd0842
JS
129 s->period_bytes = frames_to_bytes(runtime,
130 runtime->period_size);
8f159d72
GL
131 s->period_next = 0;
132 s->period_current = 0;
89dd0842 133 s->active = 1;
c4878274 134 s->period_count = 0;
dbcc3475 135 s->runtime = runtime;
dbcc3475
JS
136
137 /* Fill up the bestcomm bd queue and enable DMA.
138 * This will begin filling the PSC's fifo.
139 */
140 spin_lock_irqsave(&psc_dma->lock, flags);
141
d56b6eb6 142 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
dbcc3475 143 bcom_gen_bd_rx_reset(s->bcom_task);
d56b6eb6 144 else
dbcc3475 145 bcom_gen_bd_tx_reset(s->bcom_task);
d56b6eb6
GL
146
147 for (i = 0; i < runtime->periods; i++)
148 if (!bcom_queue_full(s->bcom_task))
149 psc_dma_bcom_enqueue_next_buffer(s);
89dd0842 150
89dd0842 151 bcom_enable(s->bcom_task);
cebe7767 152 spin_unlock_irqrestore(&psc_dma->lock, flags);
89dd0842 153
dbcc3475
JS
154 out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
155
89dd0842
JS
156 break;
157
158 case SNDRV_PCM_TRIGGER_STOP:
c4878274
GL
159 dev_dbg(psc_dma->dev, "STOP: stream=%i periods_count=%i\n",
160 substream->pstr->stream, s->period_count);
89dd0842 161 s->active = 0;
89dd0842 162
dbcc3475 163 spin_lock_irqsave(&psc_dma->lock, flags);
89dd0842 164 bcom_disable(s->bcom_task);
dbcc3475
JS
165 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
166 bcom_gen_bd_rx_reset(s->bcom_task);
167 else
168 bcom_gen_bd_tx_reset(s->bcom_task);
169 spin_unlock_irqrestore(&psc_dma->lock, flags);
89dd0842
JS
170
171 break;
172
173 default:
c4878274
GL
174 dev_dbg(psc_dma->dev, "unhandled trigger: stream=%i cmd=%i\n",
175 substream->pstr->stream, cmd);
89dd0842
JS
176 return -EINVAL;
177 }
178
179 /* Update interrupt enable settings */
180 imr = 0;
cebe7767 181 if (psc_dma->playback.active)
89dd0842 182 imr |= MPC52xx_PSC_IMR_TXEMP;
cebe7767 183 if (psc_dma->capture.active)
89dd0842 184 imr |= MPC52xx_PSC_IMR_ORERR;
dbcc3475 185 out_be16(&regs->isr_imr.imr, psc_dma->imr | imr);
89dd0842
JS
186
187 return 0;
188}
189
89dd0842
JS
190
191/* ---------------------------------------------------------------------
192 * The PSC DMA 'ASoC platform' driver
193 *
194 * Can be referenced by an 'ASoC machine' driver
195 * This driver only deals with the audio bus; it doesn't have any
196 * interaction with the attached codec
197 */
198
dbcc3475 199static const struct snd_pcm_hardware psc_dma_hardware = {
89dd0842
JS
200 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
201 SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
202 SNDRV_PCM_INFO_BATCH,
203 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE |
dbcc3475 204 SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE,
89dd0842
JS
205 .period_bytes_max = 1024 * 1024,
206 .period_bytes_min = 32,
207 .periods_min = 2,
208 .periods_max = 256,
209 .buffer_bytes_max = 2 * 1024 * 1024,
dbcc3475 210 .fifo_size = 512,
89dd0842
JS
211};
212
dbcc3475 213static int psc_dma_open(struct snd_pcm_substream *substream)
89dd0842 214{
dbcc3475 215 struct snd_pcm_runtime *runtime = substream->runtime;
89dd0842 216 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 217 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
cebe7767 218 struct psc_dma_stream *s;
dbcc3475 219 int rc;
89dd0842 220
dbcc3475 221 dev_dbg(psc_dma->dev, "psc_dma_open(substream=%p)\n", substream);
89dd0842
JS
222
223 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
cebe7767 224 s = &psc_dma->capture;
89dd0842 225 else
cebe7767 226 s = &psc_dma->playback;
89dd0842 227
dbcc3475
JS
228 snd_soc_set_runtime_hwparams(substream, &psc_dma_hardware);
229
230 rc = snd_pcm_hw_constraint_integer(runtime,
231 SNDRV_PCM_HW_PARAM_PERIODS);
232 if (rc < 0) {
233 dev_err(substream->pcm->card->dev, "invalid buffer size\n");
234 return rc;
235 }
89dd0842
JS
236
237 s->stream = substream;
238 return 0;
239}
240
dbcc3475 241static int psc_dma_close(struct snd_pcm_substream *substream)
89dd0842
JS
242{
243 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 244 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
cebe7767 245 struct psc_dma_stream *s;
89dd0842 246
dbcc3475 247 dev_dbg(psc_dma->dev, "psc_dma_close(substream=%p)\n", substream);
89dd0842
JS
248
249 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
cebe7767 250 s = &psc_dma->capture;
89dd0842 251 else
cebe7767 252 s = &psc_dma->playback;
89dd0842 253
dbcc3475
JS
254 if (!psc_dma->playback.active &&
255 !psc_dma->capture.active) {
256
257 /* Disable all interrupts and reset the PSC */
258 out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
259 out_8(&psc_dma->psc_regs->command, 4 << 4); /* reset error */
260 }
89dd0842
JS
261 s->stream = NULL;
262 return 0;
263}
264
265static snd_pcm_uframes_t
dbcc3475 266psc_dma_pointer(struct snd_pcm_substream *substream)
89dd0842
JS
267{
268 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 269 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
cebe7767 270 struct psc_dma_stream *s;
89dd0842
JS
271 dma_addr_t count;
272
273 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
cebe7767 274 s = &psc_dma->capture;
89dd0842 275 else
cebe7767 276 s = &psc_dma->playback;
89dd0842 277
8f159d72 278 count = s->period_current * s->period_bytes;
89dd0842
JS
279
280 return bytes_to_frames(substream->runtime, count);
281}
282
dbcc3475
JS
283static int
284psc_dma_hw_params(struct snd_pcm_substream *substream,
285 struct snd_pcm_hw_params *params)
286{
287 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
288
289 return 0;
290}
291
b6ed0720 292static const struct snd_pcm_ops psc_dma_ops = {
dbcc3475
JS
293 .open = psc_dma_open,
294 .close = psc_dma_close,
295 .hw_free = psc_dma_hw_free,
89dd0842 296 .ioctl = snd_pcm_lib_ioctl,
dbcc3475
JS
297 .pointer = psc_dma_pointer,
298 .trigger = psc_dma_trigger,
299 .hw_params = psc_dma_hw_params,
89dd0842
JS
300};
301
552d1ef6 302static int psc_dma_new(struct snd_soc_pcm_runtime *rtd)
89dd0842 303{
552d1ef6 304 struct snd_card *card = rtd->card->snd_card;
60bceb80 305 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME);
552d1ef6
LG
306 struct snd_soc_dai *dai = rtd->cpu_dai;
307 struct snd_pcm *pcm = rtd->pcm;
dbcc3475 308 size_t size = psc_dma_hardware.buffer_bytes_max;
c9bd5e69 309 int rc;
89dd0842 310
60bceb80 311 dev_dbg(component->dev, "psc_dma_new(card=%p, dai=%p, pcm=%p)\n",
89dd0842
JS
312 card, dai, pcm);
313
c9bd5e69
RK
314 rc = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
315 if (rc)
316 return rc;
89dd0842 317
6296914c 318 if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
dbcc3475 319 rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
6296914c 320 size, &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
89dd0842
JS
321 if (rc)
322 goto playback_alloc_err;
323 }
324
6296914c 325 if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
dbcc3475 326 rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
6296914c 327 size, &pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer);
89dd0842
JS
328 if (rc)
329 goto capture_alloc_err;
330 }
331
332 return 0;
333
334 capture_alloc_err:
6296914c
JE
335 if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream)
336 snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
dbcc3475 337
89dd0842
JS
338 playback_alloc_err:
339 dev_err(card->dev, "Cannot allocate buffer(s)\n");
dbcc3475 340
89dd0842
JS
341 return -ENOMEM;
342}
343
dbcc3475 344static void psc_dma_free(struct snd_pcm *pcm)
89dd0842
JS
345{
346 struct snd_soc_pcm_runtime *rtd = pcm->private_data;
60bceb80 347 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME);
89dd0842
JS
348 struct snd_pcm_substream *substream;
349 int stream;
350
60bceb80 351 dev_dbg(component->dev, "psc_dma_free(pcm=%p)\n", pcm);
89dd0842
JS
352
353 for (stream = 0; stream < 2; stream++) {
354 substream = pcm->streams[stream].substream;
355 if (substream) {
356 snd_dma_free_pages(&substream->dma_buffer);
357 substream->dma_buffer.area = NULL;
358 substream->dma_buffer.addr = 0;
359 }
360 }
361}
362
60bceb80
KM
363static const struct snd_soc_component_driver mpc5200_audio_dma_component = {
364 .name = DRV_NAME,
f0fba2ad 365 .ops = &psc_dma_ops,
dbcc3475
JS
366 .pcm_new = &psc_dma_new,
367 .pcm_free = &psc_dma_free,
89dd0842 368};
dbcc3475 369
f515b673 370int mpc5200_audio_dma_create(struct platform_device *op)
dbcc3475
JS
371{
372 phys_addr_t fifo;
373 struct psc_dma *psc_dma;
374 struct resource res;
375 int size, irq, rc;
376 const __be32 *prop;
377 void __iomem *regs;
33d7f778 378 int ret;
dbcc3475
JS
379
380 /* Fetch the registers and IRQ of the PSC */
61c7a080
GL
381 irq = irq_of_parse_and_map(op->dev.of_node, 0);
382 if (of_address_to_resource(op->dev.of_node, 0, &res)) {
dbcc3475
JS
383 dev_err(&op->dev, "Missing reg property\n");
384 return -ENODEV;
385 }
28f65c11 386 regs = ioremap(res.start, resource_size(&res));
dbcc3475
JS
387 if (!regs) {
388 dev_err(&op->dev, "Could not map registers\n");
389 return -ENODEV;
390 }
391
392 /* Allocate and initialize the driver private data */
393 psc_dma = kzalloc(sizeof *psc_dma, GFP_KERNEL);
394 if (!psc_dma) {
33d7f778
JL
395 ret = -ENOMEM;
396 goto out_unmap;
dbcc3475
JS
397 }
398
399 /* Get the PSC ID */
61c7a080 400 prop = of_get_property(op->dev.of_node, "cell-index", &size);
33d7f778
JL
401 if (!prop || size < sizeof *prop) {
402 ret = -ENODEV;
403 goto out_free;
404 }
dbcc3475
JS
405
406 spin_lock_init(&psc_dma->lock);
0827d6ba 407 mutex_init(&psc_dma->mutex);
dbcc3475
JS
408 psc_dma->id = be32_to_cpu(*prop);
409 psc_dma->irq = irq;
410 psc_dma->psc_regs = regs;
411 psc_dma->fifo_regs = regs + sizeof *psc_dma->psc_regs;
412 psc_dma->dev = &op->dev;
413 psc_dma->playback.psc_dma = psc_dma;
414 psc_dma->capture.psc_dma = psc_dma;
415 snprintf(psc_dma->name, sizeof psc_dma->name, "PSC%u", psc_dma->id);
416
417 /* Find the address of the fifo data registers and setup the
418 * DMA tasks */
419 fifo = res.start + offsetof(struct mpc52xx_psc, buffer.buffer_32);
420 psc_dma->capture.bcom_task =
421 bcom_psc_gen_bd_rx_init(psc_dma->id, 10, fifo, 512);
422 psc_dma->playback.bcom_task =
423 bcom_psc_gen_bd_tx_init(psc_dma->id, 10, fifo);
424 if (!psc_dma->capture.bcom_task ||
425 !psc_dma->playback.bcom_task) {
426 dev_err(&op->dev, "Could not allocate bestcomm tasks\n");
33d7f778
JL
427 ret = -ENODEV;
428 goto out_free;
dbcc3475
JS
429 }
430
431 /* Disable all interrupts and reset the PSC */
432 out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
433 /* reset receiver */
434 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_RX);
435 /* reset transmitter */
436 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_TX);
437 /* reset error */
438 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_ERR_STAT);
439 /* reset mode */
440 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_SEL_MODE_REG_1);
441
442 /* Set up mode register;
443 * First write: RxRdy (FIFO Alarm) generates rx FIFO irq
444 * Second write: register Normal mode for non loopback
445 */
446 out_8(&psc_dma->psc_regs->mode, 0);
447 out_8(&psc_dma->psc_regs->mode, 0);
448
449 /* Set the TX and RX fifo alarm thresholds */
450 out_be16(&psc_dma->fifo_regs->rfalarm, 0x100);
451 out_8(&psc_dma->fifo_regs->rfcntl, 0x4);
452 out_be16(&psc_dma->fifo_regs->tfalarm, 0x100);
453 out_8(&psc_dma->fifo_regs->tfcntl, 0x7);
454
455 /* Lookup the IRQ numbers */
456 psc_dma->playback.irq =
457 bcom_get_task_irq(psc_dma->playback.bcom_task);
458 psc_dma->capture.irq =
459 bcom_get_task_irq(psc_dma->capture.bcom_task);
460
461 rc = request_irq(psc_dma->irq, &psc_dma_status_irq, IRQF_SHARED,
462 "psc-dma-status", psc_dma);
a68cc8da 463 rc |= request_irq(psc_dma->capture.irq, &psc_dma_bcom_irq, IRQF_SHARED,
dbcc3475 464 "psc-dma-capture", &psc_dma->capture);
a68cc8da 465 rc |= request_irq(psc_dma->playback.irq, &psc_dma_bcom_irq, IRQF_SHARED,
dbcc3475
JS
466 "psc-dma-playback", &psc_dma->playback);
467 if (rc) {
33d7f778
JL
468 ret = -ENODEV;
469 goto out_irq;
dbcc3475 470 }
89dd0842 471
dbcc3475
JS
472 /* Save what we've done so it can be found again later */
473 dev_set_drvdata(&op->dev, psc_dma);
474
475 /* Tell the ASoC OF helpers about it */
60bceb80
KM
476 return devm_snd_soc_register_component(&op->dev,
477 &mpc5200_audio_dma_component, NULL, 0);
33d7f778
JL
478out_irq:
479 free_irq(psc_dma->irq, psc_dma);
480 free_irq(psc_dma->capture.irq, &psc_dma->capture);
481 free_irq(psc_dma->playback.irq, &psc_dma->playback);
482out_free:
483 kfree(psc_dma);
484out_unmap:
485 iounmap(regs);
486 return ret;
dbcc3475 487}
f515b673 488EXPORT_SYMBOL_GPL(mpc5200_audio_dma_create);
dbcc3475 489
f515b673 490int mpc5200_audio_dma_destroy(struct platform_device *op)
dbcc3475
JS
491{
492 struct psc_dma *psc_dma = dev_get_drvdata(&op->dev);
493
494 dev_dbg(&op->dev, "mpc5200_audio_dma_destroy()\n");
495
dbcc3475
JS
496 bcom_gen_bd_rx_release(psc_dma->capture.bcom_task);
497 bcom_gen_bd_tx_release(psc_dma->playback.bcom_task);
498
499 /* Release irqs */
500 free_irq(psc_dma->irq, psc_dma);
501 free_irq(psc_dma->capture.irq, &psc_dma->capture);
502 free_irq(psc_dma->playback.irq, &psc_dma->playback);
503
504 iounmap(psc_dma->psc_regs);
505 kfree(psc_dma);
506 dev_set_drvdata(&op->dev, NULL);
507
508 return 0;
509}
f515b673 510EXPORT_SYMBOL_GPL(mpc5200_audio_dma_destroy);
dbcc3475
JS
511
512MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
513MODULE_DESCRIPTION("Freescale MPC5200 PSC in DMA mode ASoC Driver");
514MODULE_LICENSE("GPL");