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17467f23 TT |
1 | /* |
2 | * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
f0fba2ad LG |
6 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
de623ece MP |
11 | * |
12 | * | |
13 | * Some notes why imx-pcm-fiq is used instead of DMA on some boards: | |
14 | * | |
15 | * The i.MX SSI core has some nasty limitations in AC97 mode. While most | |
16 | * sane processor vendors have a FIFO per AC97 slot, the i.MX has only | |
17 | * one FIFO which combines all valid receive slots. We cannot even select | |
18 | * which slots we want to receive. The WM9712 with which this driver | |
19 | * was developed with always sends GPIO status data in slot 12 which | |
20 | * we receive in our (PCM-) data stream. The only chance we have is to | |
21 | * manually skip this data in the FIQ handler. With sampling rates different | |
22 | * from 48000Hz not every frame has valid receive data, so the ratio | |
23 | * between pcm data and GPIO status data changes. Our FIQ handler is not | |
24 | * able to handle this, hence this driver only works with 48000Hz sampling | |
25 | * rate. | |
26 | * Reading and writing AC97 registers is another challenge. The core | |
27 | * provides us status bits when the read register is updated with *another* | |
28 | * value. When we read the same register two times (and the register still | |
29 | * contains the same value) these status bits are not set. We work | |
30 | * around this by not polling these bits but only wait a fixed delay. | |
17467f23 TT |
31 | */ |
32 | ||
33 | #include <linux/init.h> | |
dfa1a107 | 34 | #include <linux/io.h> |
17467f23 TT |
35 | #include <linux/module.h> |
36 | #include <linux/interrupt.h> | |
95cd98f9 | 37 | #include <linux/clk.h> |
9368acc4 | 38 | #include <linux/debugfs.h> |
17467f23 TT |
39 | #include <linux/device.h> |
40 | #include <linux/delay.h> | |
5a0e3ad6 | 41 | #include <linux/slab.h> |
aafa85e7 | 42 | #include <linux/spinlock.h> |
dfa1a107 SG |
43 | #include <linux/of_address.h> |
44 | #include <linux/of_irq.h> | |
f0fba2ad | 45 | #include <linux/of_platform.h> |
17467f23 | 46 | |
17467f23 TT |
47 | #include <sound/core.h> |
48 | #include <sound/pcm.h> | |
49 | #include <sound/pcm_params.h> | |
50 | #include <sound/initval.h> | |
51 | #include <sound/soc.h> | |
a8909c9b | 52 | #include <sound/dmaengine_pcm.h> |
17467f23 | 53 | |
17467f23 | 54 | #include "fsl_ssi.h" |
09ce1111 | 55 | #include "imx-pcm.h" |
17467f23 | 56 | |
dfa1a107 SG |
57 | #ifdef PPC |
58 | #define read_ssi(addr) in_be32(addr) | |
59 | #define write_ssi(val, addr) out_be32(addr, val) | |
60 | #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set) | |
0a9eaa39 | 61 | #else |
dfa1a107 SG |
62 | #define read_ssi(addr) readl(addr) |
63 | #define write_ssi(val, addr) writel(val, addr) | |
64 | /* | |
65 | * FIXME: Proper locking should be added at write_ssi_mask caller level | |
66 | * to ensure this register read/modify/write sequence is race free. | |
67 | */ | |
68 | static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set) | |
69 | { | |
70 | u32 val = readl(addr); | |
71 | val = (val & ~clear) | set; | |
72 | writel(val, addr); | |
73 | } | |
74 | #endif | |
75 | ||
17467f23 TT |
76 | /** |
77 | * FSLSSI_I2S_RATES: sample rates supported by the I2S | |
78 | * | |
79 | * This driver currently only supports the SSI running in I2S slave mode, | |
80 | * which means the codec determines the sample rate. Therefore, we tell | |
81 | * ALSA that we support all rates and let the codec driver decide what rates | |
82 | * are really supported. | |
83 | */ | |
84 | #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ | |
85 | SNDRV_PCM_RATE_CONTINUOUS) | |
86 | ||
87 | /** | |
88 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI | |
89 | * | |
90 | * This driver currently only supports the SSI running in I2S slave mode. | |
91 | * | |
92 | * The SSI has a limitation in that the samples must be in the same byte | |
93 | * order as the host CPU. This is because when multiple bytes are written | |
94 | * to the STX register, the bytes and bits must be written in the same | |
95 | * order. The STX is a shift register, so all the bits need to be aligned | |
96 | * (bit-endianness must match byte-endianness). Processors typically write | |
97 | * the bits within a byte in the same order that the bytes of a word are | |
98 | * written in. So if the host CPU is big-endian, then only big-endian | |
99 | * samples will be written to STX properly. | |
100 | */ | |
101 | #ifdef __BIG_ENDIAN | |
102 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ | |
103 | SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
104 | SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) | |
105 | #else | |
106 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
107 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
108 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) | |
109 | #endif | |
110 | ||
d5a908b2 TT |
111 | /* SIER bitflag of interrupts to enable */ |
112 | #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \ | |
113 | CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \ | |
114 | CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \ | |
115 | CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \ | |
116 | CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN) | |
117 | ||
9368acc4 MP |
118 | #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \ |
119 | CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \ | |
120 | CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN) | |
121 | #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \ | |
122 | CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \ | |
123 | CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN) | |
124 | #define FSLSSI_SISR_MASK (FSLSSI_SIER_DBG_RX_FLAGS | FSLSSI_SIER_DBG_TX_FLAGS) | |
125 | ||
c1953bfe MP |
126 | |
127 | enum fsl_ssi_type { | |
128 | FSL_SSI_MCP8610, | |
129 | FSL_SSI_MX21, | |
130 | FSL_SSI_MX51, | |
131 | }; | |
132 | ||
17467f23 TT |
133 | /** |
134 | * fsl_ssi_private: per-SSI private data | |
135 | * | |
17467f23 TT |
136 | * @ssi: pointer to the SSI's registers |
137 | * @ssi_phys: physical address of the SSI registers | |
138 | * @irq: IRQ of this SSI | |
17467f23 TT |
139 | * @playback: the number of playback streams opened |
140 | * @capture: the number of capture streams opened | |
141 | * @cpu_dai: the CPU DAI for this device | |
142 | * @dev_attr: the sysfs device attribute structure | |
143 | * @stats: SSI statistics | |
f0fba2ad | 144 | * @name: name for this device |
17467f23 TT |
145 | */ |
146 | struct fsl_ssi_private { | |
17467f23 TT |
147 | struct ccsr_ssi __iomem *ssi; |
148 | dma_addr_t ssi_phys; | |
149 | unsigned int irq; | |
8e9d8690 | 150 | unsigned int fifo_depth; |
f0fba2ad | 151 | struct snd_soc_dai_driver cpu_dai_drv; |
f0fba2ad | 152 | struct platform_device *pdev; |
17467f23 | 153 | |
09ce1111 SG |
154 | bool new_binding; |
155 | bool ssi_on_imx; | |
cd7f0295 | 156 | bool imx_ac97; |
de623ece | 157 | bool use_dma; |
aafa85e7 | 158 | bool baudclk_locked; |
2841be9a | 159 | bool irq_stats; |
2924a998 | 160 | u8 i2s_mode; |
aafa85e7 NC |
161 | spinlock_t baudclk_lock; |
162 | struct clk *baudclk; | |
95cd98f9 | 163 | struct clk *clk; |
a8909c9b LPC |
164 | struct snd_dmaengine_dai_dma_data dma_params_tx; |
165 | struct snd_dmaengine_dai_dma_data dma_params_rx; | |
166 | struct imx_dma_data filter_data_tx; | |
167 | struct imx_dma_data filter_data_rx; | |
de623ece | 168 | struct imx_pcm_fiq_params fiq_params; |
09ce1111 | 169 | |
17467f23 TT |
170 | struct { |
171 | unsigned int rfrc; | |
172 | unsigned int tfrc; | |
173 | unsigned int cmdau; | |
174 | unsigned int cmddu; | |
175 | unsigned int rxt; | |
176 | unsigned int rdr1; | |
177 | unsigned int rdr0; | |
178 | unsigned int tde1; | |
179 | unsigned int tde0; | |
180 | unsigned int roe1; | |
181 | unsigned int roe0; | |
182 | unsigned int tue1; | |
183 | unsigned int tue0; | |
184 | unsigned int tfs; | |
185 | unsigned int rfs; | |
186 | unsigned int tls; | |
187 | unsigned int rls; | |
188 | unsigned int rff1; | |
189 | unsigned int rff0; | |
190 | unsigned int tfe1; | |
191 | unsigned int tfe0; | |
192 | } stats; | |
9368acc4 MP |
193 | struct dentry *dbg_dir; |
194 | struct dentry *dbg_stats; | |
f0fba2ad LG |
195 | |
196 | char name[1]; | |
17467f23 TT |
197 | }; |
198 | ||
c1953bfe MP |
199 | static const struct of_device_id fsl_ssi_ids[] = { |
200 | { .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610}, | |
201 | { .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51}, | |
202 | { .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21}, | |
203 | {} | |
204 | }; | |
205 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); | |
206 | ||
17467f23 TT |
207 | /** |
208 | * fsl_ssi_isr: SSI interrupt handler | |
209 | * | |
210 | * Although it's possible to use the interrupt handler to send and receive | |
211 | * data to/from the SSI, we use the DMA instead. Programming is more | |
212 | * complicated, but the performance is much better. | |
213 | * | |
214 | * This interrupt handler is used only to gather statistics. | |
215 | * | |
216 | * @irq: IRQ of the SSI device | |
217 | * @dev_id: pointer to the ssi_private structure for this SSI device | |
218 | */ | |
219 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) | |
220 | { | |
221 | struct fsl_ssi_private *ssi_private = dev_id; | |
222 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
223 | irqreturn_t ret = IRQ_NONE; | |
224 | __be32 sisr; | |
225 | __be32 sisr2 = 0; | |
226 | ||
227 | /* We got an interrupt, so read the status register to see what we | |
228 | were interrupted for. We mask it with the Interrupt Enable register | |
229 | so that we only check for events that we're interested in. | |
230 | */ | |
9368acc4 | 231 | sisr = read_ssi(&ssi->sisr) & FSLSSI_SISR_MASK; |
17467f23 TT |
232 | |
233 | if (sisr & CCSR_SSI_SISR_RFRC) { | |
234 | ssi_private->stats.rfrc++; | |
235 | sisr2 |= CCSR_SSI_SISR_RFRC; | |
236 | ret = IRQ_HANDLED; | |
237 | } | |
238 | ||
239 | if (sisr & CCSR_SSI_SISR_TFRC) { | |
240 | ssi_private->stats.tfrc++; | |
241 | sisr2 |= CCSR_SSI_SISR_TFRC; | |
242 | ret = IRQ_HANDLED; | |
243 | } | |
244 | ||
245 | if (sisr & CCSR_SSI_SISR_CMDAU) { | |
246 | ssi_private->stats.cmdau++; | |
247 | ret = IRQ_HANDLED; | |
248 | } | |
249 | ||
250 | if (sisr & CCSR_SSI_SISR_CMDDU) { | |
251 | ssi_private->stats.cmddu++; | |
252 | ret = IRQ_HANDLED; | |
253 | } | |
254 | ||
255 | if (sisr & CCSR_SSI_SISR_RXT) { | |
256 | ssi_private->stats.rxt++; | |
257 | ret = IRQ_HANDLED; | |
258 | } | |
259 | ||
260 | if (sisr & CCSR_SSI_SISR_RDR1) { | |
261 | ssi_private->stats.rdr1++; | |
262 | ret = IRQ_HANDLED; | |
263 | } | |
264 | ||
265 | if (sisr & CCSR_SSI_SISR_RDR0) { | |
266 | ssi_private->stats.rdr0++; | |
267 | ret = IRQ_HANDLED; | |
268 | } | |
269 | ||
270 | if (sisr & CCSR_SSI_SISR_TDE1) { | |
271 | ssi_private->stats.tde1++; | |
272 | ret = IRQ_HANDLED; | |
273 | } | |
274 | ||
275 | if (sisr & CCSR_SSI_SISR_TDE0) { | |
276 | ssi_private->stats.tde0++; | |
277 | ret = IRQ_HANDLED; | |
278 | } | |
279 | ||
280 | if (sisr & CCSR_SSI_SISR_ROE1) { | |
281 | ssi_private->stats.roe1++; | |
282 | sisr2 |= CCSR_SSI_SISR_ROE1; | |
283 | ret = IRQ_HANDLED; | |
284 | } | |
285 | ||
286 | if (sisr & CCSR_SSI_SISR_ROE0) { | |
287 | ssi_private->stats.roe0++; | |
288 | sisr2 |= CCSR_SSI_SISR_ROE0; | |
289 | ret = IRQ_HANDLED; | |
290 | } | |
291 | ||
292 | if (sisr & CCSR_SSI_SISR_TUE1) { | |
293 | ssi_private->stats.tue1++; | |
294 | sisr2 |= CCSR_SSI_SISR_TUE1; | |
295 | ret = IRQ_HANDLED; | |
296 | } | |
297 | ||
298 | if (sisr & CCSR_SSI_SISR_TUE0) { | |
299 | ssi_private->stats.tue0++; | |
300 | sisr2 |= CCSR_SSI_SISR_TUE0; | |
301 | ret = IRQ_HANDLED; | |
302 | } | |
303 | ||
304 | if (sisr & CCSR_SSI_SISR_TFS) { | |
305 | ssi_private->stats.tfs++; | |
306 | ret = IRQ_HANDLED; | |
307 | } | |
308 | ||
309 | if (sisr & CCSR_SSI_SISR_RFS) { | |
310 | ssi_private->stats.rfs++; | |
311 | ret = IRQ_HANDLED; | |
312 | } | |
313 | ||
314 | if (sisr & CCSR_SSI_SISR_TLS) { | |
315 | ssi_private->stats.tls++; | |
316 | ret = IRQ_HANDLED; | |
317 | } | |
318 | ||
319 | if (sisr & CCSR_SSI_SISR_RLS) { | |
320 | ssi_private->stats.rls++; | |
321 | ret = IRQ_HANDLED; | |
322 | } | |
323 | ||
324 | if (sisr & CCSR_SSI_SISR_RFF1) { | |
325 | ssi_private->stats.rff1++; | |
326 | ret = IRQ_HANDLED; | |
327 | } | |
328 | ||
329 | if (sisr & CCSR_SSI_SISR_RFF0) { | |
330 | ssi_private->stats.rff0++; | |
331 | ret = IRQ_HANDLED; | |
332 | } | |
333 | ||
334 | if (sisr & CCSR_SSI_SISR_TFE1) { | |
335 | ssi_private->stats.tfe1++; | |
336 | ret = IRQ_HANDLED; | |
337 | } | |
338 | ||
339 | if (sisr & CCSR_SSI_SISR_TFE0) { | |
340 | ssi_private->stats.tfe0++; | |
341 | ret = IRQ_HANDLED; | |
342 | } | |
343 | ||
344 | /* Clear the bits that we set */ | |
345 | if (sisr2) | |
dfa1a107 | 346 | write_ssi(sisr2, &ssi->sisr); |
17467f23 TT |
347 | |
348 | return ret; | |
349 | } | |
350 | ||
9368acc4 MP |
351 | #if IS_ENABLED(CONFIG_DEBUG_FS) |
352 | /* Show the statistics of a flag only if its interrupt is enabled. The | |
353 | * compiler will optimze this code to a no-op if the interrupt is not | |
354 | * enabled. | |
355 | */ | |
356 | #define SIER_SHOW(flag, name) \ | |
357 | do { \ | |
358 | if (FSLSSI_SISR_MASK & CCSR_SSI_SIER_##flag) \ | |
359 | seq_printf(s, #name "=%u\n", ssi_private->stats.name); \ | |
360 | } while (0) | |
361 | ||
362 | ||
363 | /** | |
364 | * fsl_sysfs_ssi_show: display SSI statistics | |
365 | * | |
366 | * Display the statistics for the current SSI device. To avoid confusion, | |
367 | * we only show those counts that are enabled. | |
368 | */ | |
369 | static ssize_t fsl_ssi_stats_show(struct seq_file *s, void *unused) | |
370 | { | |
371 | struct fsl_ssi_private *ssi_private = s->private; | |
372 | ||
373 | SIER_SHOW(RFRC_EN, rfrc); | |
374 | SIER_SHOW(TFRC_EN, tfrc); | |
375 | SIER_SHOW(CMDAU_EN, cmdau); | |
376 | SIER_SHOW(CMDDU_EN, cmddu); | |
377 | SIER_SHOW(RXT_EN, rxt); | |
378 | SIER_SHOW(RDR1_EN, rdr1); | |
379 | SIER_SHOW(RDR0_EN, rdr0); | |
380 | SIER_SHOW(TDE1_EN, tde1); | |
381 | SIER_SHOW(TDE0_EN, tde0); | |
382 | SIER_SHOW(ROE1_EN, roe1); | |
383 | SIER_SHOW(ROE0_EN, roe0); | |
384 | SIER_SHOW(TUE1_EN, tue1); | |
385 | SIER_SHOW(TUE0_EN, tue0); | |
386 | SIER_SHOW(TFS_EN, tfs); | |
387 | SIER_SHOW(RFS_EN, rfs); | |
388 | SIER_SHOW(TLS_EN, tls); | |
389 | SIER_SHOW(RLS_EN, rls); | |
390 | SIER_SHOW(RFF1_EN, rff1); | |
391 | SIER_SHOW(RFF0_EN, rff0); | |
392 | SIER_SHOW(TFE1_EN, tfe1); | |
393 | SIER_SHOW(TFE0_EN, tfe0); | |
394 | ||
395 | return 0; | |
396 | } | |
397 | ||
398 | static int fsl_ssi_stats_open(struct inode *inode, struct file *file) | |
399 | { | |
400 | return single_open(file, fsl_ssi_stats_show, inode->i_private); | |
401 | } | |
402 | ||
403 | static const struct file_operations fsl_ssi_stats_ops = { | |
404 | .open = fsl_ssi_stats_open, | |
405 | .read = seq_read, | |
406 | .llseek = seq_lseek, | |
407 | .release = single_release, | |
408 | }; | |
409 | ||
410 | static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private, | |
411 | struct device *dev) | |
412 | { | |
413 | ssi_private->dbg_dir = debugfs_create_dir(dev_name(dev), NULL); | |
414 | if (!ssi_private->dbg_dir) | |
415 | return -ENOMEM; | |
416 | ||
417 | ssi_private->dbg_stats = debugfs_create_file("stats", S_IRUGO, | |
418 | ssi_private->dbg_dir, ssi_private, &fsl_ssi_stats_ops); | |
419 | if (!ssi_private->dbg_stats) { | |
420 | debugfs_remove(ssi_private->dbg_dir); | |
421 | return -ENOMEM; | |
422 | } | |
423 | ||
424 | return 0; | |
425 | } | |
426 | ||
427 | static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private) | |
428 | { | |
429 | debugfs_remove(ssi_private->dbg_stats); | |
430 | debugfs_remove(ssi_private->dbg_dir); | |
431 | } | |
432 | ||
433 | #else | |
434 | ||
435 | static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private, | |
436 | struct device *dev) | |
437 | { | |
438 | return 0; | |
439 | } | |
440 | ||
441 | static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private) | |
442 | { | |
443 | } | |
444 | ||
445 | #endif /* IS_ENABLED(CONFIG_DEBUG_FS) */ | |
446 | ||
d8764646 MP |
447 | static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) |
448 | { | |
449 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
450 | ||
451 | /* | |
452 | * Setup the clock control register | |
453 | */ | |
454 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | |
455 | &ssi->stccr); | |
456 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | |
457 | &ssi->srccr); | |
458 | ||
459 | /* | |
460 | * Enable AC97 mode and startup the SSI | |
461 | */ | |
462 | write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV, | |
463 | &ssi->sacnt); | |
464 | write_ssi(0xff, &ssi->saccdis); | |
465 | write_ssi(0x300, &ssi->saccen); | |
466 | ||
467 | /* | |
468 | * Enable SSI, Transmit and Receive. AC97 has to communicate with the | |
469 | * codec before a stream is started. | |
470 | */ | |
471 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN | | |
472 | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); | |
473 | ||
474 | write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor); | |
475 | } | |
476 | ||
cd7f0295 MP |
477 | static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private) |
478 | { | |
479 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
cd7f0295 MP |
480 | u8 wm; |
481 | int synchronous = ssi_private->cpu_dai_drv.symmetric_rates; | |
482 | ||
483 | if (ssi_private->imx_ac97) | |
2924a998 | 484 | ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET; |
cd7f0295 | 485 | else |
2924a998 | 486 | ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE; |
cd7f0295 MP |
487 | |
488 | /* | |
489 | * Section 16.5 of the MPC8610 reference manual says that the SSI needs | |
490 | * to be disabled before updating the registers we set here. | |
491 | */ | |
492 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0); | |
493 | ||
494 | /* | |
495 | * Program the SSI into I2S Slave Non-Network Synchronous mode. Also | |
496 | * enable the transmit and receive FIFO. | |
497 | * | |
498 | * FIXME: Little-endian samples require a different shift dir | |
499 | */ | |
500 | write_ssi_mask(&ssi->scr, | |
501 | CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN, | |
502 | CCSR_SSI_SCR_TFR_CLK_DIS | | |
2924a998 | 503 | ssi_private->i2s_mode | |
cd7f0295 MP |
504 | (synchronous ? CCSR_SSI_SCR_SYN : 0)); |
505 | ||
506 | write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 | | |
507 | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS | | |
508 | CCSR_SSI_STCR_TSCKP, &ssi->stcr); | |
509 | ||
510 | write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 | | |
511 | CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS | | |
512 | CCSR_SSI_SRCR_RSCKP, &ssi->srcr); | |
513 | /* | |
514 | * The DC and PM bits are only used if the SSI is the clock master. | |
515 | */ | |
516 | ||
517 | /* | |
518 | * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't | |
519 | * use FIFO 1. We program the transmit water to signal a DMA transfer | |
520 | * if there are only two (or fewer) elements left in the FIFO. Two | |
521 | * elements equals one frame (left channel, right channel). This value, | |
522 | * however, depends on the depth of the transmit buffer. | |
523 | * | |
524 | * We set the watermark on the same level as the DMA burstsize. For | |
525 | * fiq it is probably better to use the biggest possible watermark | |
526 | * size. | |
527 | */ | |
528 | if (ssi_private->use_dma) | |
529 | wm = ssi_private->fifo_depth - 2; | |
530 | else | |
531 | wm = ssi_private->fifo_depth; | |
532 | ||
533 | write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | | |
534 | CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm), | |
535 | &ssi->sfcsr); | |
536 | ||
cd7f0295 MP |
537 | /* |
538 | * For ac97 interrupts are enabled with the startup of the substream | |
539 | * because it is also running without an active substream. Normally SSI | |
540 | * is only enabled when there is a substream. | |
541 | */ | |
d8764646 MP |
542 | if (ssi_private->imx_ac97) |
543 | fsl_ssi_setup_ac97(ssi_private); | |
cd7f0295 MP |
544 | |
545 | return 0; | |
546 | } | |
547 | ||
548 | ||
17467f23 TT |
549 | /** |
550 | * fsl_ssi_startup: create a new substream | |
551 | * | |
552 | * This is the first function called when a stream is opened. | |
553 | * | |
554 | * If this is the first stream open, then grab the IRQ and program most of | |
555 | * the SSI registers. | |
556 | */ | |
dee89c4d MB |
557 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
558 | struct snd_soc_dai *dai) | |
17467f23 TT |
559 | { |
560 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
5e538eca TT |
561 | struct fsl_ssi_private *ssi_private = |
562 | snd_soc_dai_get_drvdata(rtd->cpu_dai); | |
aafa85e7 | 563 | unsigned long flags; |
17467f23 | 564 | |
07a9483a NC |
565 | /* First, we only do fsl_ssi_setup() when SSI is going to be active. |
566 | * Second, fsl_ssi_setup was already called by ac97_init earlier if | |
567 | * the driver is in ac97 mode. | |
17467f23 | 568 | */ |
aafa85e7 | 569 | if (!dai->active && !ssi_private->imx_ac97) { |
07a9483a | 570 | fsl_ssi_setup(ssi_private); |
aafa85e7 NC |
571 | spin_lock_irqsave(&ssi_private->baudclk_lock, flags); |
572 | ssi_private->baudclk_locked = false; | |
573 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
574 | } | |
be41e941 | 575 | |
17467f23 TT |
576 | return 0; |
577 | } | |
578 | ||
579 | /** | |
85ef2375 | 580 | * fsl_ssi_hw_params - program the sample size |
17467f23 TT |
581 | * |
582 | * Most of the SSI registers have been programmed in the startup function, | |
583 | * but the word length must be programmed here. Unfortunately, programming | |
584 | * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can | |
585 | * cause a problem with supporting simultaneous playback and capture. If | |
586 | * the SSI is already playing a stream, then that stream may be temporarily | |
587 | * stopped when you start capture. | |
588 | * | |
589 | * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the | |
590 | * clock master. | |
591 | */ | |
85ef2375 TT |
592 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
593 | struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) | |
17467f23 | 594 | { |
f0fba2ad | 595 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
5e538eca | 596 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
2924a998 | 597 | unsigned int channels = params_channels(hw_params); |
5e538eca TT |
598 | unsigned int sample_size = |
599 | snd_pcm_format_width(params_format(hw_params)); | |
600 | u32 wl = CCSR_SSI_SxCCR_WL(sample_size); | |
dfa1a107 | 601 | int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; |
17467f23 | 602 | |
5e538eca TT |
603 | /* |
604 | * If we're in synchronous mode, and the SSI is already enabled, | |
605 | * then STCCR is already set properly. | |
606 | */ | |
607 | if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) | |
608 | return 0; | |
17467f23 | 609 | |
5e538eca TT |
610 | /* |
611 | * FIXME: The documentation says that SxCCR[WL] should not be | |
612 | * modified while the SSI is enabled. The only time this can | |
613 | * happen is if we're trying to do simultaneous playback and | |
614 | * capture in asynchronous mode. Unfortunately, I have been enable | |
615 | * to get that to work at all on the P1022DS. Therefore, we don't | |
616 | * bother to disable/enable the SSI when setting SxCCR[WL], because | |
617 | * the SSI will stop anyway. Maybe one day, this will get fixed. | |
618 | */ | |
17467f23 | 619 | |
5e538eca TT |
620 | /* In synchronous mode, the SSI uses STCCR for capture */ |
621 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || | |
622 | ssi_private->cpu_dai_drv.symmetric_rates) | |
dfa1a107 | 623 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
5e538eca | 624 | else |
dfa1a107 | 625 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
17467f23 | 626 | |
2924a998 NC |
627 | if (!ssi_private->imx_ac97) |
628 | write_ssi_mask(&ssi->scr, | |
629 | CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, | |
630 | channels == 1 ? 0 : ssi_private->i2s_mode); | |
631 | ||
17467f23 TT |
632 | return 0; |
633 | } | |
634 | ||
aafa85e7 NC |
635 | /** |
636 | * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format. | |
637 | */ | |
638 | static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
639 | { | |
640 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
641 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
642 | u32 strcr = 0, stcr, srcr, scr, mask; | |
643 | ||
644 | scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); | |
645 | scr |= CCSR_SSI_SCR_NET; | |
646 | ||
647 | mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | | |
648 | CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | | |
649 | CCSR_SSI_STCR_TEFS; | |
650 | stcr = read_ssi(&ssi->stcr) & ~mask; | |
651 | srcr = read_ssi(&ssi->srcr) & ~mask; | |
652 | ||
653 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
654 | case SND_SOC_DAIFMT_I2S: | |
655 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
656 | case SND_SOC_DAIFMT_CBS_CFS: | |
657 | ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_MASTER; | |
658 | break; | |
659 | case SND_SOC_DAIFMT_CBM_CFM: | |
660 | ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE; | |
661 | break; | |
662 | default: | |
663 | return -EINVAL; | |
664 | } | |
665 | scr |= ssi_private->i2s_mode; | |
666 | ||
667 | /* Data on rising edge of bclk, frame low, 1clk before data */ | |
668 | strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP | | |
669 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; | |
670 | break; | |
671 | case SND_SOC_DAIFMT_LEFT_J: | |
672 | /* Data on rising edge of bclk, frame high */ | |
673 | strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP; | |
674 | break; | |
675 | case SND_SOC_DAIFMT_DSP_A: | |
676 | /* Data on rising edge of bclk, frame high, 1clk before data */ | |
677 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | | |
678 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; | |
679 | break; | |
680 | case SND_SOC_DAIFMT_DSP_B: | |
681 | /* Data on rising edge of bclk, frame high */ | |
682 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | | |
683 | CCSR_SSI_STCR_TXBIT0; | |
684 | break; | |
685 | default: | |
686 | return -EINVAL; | |
687 | } | |
688 | ||
689 | /* DAI clock inversion */ | |
690 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
691 | case SND_SOC_DAIFMT_NB_NF: | |
692 | /* Nothing to do for both normal cases */ | |
693 | break; | |
694 | case SND_SOC_DAIFMT_IB_NF: | |
695 | /* Invert bit clock */ | |
696 | strcr ^= CCSR_SSI_STCR_TSCKP; | |
697 | break; | |
698 | case SND_SOC_DAIFMT_NB_IF: | |
699 | /* Invert frame clock */ | |
700 | strcr ^= CCSR_SSI_STCR_TFSI; | |
701 | break; | |
702 | case SND_SOC_DAIFMT_IB_IF: | |
703 | /* Invert both clocks */ | |
704 | strcr ^= CCSR_SSI_STCR_TSCKP; | |
705 | strcr ^= CCSR_SSI_STCR_TFSI; | |
706 | break; | |
707 | default: | |
708 | return -EINVAL; | |
709 | } | |
710 | ||
711 | /* DAI clock master masks */ | |
712 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
713 | case SND_SOC_DAIFMT_CBS_CFS: | |
714 | strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR; | |
715 | scr |= CCSR_SSI_SCR_SYS_CLK_EN; | |
716 | break; | |
717 | case SND_SOC_DAIFMT_CBM_CFM: | |
718 | scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; | |
719 | break; | |
720 | default: | |
721 | return -EINVAL; | |
722 | } | |
723 | ||
724 | stcr |= strcr; | |
725 | srcr |= strcr; | |
726 | ||
727 | if (ssi_private->cpu_dai_drv.symmetric_rates) { | |
728 | /* Need to clear RXDIR when using SYNC mode */ | |
729 | srcr &= ~CCSR_SSI_SRCR_RXDIR; | |
730 | scr |= CCSR_SSI_SCR_SYN; | |
731 | } | |
732 | ||
733 | write_ssi(stcr, &ssi->stcr); | |
734 | write_ssi(srcr, &ssi->srcr); | |
735 | write_ssi(scr, &ssi->scr); | |
736 | ||
737 | return 0; | |
738 | } | |
739 | ||
740 | /** | |
741 | * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock | |
742 | * | |
743 | * Note: This function can be only called when using SSI as DAI master | |
744 | * | |
745 | * Quick instruction for parameters: | |
746 | * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels | |
747 | * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK. | |
748 | */ | |
749 | static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
750 | int clk_id, unsigned int freq, int dir) | |
751 | { | |
752 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
753 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
754 | int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret; | |
755 | u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; | |
756 | unsigned long flags, clkrate, baudrate, tmprate; | |
757 | u64 sub, savesub = 100000; | |
758 | ||
759 | /* Don't apply it to any non-baudclk circumstance */ | |
760 | if (IS_ERR(ssi_private->baudclk)) | |
761 | return -EINVAL; | |
762 | ||
763 | /* It should be already enough to divide clock by setting pm alone */ | |
764 | psr = 0; | |
765 | div2 = 0; | |
766 | ||
767 | factor = (div2 + 1) * (7 * psr + 1) * 2; | |
768 | ||
769 | for (i = 0; i < 255; i++) { | |
770 | /* The bclk rate must be smaller than 1/5 sysclk rate */ | |
771 | if (factor * (i + 1) < 5) | |
772 | continue; | |
773 | ||
774 | tmprate = freq * factor * (i + 2); | |
775 | clkrate = clk_round_rate(ssi_private->baudclk, tmprate); | |
776 | ||
777 | do_div(clkrate, factor); | |
778 | afreq = (u32)clkrate / (i + 1); | |
779 | ||
780 | if (freq == afreq) | |
781 | sub = 0; | |
782 | else if (freq / afreq == 1) | |
783 | sub = freq - afreq; | |
784 | else if (afreq / freq == 1) | |
785 | sub = afreq - freq; | |
786 | else | |
787 | continue; | |
788 | ||
789 | /* Calculate the fraction */ | |
790 | sub *= 100000; | |
791 | do_div(sub, freq); | |
792 | ||
793 | if (sub < savesub) { | |
794 | baudrate = tmprate; | |
795 | savesub = sub; | |
796 | pm = i; | |
797 | } | |
798 | ||
799 | /* We are lucky */ | |
800 | if (savesub == 0) | |
801 | break; | |
802 | } | |
803 | ||
804 | /* No proper pm found if it is still remaining the initial value */ | |
805 | if (pm == 999) { | |
806 | dev_err(cpu_dai->dev, "failed to handle the required sysclk\n"); | |
807 | return -EINVAL; | |
808 | } | |
809 | ||
810 | stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) | | |
811 | (psr ? CCSR_SSI_SxCCR_PSR : 0); | |
812 | mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | CCSR_SSI_SxCCR_PSR; | |
813 | ||
814 | if (dir == SND_SOC_CLOCK_OUT || synchronous) | |
815 | write_ssi_mask(&ssi->stccr, mask, stccr); | |
816 | else | |
817 | write_ssi_mask(&ssi->srccr, mask, stccr); | |
818 | ||
819 | spin_lock_irqsave(&ssi_private->baudclk_lock, flags); | |
820 | if (!ssi_private->baudclk_locked) { | |
821 | ret = clk_set_rate(ssi_private->baudclk, baudrate); | |
822 | if (ret) { | |
823 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
824 | dev_err(cpu_dai->dev, "failed to set baudclk rate\n"); | |
825 | return -EINVAL; | |
826 | } | |
827 | ssi_private->baudclk_locked = true; | |
828 | } | |
829 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
830 | ||
831 | return 0; | |
832 | } | |
833 | ||
834 | /** | |
835 | * fsl_ssi_set_dai_tdm_slot - set TDM slot number | |
836 | * | |
837 | * Note: This function can be only called when using SSI as DAI master | |
838 | */ | |
839 | static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, | |
840 | u32 rx_mask, int slots, int slot_width) | |
841 | { | |
842 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
843 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
844 | u32 val; | |
845 | ||
846 | /* The slot number should be >= 2 if using Network mode or I2S mode */ | |
847 | val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET); | |
848 | if (val && slots < 2) { | |
849 | dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); | |
850 | return -EINVAL; | |
851 | } | |
852 | ||
853 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK, | |
854 | CCSR_SSI_SxCCR_DC(slots)); | |
855 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK, | |
856 | CCSR_SSI_SxCCR_DC(slots)); | |
857 | ||
858 | /* The register SxMSKs needs SSI to provide essential clock due to | |
859 | * hardware design. So we here temporarily enable SSI to set them. | |
860 | */ | |
861 | val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; | |
862 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN); | |
863 | ||
864 | write_ssi(tx_mask, &ssi->stmsk); | |
865 | write_ssi(rx_mask, &ssi->srmsk); | |
866 | ||
867 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val); | |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
17467f23 TT |
872 | /** |
873 | * fsl_ssi_trigger: start and stop the DMA transfer. | |
874 | * | |
875 | * This function is called by ALSA to start, stop, pause, and resume the DMA | |
876 | * transfer of data. | |
877 | * | |
878 | * The DMA channel is in external master start and pause mode, which | |
879 | * means the SSI completely controls the flow of data. | |
880 | */ | |
dee89c4d MB |
881 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
882 | struct snd_soc_dai *dai) | |
17467f23 TT |
883 | { |
884 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 885 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 | 886 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
9b443e3d | 887 | unsigned int sier_bits; |
aafa85e7 | 888 | unsigned long flags; |
9b443e3d MG |
889 | |
890 | /* | |
891 | * Enable only the interrupts and DMA requests | |
892 | * that are needed for the channel. As the fiq | |
893 | * is polling for this bits, we have to ensure | |
894 | * that this are aligned with the preallocated | |
895 | * buffers | |
896 | */ | |
897 | ||
898 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
899 | if (ssi_private->use_dma) | |
900 | sier_bits = SIER_FLAGS; | |
901 | else | |
902 | sier_bits = CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN; | |
903 | } else { | |
904 | if (ssi_private->use_dma) | |
905 | sier_bits = SIER_FLAGS; | |
906 | else | |
907 | sier_bits = CCSR_SSI_SIER_RIE | CCSR_SSI_SIER_RFF0_EN; | |
908 | } | |
17467f23 TT |
909 | |
910 | switch (cmd) { | |
911 | case SNDRV_PCM_TRIGGER_START: | |
17467f23 | 912 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
a4d11fe5 | 913 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
dfa1a107 | 914 | write_ssi_mask(&ssi->scr, 0, |
be41e941 | 915 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE); |
a4d11fe5 | 916 | else |
dfa1a107 | 917 | write_ssi_mask(&ssi->scr, 0, |
be41e941 | 918 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE); |
17467f23 TT |
919 | break; |
920 | ||
921 | case SNDRV_PCM_TRIGGER_STOP: | |
17467f23 TT |
922 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
923 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
dfa1a107 | 924 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0); |
17467f23 | 925 | else |
dfa1a107 | 926 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0); |
b2c119b0 | 927 | |
cd7f0295 | 928 | if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) & |
aafa85e7 | 929 | (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) { |
b2c119b0 | 930 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0); |
aafa85e7 NC |
931 | spin_lock_irqsave(&ssi_private->baudclk_lock, flags); |
932 | ssi_private->baudclk_locked = false; | |
933 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
934 | } | |
17467f23 TT |
935 | break; |
936 | ||
937 | default: | |
938 | return -EINVAL; | |
939 | } | |
940 | ||
9b443e3d MG |
941 | write_ssi(sier_bits, &ssi->sier); |
942 | ||
17467f23 TT |
943 | return 0; |
944 | } | |
945 | ||
fc8ba7f9 LPC |
946 | static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) |
947 | { | |
948 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai); | |
949 | ||
de623ece | 950 | if (ssi_private->ssi_on_imx && ssi_private->use_dma) { |
fc8ba7f9 LPC |
951 | dai->playback_dma_data = &ssi_private->dma_params_tx; |
952 | dai->capture_dma_data = &ssi_private->dma_params_rx; | |
953 | } | |
954 | ||
955 | return 0; | |
956 | } | |
957 | ||
85e7652d | 958 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
6335d055 EM |
959 | .startup = fsl_ssi_startup, |
960 | .hw_params = fsl_ssi_hw_params, | |
aafa85e7 NC |
961 | .set_fmt = fsl_ssi_set_dai_fmt, |
962 | .set_sysclk = fsl_ssi_set_dai_sysclk, | |
963 | .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, | |
6335d055 | 964 | .trigger = fsl_ssi_trigger, |
6335d055 EM |
965 | }; |
966 | ||
f0fba2ad LG |
967 | /* Template for the CPU dai driver structure */ |
968 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { | |
fc8ba7f9 | 969 | .probe = fsl_ssi_dai_probe, |
17467f23 | 970 | .playback = { |
2924a998 | 971 | .channels_min = 1, |
17467f23 TT |
972 | .channels_max = 2, |
973 | .rates = FSLSSI_I2S_RATES, | |
974 | .formats = FSLSSI_I2S_FORMATS, | |
975 | }, | |
976 | .capture = { | |
2924a998 | 977 | .channels_min = 1, |
17467f23 TT |
978 | .channels_max = 2, |
979 | .rates = FSLSSI_I2S_RATES, | |
980 | .formats = FSLSSI_I2S_FORMATS, | |
981 | }, | |
6335d055 | 982 | .ops = &fsl_ssi_dai_ops, |
17467f23 TT |
983 | }; |
984 | ||
3580aa10 KM |
985 | static const struct snd_soc_component_driver fsl_ssi_component = { |
986 | .name = "fsl-ssi", | |
987 | }; | |
988 | ||
cd7f0295 MP |
989 | /** |
990 | * fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit. | |
991 | * | |
992 | * This function is called by ALSA to start, stop, pause, and resume the | |
993 | * transfer of data. | |
994 | */ | |
995 | static int fsl_ssi_ac97_trigger(struct snd_pcm_substream *substream, int cmd, | |
996 | struct snd_soc_dai *dai) | |
997 | { | |
998 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
999 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata( | |
1000 | rtd->cpu_dai); | |
1001 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
1002 | ||
1003 | switch (cmd) { | |
1004 | case SNDRV_PCM_TRIGGER_START: | |
1005 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
1006 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1007 | write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TIE | | |
1008 | CCSR_SSI_SIER_TFE0_EN); | |
1009 | else | |
1010 | write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RIE | | |
1011 | CCSR_SSI_SIER_RFF0_EN); | |
1012 | break; | |
1013 | ||
1014 | case SNDRV_PCM_TRIGGER_STOP: | |
1015 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
1016 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1017 | write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TIE | | |
1018 | CCSR_SSI_SIER_TFE0_EN, 0); | |
1019 | else | |
1020 | write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RIE | | |
1021 | CCSR_SSI_SIER_RFF0_EN, 0); | |
1022 | break; | |
1023 | ||
1024 | default: | |
1025 | return -EINVAL; | |
1026 | } | |
1027 | ||
1028 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1029 | write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor); | |
1030 | else | |
1031 | write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor); | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops = { | |
1037 | .startup = fsl_ssi_startup, | |
cd7f0295 MP |
1038 | .trigger = fsl_ssi_ac97_trigger, |
1039 | }; | |
1040 | ||
1041 | static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { | |
1042 | .ac97_control = 1, | |
1043 | .playback = { | |
1044 | .stream_name = "AC97 Playback", | |
1045 | .channels_min = 2, | |
1046 | .channels_max = 2, | |
1047 | .rates = SNDRV_PCM_RATE_8000_48000, | |
1048 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
1049 | }, | |
1050 | .capture = { | |
1051 | .stream_name = "AC97 Capture", | |
1052 | .channels_min = 2, | |
1053 | .channels_max = 2, | |
1054 | .rates = SNDRV_PCM_RATE_48000, | |
1055 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
1056 | }, | |
1057 | .ops = &fsl_ssi_ac97_dai_ops, | |
1058 | }; | |
1059 | ||
1060 | ||
1061 | static struct fsl_ssi_private *fsl_ac97_data; | |
1062 | ||
1063 | static void fsl_ssi_ac97_init(void) | |
1064 | { | |
1065 | fsl_ssi_setup(fsl_ac97_data); | |
1066 | } | |
1067 | ||
a851a2bb | 1068 | static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
cd7f0295 MP |
1069 | unsigned short val) |
1070 | { | |
1071 | struct ccsr_ssi *ssi = fsl_ac97_data->ssi; | |
1072 | unsigned int lreg; | |
1073 | unsigned int lval; | |
1074 | ||
1075 | if (reg > 0x7f) | |
1076 | return; | |
1077 | ||
1078 | ||
1079 | lreg = reg << 12; | |
1080 | write_ssi(lreg, &ssi->sacadd); | |
1081 | ||
1082 | lval = val << 4; | |
1083 | write_ssi(lval , &ssi->sacdat); | |
1084 | ||
1085 | write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, | |
1086 | CCSR_SSI_SACNT_WR); | |
1087 | udelay(100); | |
1088 | } | |
1089 | ||
a851a2bb | 1090 | static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, |
cd7f0295 MP |
1091 | unsigned short reg) |
1092 | { | |
1093 | struct ccsr_ssi *ssi = fsl_ac97_data->ssi; | |
1094 | ||
1095 | unsigned short val = -1; | |
1096 | unsigned int lreg; | |
1097 | ||
1098 | lreg = (reg & 0x7f) << 12; | |
1099 | write_ssi(lreg, &ssi->sacadd); | |
1100 | write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, | |
1101 | CCSR_SSI_SACNT_RD); | |
1102 | ||
1103 | udelay(100); | |
1104 | ||
1105 | val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff; | |
1106 | ||
1107 | return val; | |
1108 | } | |
1109 | ||
1110 | static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { | |
1111 | .read = fsl_ssi_ac97_read, | |
1112 | .write = fsl_ssi_ac97_write, | |
1113 | }; | |
1114 | ||
17467f23 | 1115 | /** |
f0fba2ad | 1116 | * Make every character in a string lower-case |
17467f23 | 1117 | */ |
f0fba2ad LG |
1118 | static void make_lowercase(char *s) |
1119 | { | |
1120 | char *p = s; | |
1121 | char c; | |
1122 | ||
1123 | while ((c = *p)) { | |
1124 | if ((c >= 'A') && (c <= 'Z')) | |
1125 | *p = c + ('a' - 'A'); | |
1126 | p++; | |
1127 | } | |
1128 | } | |
1129 | ||
a0a3d518 | 1130 | static int fsl_ssi_probe(struct platform_device *pdev) |
17467f23 | 1131 | { |
17467f23 TT |
1132 | struct fsl_ssi_private *ssi_private; |
1133 | int ret = 0; | |
87a0632b | 1134 | struct device_attribute *dev_attr = NULL; |
38fec727 | 1135 | struct device_node *np = pdev->dev.of_node; |
c1953bfe MP |
1136 | const struct of_device_id *of_id; |
1137 | enum fsl_ssi_type hw_type; | |
f0fba2ad | 1138 | const char *p, *sprop; |
8e9d8690 | 1139 | const uint32_t *iprop; |
f0fba2ad LG |
1140 | struct resource res; |
1141 | char name[64]; | |
312bb4f6 | 1142 | bool shared; |
cd7f0295 | 1143 | bool ac97 = false; |
17467f23 | 1144 | |
ff71334a TT |
1145 | /* SSIs that are not connected on the board should have a |
1146 | * status = "disabled" | |
1147 | * property in their device tree nodes. | |
f0fba2ad | 1148 | */ |
ff71334a | 1149 | if (!of_device_is_available(np)) |
f0fba2ad LG |
1150 | return -ENODEV; |
1151 | ||
c1953bfe MP |
1152 | of_id = of_match_device(fsl_ssi_ids, &pdev->dev); |
1153 | if (!of_id) | |
1154 | return -EINVAL; | |
1155 | hw_type = (enum fsl_ssi_type) of_id->data; | |
1156 | ||
f0fba2ad LG |
1157 | /* We only support the SSI in "I2S Slave" mode */ |
1158 | sprop = of_get_property(np, "fsl,mode", NULL); | |
cd7f0295 MP |
1159 | if (!sprop) { |
1160 | dev_err(&pdev->dev, "fsl,mode property is necessary\n"); | |
1161 | return -EINVAL; | |
1162 | } | |
1163 | if (!strcmp(sprop, "ac97-slave")) { | |
1164 | ac97 = true; | |
1165 | } else if (strcmp(sprop, "i2s-slave")) { | |
38fec727 | 1166 | dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop); |
f0fba2ad LG |
1167 | return -ENODEV; |
1168 | } | |
1169 | ||
1170 | /* The DAI name is the last part of the full name of the node. */ | |
1171 | p = strrchr(np->full_name, '/') + 1; | |
b0a4747a | 1172 | ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p), |
f0fba2ad | 1173 | GFP_KERNEL); |
17467f23 | 1174 | if (!ssi_private) { |
38fec727 | 1175 | dev_err(&pdev->dev, "could not allocate DAI object\n"); |
f0fba2ad | 1176 | return -ENOMEM; |
17467f23 | 1177 | } |
17467f23 | 1178 | |
f0fba2ad | 1179 | strcpy(ssi_private->name, p); |
17467f23 | 1180 | |
de623ece MP |
1181 | ssi_private->use_dma = !of_property_read_bool(np, |
1182 | "fsl,fiq-stream-filter"); | |
1183 | ||
cd7f0295 MP |
1184 | if (ac97) { |
1185 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, | |
1186 | sizeof(fsl_ssi_ac97_dai)); | |
1187 | ||
1188 | fsl_ac97_data = ssi_private; | |
1189 | ssi_private->imx_ac97 = true; | |
1190 | ||
1191 | snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); | |
1192 | } else { | |
1193 | /* Initialize this copy of the CPU DAI driver structure */ | |
1194 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, | |
1195 | sizeof(fsl_ssi_dai_template)); | |
1196 | } | |
f0fba2ad LG |
1197 | ssi_private->cpu_dai_drv.name = ssi_private->name; |
1198 | ||
1199 | /* Get the addresses and IRQ */ | |
1200 | ret = of_address_to_resource(np, 0, &res); | |
1201 | if (ret) { | |
38fec727 | 1202 | dev_err(&pdev->dev, "could not determine device resources\n"); |
b0a4747a | 1203 | return ret; |
f0fba2ad | 1204 | } |
147dfe90 TT |
1205 | ssi_private->ssi = of_iomap(np, 0); |
1206 | if (!ssi_private->ssi) { | |
1207 | dev_err(&pdev->dev, "could not map device resources\n"); | |
b0a4747a | 1208 | return -ENOMEM; |
147dfe90 | 1209 | } |
f0fba2ad | 1210 | ssi_private->ssi_phys = res.start; |
1fab6caf | 1211 | |
f0fba2ad | 1212 | ssi_private->irq = irq_of_parse_and_map(np, 0); |
d60336e2 | 1213 | if (!ssi_private->irq) { |
1fab6caf | 1214 | dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); |
b0a4747a | 1215 | return -ENXIO; |
1fab6caf TT |
1216 | } |
1217 | ||
f0fba2ad | 1218 | /* Are the RX and the TX clocks locked? */ |
07a9483a | 1219 | if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { |
f0fba2ad | 1220 | ssi_private->cpu_dai_drv.symmetric_rates = 1; |
07a9483a NC |
1221 | ssi_private->cpu_dai_drv.symmetric_channels = 1; |
1222 | ssi_private->cpu_dai_drv.symmetric_samplebits = 1; | |
1223 | } | |
17467f23 | 1224 | |
8e9d8690 TT |
1225 | /* Determine the FIFO depth. */ |
1226 | iprop = of_get_property(np, "fsl,fifo-depth", NULL); | |
1227 | if (iprop) | |
147dfe90 | 1228 | ssi_private->fifo_depth = be32_to_cpup(iprop); |
8e9d8690 TT |
1229 | else |
1230 | /* Older 8610 DTs didn't have the fifo-depth property */ | |
1231 | ssi_private->fifo_depth = 8; | |
1232 | ||
aafa85e7 NC |
1233 | ssi_private->baudclk_locked = false; |
1234 | spin_lock_init(&ssi_private->baudclk_lock); | |
1235 | ||
c1953bfe MP |
1236 | if (hw_type == FSL_SSI_MX21 || hw_type == FSL_SSI_MX51 || |
1237 | hw_type == FSL_SSI_MX35) { | |
09ce1111 SG |
1238 | u32 dma_events[2]; |
1239 | ssi_private->ssi_on_imx = true; | |
95cd98f9 | 1240 | |
b0a4747a | 1241 | ssi_private->clk = devm_clk_get(&pdev->dev, NULL); |
95cd98f9 SG |
1242 | if (IS_ERR(ssi_private->clk)) { |
1243 | ret = PTR_ERR(ssi_private->clk); | |
1244 | dev_err(&pdev->dev, "could not get clock: %d\n", ret); | |
b0a4747a | 1245 | goto error_irqmap; |
95cd98f9 | 1246 | } |
ede32d3a FE |
1247 | ret = clk_prepare_enable(ssi_private->clk); |
1248 | if (ret) { | |
1249 | dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", | |
1250 | ret); | |
1251 | goto error_irqmap; | |
1252 | } | |
95cd98f9 | 1253 | |
aafa85e7 NC |
1254 | /* For those SLAVE implementations, we ingore non-baudclk cases |
1255 | * and, instead, abandon MASTER mode that needs baud clock. | |
1256 | */ | |
1257 | ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); | |
1258 | if (IS_ERR(ssi_private->baudclk)) | |
ff1b15ac | 1259 | dev_warn(&pdev->dev, "could not get baud clock: %ld\n", |
6873ee46 | 1260 | PTR_ERR(ssi_private->baudclk)); |
aafa85e7 NC |
1261 | else |
1262 | clk_prepare_enable(ssi_private->baudclk); | |
1263 | ||
09ce1111 SG |
1264 | /* |
1265 | * We have burstsize be "fifo_depth - 2" to match the SSI | |
1266 | * watermark setting in fsl_ssi_startup(). | |
1267 | */ | |
a8909c9b | 1268 | ssi_private->dma_params_tx.maxburst = |
09ce1111 | 1269 | ssi_private->fifo_depth - 2; |
a8909c9b | 1270 | ssi_private->dma_params_rx.maxburst = |
09ce1111 | 1271 | ssi_private->fifo_depth - 2; |
a8909c9b | 1272 | ssi_private->dma_params_tx.addr = |
09ce1111 | 1273 | ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0); |
a8909c9b | 1274 | ssi_private->dma_params_rx.addr = |
09ce1111 | 1275 | ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0); |
a8909c9b LPC |
1276 | ssi_private->dma_params_tx.filter_data = |
1277 | &ssi_private->filter_data_tx; | |
1278 | ssi_private->dma_params_rx.filter_data = | |
1279 | &ssi_private->filter_data_rx; | |
3a5e517b MP |
1280 | if (!of_property_read_bool(pdev->dev.of_node, "dmas") && |
1281 | ssi_private->use_dma) { | |
1282 | /* | |
1283 | * FIXME: This is a temporary solution until all | |
1284 | * necessary dma drivers support the generic dma | |
1285 | * bindings. | |
1286 | */ | |
1287 | ret = of_property_read_u32_array(pdev->dev.of_node, | |
09ce1111 | 1288 | "fsl,ssi-dma-events", dma_events, 2); |
3a5e517b MP |
1289 | if (ret && ssi_private->use_dma) { |
1290 | dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n"); | |
1291 | goto error_clk; | |
1292 | } | |
09ce1111 | 1293 | } |
312bb4f6 LPC |
1294 | |
1295 | shared = of_device_is_compatible(of_get_parent(np), | |
1296 | "fsl,spba-bus"); | |
1297 | ||
a8909c9b | 1298 | imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx, |
32bd8cd2 | 1299 | dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI); |
a8909c9b | 1300 | imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx, |
32bd8cd2 | 1301 | dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI); |
f0377086 MG |
1302 | } else if (ssi_private->use_dma) { |
1303 | /* The 'name' should not have any slashes in it. */ | |
1304 | ret = devm_request_irq(&pdev->dev, ssi_private->irq, | |
1305 | fsl_ssi_isr, 0, ssi_private->name, | |
1306 | ssi_private); | |
2841be9a | 1307 | ssi_private->irq_stats = true; |
f0377086 MG |
1308 | if (ret < 0) { |
1309 | dev_err(&pdev->dev, "could not claim irq %u\n", | |
1310 | ssi_private->irq); | |
1311 | goto error_irqmap; | |
1312 | } | |
09ce1111 SG |
1313 | } |
1314 | ||
f0fba2ad | 1315 | /* Register with ASoC */ |
38fec727 | 1316 | dev_set_drvdata(&pdev->dev, ssi_private); |
3f4b783c | 1317 | |
3580aa10 KM |
1318 | ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component, |
1319 | &ssi_private->cpu_dai_drv, 1); | |
87a0632b | 1320 | if (ret) { |
38fec727 | 1321 | dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); |
1fab6caf | 1322 | goto error_dev; |
f0fba2ad LG |
1323 | } |
1324 | ||
9368acc4 MP |
1325 | ret = fsl_ssi_debugfs_create(ssi_private, &pdev->dev); |
1326 | if (ret) | |
1327 | goto error_dbgfs; | |
1328 | ||
09ce1111 | 1329 | if (ssi_private->ssi_on_imx) { |
de623ece MP |
1330 | if (!ssi_private->use_dma) { |
1331 | ||
1332 | /* | |
1333 | * Some boards use an incompatible codec. To get it | |
1334 | * working, we are using imx-fiq-pcm-audio, that | |
1335 | * can handle those codecs. DMA is not possible in this | |
1336 | * situation. | |
1337 | */ | |
1338 | ||
1339 | ssi_private->fiq_params.irq = ssi_private->irq; | |
1340 | ssi_private->fiq_params.base = ssi_private->ssi; | |
1341 | ssi_private->fiq_params.dma_params_rx = | |
1342 | &ssi_private->dma_params_rx; | |
1343 | ssi_private->fiq_params.dma_params_tx = | |
1344 | &ssi_private->dma_params_tx; | |
1345 | ||
1346 | ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params); | |
1347 | if (ret) | |
2841be9a | 1348 | goto error_pcm; |
de623ece MP |
1349 | } else { |
1350 | ret = imx_pcm_dma_init(pdev); | |
1351 | if (ret) | |
2841be9a | 1352 | goto error_pcm; |
de623ece | 1353 | } |
09ce1111 SG |
1354 | } |
1355 | ||
1356 | /* | |
1357 | * If codec-handle property is missing from SSI node, we assume | |
1358 | * that the machine driver uses new binding which does not require | |
1359 | * SSI driver to trigger machine driver's probe. | |
1360 | */ | |
1361 | if (!of_get_property(np, "codec-handle", NULL)) { | |
1362 | ssi_private->new_binding = true; | |
1363 | goto done; | |
1364 | } | |
1365 | ||
f0fba2ad | 1366 | /* Trigger the machine driver's probe function. The platform driver |
2b81ec69 | 1367 | * name of the machine driver is taken from /compatible property of the |
f0fba2ad LG |
1368 | * device tree. We also pass the address of the CPU DAI driver |
1369 | * structure. | |
1370 | */ | |
2b81ec69 SG |
1371 | sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); |
1372 | /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ | |
f0fba2ad LG |
1373 | p = strrchr(sprop, ','); |
1374 | if (p) | |
1375 | sprop = p + 1; | |
1376 | snprintf(name, sizeof(name), "snd-soc-%s", sprop); | |
1377 | make_lowercase(name); | |
1378 | ||
1379 | ssi_private->pdev = | |
38fec727 | 1380 | platform_device_register_data(&pdev->dev, name, 0, NULL, 0); |
f0fba2ad LG |
1381 | if (IS_ERR(ssi_private->pdev)) { |
1382 | ret = PTR_ERR(ssi_private->pdev); | |
38fec727 | 1383 | dev_err(&pdev->dev, "failed to register platform: %d\n", ret); |
1fab6caf | 1384 | goto error_dai; |
3f4b783c | 1385 | } |
17467f23 | 1386 | |
09ce1111 | 1387 | done: |
cd7f0295 MP |
1388 | if (ssi_private->imx_ac97) |
1389 | fsl_ssi_ac97_init(); | |
1390 | ||
f0fba2ad | 1391 | return 0; |
87a0632b | 1392 | |
1fab6caf | 1393 | error_dai: |
2841be9a MP |
1394 | if (ssi_private->ssi_on_imx && !ssi_private->use_dma) |
1395 | imx_pcm_fiq_exit(pdev); | |
1396 | ||
1397 | error_pcm: | |
9368acc4 MP |
1398 | fsl_ssi_debugfs_remove(ssi_private); |
1399 | ||
1400 | error_dbgfs: | |
3580aa10 | 1401 | snd_soc_unregister_component(&pdev->dev); |
1fab6caf TT |
1402 | |
1403 | error_dev: | |
1fab6caf TT |
1404 | device_remove_file(&pdev->dev, dev_attr); |
1405 | ||
95cd98f9 | 1406 | error_clk: |
aafa85e7 NC |
1407 | if (ssi_private->ssi_on_imx) { |
1408 | if (!IS_ERR(ssi_private->baudclk)) | |
1409 | clk_disable_unprepare(ssi_private->baudclk); | |
95cd98f9 | 1410 | clk_disable_unprepare(ssi_private->clk); |
aafa85e7 | 1411 | } |
1fab6caf TT |
1412 | |
1413 | error_irqmap: | |
2841be9a MP |
1414 | if (ssi_private->irq_stats) |
1415 | irq_dispose_mapping(ssi_private->irq); | |
1fab6caf | 1416 | |
87a0632b | 1417 | return ret; |
17467f23 | 1418 | } |
17467f23 | 1419 | |
38fec727 | 1420 | static int fsl_ssi_remove(struct platform_device *pdev) |
17467f23 | 1421 | { |
38fec727 | 1422 | struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); |
17467f23 | 1423 | |
9368acc4 MP |
1424 | fsl_ssi_debugfs_remove(ssi_private); |
1425 | ||
09ce1111 SG |
1426 | if (!ssi_private->new_binding) |
1427 | platform_device_unregister(ssi_private->pdev); | |
3580aa10 | 1428 | snd_soc_unregister_component(&pdev->dev); |
aafa85e7 NC |
1429 | if (ssi_private->ssi_on_imx) { |
1430 | if (!IS_ERR(ssi_private->baudclk)) | |
1431 | clk_disable_unprepare(ssi_private->baudclk); | |
0783e648 | 1432 | clk_disable_unprepare(ssi_private->clk); |
aafa85e7 | 1433 | } |
2841be9a MP |
1434 | if (ssi_private->irq_stats) |
1435 | irq_dispose_mapping(ssi_private->irq); | |
f0fba2ad LG |
1436 | |
1437 | return 0; | |
17467f23 | 1438 | } |
f0fba2ad | 1439 | |
f07eb223 | 1440 | static struct platform_driver fsl_ssi_driver = { |
f0fba2ad LG |
1441 | .driver = { |
1442 | .name = "fsl-ssi-dai", | |
1443 | .owner = THIS_MODULE, | |
1444 | .of_match_table = fsl_ssi_ids, | |
1445 | }, | |
1446 | .probe = fsl_ssi_probe, | |
1447 | .remove = fsl_ssi_remove, | |
1448 | }; | |
17467f23 | 1449 | |
ba0a7e02 | 1450 | module_platform_driver(fsl_ssi_driver); |
a454dad1 | 1451 | |
f3142807 | 1452 | MODULE_ALIAS("platform:fsl-ssi-dai"); |
17467f23 TT |
1453 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
1454 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); | |
f0fba2ad | 1455 | MODULE_LICENSE("GPL v2"); |